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From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: kan.liang@intel.com, eranian@google.com, acme@infradead.org,
	linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling
Date: Fri, 8 May 2015 14:06:43 +0200	[thread overview]
Message-ID: <20150508120643.GG27504@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20150508115954.GT2366@two.firstfloor.org>

On Fri, May 08, 2015 at 01:59:54PM +0200, Andi Kleen wrote:
> > That's wrong. It does not respect perf_event_attr::clock_id.
> 
> Ok.
> 
> Are we really defaulting to real time now? 

No, we still default to the thing you implemented.

However, when the event is configured differently, you'll write the
wrong stamps in. This code needs to consider that.

> (CLOCK_REALTIME == 0)
> What happens when ntpd is active and lets the time drift? That
> sounds very bad for event accuracy.

NTP slew rate adjustment should still keep the thing monotonic, so its
still useful to order events.

But as is, CLOCK_REALTIME is not supported for hardware events, only
CLOCK_MONOTONIC and CLOCK_MONOTONIC_RAW are.

> The clockid patch looks broken to me. At least it should default
> to MONOTONIC time, not just the time that happens to be 0 by 
> accident.

You've not looked good enough, the Changelog states and the code matches
that the default is unchanged.

> Also I question we really need that many different kinds of
> time stamps.

CLOCK_MONOTONIC is useful for cluster wide timestamps,
CLOCK_MONOTONIC_RAW is useful for things that need/want to correlate to
fixed rate clocks.

Most of the other clocks are just a side effect of using the generic
clockid API for selecting clocks.

  reply	other threads:[~2015-05-08 12:06 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-07 22:56 perf: Add basic Skylake PMU support Andi Kleen
2015-05-07 22:56 ` [PATCH 1/9] x86: Add a native_perf_sched_clock_from_tsc Andi Kleen
2015-05-07 22:56 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen
2015-05-08 10:59   ` Peter Zijlstra
2015-05-08 11:59     ` Andi Kleen
2015-05-08 12:06       ` Peter Zijlstra [this message]
2015-05-07 22:56 ` [PATCH 3/9] x86: Add new MSRs and MSR bits used for Skylake perfmon Andi Kleen
2015-05-07 22:56 ` [PATCH 4/9] perf: Add cycles to branch_info Andi Kleen
2015-05-07 22:56 ` [PATCH 5/9] x86, perf: Add support for LBRv5 Andi Kleen
2015-05-07 22:56 ` [PATCH 6/9] x86, perf: Add Skylake support Andi Kleen
2015-05-07 22:56 ` [PATCH 7/9] perf, x86: Handle new status bits Andi Kleen
2015-05-07 22:56 ` [PATCH 8/9] perf, x86: Optimize v4 LBR unfreezing Andi Kleen
2015-05-08 11:19   ` Peter Zijlstra
2015-05-07 22:56 ` [PATCH 9/9] perf, tools: Add tools support for cycles, weight branch_info field Andi Kleen
  -- strict thread matches above, loose matches on Subject: below --
2015-05-10 19:22 perf: Add basic Skylake PMU support v2 Andi Kleen
2015-05-10 19:22 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen

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