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From: Andi Kleen <andi@firstfloor.org>
To: peterz@infradead.org
Cc: kan.liang@intel.com, eranian@google.com, acme@infradead.org,
	linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 8/9] perf, x86: Optimize v4 LBR unfreezing
Date: Thu,  7 May 2015 15:56:31 -0700	[thread overview]
Message-ID: <1431039392-12589-9-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1431039392-12589-1-git-send-email-andi@firstfloor.org>

From: Andi Kleen <ak@linux.intel.com>

In Arch perfmon v4 the GLOBAL_STATUS reset automatically unfreezes
LBRs. So no need to do it manually in the LBR code. Add a check
to skip it.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel_lbr.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 6c48c97..64d3122 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -147,6 +147,13 @@ static void __intel_pmu_lbr_enable(bool pmi)
 		wrmsrl(MSR_LBR_SELECT, lbr_select);
 	}
 
+	/*
+	 * No need to unfreeze manually, as v4 can do that as part
+	 * of the GLOBAL_STATUS ack.
+	 */
+	if (pmi && x86_pmu.version >= 4)
+		return;
+
 	rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 	orig_debugctl = debugctl;
 	debugctl |= DEBUGCTLMSR_LBR;
-- 
1.9.3


  parent reply	other threads:[~2015-05-07 22:57 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-07 22:56 perf: Add basic Skylake PMU support Andi Kleen
2015-05-07 22:56 ` [PATCH 1/9] x86: Add a native_perf_sched_clock_from_tsc Andi Kleen
2015-05-07 22:56 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen
2015-05-08 10:59   ` Peter Zijlstra
2015-05-08 11:59     ` Andi Kleen
2015-05-08 12:06       ` Peter Zijlstra
2015-05-07 22:56 ` [PATCH 3/9] x86: Add new MSRs and MSR bits used for Skylake perfmon Andi Kleen
2015-05-07 22:56 ` [PATCH 4/9] perf: Add cycles to branch_info Andi Kleen
2015-05-07 22:56 ` [PATCH 5/9] x86, perf: Add support for LBRv5 Andi Kleen
2015-05-07 22:56 ` [PATCH 6/9] x86, perf: Add Skylake support Andi Kleen
2015-05-07 22:56 ` [PATCH 7/9] perf, x86: Handle new status bits Andi Kleen
2015-05-07 22:56 ` Andi Kleen [this message]
2015-05-08 11:19   ` [PATCH 8/9] perf, x86: Optimize v4 LBR unfreezing Peter Zijlstra
2015-05-07 22:56 ` [PATCH 9/9] perf, tools: Add tools support for cycles, weight branch_info field Andi Kleen

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