From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: kan.liang@intel.com, eranian@google.com, acme@infradead.org,
linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling
Date: Fri, 8 May 2015 12:59:58 +0200 [thread overview]
Message-ID: <20150508105958.GD27504@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1431039392-12589-3-git-send-email-andi@firstfloor.org>
On Thu, May 07, 2015 at 03:56:25PM -0700, Andi Kleen wrote:
> +/* Same as HSW, plus TSC */
> +
> +struct pebs_record_v3 {
This is inconsistently named.
> + u64 flags, ip;
> + u64 ax, bx, cx, dx;
> + u64 si, di, bp, sp;
> + u64 r8, r9, r10, r11;
> + u64 r12, r13, r14, r15;
> + u64 status, dla, dse, lat;
> + u64 real_ip, tsx_tuning;
> + u64 tsc;
> +};
> @@ -958,6 +971,13 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
> data.txn = intel_hsw_transaction(pebs);
> }
>
> + /*
> + * v3 supplies an accurate time stamp, so we use that
> + * for the time stamp.
> + */
> + if (x86_pmu.intel_cap.pebs_format >= 3)
> + data.time = native_sched_clock_from_tsc(pebs->tsc);
That's wrong. It does not respect perf_event_attr::clock_id.
next prev parent reply other threads:[~2015-05-08 11:00 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-07 22:56 perf: Add basic Skylake PMU support Andi Kleen
2015-05-07 22:56 ` [PATCH 1/9] x86: Add a native_perf_sched_clock_from_tsc Andi Kleen
2015-05-07 22:56 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen
2015-05-08 10:59 ` Peter Zijlstra [this message]
2015-05-08 11:59 ` Andi Kleen
2015-05-08 12:06 ` Peter Zijlstra
2015-05-07 22:56 ` [PATCH 3/9] x86: Add new MSRs and MSR bits used for Skylake perfmon Andi Kleen
2015-05-07 22:56 ` [PATCH 4/9] perf: Add cycles to branch_info Andi Kleen
2015-05-07 22:56 ` [PATCH 5/9] x86, perf: Add support for LBRv5 Andi Kleen
2015-05-07 22:56 ` [PATCH 6/9] x86, perf: Add Skylake support Andi Kleen
2015-05-07 22:56 ` [PATCH 7/9] perf, x86: Handle new status bits Andi Kleen
2015-05-07 22:56 ` [PATCH 8/9] perf, x86: Optimize v4 LBR unfreezing Andi Kleen
2015-05-08 11:19 ` Peter Zijlstra
2015-05-07 22:56 ` [PATCH 9/9] perf, tools: Add tools support for cycles, weight branch_info field Andi Kleen
-- strict thread matches above, loose matches on Subject: below --
2015-05-10 19:22 perf: Add basic Skylake PMU support v2 Andi Kleen
2015-05-10 19:22 ` [PATCH 2/9] x86, perf: Add support for PEBSv3 profiling Andi Kleen
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