From: Like Xu <like.xu@linux.intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Peter Zijlstra <peterz@infradead.org>,
kvm@vger.kernel.org, Andi Kleen <ak@linux.intel.com>,
Jim Mattson <jmattson@google.com>,
Wanpeng Li <wanpengli@tencent.com>
Cc: Sean Christopherson <sean.j.christopherson@intel.com>,
Joerg Roedel <joro@8bytes.org>,
Liran Alon <liran.alon@oracle.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Liang Kan <kan.liang@linux.intel.com>,
Wei Wang <wei.w.wang@intel.com>,
Like Xu <like.xu@linux.intel.com>,
linux-kernel@vger.kernel.org, Ingo Molnar <mingo@kernel.org>
Subject: [PATCH v9 01/10] perf/x86: Fix msr variable type for the LBR msrs
Date: Fri, 13 Mar 2020 10:16:07 +0800 [thread overview]
Message-ID: <20200313021616.112322-2-like.xu@linux.intel.com> (raw)
In-Reply-To: <20200313021616.112322-1-like.xu@linux.intel.com>
From: Wei Wang <wei.w.wang@intel.com>
The MSR variable type can be 'unsigned int', which uses less memory than
the longer 'unsigned long'. Fix struct x86_pmu for that. the lbr_nr won't
be a negative number, so make it 'unsigned int' as well.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Suggested-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
---
arch/x86/events/perf_event.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index f1cd1ca1a77b..1025bc6eb04f 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -672,8 +672,8 @@ struct x86_pmu {
/*
* Intel LBR
*/
- unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
- int lbr_nr; /* hardware stack size */
+ unsigned int lbr_tos, lbr_from, lbr_to,
+ lbr_nr; /* LBR base regs and size */
u64 lbr_sel_mask; /* LBR_SELECT valid bits */
const int *lbr_sel_map; /* lbr_select mappings */
bool lbr_double_abort; /* duplicated lbr aborts */
--
2.21.1
next prev parent reply other threads:[~2020-03-13 2:18 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-13 2:16 [PATCH v9 00/10] Guest Last Branch Recording Enabling Like Xu
2020-03-13 2:16 ` Like Xu [this message]
2020-03-13 2:16 ` [PATCH v9 02/10] perf/x86/lbr: Add interface to get basic information about LBR stack Like Xu
2020-03-13 2:16 ` [PATCH v9 03/10] perf/x86: Add constraint to create guest LBR event without hw counter Like Xu
2020-04-09 16:37 ` Peter Zijlstra
2020-04-10 3:03 ` Xu, Like
2020-04-17 8:40 ` Xu, Like
2020-04-17 10:30 ` Peter Zijlstra
2020-03-13 2:16 ` [PATCH v9 04/10] perf/x86: Keep LBR stack unchanged on the host for guest LBR event Like Xu
2020-04-09 16:45 ` Peter Zijlstra
2020-04-10 3:10 ` Xu, Like
2020-03-13 2:16 ` [PATCH v9 05/10] KVM: x86: Add KVM_CAP_X86_GUEST_LBR interface to dis/enable LBR feature Like Xu
2020-03-13 2:16 ` [PATCH v9 06/10] KVM: x86/pmu: Tweak kvm_pmu_get_msr to pass 'struct msr_data' in Like Xu
2020-03-13 2:16 ` [PATCH v9 07/10] KVM: x86/pmu: Add LBR feature emulation via guest LBR event Like Xu
2020-03-13 2:16 ` [PATCH v9 08/10] KVM: x86/pmu: Release guest LBR event via vPMU lazy release mechanism Like Xu
2020-03-13 2:16 ` [PATCH v9 09/10] KVM: x86: Expose MSR_IA32_PERF_CAPABILITIES to guest for LBR record format Like Xu
2020-03-13 2:16 ` [PATCH v9 10/10] KVM: x86: Remove the common trap handler of the MSR_IA32_DEBUGCTLMSR Like Xu
2020-03-20 8:45 ` [PATCH v9 00/10] Guest Last Branch Recording Enabling Xu, Like
2020-04-02 12:59 ` Xu, Like
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