[PATCH] memory: tegra: Correct num_tlb_lines for tegra210

[PATCH] memory: tegra: Correct num_tlb_lines for tegra210

[Nicolin Chen]

According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES
field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines
should be 48 (0x30) rather than 32 (0x20).

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
---
 drivers/memory/tegra/tegra210.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index 51b537cfa5a7..4fbf8cbc6666 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -1074,7 +1074,7 @@ static const struct tegra_smmu_soc tegra210_smmu_soc = {
 	.num_groups = ARRAY_SIZE(tegra210_groups),
 	.supports_round_robin_arbitration = true,
 	.supports_request_limit = true,
-	.num_tlb_lines = 32,
+	.num_tlb_lines = 48,
 	.num_asids = 128,
 };
 
-- 
2.17.1

Re: [PATCH] memory: tegra: Correct num_tlb_lines for tegra210

[Thierry Reding]

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On Tue, Sep 15, 2020 at 04:28:03PM -0700, Nicolin Chen wrote:
> According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES
> field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines
> should be 48 (0x30) rather than 32 (0x20).
> 
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
>  drivers/memory/tegra/tegra210.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Please send this as part of a series including:

    https://patchwork.ozlabs.org/project/linux-tegra/patch/20200916002359.10823-1-nicoleotsuka@gmail.com/

Adding Joerg for visibility. From the Tegra side:

Acked-by: Thierry Reding <treding@nvidia.com>

> diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> index 51b537cfa5a7..4fbf8cbc6666 100644
> --- a/drivers/memory/tegra/tegra210.c
> +++ b/drivers/memory/tegra/tegra210.c
> @@ -1074,7 +1074,7 @@ static const struct tegra_smmu_soc tegra210_smmu_soc = {
>  	.num_groups = ARRAY_SIZE(tegra210_groups),
>  	.supports_round_robin_arbitration = true,
>  	.supports_request_limit = true,
> -	.num_tlb_lines = 32,
> +	.num_tlb_lines = 48,
>  	.num_asids = 128,
>  };
>  
> -- 
> 2.17.1
> 

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Re: [PATCH] memory: tegra: Correct num_tlb_lines for tegra210

[Krzysztof Kozlowski]

On Thu, 17 Sep 2020 at 12:43, Thierry Reding <thierry.reding@gmail.com> wrote:
>
> On Tue, Sep 15, 2020 at 04:28:03PM -0700, Nicolin Chen wrote:
> > According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES
> > field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines
> > should be 48 (0x30) rather than 32 (0x20).
> >
> > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > ---
> >  drivers/memory/tegra/tegra210.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Please send this as part of a series including:
>
>     https://patchwork.ozlabs.org/project/linux-tegra/patch/20200916002359.10823-1-nicoleotsuka@gmail.com/
>
> Adding Joerg for visibility. From the Tegra side:
>
> Acked-by: Thierry Reding <treding@nvidia.com>

So basically applying this one alone breaks existing platforms and
makes history non-bisectable...

Nicolin, the bisectability is important requirement so you must always
mention the dependencies between patches.

Best regards,
Krzysztof

Re: [PATCH] memory: tegra: Correct num_tlb_lines for tegra210

[Nicolin Chen]

On Thu, Sep 17, 2020 at 12:54:42PM +0200, Krzysztof Kozlowski wrote:
> On Thu, 17 Sep 2020 at 12:43, Thierry Reding <thierry.reding@gmail.com> wrote:
> >
> > On Tue, Sep 15, 2020 at 04:28:03PM -0700, Nicolin Chen wrote:
> > > According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES
> > > field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines
> > > should be 48 (0x30) rather than 32 (0x20).
> > >
> > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > > ---
> > >  drivers/memory/tegra/tegra210.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > Please send this as part of a series including:
> >
> >     https://patchwork.ozlabs.org/project/linux-tegra/patch/20200916002359.10823-1-nicoleotsuka@gmail.com/
> >
> > Adding Joerg for visibility. From the Tegra side:
> >
> > Acked-by: Thierry Reding <treding@nvidia.com>
> 
> So basically applying this one alone breaks existing platforms and
> makes history non-bisectable...
>
> Nicolin, the bisectability is important requirement so you must always
> mention the dependencies between patches.

Sorry. Will be careful next time.

And I am resending both in a series.

Thanks
Nic