[GIT PULL] irqchip fixes for 5.16, take #2

[GIT PULL] irqchip fixes for 5.16, take #2

[Marc Zyngier]

Thomas,

Here's another set of irqchip fixes for 5.16. The main ones are the
MSI allocation fixes for an old Marvell system, another for the Aspeed
SCU driver acking interrupts the wrong way, and one for the ARM NVIC
having the wrong offset of one of the registers.

Please pull,

	M.

The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:

  Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-fixes-5.16-2

for you to fetch changes up to c5e0cbe2858d278a27d5b3fe31890aea5be064c4:

  irqchip: nvic: Fix offset for Interrupt Priority Offsets (2021-12-02 09:27:06 +0000)

----------------------------------------------------------------
irqchip fixes for Linux 5.16, take #2

- Fix Armada-370-XP Multi-MSi allocation to be aligned on the allocation
  size, as required by the PCI spec

- Fix aspeed-scu interrupt acknowledgement by directly writing to the
  register instead of a read-modify-write sequence

- Use standard bitfirl helpers in the MIPS GIC driver instead of custom
  constructs

- Fix the NVIC driver IPR register offset

----------------------------------------------------------------
Billy Tsai (1):
      irqchip/aspeed-scu: Replace update_bits with write_bits.

Geert Uytterhoeven (1):
      irqchip/mips-gic: Use bitfield helpers

Pali Rohár (2):
      irqchip/armada-370-xp: Fix return value of armada_370_xp_msi_alloc()
      irqchip/armada-370-xp: Fix support for Multi-MSI interrupts

Vladimir Murzin (1):
      irqchip: nvic: Fix offset for Interrupt Priority Offsets

 drivers/irqchip/irq-armada-370-xp.c | 16 ++++++----------
 drivers/irqchip/irq-aspeed-scu-ic.c |  4 ++--
 drivers/irqchip/irq-mips-gic.c      |  4 ++--
 drivers/irqchip/irq-nvic.c          |  2 +-
 4 files changed, 11 insertions(+), 15 deletions(-)

[GIT PULL] irqchip fixes for 5.16, take #2

[Marc Zyngier]

Hi Thomas,

Here's another set of irqchip fixes for 5.16. The main ones are the
MSI allocation fixes for an old Marvell system, another for the Aspeed
SCU driver acking interrupts the wrong way, and one for the ARM NVIC
having the wrong offset of one of the registers.

We also gained a fix for the GICv3 ITS INVALL command, as well as some
more tidying up (bcm7180-l2, Apple AIC).

Please pull,

	M.

The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:

  Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-fixes-5.16-2

for you to fetch changes up to c3fbab7767c53397d7b849799474f5a27cf306e6:

  irqchip/irq-bcm7120-l2: Add put_device() after of_find_device_by_node() (2021-12-10 13:23:13 +0000)

----------------------------------------------------------------
irqchip fixes for Linux 5.16, take #2

- Fix Armada-370-XP Multi-MSi allocation to be aligned on the allocation
  size, as required by the PCI spec

- Fix aspeed-scu interrupt acknowledgement by directly writing to the
  register instead of a read-modify-write sequence

- Use standard bitfirl helpers in the MIPS GIC driver instead of custom
  constructs

- Fix the NVIC driver IPR register offset

- Correctly drop the reference of the device node in the irq-bcm7120-l2
  driver

- Fix the GICv3 ITS INVALL command by issueing a following SYNC command

- Add a missing __init attribute to the init function of the Apple AIC
  driver

----------------------------------------------------------------
Billy Tsai (1):
      irqchip/aspeed-scu: Replace update_bits with write_bits.

Donghyeok Kim (1):
      irqchip/apple-aic: Mark aic_init_smp() as __init

Geert Uytterhoeven (1):
      irqchip/mips-gic: Use bitfield helpers

Pali Rohár (2):
      irqchip/armada-370-xp: Fix return value of armada_370_xp_msi_alloc()
      irqchip/armada-370-xp: Fix support for Multi-MSI interrupts

Vladimir Murzin (1):
      irqchip: nvic: Fix offset for Interrupt Priority Offsets

Wudi Wang (1):
      irqchip/irq-gic-v3-its.c: Force synchronisation when issuing INVALL

Ye Guojin (1):
      irqchip/irq-bcm7120-l2: Add put_device() after of_find_device_by_node()

 drivers/irqchip/irq-apple-aic.c     |  2 +-
 drivers/irqchip/irq-armada-370-xp.c | 16 ++++++----------
 drivers/irqchip/irq-aspeed-scu-ic.c |  4 ++--
 drivers/irqchip/irq-bcm7120-l2.c    |  1 +
 drivers/irqchip/irq-gic-v3-its.c    |  2 +-
 drivers/irqchip/irq-mips-gic.c      |  4 ++--
 drivers/irqchip/irq-nvic.c          |  2 +-
 7 files changed, 14 insertions(+), 17 deletions(-)

[tip: irq/urgent] Merge tag 'irqchip-fixes-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

[tip-bot2 for Thomas Gleixner]

The following commit has been merged into the irq/urgent branch of tip:

Commit-ID:     b7fd35a0ad976ee8e7d4914e063410686b5fa353
Gitweb:        https://git.kernel.org/tip/b7fd35a0ad976ee8e7d4914e063410686b5fa353
Author:        Thomas Gleixner <tglx@linutronix.de>
AuthorDate:    Sat, 11 Dec 2021 10:51:23 +01:00
Committer:     Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Sat, 11 Dec 2021 10:51:23 +01:00

Merge tag 'irqchip-fixes-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip fixes from Marc Zyngier:

 - Fix Armada-370-XP Multi-MSi allocation to be aligned on the allocation
   size, as required by the PCI spec

 - Fix aspeed-scu interrupt acknowledgement by directly writing to the
   register instead of a read-modify-write sequence

 - Use standard bitfirl helpers in the MIPS GIC driver instead of custom
   constructs

 - Fix the NVIC driver IPR register offset

 - Correctly drop the reference of the device node in the irq-bcm7120-l2
   driver

 - Fix the GICv3 ITS INVALL command by issueing a following SYNC command

 - Add a missing __init attribute to the init function of the Apple AIC
   driver

Link: https://lore.kernel.org/r/20211210133516.664497-1-maz@kernel.org
---