From: Robert Foss <robert.foss@linaro.org>
To: andrzej.hajda@intel.com, narmstrong@baylibre.com,
robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@linux.ie,
daniel@ffwll.ch, dianders@chromium.org,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Chris Morgan <macromorgan@hotmail.com>,
devicetree@vger.kernel.org
Subject: [PATCH v2 2/2] Revert "drm/bridge: chrontel-ch7033: Add byteswap order setting"
Date: Mon, 19 Sep 2022 12:20:09 +0200 [thread overview]
Message-ID: <20220919102009.150503-3-robert.foss@linaro.org> (raw)
In-Reply-To: <20220919102009.150503-1-robert.foss@linaro.org>
Revert this patch since it depends on devicetree functionality that
previously has been reverted in the below commit.
commit e798ba3374a1 ("Revert "dt-bindings: Add byteswap order to chrontel ch7033"")
This reverts commit ce9564cfc9aea65e68eb343c599317633bc2321a.
Fixes: 8c9c40ec8344 ("Revert "drm/bridge: ti-sn65dsi86: Implement bridge connector operations for DP"")
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c
index c5719908ce2d..ba060277c3fd 100644
--- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -68,7 +68,6 @@ enum {
BYTE_SWAP_GBR = 3,
BYTE_SWAP_BRG = 4,
BYTE_SWAP_BGR = 5,
- BYTE_SWAP_MAX = 6,
};
/* Page 0, Register 0x19 */
@@ -356,8 +355,6 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
int hsynclen = mode->hsync_end - mode->hsync_start;
int vbporch = mode->vsync_start - mode->vdisplay;
int vsynclen = mode->vsync_end - mode->vsync_start;
- u8 byte_swap;
- int ret;
/*
* Page 4
@@ -401,16 +398,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
regmap_write(priv->regmap, 0x15, vbporch);
regmap_write(priv->regmap, 0x16, vsynclen);
- /* Input color swap. Byte order is optional and will default to
- * BYTE_SWAP_BGR to preserve backwards compatibility with existing
- * driver.
- */
- ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap",
- &byte_swap);
- if (!ret && byte_swap < BYTE_SWAP_MAX)
- regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap);
- else
- regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
+ /* Input color swap. */
+ regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
/* Input clock and sync polarity. */
regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
--
2.34.1
next prev parent reply other threads:[~2022-09-19 10:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-19 10:20 [PATCH v2 0/2] Fix chrontel-ch7033 reversion Robert Foss
2022-09-19 10:20 ` [PATCH v2 1/2] Revert "Revert "drm/bridge: ti-sn65dsi86: Implement bridge connector operations for DP"" Robert Foss
2022-09-19 10:43 ` Laurent Pinchart
2022-09-19 10:20 ` Robert Foss [this message]
2022-09-19 10:47 ` [PATCH v2 2/2] Revert "drm/bridge: chrontel-ch7033: Add byteswap order setting" Laurent Pinchart
2022-09-19 13:18 ` Robert Foss
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