From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Gregory Price <gourry@gourry.net>,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>,
Robert Richter <rrichter@amd.com>
Subject: [PATCH v2 01/15] cxl: Modify address translation callback for generic use
Date: Tue, 18 Feb 2025 14:23:42 +0100 [thread overview]
Message-ID: <20250218132356.1809075-2-rrichter@amd.com> (raw)
In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com>
The root decoder address translation callback could be reused for
other decoders too. For generic use of the callback, change the
function interface to use a decoder argument instead of the root
decoder.
Note that a root decoder's HPA is equal to its SPA, but else it may be
different. Thus, change the name of the function type to
cxl_to_hpa_fn.
Signed-off-by: Robert Richter <rrichter@amd.com>
---
drivers/cxl/acpi.c | 4 ++--
drivers/cxl/core/region.c | 7 +++++--
drivers/cxl/cxl.h | 5 ++---
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index 93c73b163c28..48ad90025d77 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -22,9 +22,9 @@ static const guid_t acpi_cxl_qtg_id_guid =
GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
-
-static u64 cxl_xor_hpa_to_spa(struct cxl_root_decoder *cxlrd, u64 hpa)
+static u64 cxl_xor_hpa_to_spa(struct cxl_decoder *cxld, u64 hpa)
{
+ struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(&cxld->dev);
struct cxl_cxims_data *cximsd = cxlrd->platform_data;
int hbiw = cxlrd->cxlsd.nr_targets;
u64 val;
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index a56b84e7103a..c118bda93e86 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -2936,9 +2936,12 @@ u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
/* Apply the hpa_offset to the region base address */
hpa = hpa_offset + p->res->start;
- /* Root decoder translation overrides typical modulo decode */
+ /*
+ * Root decoder translation overrides typical modulo decode.
+ * Note that a root decoder's HPA is equal to its SPA.
+ */
if (cxlrd->hpa_to_spa)
- hpa = cxlrd->hpa_to_spa(cxlrd, hpa);
+ hpa = cxlrd->hpa_to_spa(&cxlrd->cxlsd.cxld, hpa);
if (hpa < p->res->start || hpa > p->res->end) {
dev_dbg(&cxlr->dev,
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 50e7d878bb6f..b19ba47242c6 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -418,8 +418,7 @@ struct cxl_switch_decoder {
struct cxl_dport *target[];
};
-struct cxl_root_decoder;
-typedef u64 (*cxl_hpa_to_spa_fn)(struct cxl_root_decoder *cxlrd, u64 hpa);
+typedef u64 (*cxl_to_hpa_fn)(struct cxl_decoder *cxld, u64 hpa);
/**
* struct cxl_root_decoder - Static platform CXL address decoder
@@ -434,7 +433,7 @@ typedef u64 (*cxl_hpa_to_spa_fn)(struct cxl_root_decoder *cxlrd, u64 hpa);
struct cxl_root_decoder {
struct resource *res;
atomic_t region_id;
- cxl_hpa_to_spa_fn hpa_to_spa;
+ cxl_to_hpa_fn hpa_to_spa;
void *platform_data;
struct mutex range_lock;
int qos_class;
--
2.39.5
next prev parent reply other threads:[~2025-02-18 13:24 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 13:23 [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Robert Richter
2025-02-18 13:23 ` Robert Richter [this message]
2025-02-20 16:00 ` [PATCH v2 01/15] cxl: Modify address translation callback for generic use Gregory Price
2025-02-20 21:03 ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 02/15] cxl: Introduce callback to translate an HPA range from a port to its parent Robert Richter
2025-02-20 21:19 ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 03/15] cxl/region: Factor out code for interleaving calculations Robert Richter
2025-02-20 16:28 ` Gregory Price
2025-02-20 16:41 ` Gregory Price
2025-03-14 12:45 ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 04/15] cxl/region: Calculate endpoint's region position during init Robert Richter
2025-02-19 23:32 ` Gregory Price
2025-02-20 17:31 ` Gregory Price
2025-02-20 21:56 ` Dave Jiang
2025-04-04 4:38 ` Gregory Price
2025-04-04 15:36 ` [PATCH] cxl/region: Continue recalculating position during sort Gregory Price
2025-04-04 17:22 ` Gregory Price
2025-04-05 2:35 ` [PATCH] cxl region: recalculate interleave pos during region probe Gregory Price
2025-04-08 15:30 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 05/15] cxl/region: Calculate and store the SPA range of an endpoint Robert Richter
2025-02-20 18:42 ` Gregory Price
2025-02-20 22:31 ` Dave Jiang
2025-02-20 22:37 ` Gregory Price
2025-03-14 12:41 ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 06/15] cxl/region: Use endpoint's HPA range to find the port's decoder Robert Richter
2025-04-24 0:28 ` Gregory Price
2025-04-24 21:49 ` Gregory Price
2025-04-24 23:46 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 07/15] cxl/region: Use translated HPA ranges " Robert Richter
2025-02-20 19:13 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 08/15] cxl/region: Use the endpoint's SPA range to find a region Robert Richter
2025-02-20 19:28 ` Gregory Price
2025-03-14 12:45 ` Jonathan Cameron
2025-04-08 15:45 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 09/15] cxl/region: Use the endpoint's SPA range to create " Robert Richter
2025-02-20 19:31 ` Gregory Price
2025-03-14 12:46 ` Jonathan Cameron
2025-04-08 15:50 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters " Robert Richter
2025-02-20 19:43 ` Gregory Price
2025-03-14 12:49 ` Jonathan Cameron
2025-04-01 1:59 ` Gregory Price
2025-04-01 5:26 ` Gregory Price
2025-04-01 18:03 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 11/15] cxl/region: Use the endpoint's SPA range to check " Robert Richter
2025-02-20 19:50 ` Gregory Price
2025-04-08 15:54 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 12/15] cxl/region: Lock decoders that need address translation Robert Richter
2025-02-20 19:57 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 13/15] cxl/x86: Prepare for architectural platform setup Robert Richter
2025-02-20 19:57 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 14/15] cxl/amd: Enable Zen5 address translation using ACPI PRMT Robert Richter
2025-02-21 0:40 ` Dave Jiang
2025-03-14 13:01 ` Jonathan Cameron
2025-04-05 2:38 ` [PATCH] [HACK] drop zen5_init checks due to segfault Gregory Price
2025-05-13 21:10 ` Robert Richter
2025-06-17 20:33 ` Joshua Hahn
2025-06-24 5:43 ` Robert Richter
2025-06-24 21:46 ` Joshua Hahn
2025-02-18 13:23 ` [PATCH v2 15/15] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Robert Richter
2025-02-20 1:00 ` [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Gregory Price
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