From: Gregory Price <gourry@gourry.net>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters to create a region
Date: Thu, 20 Feb 2025 14:43:15 -0500 [thread overview]
Message-ID: <Z7eF04PLfr5rhiLT@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <20250218132356.1809075-11-rrichter@amd.com>
On Tue, Feb 18, 2025 at 02:23:51PM +0100, Robert Richter wrote:
... snip ...
> static int find_pos_and_ways(struct cxl_port *port, struct range *range,
> - int *pos, int *ways)
> + int *pos, int *ways, int *granularity)
Function name starting to diverge from functionality
find_interleave_config() ?
~Gregory
next prev parent reply other threads:[~2025-02-20 19:43 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 13:23 [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Robert Richter
2025-02-18 13:23 ` [PATCH v2 01/15] cxl: Modify address translation callback for generic use Robert Richter
2025-02-20 16:00 ` Gregory Price
2025-02-20 21:03 ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 02/15] cxl: Introduce callback to translate an HPA range from a port to its parent Robert Richter
2025-02-20 21:19 ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 03/15] cxl/region: Factor out code for interleaving calculations Robert Richter
2025-02-20 16:28 ` Gregory Price
2025-02-20 16:41 ` Gregory Price
2025-03-14 12:45 ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 04/15] cxl/region: Calculate endpoint's region position during init Robert Richter
2025-02-19 23:32 ` Gregory Price
2025-02-20 17:31 ` Gregory Price
2025-02-20 21:56 ` Dave Jiang
2025-04-04 4:38 ` Gregory Price
2025-04-04 15:36 ` [PATCH] cxl/region: Continue recalculating position during sort Gregory Price
2025-04-04 17:22 ` Gregory Price
2025-04-05 2:35 ` [PATCH] cxl region: recalculate interleave pos during region probe Gregory Price
2025-04-08 15:30 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 05/15] cxl/region: Calculate and store the SPA range of an endpoint Robert Richter
2025-02-20 18:42 ` Gregory Price
2025-02-20 22:31 ` Dave Jiang
2025-02-20 22:37 ` Gregory Price
2025-03-14 12:41 ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 06/15] cxl/region: Use endpoint's HPA range to find the port's decoder Robert Richter
2025-04-24 0:28 ` Gregory Price
2025-04-24 21:49 ` Gregory Price
2025-04-24 23:46 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 07/15] cxl/region: Use translated HPA ranges " Robert Richter
2025-02-20 19:13 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 08/15] cxl/region: Use the endpoint's SPA range to find a region Robert Richter
2025-02-20 19:28 ` Gregory Price
2025-03-14 12:45 ` Jonathan Cameron
2025-04-08 15:45 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 09/15] cxl/region: Use the endpoint's SPA range to create " Robert Richter
2025-02-20 19:31 ` Gregory Price
2025-03-14 12:46 ` Jonathan Cameron
2025-04-08 15:50 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters " Robert Richter
2025-02-20 19:43 ` Gregory Price [this message]
2025-03-14 12:49 ` Jonathan Cameron
2025-04-01 1:59 ` Gregory Price
2025-04-01 5:26 ` Gregory Price
2025-04-01 18:03 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 11/15] cxl/region: Use the endpoint's SPA range to check " Robert Richter
2025-02-20 19:50 ` Gregory Price
2025-04-08 15:54 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 12/15] cxl/region: Lock decoders that need address translation Robert Richter
2025-02-20 19:57 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 13/15] cxl/x86: Prepare for architectural platform setup Robert Richter
2025-02-20 19:57 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 14/15] cxl/amd: Enable Zen5 address translation using ACPI PRMT Robert Richter
2025-02-21 0:40 ` Dave Jiang
2025-03-14 13:01 ` Jonathan Cameron
2025-04-05 2:38 ` [PATCH] [HACK] drop zen5_init checks due to segfault Gregory Price
2025-05-13 21:10 ` Robert Richter
2025-06-17 20:33 ` Joshua Hahn
2025-06-24 5:43 ` Robert Richter
2025-06-24 21:46 ` Joshua Hahn
2025-02-18 13:23 ` [PATCH v2 15/15] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Robert Richter
2025-02-20 1:00 ` [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Gregory Price
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