From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Gregory Price <gourry@gourry.net>,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters to create a region
Date: Fri, 14 Mar 2025 12:49:47 +0000 [thread overview]
Message-ID: <20250314124947.00001d93@huawei.com> (raw)
In-Reply-To: <20250218132356.1809075-11-rrichter@amd.com>
On Tue, 18 Feb 2025 14:23:51 +0100
Robert Richter <rrichter@amd.com> wrote:
> Endpoints requiring address translation might not be aware of the
> system's interleaving configuration. Instead, interleaving can be
> configured on an upper memory domain (from an endpoint view) and thus
> is not visible to the endpoint. For region creation this might cause
> an invalid interleaving config that does not match the CFMWS entries.
>
> Use the interleaving configuration of the root decoders to create a
> region which bases on CFMWS entries. This always matches the system's
> interleaving configuration and is independent of the underlying memory
> topology.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> ---
> drivers/cxl/core/region.c | 39 ++++++++++++++++++++++++++++++++++-----
> drivers/cxl/cxl.h | 2 ++
> 2 files changed, 36 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 6e0434eee6df..3afcc9ca06ae 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1749,6 +1749,15 @@ static int cxl_region_validate_position(struct cxl_region *cxlr,
> }
> }
>
> + if (p->interleave_ways != cxled->interleave_ways ||
> + p->interleave_granularity != cxled->interleave_granularity ) {
> + dev_dbg(&cxlr->dev, "interleaving config mismatch with %s: ways: %d:%d granularity: %d:%d\n",
> + dev_name(&cxled->cxld.dev), p->interleave_ways,
> + cxled->interleave_ways, p->interleave_granularity,
> + cxled->interleave_granularity);
> + return -ENXIO;
> + }
> +
> return 0;
> }
>
> @@ -1852,7 +1861,7 @@ static int match_switch_decoder_by_range(struct device *dev,
> }
>
> static int find_pos_and_ways(struct cxl_port *port, struct range *range,
> - int *pos, int *ways)
> + int *pos, int *ways, int *granularity)
> {
> struct cxl_switch_decoder *cxlsd;
> struct cxl_port *parent;
> @@ -1873,6 +1882,7 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range,
> }
> cxlsd = to_cxl_switch_decoder(dev);
> *ways = cxlsd->cxld.interleave_ways;
> + *granularity = cxlsd->cxld.interleave_granularity;
>
> for (int i = 0; i < *ways; i++) {
> if (cxlsd->target[i] == port->parent_dport) {
> @@ -1896,6 +1906,8 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range,
> struct cxl_interleave_context {
> struct range *hpa_range;
> int pos;
> + int interleave_ways;
> + int interleave_granularity;
Ah. And here is our context expansion
> };
>
> /**
> @@ -1914,13 +1926,17 @@ struct cxl_interleave_context {
> * the topology from the endpoint to the root decoder and iteratively
> * applying the function for each port.
> *
> + * Calculation of interleaving ways:
> + *
> + * interleave_ways = interleave_ways * parent_ways;
> + *
> * Return: position >= 0 on success
> * -ENXIO on failure
> */
> static int cxl_port_calc_interleave(struct cxl_port *port,
> struct cxl_interleave_context *ctx)
> {
> - int parent_ways = 0, parent_pos = 0;
> + int parent_ways = 0, parent_pos = 0, parent_granularity = 0;
> int rc;
>
> /*
> @@ -1955,12 +1971,23 @@ static int cxl_port_calc_interleave(struct cxl_port *port,
> if (is_cxl_root(port))
> return 0;
>
> - rc = find_pos_and_ways(port, ctx->hpa_range, &parent_pos, &parent_ways);
> + rc = find_pos_and_ways(port, ctx->hpa_range, &parent_pos, &parent_ways,
> + &parent_granularity);
> if (rc)
> return rc;
>
> ctx->pos = ctx->pos * parent_ways + parent_pos;
>
> + if (ctx->interleave_ways)
> + ctx->interleave_ways *= parent_ways;
> + else
> + ctx->interleave_ways = parent_ways;
> +
> + if (ctx->interleave_granularity)
> + ctx->interleave_granularity *= ctx->interleave_ways;
> + else
> + ctx->interleave_granularity = parent_granularity;
> +
> return ctx->pos;
I think Gregory called this out in earlier patch. Mixing and matching
between returning pos and use of ctx makes things hard to read. If
we need to have it in context, then make this return 0 or -ERR instead.
> }
next prev parent reply other threads:[~2025-03-14 12:49 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 13:23 [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Robert Richter
2025-02-18 13:23 ` [PATCH v2 01/15] cxl: Modify address translation callback for generic use Robert Richter
2025-02-20 16:00 ` Gregory Price
2025-02-20 21:03 ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 02/15] cxl: Introduce callback to translate an HPA range from a port to its parent Robert Richter
2025-02-20 21:19 ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 03/15] cxl/region: Factor out code for interleaving calculations Robert Richter
2025-02-20 16:28 ` Gregory Price
2025-02-20 16:41 ` Gregory Price
2025-03-14 12:45 ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 04/15] cxl/region: Calculate endpoint's region position during init Robert Richter
2025-02-19 23:32 ` Gregory Price
2025-02-20 17:31 ` Gregory Price
2025-02-20 21:56 ` Dave Jiang
2025-04-04 4:38 ` Gregory Price
2025-04-04 15:36 ` [PATCH] cxl/region: Continue recalculating position during sort Gregory Price
2025-04-04 17:22 ` Gregory Price
2025-04-05 2:35 ` [PATCH] cxl region: recalculate interleave pos during region probe Gregory Price
2025-04-08 15:30 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 05/15] cxl/region: Calculate and store the SPA range of an endpoint Robert Richter
2025-02-20 18:42 ` Gregory Price
2025-02-20 22:31 ` Dave Jiang
2025-02-20 22:37 ` Gregory Price
2025-03-14 12:41 ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 06/15] cxl/region: Use endpoint's HPA range to find the port's decoder Robert Richter
2025-04-24 0:28 ` Gregory Price
2025-04-24 21:49 ` Gregory Price
2025-04-24 23:46 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 07/15] cxl/region: Use translated HPA ranges " Robert Richter
2025-02-20 19:13 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 08/15] cxl/region: Use the endpoint's SPA range to find a region Robert Richter
2025-02-20 19:28 ` Gregory Price
2025-03-14 12:45 ` Jonathan Cameron
2025-04-08 15:45 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 09/15] cxl/region: Use the endpoint's SPA range to create " Robert Richter
2025-02-20 19:31 ` Gregory Price
2025-03-14 12:46 ` Jonathan Cameron
2025-04-08 15:50 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters " Robert Richter
2025-02-20 19:43 ` Gregory Price
2025-03-14 12:49 ` Jonathan Cameron [this message]
2025-04-01 1:59 ` Gregory Price
2025-04-01 5:26 ` Gregory Price
2025-04-01 18:03 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 11/15] cxl/region: Use the endpoint's SPA range to check " Robert Richter
2025-02-20 19:50 ` Gregory Price
2025-04-08 15:54 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 12/15] cxl/region: Lock decoders that need address translation Robert Richter
2025-02-20 19:57 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 13/15] cxl/x86: Prepare for architectural platform setup Robert Richter
2025-02-20 19:57 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 14/15] cxl/amd: Enable Zen5 address translation using ACPI PRMT Robert Richter
2025-02-21 0:40 ` Dave Jiang
2025-03-14 13:01 ` Jonathan Cameron
2025-04-05 2:38 ` [PATCH] [HACK] drop zen5_init checks due to segfault Gregory Price
2025-05-13 21:10 ` Robert Richter
2025-06-17 20:33 ` Joshua Hahn
2025-06-24 5:43 ` Robert Richter
2025-06-24 21:46 ` Joshua Hahn
2025-02-18 13:23 ` [PATCH v2 15/15] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Robert Richter
2025-02-20 1:00 ` [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Gregory Price
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