From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Gregory Price <gourry@gourry.net>,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>,
Joshua Hahn <joshua.hahnjy@gmail.com>,
<alejandro.lucero-palau@amd.com>
Subject: Re: [PATCH v4 01/14] cxl/region: Store root decoder in struct cxl_region
Date: Tue, 11 Nov 2025 14:45:41 +0000 [thread overview]
Message-ID: <20251111144541.0000714d@huawei.com> (raw)
In-Reply-To: <20251103184804.509762-2-rrichter@amd.com>
On Mon, 3 Nov 2025 19:47:42 +0100
Robert Richter <rrichter@amd.com> wrote:
> A region is always bound to a root decoder. The region's associated
> root decoder is often needed. Add it to struct cxl_region.
>
> This simplifies the code by removing dynamic lookups and the root
> decoder argument from the function argument list where possible.
>
> Patch is a prerequisite to implement address translation which uses
> struct cxl_region to store all relevant region and interleaving
> parameters. It changes the argument list of __construct_region() in
> preparation of adding a context argument. Additionally the arg list of
> cxl_region_attach_position() is simplified and the use of
> to_cxl_root_decoder() removed, which always reconstructs and checks
> the pointer. The pointer never changes and is frequently used. Code
> becomes more readable as this amphazises the binding between both
> objects.
>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Signed-off-by: Robert Richter <rrichter@amd.com>
Just a note to say this will (maybe just context) clash with Alejandro's rework
around construct_region_begin()
https://lore.kernel.org/all/20251110153657.2706192-19-alejandro.lucero-palau@amd.com/
Probably easy to resolve, but worth both of you being aware if you hadn't noticed
already!
Jonathan
> ---
> drivers/cxl/core/region.c | 37 +++++++++++++++++++------------------
> drivers/cxl/cxl.h | 2 ++
> 2 files changed, 21 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index b06fee1978ba..45b1386a18d7 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -495,9 +495,9 @@ static ssize_t interleave_ways_store(struct device *dev,
> struct device_attribute *attr,
> const char *buf, size_t len)
> {
> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev->parent);
> - struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
> struct cxl_region *cxlr = to_cxl_region(dev);
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> + struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
> struct cxl_region_params *p = &cxlr->params;
> unsigned int val, save;
> int rc;
> @@ -558,9 +558,9 @@ static ssize_t interleave_granularity_store(struct device *dev,
> struct device_attribute *attr,
> const char *buf, size_t len)
> {
> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev->parent);
> - struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
> struct cxl_region *cxlr = to_cxl_region(dev);
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> + struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
> struct cxl_region_params *p = &cxlr->params;
> int rc, val;
> u16 ig;
> @@ -634,7 +634,7 @@ static DEVICE_ATTR_RO(mode);
>
> static int alloc_hpa(struct cxl_region *cxlr, resource_size_t size)
> {
> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> struct cxl_region_params *p = &cxlr->params;
> struct resource *res;
> u64 remainder = 0;
> @@ -1327,7 +1327,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
> struct cxl_region *cxlr,
> struct cxl_endpoint_decoder *cxled)
> {
> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> int parent_iw, parent_ig, ig, iw, rc, inc = 0, pos = cxled->pos;
> struct cxl_port *parent_port = to_cxl_port(port->dev.parent);
> struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr);
> @@ -1686,10 +1686,10 @@ static int cxl_region_validate_position(struct cxl_region *cxlr,
> }
>
> static int cxl_region_attach_position(struct cxl_region *cxlr,
> - struct cxl_root_decoder *cxlrd,
> struct cxl_endpoint_decoder *cxled,
> const struct cxl_dport *dport, int pos)
> {
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
> struct cxl_decoder *cxld = &cxlsd->cxld;
> @@ -1926,7 +1926,7 @@ static int cxl_region_sort_targets(struct cxl_region *cxlr)
> static int cxl_region_attach(struct cxl_region *cxlr,
> struct cxl_endpoint_decoder *cxled, int pos)
> {
> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> struct cxl_dev_state *cxlds = cxlmd->cxlds;
> struct cxl_region_params *p = &cxlr->params;
> @@ -2031,8 +2031,7 @@ static int cxl_region_attach(struct cxl_region *cxlr,
> ep_port = cxled_to_port(cxled);
> dport = cxl_find_dport_by_dev(root_port,
> ep_port->host_bridge);
> - rc = cxl_region_attach_position(cxlr, cxlrd, cxled,
> - dport, i);
> + rc = cxl_region_attach_position(cxlr, cxled, dport, i);
> if (rc)
> return rc;
> }
> @@ -2055,7 +2054,7 @@ static int cxl_region_attach(struct cxl_region *cxlr,
> if (rc)
> return rc;
>
> - rc = cxl_region_attach_position(cxlr, cxlrd, cxled, dport, pos);
> + rc = cxl_region_attach_position(cxlr, cxled, dport, pos);
> if (rc)
> return rc;
>
> @@ -2351,8 +2350,8 @@ static const struct attribute_group *region_groups[] = {
>
> static void cxl_region_release(struct device *dev)
> {
> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev->parent);
> struct cxl_region *cxlr = to_cxl_region(dev);
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> int id = atomic_read(&cxlrd->region_id);
>
> /*
> @@ -2435,10 +2434,12 @@ static struct cxl_region *cxl_region_alloc(struct cxl_root_decoder *cxlrd, int i
> * region id allocations
> */
> get_device(dev->parent);
> + cxlr->cxlrd = cxlrd;
> + cxlr->id = id;
> +
> device_set_pm_not_required(dev);
> dev->bus = &cxl_bus_type;
> dev->type = &cxl_region_type;
> - cxlr->id = id;
>
> return cxlr;
> }
> @@ -2937,7 +2938,7 @@ static bool has_spa_to_hpa(struct cxl_root_decoder *cxlrd)
> u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
> u64 dpa)
> {
> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> u64 dpa_offset, hpa_offset, bits_upper, mask_upper, hpa;
> struct cxl_region_params *p = &cxlr->params;
> struct cxl_endpoint_decoder *cxled = NULL;
> @@ -3013,7 +3014,7 @@ static int region_offset_to_dpa_result(struct cxl_region *cxlr, u64 offset,
> struct dpa_result *result)
> {
> struct cxl_region_params *p = &cxlr->params;
> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> struct cxl_endpoint_decoder *cxled;
> u64 hpa, hpa_offset, dpa_offset;
> u64 bits_upper, bits_lower;
> @@ -3404,7 +3405,7 @@ static int match_region_by_range(struct device *dev, const void *data)
> static int cxl_extended_linear_cache_resize(struct cxl_region *cxlr,
> struct resource *res)
> {
> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> struct cxl_region_params *p = &cxlr->params;
> resource_size_t size = resource_size(res);
> resource_size_t cache_size, start;
> @@ -3440,9 +3441,9 @@ static int cxl_extended_linear_cache_resize(struct cxl_region *cxlr,
> }
>
> static int __construct_region(struct cxl_region *cxlr,
> - struct cxl_root_decoder *cxlrd,
> struct cxl_endpoint_decoder *cxled)
> {
> + struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> struct range *hpa = &cxled->cxld.hpa_range;
> struct cxl_region_params *p;
> @@ -3534,7 +3535,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> return cxlr;
> }
>
> - rc = __construct_region(cxlr, cxlrd, cxled);
> + rc = __construct_region(cxlr, cxled);
> if (rc) {
> devm_release_action(port->uport_dev, unregister_region, cxlr);
> return ERR_PTR(rc);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 231ddccf8977..19b8b62a1322 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -521,6 +521,7 @@ enum cxl_partition_mode {
> * struct cxl_region - CXL region
> * @dev: This region's device
> * @id: This region's id. Id is globally unique across all regions
> + * @cxlrd: Region's root decoder
> * @mode: Operational mode of the mapped capacity
> * @type: Endpoint decoder target type
> * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown
> @@ -534,6 +535,7 @@ enum cxl_partition_mode {
> struct cxl_region {
> struct device dev;
> int id;
> + struct cxl_root_decoder *cxlrd;
> enum cxl_partition_mode mode;
> enum cxl_decoder_type type;
> struct cxl_nvdimm_bridge *cxl_nvb;
next prev parent reply other threads:[~2025-11-11 14:45 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 18:47 [PATCH v4 00/14] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Robert Richter
2025-11-03 18:47 ` [PATCH v4 01/14] cxl/region: Store root decoder in struct cxl_region Robert Richter
2025-11-11 14:45 ` Jonathan Cameron [this message]
2025-11-14 9:38 ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 02/14] cxl/region: Store HPA range " Robert Richter
2025-11-11 11:25 ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 03/14] cxl/region: Rename misleading variable name @hpa to @hpa_range Robert Richter
2025-11-03 21:36 ` Dave Jiang
2025-11-11 14:41 ` Jonathan Cameron
2025-11-12 16:23 ` Dave Jiang
2025-11-03 18:47 ` [PATCH v4 04/14] cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos() Robert Richter
2025-11-03 21:52 ` Dave Jiang
2025-11-04 3:04 ` Alison Schofield
2025-11-11 11:28 ` Robert Richter
2025-11-04 16:52 ` kernel test robot
2025-11-03 18:47 ` [PATCH v4 05/14] cxl: Simplify cxl_root_ops allocation and handling Robert Richter
2025-11-03 21:53 ` Dave Jiang
2025-11-04 23:02 ` Dave Jiang
2025-11-07 15:45 ` Robert Richter
2025-11-07 15:50 ` Dave Jiang
2025-11-11 14:52 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 06/14] cxl/region: Separate region parameter setup and region construction Robert Richter
2025-11-03 22:05 ` Dave Jiang
2025-11-07 15:59 ` Robert Richter
2025-11-11 14:59 ` Jonathan Cameron
2025-11-11 15:02 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 07/14] cxl/region: Use region data to get the root decoder Robert Richter
2025-11-03 22:30 ` Dave Jiang
2025-11-11 15:14 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 08/14] cxl: Introduce callback for HPA address ranges translation Robert Richter
2025-11-03 23:09 ` Dave Jiang
2025-11-11 15:15 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 09/14] cxl/acpi: Prepare use of EFI runtime services Robert Richter
2025-11-03 23:34 ` Dave Jiang
2025-11-11 15:17 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 10/14] cxl: Enable AMD Zen5 address translation using ACPI PRMT Robert Richter
2025-11-04 1:00 ` Dave Jiang
2025-11-11 9:23 ` Robert Richter
2025-11-04 9:33 ` kernel test robot
2025-11-04 12:49 ` Robert Richter
2025-11-04 23:35 ` kernel test robot
2025-11-11 15:30 ` Jonathan Cameron
2025-11-13 11:24 ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 11/14] cxl/atl: Lock decoders that need address translation Robert Richter
2025-11-04 17:13 ` Dave Jiang
2025-11-11 12:54 ` Robert Richter
2025-11-12 16:34 ` Dave Jiang
2025-11-13 20:05 ` Robert Richter
2025-11-13 20:36 ` Dave Jiang
2025-11-14 7:34 ` Robert Richter
2025-11-14 15:21 ` Dave Jiang
2025-11-11 15:31 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 12/14] cxl: Simplify cxl_rd_ops allocation and handling Robert Richter
2025-11-04 17:26 ` Dave Jiang
2025-11-04 23:02 ` Alison Schofield
2025-11-11 12:07 ` Robert Richter
2025-11-11 15:34 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 13/14] cxl/acpi: Group xor arithmetric setup code in a single block Robert Richter
2025-11-11 15:35 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 14/14] cxl/region: Remove local variable @inc in cxl_port_setup_targets() Robert Richter
2025-11-11 15:36 ` Jonathan Cameron
2025-11-13 20:10 ` Robert Richter
2025-11-04 16:17 ` [PATCH v4 00/14] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Alison Schofield
2025-11-17 15:34 ` Robert Richter
2025-11-17 17:23 ` Gregory Price
2025-11-11 14:01 ` Gregory Price
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