From: Dave Jiang <dave.jiang@intel.com>
To: Robert Richter <rrichter@amd.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Davidlohr Bueso <dave@stgolabs.net>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Gregory Price <gourry@gourry.net>,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>,
Joshua Hahn <joshua.hahnjy@gmail.com>
Subject: Re: [PATCH v4 06/14] cxl/region: Separate region parameter setup and region construction
Date: Mon, 3 Nov 2025 15:05:28 -0700 [thread overview]
Message-ID: <d34130ca-83fb-4f9d-b724-007b549f6f34@intel.com> (raw)
In-Reply-To: <20251103184804.509762-7-rrichter@amd.com>
On 11/3/25 11:47 AM, Robert Richter wrote:
> To construct a region, the region parameters such as address range and
> interleaving config need to be determined. This is done while
> constructing the region by inspecting the endpoint decoder
> configuration. The endpoint decoder is passed as a function argument.
>
> With address translation the endpoint decoder data is no longer
> sufficient to extract the region parameters as some of the information
> is obtained using other methods such as using firmware calls.
>
> In a first step, separate code to determine the region parameters from
> the region construction. Temporarily store all the data to create the
> region in the new struct cxl_region_context. Once the region data is
> determined and struct cxl_region_context is filled, construct the
> region.
>
> Patch is a prerequisite to implement address translation. The code
> separation helps to later extend it to determine region parameters
> using other methods as needed, esp. to support address translation.
>
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Signed-off-by: Robert Richter <rrichter@amd.com>
Just a small thing below, otherwise
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/core.h | 9 +++++++++
> drivers/cxl/core/region.c | 32 +++++++++++++++++++++-----------
> 2 files changed, 30 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 1fb66132b777..2bc37f3aee21 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -19,6 +19,15 @@ enum cxl_detach_mode {
> };
>
> #ifdef CONFIG_CXL_REGION
> +
> +struct cxl_region_context {
> + struct cxl_endpoint_decoder *cxled;
> + struct cxl_memdev *cxlmd;
cxlmd may not be needed.
struct cxl_memdev *cxlmd = cxled_to_memdev(cxlr_ctx->cxled);
which you used later on in this patch to init the cxlmd member :)
DJ
> + struct range hpa_range;
> + int interleave_ways;
> + int interleave_granularity;
> +};
> +
> extern struct device_attribute dev_attr_create_pmem_region;
> extern struct device_attribute dev_attr_create_ram_region;
> extern struct device_attribute dev_attr_delete_region;
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index d3557d9d5b0f..2cfc29a2b588 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -3448,11 +3448,12 @@ static int cxl_extended_linear_cache_resize(struct cxl_region *cxlr,
> }
>
> static int __construct_region(struct cxl_region *cxlr,
> - struct cxl_endpoint_decoder *cxled)
> + struct cxl_region_context *ctx)
> {
> + struct cxl_endpoint_decoder *cxled = ctx->cxled;
> struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> - struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> - struct range *hpa_range = &cxled->cxld.hpa_range;
> + struct cxl_memdev *cxlmd = ctx->cxlmd;
> + struct range *hpa_range = &ctx->hpa_range;
> struct cxl_region_params *p;
> struct resource *res;
> int rc;
> @@ -3501,8 +3502,8 @@ static int __construct_region(struct cxl_region *cxlr,
> }
>
> p->res = res;
> - p->interleave_ways = cxled->cxld.interleave_ways;
> - p->interleave_granularity = cxled->cxld.interleave_granularity;
> + p->interleave_ways = ctx->interleave_ways;
> + p->interleave_granularity = ctx->interleave_granularity;
> p->state = CXL_CONFIG_INTERLEAVE_ACTIVE;
>
> rc = sysfs_update_group(&cxlr->dev.kobj, get_cxl_region_target_group());
> @@ -3522,9 +3523,10 @@ static int __construct_region(struct cxl_region *cxlr,
>
> /* Establish an empty region covering the given HPA range */
> static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> - struct cxl_endpoint_decoder *cxled)
> + struct cxl_region_context *ctx)
> {
> - struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> + struct cxl_endpoint_decoder *cxled = ctx->cxled;
> + struct cxl_memdev *cxlmd = ctx->cxlmd;
> struct cxl_port *port = cxlrd_to_port(cxlrd);
> struct cxl_dev_state *cxlds = cxlmd->cxlds;
> int rc, part = READ_ONCE(cxled->part);
> @@ -3543,7 +3545,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> return cxlr;
> }
>
> - rc = __construct_region(cxlr, cxled);
> + rc = __construct_region(cxlr, ctx);
> if (rc) {
> devm_release_action(port->uport_dev, unregister_region, cxlr);
> return ERR_PTR(rc);
> @@ -3568,11 +3570,19 @@ cxl_find_region_by_range(struct cxl_root_decoder *cxlrd,
>
> int cxl_add_to_region(struct cxl_endpoint_decoder *cxled)
> {
> - struct range *hpa_range = &cxled->cxld.hpa_range;
> + struct cxl_region_context ctx;
> struct cxl_region_params *p;
> bool attach = false;
> int rc;
>
> + ctx = (struct cxl_region_context) {
> + .cxled = cxled,
> + .cxlmd = cxled_to_memdev(cxled),
> + .hpa_range = cxled->cxld.hpa_range,
> + .interleave_ways = cxled->cxld.interleave_ways,
> + .interleave_granularity = cxled->cxld.interleave_granularity,
> + };
> +
> struct cxl_root_decoder *cxlrd __free(put_cxl_root_decoder) =
> cxl_find_root_decoder(cxled);
> if (!cxlrd)
> @@ -3585,9 +3595,9 @@ int cxl_add_to_region(struct cxl_endpoint_decoder *cxled)
> */
> mutex_lock(&cxlrd->range_lock);
> struct cxl_region *cxlr __free(put_cxl_region) =
> - cxl_find_region_by_range(cxlrd, hpa_range);
> + cxl_find_region_by_range(cxlrd, &ctx.hpa_range);
> if (!cxlr)
> - cxlr = construct_region(cxlrd, cxled);
> + cxlr = construct_region(cxlrd, &ctx);
> mutex_unlock(&cxlrd->range_lock);
>
> rc = PTR_ERR_OR_ZERO(cxlr);
next prev parent reply other threads:[~2025-11-03 22:05 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 18:47 [PATCH v4 00/14] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Robert Richter
2025-11-03 18:47 ` [PATCH v4 01/14] cxl/region: Store root decoder in struct cxl_region Robert Richter
2025-11-11 14:45 ` Jonathan Cameron
2025-11-14 9:38 ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 02/14] cxl/region: Store HPA range " Robert Richter
2025-11-11 11:25 ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 03/14] cxl/region: Rename misleading variable name @hpa to @hpa_range Robert Richter
2025-11-03 21:36 ` Dave Jiang
2025-11-11 14:41 ` Jonathan Cameron
2025-11-12 16:23 ` Dave Jiang
2025-11-03 18:47 ` [PATCH v4 04/14] cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos() Robert Richter
2025-11-03 21:52 ` Dave Jiang
2025-11-04 3:04 ` Alison Schofield
2025-11-11 11:28 ` Robert Richter
2025-11-04 16:52 ` kernel test robot
2025-11-03 18:47 ` [PATCH v4 05/14] cxl: Simplify cxl_root_ops allocation and handling Robert Richter
2025-11-03 21:53 ` Dave Jiang
2025-11-04 23:02 ` Dave Jiang
2025-11-07 15:45 ` Robert Richter
2025-11-07 15:50 ` Dave Jiang
2025-11-11 14:52 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 06/14] cxl/region: Separate region parameter setup and region construction Robert Richter
2025-11-03 22:05 ` Dave Jiang [this message]
2025-11-07 15:59 ` Robert Richter
2025-11-11 14:59 ` Jonathan Cameron
2025-11-11 15:02 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 07/14] cxl/region: Use region data to get the root decoder Robert Richter
2025-11-03 22:30 ` Dave Jiang
2025-11-11 15:14 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 08/14] cxl: Introduce callback for HPA address ranges translation Robert Richter
2025-11-03 23:09 ` Dave Jiang
2025-11-11 15:15 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 09/14] cxl/acpi: Prepare use of EFI runtime services Robert Richter
2025-11-03 23:34 ` Dave Jiang
2025-11-11 15:17 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 10/14] cxl: Enable AMD Zen5 address translation using ACPI PRMT Robert Richter
2025-11-04 1:00 ` Dave Jiang
2025-11-11 9:23 ` Robert Richter
2025-11-04 9:33 ` kernel test robot
2025-11-04 12:49 ` Robert Richter
2025-11-04 23:35 ` kernel test robot
2025-11-11 15:30 ` Jonathan Cameron
2025-11-13 11:24 ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 11/14] cxl/atl: Lock decoders that need address translation Robert Richter
2025-11-04 17:13 ` Dave Jiang
2025-11-11 12:54 ` Robert Richter
2025-11-12 16:34 ` Dave Jiang
2025-11-13 20:05 ` Robert Richter
2025-11-13 20:36 ` Dave Jiang
2025-11-14 7:34 ` Robert Richter
2025-11-14 15:21 ` Dave Jiang
2025-11-11 15:31 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 12/14] cxl: Simplify cxl_rd_ops allocation and handling Robert Richter
2025-11-04 17:26 ` Dave Jiang
2025-11-04 23:02 ` Alison Schofield
2025-11-11 12:07 ` Robert Richter
2025-11-11 15:34 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 13/14] cxl/acpi: Group xor arithmetric setup code in a single block Robert Richter
2025-11-11 15:35 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 14/14] cxl/region: Remove local variable @inc in cxl_port_setup_targets() Robert Richter
2025-11-11 15:36 ` Jonathan Cameron
2025-11-13 20:10 ` Robert Richter
2025-11-04 16:17 ` [PATCH v4 00/14] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Alison Schofield
2025-11-17 15:34 ` Robert Richter
2025-11-17 17:23 ` Gregory Price
2025-11-11 14:01 ` Gregory Price
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