From: Dave Jiang <dave.jiang@intel.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Davidlohr Bueso <dave@stgolabs.net>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Gregory Price <gourry@gourry.net>,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>,
Joshua Hahn <joshua.hahnjy@gmail.com>
Subject: Re: [PATCH v4 11/14] cxl/atl: Lock decoders that need address translation
Date: Fri, 14 Nov 2025 08:21:44 -0700 [thread overview]
Message-ID: <ac8dae0d-251e-405a-be24-c553fcedf05f@intel.com> (raw)
In-Reply-To: <aRbboCjBhCujhh67@rric.localdomain>
On 11/14/25 12:34 AM, Robert Richter wrote:
> On Thu, Nov 13, 2025 at 01:36:26PM -0700, Dave Jiang wrote:
>>
>>
>> On 11/13/25 1:05 PM, Robert Richter wrote:
>>> On 12.11.25 09:34:34, Dave Jiang wrote:
>>>>
>>>>
>>>> On 11/11/25 5:54 AM, Robert Richter wrote:
>>>>> On 04.11.25 10:13:34, Dave Jiang wrote:
>>>>>>
>>>>>>
>>>>>> On 11/3/25 11:47 AM, Robert Richter wrote:
>>>>>>> There is only support to translate addresses from an endpoint to its
>>>>>>> CXL host bridge, but not in the opposite direction from the bridge to
>>>>>>> the endpoint. Thus, the endpoint address range cannot be determined
>>>>>>> and setup manually for a given SPA range of a region. If the endpoint
>>>>>>> has address translation enabled, lock it to prevent the kernel from
>>>>>>> reconfiguring it.
>>>>>>>
>>>>>>> Reviewed-by: Gregory Price <gourry@gourry.net>
>>>>>>> Signed-off-by: Robert Richter <rrichter@amd.com>
>>>>>>> ---
>>>>>>> drivers/cxl/core/atl.c | 10 ++++++++++
>>>>>>> 1 file changed, 10 insertions(+)
>>>>>>>
>>>>>>> diff --git a/drivers/cxl/core/atl.c b/drivers/cxl/core/atl.c
>>>>>>> index d6aa7e6d0ac5..5c15e4d12193 100644
>>>>>>> --- a/drivers/cxl/core/atl.c
>>>>>>> +++ b/drivers/cxl/core/atl.c
>>>>>>> @@ -158,6 +158,16 @@ static int cxl_prm_translate_hpa_range(struct cxl_root *cxl_root, void *data)
>>>>>>> return -ENXIO;
>>>>>>> }
>>>>>>>
>>>>>>> + /*
>>>>>>> + * There is only support to translate from the endpoint to its
>>>>>>> + * parent port, but not in the opposite direction from the
>>>>>>> + * parent to the endpoint. Thus, the endpoint address range
>>>>>>> + * cannot be determined and setup manually. If the address range
>>>>>>> + * was translated and modified, forbid reprogramming of the
>>>>>>> + * decoders and lock them.
>>>>>>> + */
>>>>>>> + cxld->flags |= CXL_DECODER_F_LOCK;
>>>>>>
>>>>>
>>>>>> Feels like this should be something the BIOS should enforce if that
>>>>>> is the expectation? And the kernel checks and warns if that is not
>>>>>> the case.
>>>>>
>>>>> I think this is more a limitation of the kernel implementation rather
>>>>> than the BIOS. The BIOS provides enought information by CFMWS, PRM,
>>>>> HDM and PCI topology. In theory and if there is demand for it, support
>>>>> could be added for driver region setup.
>>>>
>>>
>>>> But shouldn't the BIOS set the decoder lock rather than the kernel
>>>> setting a software lock flag based on assumption of the PRM based
>>>> setup?
>>>
>>> If BIOS locks the decoders, it cannot be removed even for the case
>>> there the OS can actually handle it.
>>
>
>> Oh so the current implementation is auto region by BIOS but in the
>> future it may not be? But if you add a lock flag, you wouldn't be
>> able to remove it later anyhow since it's presented as locked?
>
> The BIOS provides all necessary data for address translation, so that
> decoders can be reconfigured (including normalized endpoint
> addresses). There is no reason to lock the decoders by the BIOS, as
> otherwise, with a capable kernel (or other OS), it would not be
> possible to shutdown auto-generated regions.
>
> However, current kernel implementation does not support this and is
> unable to create the region. That is why the kernel and not the BIOS
> should lock the decoders.
Ok I see what you are saying. Fair enough. As long as we have a comment that makes note of this detail.
>
> -Robert
next prev parent reply other threads:[~2025-11-14 15:21 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 18:47 [PATCH v4 00/14] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Robert Richter
2025-11-03 18:47 ` [PATCH v4 01/14] cxl/region: Store root decoder in struct cxl_region Robert Richter
2025-11-11 14:45 ` Jonathan Cameron
2025-11-14 9:38 ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 02/14] cxl/region: Store HPA range " Robert Richter
2025-11-11 11:25 ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 03/14] cxl/region: Rename misleading variable name @hpa to @hpa_range Robert Richter
2025-11-03 21:36 ` Dave Jiang
2025-11-11 14:41 ` Jonathan Cameron
2025-11-12 16:23 ` Dave Jiang
2025-11-03 18:47 ` [PATCH v4 04/14] cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos() Robert Richter
2025-11-03 21:52 ` Dave Jiang
2025-11-04 3:04 ` Alison Schofield
2025-11-11 11:28 ` Robert Richter
2025-11-04 16:52 ` kernel test robot
2025-11-03 18:47 ` [PATCH v4 05/14] cxl: Simplify cxl_root_ops allocation and handling Robert Richter
2025-11-03 21:53 ` Dave Jiang
2025-11-04 23:02 ` Dave Jiang
2025-11-07 15:45 ` Robert Richter
2025-11-07 15:50 ` Dave Jiang
2025-11-11 14:52 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 06/14] cxl/region: Separate region parameter setup and region construction Robert Richter
2025-11-03 22:05 ` Dave Jiang
2025-11-07 15:59 ` Robert Richter
2025-11-11 14:59 ` Jonathan Cameron
2025-11-11 15:02 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 07/14] cxl/region: Use region data to get the root decoder Robert Richter
2025-11-03 22:30 ` Dave Jiang
2025-11-11 15:14 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 08/14] cxl: Introduce callback for HPA address ranges translation Robert Richter
2025-11-03 23:09 ` Dave Jiang
2025-11-11 15:15 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 09/14] cxl/acpi: Prepare use of EFI runtime services Robert Richter
2025-11-03 23:34 ` Dave Jiang
2025-11-11 15:17 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 10/14] cxl: Enable AMD Zen5 address translation using ACPI PRMT Robert Richter
2025-11-04 1:00 ` Dave Jiang
2025-11-11 9:23 ` Robert Richter
2025-11-04 9:33 ` kernel test robot
2025-11-04 12:49 ` Robert Richter
2025-11-04 23:35 ` kernel test robot
2025-11-11 15:30 ` Jonathan Cameron
2025-11-13 11:24 ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 11/14] cxl/atl: Lock decoders that need address translation Robert Richter
2025-11-04 17:13 ` Dave Jiang
2025-11-11 12:54 ` Robert Richter
2025-11-12 16:34 ` Dave Jiang
2025-11-13 20:05 ` Robert Richter
2025-11-13 20:36 ` Dave Jiang
2025-11-14 7:34 ` Robert Richter
2025-11-14 15:21 ` Dave Jiang [this message]
2025-11-11 15:31 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 12/14] cxl: Simplify cxl_rd_ops allocation and handling Robert Richter
2025-11-04 17:26 ` Dave Jiang
2025-11-04 23:02 ` Alison Schofield
2025-11-11 12:07 ` Robert Richter
2025-11-11 15:34 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 13/14] cxl/acpi: Group xor arithmetric setup code in a single block Robert Richter
2025-11-11 15:35 ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 14/14] cxl/region: Remove local variable @inc in cxl_port_setup_targets() Robert Richter
2025-11-11 15:36 ` Jonathan Cameron
2025-11-13 20:10 ` Robert Richter
2025-11-04 16:17 ` [PATCH v4 00/14] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Alison Schofield
2025-11-17 15:34 ` Robert Richter
2025-11-17 17:23 ` Gregory Price
2025-11-11 14:01 ` Gregory Price
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