[PATCH v2 00/12] Add StarFive JHB100 syscon modules

[Changhuang Liang <changhuang.liang@starfivetech.com>]

StarFive JHB100 has many syscon modules, as listed below:
- pcieep0_ecsr_syscon	(PCIe endpoint 0 externel syscon)
- pcieep1_ecsr_syscon
- host0_syscon		(Host0 syscon)
- host1_syscon
- husb0_syscon		(Host USB 0 syscon)
- husb1_syscon
- husbd0_syscon		(Host USB device 0 syscon)
- husbd1_syscon
- husbcmn_syscon	(Host USB common)
- gpu0_syscon		(GPU0 syscon)
- gpu1_syscon
- b2h_syscon		(BMC to Host syscon)
- h2b_syscon		(Host to BMC syscon)
- vout_syscon		(Video output syscon)
- pcierp_ecsr_syscon	(PCIe root port externel syscon)
- pcierp_syscon		(PCIe root port syscon)
- usb_syscon
- npu_syscon
- per0_syscon		(Peripheral 0 syscon)
- per1_syscon
- per2_syscon
- per3_syscon
- sys0_syscon		(System 0 syscon)
- sys1_syscon
- sys2_syscon
- strap_syscon

Some syscon modules contain PLL, reset, and socinfo nodes
This series will add these syscon modules, as well as the
nodes under them.

-PATCH 1:	syscon binging
-PATCH 2-7:	syscon PLL driver
-PATCH 8-10:	syscon reset driver
-PATCH 11:	syscon socinfo driver
-PATCH 12:	syscon device tree

This series depends on the series:
https://lore.kernel.org/all/20260508053632.818548-1-changhuang.liang@starfivetech.com/

changes since v1:
-Remove PATCH 11

PATCH 1:
- Folded PLL and syscon reset resources into the syscon node
PATCH 2/4/6:
- Remove PLL bindings
PATCH 3:
- Use HZ_PER_MHZ
- check regmap_ return value
- check val.refdiv != 0
PATCH 8:
- Remove syscon reset binding
PATCH 11:
- Changed from platform driver model to syscon-based direct initialization
PATCH 12:
- Folded PLL and syscon reset resources into the syscon node

Changhuang Liang (12):
  dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
  dt-bindings: clock: Add system-0 domain PLL clock
  clk: starfive: Add system-0 domain PLL clock driver
  dt-bindings: clock: Add peripheral-0 domain PLL clock
  clk: starfive: Add peripheral-0 domain PLL clock driver
  dt-bindings: clock: Add peripheral-1 domain PLL clock
  clk: starfive: Add Peripheral-1 domain PLL clock driver
  dt-bindings: reset: Add StarFive JHB100 reset generator
  reset: starfive: Introduce assert_polarity
  reset: starfive: Add syscon reset driver support
  soc: starfive: Add socinfo driver for JHB100 SoC
  riscv: dts: starfive: jhb100: Add syscon nodes

 .../soc/starfive/starfive,jhb100-syscon.yaml  | 107 ++++
 MAINTAINERS                                   |  10 +
 arch/riscv/boot/dts/starfive/jhb100.dtsi      | 180 ++++--
 drivers/clk/starfive/Kconfig                  |   8 +
 drivers/clk/starfive/Makefile                 |   1 +
 .../clk/starfive/clk-starfive-jhb100-pll.c    | 586 ++++++++++++++++++
 drivers/reset/starfive/Kconfig                |   9 +
 drivers/reset/starfive/Makefile               |   1 +
 .../reset/starfive/reset-starfive-common.c    |  18 +-
 .../reset/starfive/reset-starfive-common.h    |   6 +
 .../starfive/reset-starfive-jhb100-syscon.c   |  62 ++
 drivers/soc/Kconfig                           |   1 +
 drivers/soc/Makefile                          |   1 +
 drivers/soc/starfive/Kconfig                  |   6 +
 drivers/soc/starfive/Makefile                 |   2 +
 drivers/soc/starfive/socinfo/Kconfig          |  11 +
 drivers/soc/starfive/socinfo/Makefile         |   2 +
 drivers/soc/starfive/socinfo/jhb100-socinfo.c |  80 +++
 .../dt-bindings/clock/starfive,jhb100-crg.h   |  12 +
 .../dt-bindings/reset/starfive,jhb100-crg.h   |   3 +
 20 files changed, 1068 insertions(+), 38 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c
 create mode 100644 drivers/reset/starfive/reset-starfive-jhb100-syscon.c
 create mode 100644 drivers/soc/starfive/Kconfig
 create mode 100644 drivers/soc/starfive/Makefile
 create mode 100644 drivers/soc/starfive/socinfo/Kconfig
 create mode 100644 drivers/soc/starfive/socinfo/Makefile
 create mode 100644 drivers/soc/starfive/socinfo/jhb100-socinfo.c

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2.25.1