* [PATCH v2 01/12] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 17:38 ` Conor Dooley
2026-05-12 8:35 ` [PATCH v2 02/12] dt-bindings: clock: Add system-0 domain PLL clock Changhuang Liang
` (11 subsequent siblings)
12 siblings, 1 reply; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add documentation to describe StarFive JHB100 SoC System Controller
Registers.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../soc/starfive/starfive,jhb100-syscon.yaml | 107 ++++++++++++++++++
MAINTAINERS | 5 +
2 files changed, 112 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
new file mode 100644
index 000000000000..0add3d9727ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC system controller
+
+maintainers:
+ - Kevin Xie <kevin.xie@starfivetech.com>
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+description:
+ The StarFive JHB100 SoC system controller contains MMIO registers used by
+ other hardware modules (e.g., PLL, eMMC, PCIe). These modules access
+ specific register offsets, bit masks, and shifts within the system
+ controller region for configuration and status.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - starfive,jhb100-b2h-syscon
+ - starfive,jhb100-gpu-syscon
+ - starfive,jhb100-h2b-syscon
+ - starfive,jhb100-host-syscon
+ - starfive,jhb100-husb-syscon
+ - starfive,jhb100-husbcmn-syscon
+ - starfive,jhb100-husbd-syscon
+ - starfive,jhb100-npu-syscon
+ - starfive,jhb100-pcieep-ecsr-syscon
+ - starfive,jhb100-pcierp-ecsr-syscon
+ - starfive,jhb100-pcierp-syscon
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-per2-syscon
+ - starfive,jhb100-per3-syscon
+ - starfive,jhb100-strap-syscon
+ - starfive,jhb100-sys0-syscon
+ - starfive,jhb100-sys1-syscon
+ - starfive,jhb100-sys2-syscon
+ - starfive,jhb100-usb-syscon
+ - starfive,jhb100-vout-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-sys0-syscon
+ then:
+ required:
+ - clocks
+ - '#clock-cells'
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jhb100-pcierp-syscon
+ then:
+ required:
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@13010000 {
+ compatible = "starfive,jhb100-sys0-syscon", "syscon";
+ reg = <0x13010000 0x2000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ syscon@13014000 {
+ compatible = "starfive,jhb100-sys1-syscon", "syscon";
+ reg = <0x13014000 0x4000>;
+ };
+
+ syscon@11719000 {
+ compatible = "starfive,jhb100-pcierp-syscon", "syscon";
+ reg = <0x11719000 0x1000>;
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 47e4b368347f..6f6aac7cea95 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25613,6 +25613,11 @@ S: Maintained
F: drivers/reset/starfive/reset-starfive-jhb1*
F: include/dt-bindings/reset/starfive,jhb1*.h
+STARFIVE JHB100 SYSCON
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 01/12] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
2026-05-12 8:35 ` [PATCH v2 01/12] dt-bindings: soc: starfive: " Changhuang Liang
@ 2026-05-12 17:38 ` Conor Dooley
0 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2026-05-12 17:38 UTC (permalink / raw)
To: Changhuang Liang
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing,
Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 4668 bytes --]
On Tue, May 12, 2026 at 01:35:10AM -0700, Changhuang Liang wrote:
> Add documentation to describe StarFive JHB100 SoC System Controller
> Registers.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> .../soc/starfive/starfive,jhb100-syscon.yaml | 107 ++++++++++++++++++
> MAINTAINERS | 5 +
> 2 files changed, 112 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
> new file mode 100644
> index 000000000000..0add3d9727ac
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
> @@ -0,0 +1,107 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JHB100 SoC system controller
> +
> +maintainers:
> + - Kevin Xie <kevin.xie@starfivetech.com>
> + - Changhuang Liang <changhuang.liang@starfivetech.com>
> +
> +description:
> + The StarFive JHB100 SoC system controller contains MMIO registers used by
> + other hardware modules (e.g., PLL, eMMC, PCIe). These modules access
> + specific register offsets, bit masks, and shifts within the system
> + controller region for configuration and status.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - starfive,jhb100-b2h-syscon
> + - starfive,jhb100-gpu-syscon
> + - starfive,jhb100-h2b-syscon
> + - starfive,jhb100-host-syscon
> + - starfive,jhb100-husb-syscon
> + - starfive,jhb100-husbcmn-syscon
> + - starfive,jhb100-husbd-syscon
> + - starfive,jhb100-npu-syscon
> + - starfive,jhb100-pcieep-ecsr-syscon
> + - starfive,jhb100-pcierp-ecsr-syscon
> + - starfive,jhb100-pcierp-syscon
> + - starfive,jhb100-per0-syscon
> + - starfive,jhb100-per1-syscon
> + - starfive,jhb100-per2-syscon
> + - starfive,jhb100-per3-syscon
> + - starfive,jhb100-strap-syscon
> + - starfive,jhb100-sys0-syscon
> + - starfive,jhb100-sys1-syscon
> + - starfive,jhb100-sys2-syscon
> + - starfive,jhb100-usb-syscon
> + - starfive,jhb100-vout-syscon
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - starfive,jhb100-per0-syscon
> + - starfive,jhb100-per1-syscon
> + - starfive,jhb100-sys0-syscon
> + then:
> + required:
> + - clocks
> + - '#clock-cells'
Probably missing and else: clocks/clock-cells: false?
And the same below for resets?
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jhb100-pcierp-syscon
> + then:
> + required:
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + syscon@13010000 {
> + compatible = "starfive,jhb100-sys0-syscon", "syscon";
> + reg = <0x13010000 0x2000>;
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
> + syscon@13014000 {
> + compatible = "starfive,jhb100-sys1-syscon", "syscon";
> + reg = <0x13014000 0x4000>;
> + };
> +
> + syscon@11719000 {
> + compatible = "starfive,jhb100-pcierp-syscon", "syscon";
> + reg = <0x11719000 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 47e4b368347f..6f6aac7cea95 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -25613,6 +25613,11 @@ S: Maintained
> F: drivers/reset/starfive/reset-starfive-jhb1*
> F: include/dt-bindings/reset/starfive,jhb1*.h
>
> +STARFIVE JHB100 SYSCON
> +M: Changhuang Liang <changhuang.liang@starfivetech.com>
> +S: Maintained
> +F: Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
> +
> STATIC BRANCH/CALL
> M: Peter Zijlstra <peterz@infradead.org>
> M: Josh Poimboeuf <jpoimboe@kernel.org>
> --
> 2.25.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 02/12] dt-bindings: clock: Add system-0 domain PLL clock
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 01/12] dt-bindings: soc: starfive: " Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 03/12] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
` (10 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add system-0 domain PLL clock for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
include/dt-bindings/clock/starfive,jhb100-crg.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index bdf7d628b381..98b3cf28b677 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -8,6 +8,12 @@
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__
+/* SYS0PLL clocks */
+#define JHB100_SYS0PLL_PLL2_OUT 0
+#define JHB100_SYS0PLL_PLL3_OUT 1
+#define JHB100_SYS0PLL_PLL4_OUT 2
+#define JHB100_SYS0PLL_PLL5_OUT 3
+
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN 17
#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG 18
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 03/12] clk: starfive: Add system-0 domain PLL clock driver
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 01/12] dt-bindings: soc: starfive: " Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 02/12] dt-bindings: clock: Add system-0 domain PLL clock Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 04/12] dt-bindings: clock: Add peripheral-0 domain PLL clock Changhuang Liang
` (9 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add system-0 domain PLL clock driver for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-pll.c | 528 ++++++++++++++++++
3 files changed, 537 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index c612f1ede7d7..cc712da68bd0 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -105,6 +105,14 @@ config CLK_STARFIVE_JHB100_PER3
Say yes here to support the peripheral-3 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PLL
+ bool "StarFive JHB100 PLL clock support"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the PLL clock controller on the
+ StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index f00690f0cdad..547a8c170728 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) += clk-starfive-jhb100-per3.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PLL) += clk-starfive-jhb100-pll.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
new file mode 100644
index 000000000000..603b928bbb81
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 PLL Clock Generator Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/units.h>
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+
+/* this driver expects a 25MHz input frequency from the oscillator */
+#define JHB100_PLL_OSC_RATE (25 * HZ_PER_MHZ)
+
+/* System-0 domain PLL */
+#define JHB100_PLL2_OFFSET 0x00
+#define JHB100_PLL3_OFFSET 0x0c
+#define JHB100_PLL4_OFFSET 0x18
+#define JHB100_PLL5_OFFSET 0x24
+
+#define JHB100_PLL_CFG0_OFFSET 0x0
+#define JHB100_PLL_CFG1_OFFSET 0x4
+#define JHB100_PLL_CFG2_OFFSET 0x8
+
+#define JHB100_PLLX_CFG0(offset) ((offset) + JHB100_PLL_CFG0_OFFSET)
+/* fbdiv value should be 16 to 4095 */
+#define JHB100_PLL_FBDIV GENMASK(13, 2)
+#define JHB100_PLL_FBDIV_SHIFT 2
+#define JHB100_PLL_FOUTPOSTDIV_EN BIT(14)
+#define JHB100_PLL_FOUTPOSTDIV_EN_SHIFT 14
+#define JHB100_PLL_FOUTVCOP_EN BIT(16)
+#define JHB100_PLL_FOUTVCOP_EN_SHIFT 16
+
+#define JHB100_PLLX_CFG1(offset) ((offset) + JHB100_PLL_CFG1_OFFSET)
+/* frac value should be decimals multiplied by 2^24 */
+#define JHB100_PLL_FRAC GENMASK(23, 0)
+#define JHB100_PLL_FRAC_SHIFT 0
+#define JHB100_PLL_LOCK BIT(24)
+#define JHB100_PLL_LOCK_SHIFT 24
+
+#define JHB100_PLLX_CFG2(offset) ((offset) + JHB100_PLL_CFG2_OFFSET)
+#define JHB100_PLL_PD BIT(13)
+#define JHB100_PLL_PD_SHIFT 13
+#define JHB100_PLL_POSTDIV GENMASK(15, 14)
+#define JHB100_PLL_POSTDIV_SHIFT 14
+#define JHB100_PLL_REFDIV GENMASK(23, 18)
+#define JHB100_PLL_REFDIV_SHIFT 18
+
+#define JHB100_PLL_TIMEOUT_US 1000
+#define JHB100_PLL_INTERVAL_US 100
+
+struct jhb100_pll_preset {
+ unsigned long freq;
+ u32 frac; /* frac value should be decimals multiplied by 2^24 */
+ unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */
+ unsigned refdiv : 6;
+ unsigned postdiv : 2;
+ unsigned foutpostdiv_en : 1;
+ unsigned foutvcop_en : 1;
+};
+
+struct jhb100_pll_info {
+ char *name;
+ const struct jhb100_pll_preset *presets;
+ unsigned int npresets;
+ unsigned long flag;
+ u8 offset;
+ bool continuous;
+};
+
+#define _JHB100_PLL(_idx, _name, _presets, _npresets, _offset, _flag, _cont) \
+ [_idx] = { \
+ .name = _name, \
+ .offset = _offset, \
+ .presets = _presets, \
+ .npresets = _npresets, \
+ .flag = _flag, \
+ .continuous = _cont, \
+ }
+
+#define JHB100_PLL(idx, name, presets, npresets, offset, cont) \
+ _JHB100_PLL(idx, name, presets, npresets, offset, 0, cont)
+
+struct jhb100_pll_match_data {
+ const struct jhb100_pll_info *pll_info;
+ int num_pll;
+};
+
+struct jhb100_pll_data {
+ struct clk_hw hw;
+ unsigned int idx;
+};
+
+struct jhb100_pll_priv {
+ struct device *dev;
+ struct regmap *regmap;
+ const struct jhb100_pll_match_data *match_data;
+ struct jhb100_pll_data pll[];
+};
+
+struct jhb100_pll_regvals {
+ u32 fbdiv;
+ u32 frac;
+ u32 postdiv;
+ u32 refdiv;
+ bool foutpostdiv_en;
+ bool foutvcop_en;
+};
+
+static struct jhb100_pll_data *jhb100_pll_data_from(struct clk_hw *hw)
+{
+ return container_of(hw, struct jhb100_pll_data, hw);
+}
+
+static struct jhb100_pll_priv *jhb100_pll_priv_from(struct jhb100_pll_data *pll)
+{
+ return container_of(pll, struct jhb100_pll_priv, pll[pll->idx]);
+}
+
+static int jhb100_pll_enable(struct clk_hw *hw)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+
+ return regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
+ JHB100_PLL_PD, 0);
+}
+
+static void jhb100_pll_disable(struct clk_hw *hw)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+
+ regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
+ JHB100_PLL_PD, BIT(JHB100_PLL_PD_SHIFT));
+}
+
+static int jhb100_pll_is_enabled(struct clk_hw *hw)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+ u32 val;
+ int ret;
+
+ ret = regmap_read(priv->regmap, JHB100_PLLX_CFG2(info->offset), &val);
+ if (ret)
+ return ret;
+
+ return !(val & JHB100_PLL_PD);
+}
+
+static int jhb100_pll_regvals_get(struct regmap *regmap,
+ const struct jhb100_pll_info *info,
+ struct jhb100_pll_regvals *val)
+{
+ u32 value;
+ int ret;
+
+ ret = regmap_read(regmap, JHB100_PLLX_CFG0(info->offset), &value);
+ if (ret)
+ return ret;
+
+ val->fbdiv = (value & JHB100_PLL_FBDIV) >> JHB100_PLL_FBDIV_SHIFT;
+ val->foutpostdiv_en = !!((value & JHB100_PLL_FOUTPOSTDIV_EN) >>
+ JHB100_PLL_FOUTPOSTDIV_EN_SHIFT);
+ val->foutvcop_en = !!((value & JHB100_PLL_FOUTVCOP_EN) >>
+ JHB100_PLL_FOUTVCOP_EN_SHIFT);
+
+ ret = regmap_read(regmap, JHB100_PLLX_CFG1(info->offset), &value);
+ if (ret)
+ return ret;
+
+ val->frac = (value & JHB100_PLL_FRAC) >> JHB100_PLL_FRAC_SHIFT;
+
+ ret = regmap_read(regmap, JHB100_PLLX_CFG2(info->offset), &value);
+ if (ret)
+ return ret;
+
+ val->postdiv = (value & JHB100_PLL_POSTDIV) >> JHB100_PLL_POSTDIV_SHIFT;
+ val->refdiv = (value & JHB100_PLL_REFDIV) >> JHB100_PLL_REFDIV_SHIFT;
+
+ return 0;
+}
+
+static unsigned long jhb100_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ struct jhb100_pll_regvals val;
+ unsigned long rate;
+ u32 power = 0;
+ int ret;
+
+ ret = jhb100_pll_regvals_get(priv->regmap, &priv->match_data->pll_info[pll->idx], &val);
+ if (ret)
+ return 0;
+
+ /*
+ *
+ * if (foutvcop_en)
+ * rate = parent * (fbdiv + frac / 2^24) / refdiv
+ *
+ * if (foutpostdiv_en)
+ * rate = parent * (fbdiv + frac / 2^24) / refdiv / 2^(postdiv + 1)
+ *
+ * parent * (fbdiv + frac / 2^24) = parent * fbdiv + parent * frac / 2^24
+ */
+
+ if (!!val.foutvcop_en == !!val.foutpostdiv_en || !val.refdiv)
+ return 0;
+
+ rate = (parent_rate * val.frac) >> 24;
+
+ if (val.foutpostdiv_en)
+ power = val.postdiv + 1;
+
+ rate += parent_rate * val.fbdiv;
+ rate /= val.refdiv << power;
+
+ return rate;
+}
+
+static int jhb100_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+ const struct jhb100_pll_preset *selected = &info->presets[0];
+ unsigned int idx;
+
+ /* if the parent rate doesn't match our expectations the presets won't work */
+ if (req->best_parent_rate != JHB100_PLL_OSC_RATE) {
+ req->rate = jhb100_pll_recalc_rate(hw, req->best_parent_rate);
+ return 0;
+ }
+
+ /* continuous means support any rate */
+ if (info->continuous)
+ return 0;
+
+ /* find highest rate lower or equal to the requested rate */
+ for (idx = 1; idx < info->npresets; idx++) {
+ const struct jhb100_pll_preset *val = &info->presets[idx];
+
+ if (req->rate < val->freq)
+ break;
+
+ selected = val;
+ }
+
+ req->rate = selected->freq;
+
+ return 0;
+}
+
+static int jhb100_pll_set_preset(struct clk_hw *hw, const struct jhb100_pll_preset *val)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+ unsigned int value, cfg;
+ int ret;
+
+ cfg = ((u32)val->fbdiv << JHB100_PLL_FBDIV_SHIFT) |
+ ((u32)val->foutpostdiv_en << JHB100_PLL_FOUTPOSTDIV_EN_SHIFT) |
+ ((u32)val->foutvcop_en << JHB100_PLL_FOUTVCOP_EN_SHIFT);
+
+ ret = regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset),
+ JHB100_PLL_FBDIV | JHB100_PLL_FOUTPOSTDIV_EN |
+ JHB100_PLL_FOUTVCOP_EN, cfg);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, JHB100_PLLX_CFG1(info->offset), JHB100_PLL_FRAC,
+ val->frac << JHB100_PLL_FRAC_SHIFT);
+ if (ret)
+ return ret;
+
+ cfg = ((u32)val->refdiv << JHB100_PLL_REFDIV_SHIFT) |
+ ((u32)val->postdiv << JHB100_PLL_POSTDIV_SHIFT);
+
+ ret = regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
+ JHB100_PLL_REFDIV | JHB100_PLL_POSTDIV, cfg);
+ if (ret)
+ return ret;
+
+ /* waiting for PLL to lock */
+ return regmap_read_poll_timeout_atomic(priv->regmap, JHB100_PLLX_CFG1(info->offset),
+ value, value & JHB100_PLL_LOCK,
+ JHB100_PLL_INTERVAL_US,
+ JHB100_PLL_TIMEOUT_US);
+}
+
+static int jhb100_pll_rate_to_preset(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jhb100_pll_preset val = {
+ .refdiv = 1,
+ .postdiv = 3,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ };
+ unsigned int power = 0;
+ unsigned long fbdiv_24, t;
+
+ if (val.foutpostdiv_en)
+ power = val.postdiv + 1;
+
+ t = val.refdiv << power;
+ t *= rate;
+
+ val.fbdiv = t / parent_rate;
+
+ fbdiv_24 = (t << 24) / parent_rate;
+ val.frac = fbdiv_24 - (val.fbdiv << 24);
+
+ return jhb100_pll_set_preset(hw, &val);
+}
+
+static int jhb100_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+ const struct jhb100_pll_preset *val;
+ unsigned int idx;
+
+ /* if the parent rate doesn't match our expectations the presets won't work */
+ if (parent_rate != JHB100_PLL_OSC_RATE)
+ return -EINVAL;
+
+ if (info->continuous)
+ return jhb100_pll_rate_to_preset(hw, rate, parent_rate);
+
+ for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {
+ if (val->freq == rate)
+ return jhb100_pll_set_preset(hw, val);
+ }
+ return -EINVAL;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int jhb100_pll_registers_read(struct seq_file *s, void *unused)
+{
+ struct jhb100_pll_data *pll = s->private;
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ struct jhb100_pll_regvals val;
+ int ret;
+
+ ret = jhb100_pll_regvals_get(priv->regmap, &priv->match_data->pll_info[pll->idx], &val);
+ if (ret)
+ return ret;
+
+ seq_printf(s, "fbdiv=%u\n"
+ "frac=%u\n"
+ "refdiv=%u\n"
+ "postdiv=%u\n"
+ "foutpostdiv_en=%u\n"
+ "foutvcop_en=%u\n",
+ val.fbdiv, val.frac, val.refdiv, val.postdiv,
+ val.foutpostdiv_en, val.foutvcop_en);
+
+ return 0;
+}
+
+static int jhb100_pll_registers_open(struct inode *inode, struct file *f)
+{
+ return single_open(f, jhb100_pll_registers_read, inode->i_private);
+}
+
+static const struct file_operations jhb100_pll_registers_ops = {
+ .owner = THIS_MODULE,
+ .open = jhb100_pll_registers_open,
+ .release = single_release,
+ .read = seq_read,
+ .llseek = seq_lseek
+};
+
+static void jhb100_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+
+ debugfs_create_file("registers", 0400, dentry, pll,
+ &jhb100_pll_registers_ops);
+}
+#else
+#define jhb100_pll_debug_init NULL
+#endif
+
+static const struct clk_ops jhb100_pll_ops = {
+ .enable = jhb100_pll_enable,
+ .disable = jhb100_pll_disable,
+ .is_enabled = jhb100_pll_is_enabled,
+ .recalc_rate = jhb100_pll_recalc_rate,
+ .determine_rate = jhb100_pll_determine_rate,
+ .set_rate = jhb100_pll_set_rate,
+ .debug_init = jhb100_pll_debug_init,
+};
+
+static struct clk_hw *jhb100_pll_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jhb100_pll_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < priv->match_data->num_pll)
+ return &priv->pll[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int __init jhb100_pll_probe(struct platform_device *pdev)
+{
+ const struct jhb100_pll_match_data *match_data;
+ struct jhb100_pll_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ match_data = of_device_get_match_data(&pdev->dev);
+ if (!match_data)
+ return -EINVAL;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, pll, match_data->num_pll),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->match_data = match_data;
+ priv->dev = &pdev->dev;
+ priv->regmap = syscon_node_to_regmap(priv->dev->of_node);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ for (idx = 0; idx < match_data->num_pll; idx++) {
+ struct clk_parent_data parents = {
+ .index = 0,
+ };
+ struct clk_init_data init = {
+ .name = match_data->pll_info[idx].name,
+ .ops = &jhb100_pll_ops,
+ .parent_data = &parents,
+ .num_parents = 1,
+ .flags = match_data->pll_info[idx].flag,
+ };
+ struct jhb100_pll_data *pll = &priv->pll[idx];
+
+ pll->hw.init = &init;
+ pll->idx = idx;
+
+ ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, jhb100_pll_get, priv);
+}
+
+static const struct jhb100_pll_preset jhb100_pll2_presets[] = {
+ {
+ .freq = 903168000,
+ .fbdiv = 72,
+ .frac = 4252017,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_preset jhb100_pll3_presets[] = {
+ {
+ .freq = 800000000,
+ .fbdiv = 64,
+ .frac = 0,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_info jhb100_sys0_pll_info[] = {
+ JHB100_PLL(JHB100_SYS0PLL_PLL2_OUT, "pll2_out", jhb100_pll2_presets,
+ ARRAY_SIZE(jhb100_pll2_presets), JHB100_PLL2_OFFSET, false),
+ _JHB100_PLL(JHB100_SYS0PLL_PLL3_OUT, "pll3_out", jhb100_pll3_presets,
+ ARRAY_SIZE(jhb100_pll3_presets), JHB100_PLL3_OFFSET,
+ CLK_IS_CRITICAL, false),
+ _JHB100_PLL(JHB100_SYS0PLL_PLL4_OUT, "pll4_out", NULL, 0,
+ JHB100_PLL4_OFFSET, CLK_IGNORE_UNUSED, true),
+ _JHB100_PLL(JHB100_SYS0PLL_PLL5_OUT, "pll5_out", NULL, 0,
+ JHB100_PLL5_OFFSET, CLK_IGNORE_UNUSED, true),
+};
+
+static const struct jhb100_pll_match_data jhb100_sys0_pll = {
+ .pll_info = jhb100_sys0_pll_info,
+ .num_pll = ARRAY_SIZE(jhb100_sys0_pll_info),
+};
+
+static const struct of_device_id jhb100_pll_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys0-syscon",
+ .data = &jhb100_sys0_pll,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_pll_match);
+
+static struct platform_driver jhb100_pll_driver = {
+ .driver = {
+ .name = "clk-starfive-jhb100-pll",
+ .of_match_table = jhb100_pll_match,
+ },
+};
+builtin_platform_driver_probe(jhb100_pll_driver, jhb100_pll_probe);
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 04/12] dt-bindings: clock: Add peripheral-0 domain PLL clock
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (2 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 03/12] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 05/12] clk: starfive: Add peripheral-0 domain PLL clock driver Changhuang Liang
` (8 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add peripheral-0 domain PLL clock for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
include/dt-bindings/clock/starfive,jhb100-crg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 98b3cf28b677..37a4535472bf 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -14,6 +14,9 @@
#define JHB100_SYS0PLL_PLL4_OUT 2
#define JHB100_SYS0PLL_PLL5_OUT 3
+/* PER0PLL clocks */
+#define JHB100_PER0PLL_PLL6_OUT 0
+
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN 17
#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG 18
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 05/12] clk: starfive: Add peripheral-0 domain PLL clock driver
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (3 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 04/12] dt-bindings: clock: Add peripheral-0 domain PLL clock Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 06/12] dt-bindings: clock: Add peripheral-1 domain PLL clock Changhuang Liang
` (7 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add peripheral-0 domain PLL clock driver support for StarFive JHB100
SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clk/starfive/clk-starfive-jhb100-pll.c | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
index 603b928bbb81..44a33afc04dd 100644
--- a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
@@ -28,6 +28,9 @@
#define JHB100_PLL4_OFFSET 0x18
#define JHB100_PLL5_OFFSET 0x24
+/* Peripheral-0 domain PLL */
+#define JHB100_PLL6_OFFSET 0x00
+
#define JHB100_PLL_CFG0_OFFSET 0x0
#define JHB100_PLL_CFG1_OFFSET 0x4
#define JHB100_PLL_CFG2_OFFSET 0x8
@@ -510,11 +513,37 @@ static const struct jhb100_pll_match_data jhb100_sys0_pll = {
.num_pll = ARRAY_SIZE(jhb100_sys0_pll_info),
};
+static const struct jhb100_pll_preset jhb100_pll6_presets[] = {
+ {
+ .freq = 2400000000,
+ .fbdiv = 192,
+ .frac = 0,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_info jhb100_per0_pll_info[] = {
+ JHB100_PLL(JHB100_PER0PLL_PLL6_OUT, "pll6_out", jhb100_pll6_presets,
+ ARRAY_SIZE(jhb100_pll6_presets), JHB100_PLL6_OFFSET, false),
+};
+
+static const struct jhb100_pll_match_data jhb100_per0_pll = {
+ .pll_info = jhb100_per0_pll_info,
+ .num_pll = ARRAY_SIZE(jhb100_per0_pll_info),
+};
+
static const struct of_device_id jhb100_pll_match[] = {
{
.compatible = "starfive,jhb100-sys0-syscon",
.data = &jhb100_sys0_pll,
},
+ {
+ .compatible = "starfive,jhb100-per0-syscon",
+ .data = (void *)&jhb100_per0_pll,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jhb100_pll_match);
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 06/12] dt-bindings: clock: Add peripheral-1 domain PLL clock
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (4 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 05/12] clk: starfive: Add peripheral-0 domain PLL clock driver Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 07/12] clk: starfive: Add Peripheral-1 domain PLL clock driver Changhuang Liang
` (6 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add peripheral-1 domain PLL clock for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
include/dt-bindings/clock/starfive,jhb100-crg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 37a4535472bf..4270bfa532e8 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -17,6 +17,9 @@
/* PER0PLL clocks */
#define JHB100_PER0PLL_PLL6_OUT 0
+/* PER1PLL clocks */
+#define JHB100_PER1PLL_PLL7_OUT 0
+
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN 17
#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG 18
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 07/12] clk: starfive: Add Peripheral-1 domain PLL clock driver
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (5 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 06/12] dt-bindings: clock: Add peripheral-1 domain PLL clock Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 08/12] dt-bindings: reset: Add StarFive JHB100 reset generator Changhuang Liang
` (5 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add Peripheral-1 domain PLL clock driver support for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clk/starfive/clk-starfive-jhb100-pll.c | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
index 44a33afc04dd..50bfb76634d1 100644
--- a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
@@ -31,6 +31,9 @@
/* Peripheral-0 domain PLL */
#define JHB100_PLL6_OFFSET 0x00
+/* Peripheral-1 domain PLL */
+#define JHB100_PLL7_OFFSET 0x40
+
#define JHB100_PLL_CFG0_OFFSET 0x0
#define JHB100_PLL_CFG1_OFFSET 0x4
#define JHB100_PLL_CFG2_OFFSET 0x8
@@ -535,6 +538,28 @@ static const struct jhb100_pll_match_data jhb100_per0_pll = {
.num_pll = ARRAY_SIZE(jhb100_per0_pll_info),
};
+static const struct jhb100_pll_preset jhb100_pll7_presets[] = {
+ {
+ .freq = 1950000000,
+ .fbdiv = 156,
+ .frac = 0,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_info jhb100_per1_pll_info[] = {
+ JHB100_PLL(JHB100_PER1PLL_PLL7_OUT, "pll7_out", jhb100_pll7_presets,
+ ARRAY_SIZE(jhb100_pll7_presets), JHB100_PLL7_OFFSET, false),
+};
+
+static const struct jhb100_pll_match_data jhb100_per1_pll = {
+ .pll_info = jhb100_per1_pll_info,
+ .num_pll = ARRAY_SIZE(jhb100_per1_pll_info),
+};
+
static const struct of_device_id jhb100_pll_match[] = {
{
.compatible = "starfive,jhb100-sys0-syscon",
@@ -544,6 +569,10 @@ static const struct of_device_id jhb100_pll_match[] = {
.compatible = "starfive,jhb100-per0-syscon",
.data = (void *)&jhb100_per0_pll,
},
+ {
+ .compatible = "starfive,jhb100-per1-syscon",
+ .data = (void *)&jhb100_per1_pll,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jhb100_pll_match);
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 08/12] dt-bindings: reset: Add StarFive JHB100 reset generator
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (6 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 07/12] clk: starfive: Add Peripheral-1 domain PLL clock driver Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 09/12] reset: starfive: Introduce assert_polarity Changhuang Liang
` (4 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add bindings for thr reset generator which locates in pcierp syscon.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
include/dt-bindings/reset/starfive,jhb100-crg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index 872a4dd25beb..1489bb01c2bd 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -183,4 +183,7 @@
#define JHB100_PER3RST_MAIN_RSTN_PERIPH3_SENSORS 5
#define JHB100_PER3RST_IOMUX_PRESETN 6
+/* PCIERP SYSCON resets */
+#define JHB100_PCIERP_SYSCONRST_PE2RST_OUT 0
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 09/12] reset: starfive: Introduce assert_polarity
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (7 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 08/12] dt-bindings: reset: Add StarFive JHB100 reset generator Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 10/12] reset: starfive: Add syscon reset driver support Changhuang Liang
` (3 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
The JHB100 SoC supports inverted operations for reset
assertion/deassertion, introducing the an assert_polarity field to
distinguish between different operation logics.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/reset/starfive/reset-starfive-common.c | 18 +++++++++++++++---
drivers/reset/starfive/reset-starfive-common.h | 6 ++++++
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/starfive/reset-starfive-common.c b/drivers/reset/starfive/reset-starfive-common.c
index 8ea142ecbd15..c7289c2b2a28 100644
--- a/drivers/reset/starfive/reset-starfive-common.c
+++ b/drivers/reset/starfive/reset-starfive-common.c
@@ -68,7 +68,7 @@ static int starfive_reset_update(struct reset_controller_dev *rcdev,
reg_status = data->status + offset * sizeof(u32);
done = data->asserted ? data->asserted[offset] & mask : 0;
- if (!assert)
+ if (data->info && data->info->assert_polarity == assert)
done ^= mask;
spin_lock_irqsave(&data->lock, flags);
@@ -90,13 +90,25 @@ static int starfive_reset_update(struct reset_controller_dev *rcdev,
static int starfive_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
- return starfive_reset_update(rcdev, id, true);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
+ bool assert = true;
+
+ if (data->info && data->info->assert_polarity)
+ assert = false;
+
+ return starfive_reset_update(rcdev, id, assert);
}
static int starfive_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
- return starfive_reset_update(rcdev, id, false);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
+ bool deassert = false;
+
+ if (data->info && data->info->assert_polarity)
+ deassert = true;
+
+ return starfive_reset_update(rcdev, id, deassert);
}
static int starfive_reset_reset(struct reset_controller_dev *rcdev,
diff --git a/drivers/reset/starfive/reset-starfive-common.h b/drivers/reset/starfive/reset-starfive-common.h
index ee457d9b90a3..d4017b8069fc 100644
--- a/drivers/reset/starfive/reset-starfive-common.h
+++ b/drivers/reset/starfive/reset-starfive-common.h
@@ -15,6 +15,12 @@ struct starfive_reset_info {
unsigned int nr_resets;
unsigned int assert_offset;
unsigned int status_offset;
+
+ /* If assert_polarity is false, setting the bit to 1 asserts
+ * the signal while clearing it to 0 deasserts it, and vice
+ * versa.
+ */
+ bool assert_polarity;
bool discontigous;
struct starfive_reset_map *map;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 10/12] reset: starfive: Add syscon reset driver support
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (8 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 09/12] reset: starfive: Introduce assert_polarity Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 11/12] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
` (2 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add syscon reset driver for JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/reset/starfive/Kconfig | 9 +++
drivers/reset/starfive/Makefile | 1 +
.../starfive/reset-starfive-jhb100-syscon.c | 62 +++++++++++++++++++
3 files changed, 72 insertions(+)
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100-syscon.c
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index ce00495be6ad..5ff73469acd2 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -28,3 +28,12 @@ config RESET_STARFIVE_JHB100
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JHB100 SoC.
+
+config RESET_STARFIVE_JHB100_SYSCON
+ bool "StarFive JHB100 SYSCON Reset Driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select RESET_STARFIVE_COMMON
+ default ARCH_STARFIVE
+ help
+ This enables the SYSCON reset controller driver for the StarFive
+ JHB100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 217002302a9f..d5033d723167 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
obj-$(CONFIG_RESET_STARFIVE_JHB100) += reset-starfive-jhb100.o
+obj-$(CONFIG_RESET_STARFIVE_JHB100_SYSCON) += reset-starfive-jhb100-syscon.o
diff --git a/drivers/reset/starfive/reset-starfive-jhb100-syscon.c b/drivers/reset/starfive/reset-starfive-jhb100-syscon.c
new file mode 100644
index 000000000000..830840148ba5
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jhb100-syscon.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * SYSCON Reset driver for the StarFive JHB110 SoC
+ *
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jhb100-crg.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <soc/starfive/reset-starfive-common.h>
+
+#include "reset-starfive-common.h"
+
+static const struct starfive_reset_info jhb100_pcierp_info = {
+ .nr_resets = JHB100_PCIERP_SYSCONRST_PE2RST_OUT + 1,
+ .assert_offset = 0x14c,
+ .status_offset = 0x14c,
+ .discontigous = false,
+ .assert_polarity = true,
+};
+
+static int jhb100_syscon_reset_probe(struct platform_device *pdev)
+{
+ struct starfive_reset_info *info;
+ void __iomem *base;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ info = (struct starfive_reset_info *)of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -ENODEV;
+
+ return reset_starfive_register_with_info(&pdev->dev, pdev->dev.of_node,
+ base + info->assert_offset,
+ base + info->status_offset,
+ NULL, info, NULL);
+}
+
+static const struct of_device_id jhb100_syscon_reset_dt_ids[] = {
+ {
+ .compatible = "starfive,jhb100-pcierp-syscon",
+ .data = &jhb100_pcierp_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_syscon_reset_dt_ids);
+
+static struct platform_driver jhb100_syscon_reset_driver = {
+ .probe = jhb100_syscon_reset_probe,
+ .driver = {
+ .name = "jhb100-syscon-reset",
+ .of_match_table = jhb100_syscon_reset_dt_ids,
+ },
+};
+module_platform_driver(jhb100_syscon_reset_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 SYSCON reset driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 11/12] soc: starfive: Add socinfo driver for JHB100 SoC
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (9 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 10/12] reset: starfive: Add syscon reset driver support Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 17:45 ` Conor Dooley
2026-05-12 8:35 ` [PATCH v2 12/12] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-05-12 17:40 ` [PATCH v2 00/12] Add StarFive JHB100 syscon modules Conor Dooley
12 siblings, 1 reply; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add socinfo driver for JHB100 SoC. Currently available for distinguishing
between the two reversions, A0 and A1.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 5 ++
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/starfive/Kconfig | 6 ++
drivers/soc/starfive/Makefile | 2 +
drivers/soc/starfive/socinfo/Kconfig | 11 +++
drivers/soc/starfive/socinfo/Makefile | 2 +
drivers/soc/starfive/socinfo/jhb100-socinfo.c | 80 +++++++++++++++++++
8 files changed, 108 insertions(+)
create mode 100644 drivers/soc/starfive/Kconfig
create mode 100644 drivers/soc/starfive/Makefile
create mode 100644 drivers/soc/starfive/socinfo/Kconfig
create mode 100644 drivers/soc/starfive/socinfo/Makefile
create mode 100644 drivers/soc/starfive/socinfo/jhb100-socinfo.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 6f6aac7cea95..66175f453d20 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25613,6 +25613,11 @@ S: Maintained
F: drivers/reset/starfive/reset-starfive-jhb1*
F: include/dt-bindings/reset/starfive,jhb1*.h
+STARFIVE JHB100 SOCINFO DRIVER
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: drivers/soc/starfive/
+
STARFIVE JHB100 SYSCON
M: Changhuang Liang <changhuang.liang@starfivetech.com>
S: Maintained
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index a2d65adffb80..b3b01fc38139 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig"
source "drivers/soc/rockchip/Kconfig"
source "drivers/soc/samsung/Kconfig"
source "drivers/soc/sophgo/Kconfig"
+source "drivers/soc/starfive/Kconfig"
source "drivers/soc/sunxi/Kconfig"
source "drivers/soc/tegra/Kconfig"
source "drivers/soc/ti/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index c9e689080ceb..009f85ff891a 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -30,6 +30,7 @@ obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
obj-y += sophgo/
+obj-y += starfive/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig
new file mode 100644
index 000000000000..04b020083d3e
--- /dev/null
+++ b/drivers/soc/starfive/Kconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "StarFive SoC (System On Chip) specific Drivers"
+
+source "drivers/soc/starfive/socinfo/Kconfig"
+
+endmenu
diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile
new file mode 100644
index 000000000000..ca1e609b8104
--- /dev/null
+++ b/drivers/soc/starfive/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += socinfo/
diff --git a/drivers/soc/starfive/socinfo/Kconfig b/drivers/soc/starfive/socinfo/Kconfig
new file mode 100644
index 000000000000..92bbab62895b
--- /dev/null
+++ b/drivers/soc/starfive/socinfo/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config STARFIVE_JHB100_SOCINFO
+ bool "StarFive JHB100 SoC Information"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select SOC_BUS
+ default y
+ help
+ Include support for the SoC bus socinfo for the StarFive JHB100 SoC
+ platforms to provide information about the SoC family and variant
+ to user space.
diff --git a/drivers/soc/starfive/socinfo/Makefile b/drivers/soc/starfive/socinfo/Makefile
new file mode 100644
index 000000000000..26c2bdf1de3b
--- /dev/null
+++ b/drivers/soc/starfive/socinfo/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_STARFIVE_JHB100_SOCINFO) += jhb100-socinfo.o
diff --git a/drivers/soc/starfive/socinfo/jhb100-socinfo.c b/drivers/soc/starfive/socinfo/jhb100-socinfo.c
new file mode 100644
index 000000000000..9c5826d7c253
--- /dev/null
+++ b/drivers/soc/starfive/socinfo/jhb100-socinfo.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/init.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include <linux/sys_soc.h>
+
+#define JHB100_REV_ID 0x38
+#define JHB100_REV_ID_CHAR GENMASK(3, 2)
+#define JHB100_REV_ID_NUM GENMASK(1, 0)
+
+static int __init starfive_socinfo_init(void)
+{
+ struct soc_device_attribute *attrs;
+ struct soc_device *soc_dev;
+ const char *machine = NULL;
+ struct device_node *np;
+ struct regmap *regmap;
+ char rev_char;
+ u32 rev_id;
+ int ret;
+
+ np = of_find_compatible_node(NULL, NULL, "starfive,jhb100-sys0-syscon");
+ if (!of_device_is_available(np)) {
+ of_node_put(np);
+ return -ENODEV;
+ }
+
+ regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(regmap)) {
+ of_node_put(np);
+ return PTR_ERR(regmap);
+ }
+
+ ret = regmap_read(regmap, JHB100_REV_ID, &rev_id);
+ if (ret) {
+ of_node_put(np);
+ return ret;
+ }
+
+ of_node_put(np);
+
+ rev_char = (char)FIELD_GET(JHB100_REV_ID_CHAR, rev_id) + 'A';
+ rev_id = (u32)FIELD_GET(JHB100_REV_ID_NUM, rev_id);
+
+ attrs = kzalloc_obj(*attrs);
+ if (!attrs)
+ return -ENOMEM;
+
+ np = of_find_node_by_path("/");
+ of_property_read_string(np, "model", &machine);
+ if (machine)
+ attrs->machine = kstrdup(machine, GFP_KERNEL);
+ of_node_put(np);
+
+ attrs->revision = kasprintf(GFP_KERNEL, "%c%u", rev_char, rev_id);
+ attrs->family = "JH";
+ attrs->soc_id = "JHB100";
+
+ soc_dev = soc_device_register(attrs);
+ if (IS_ERR(soc_dev)) {
+ kfree(attrs->revision);
+ kfree(attrs->machine);
+ kfree(attrs);
+ return PTR_ERR(soc_dev);
+ }
+
+ pr_info("StarFive %s SoC rev(%s)\n", attrs->soc_id, attrs->revision);
+
+ return 0;
+}
+
+early_initcall(starfive_socinfo_init);
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 11/12] soc: starfive: Add socinfo driver for JHB100 SoC
2026-05-12 8:35 ` [PATCH v2 11/12] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
@ 2026-05-12 17:45 ` Conor Dooley
0 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2026-05-12 17:45 UTC (permalink / raw)
To: Changhuang Liang
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing,
Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 6811 bytes --]
On Tue, May 12, 2026 at 01:35:20AM -0700, Changhuang Liang wrote:
> Add socinfo driver for JHB100 SoC. Currently available for distinguishing
> between the two reversions, A0 and A1.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> MAINTAINERS | 5 ++
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/starfive/Kconfig | 6 ++
> drivers/soc/starfive/Makefile | 2 +
> drivers/soc/starfive/socinfo/Kconfig | 11 +++
> drivers/soc/starfive/socinfo/Makefile | 2 +
> drivers/soc/starfive/socinfo/jhb100-socinfo.c | 80 +++++++++++++++++++
> 8 files changed, 108 insertions(+)
> create mode 100644 drivers/soc/starfive/Kconfig
> create mode 100644 drivers/soc/starfive/Makefile
> create mode 100644 drivers/soc/starfive/socinfo/Kconfig
> create mode 100644 drivers/soc/starfive/socinfo/Makefile
> create mode 100644 drivers/soc/starfive/socinfo/jhb100-socinfo.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6f6aac7cea95..66175f453d20 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -25613,6 +25613,11 @@ S: Maintained
> F: drivers/reset/starfive/reset-starfive-jhb1*
> F: include/dt-bindings/reset/starfive,jhb1*.h
>
> +STARFIVE JHB100 SOCINFO DRIVER
> +M: Changhuang Liang <changhuang.liang@starfivetech.com>
> +S: Maintained
> +F: drivers/soc/starfive/
FWIW, this is not what I asked for in v1, this should remain the full
path to the driver. I wanted you to add this directory back to the
"STARFIVE SOC DRIVERS" entry, since it's me that'll be applying patches
for this driver.
> +
> STARFIVE JHB100 SYSCON
> M: Changhuang Liang <changhuang.liang@starfivetech.com>
> S: Maintained
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index a2d65adffb80..b3b01fc38139 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig"
> source "drivers/soc/rockchip/Kconfig"
> source "drivers/soc/samsung/Kconfig"
> source "drivers/soc/sophgo/Kconfig"
> +source "drivers/soc/starfive/Kconfig"
> source "drivers/soc/sunxi/Kconfig"
> source "drivers/soc/tegra/Kconfig"
> source "drivers/soc/ti/Kconfig"
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index c9e689080ceb..009f85ff891a 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -30,6 +30,7 @@ obj-y += renesas/
> obj-y += rockchip/
> obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> obj-y += sophgo/
> +obj-y += starfive/
> obj-y += sunxi/
> obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-y += ti/
> diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig
> new file mode 100644
> index 000000000000..04b020083d3e
> --- /dev/null
> +++ b/drivers/soc/starfive/Kconfig
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +menu "StarFive SoC (System On Chip) specific Drivers"
> +
> +source "drivers/soc/starfive/socinfo/Kconfig"
> +
> +endmenu
> diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile
> new file mode 100644
> index 000000000000..ca1e609b8104
> --- /dev/null
> +++ b/drivers/soc/starfive/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-y += socinfo/
> diff --git a/drivers/soc/starfive/socinfo/Kconfig b/drivers/soc/starfive/socinfo/Kconfig
> new file mode 100644
> index 000000000000..92bbab62895b
> --- /dev/null
> +++ b/drivers/soc/starfive/socinfo/Kconfig
> @@ -0,0 +1,11 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +config STARFIVE_JHB100_SOCINFO
> + bool "StarFive JHB100 SoC Information"
> + depends on ARCH_STARFIVE || COMPILE_TEST
> + select SOC_BUS
> + default y
> + help
> + Include support for the SoC bus socinfo for the StarFive JHB100 SoC
> + platforms to provide information about the SoC family and variant
> + to user space.
> diff --git a/drivers/soc/starfive/socinfo/Makefile b/drivers/soc/starfive/socinfo/Makefile
> new file mode 100644
> index 000000000000..26c2bdf1de3b
> --- /dev/null
> +++ b/drivers/soc/starfive/socinfo/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_STARFIVE_JHB100_SOCINFO) += jhb100-socinfo.o
> diff --git a/drivers/soc/starfive/socinfo/jhb100-socinfo.c b/drivers/soc/starfive/socinfo/jhb100-socinfo.c
> new file mode 100644
> index 000000000000..9c5826d7c253
> --- /dev/null
> +++ b/drivers/soc/starfive/socinfo/jhb100-socinfo.c
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> + *
> + * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/init.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +#include <linux/sys_soc.h>
> +
> +#define JHB100_REV_ID 0x38
> +#define JHB100_REV_ID_CHAR GENMASK(3, 2)
> +#define JHB100_REV_ID_NUM GENMASK(1, 0)
> +
> +static int __init starfive_socinfo_init(void)
> +{
> + struct soc_device_attribute *attrs;
> + struct soc_device *soc_dev;
> + const char *machine = NULL;
> + struct device_node *np;
> + struct regmap *regmap;
> + char rev_char;
> + u32 rev_id;
> + int ret;
> +
> + np = of_find_compatible_node(NULL, NULL, "starfive,jhb100-sys0-syscon");
> + if (!of_device_is_available(np)) {
> + of_node_put(np);
> + return -ENODEV;
> + }
> +
> + regmap = syscon_node_to_regmap(np);
> + if (IS_ERR(regmap)) {
> + of_node_put(np);
> + return PTR_ERR(regmap);
> + }
> +
> + ret = regmap_read(regmap, JHB100_REV_ID, &rev_id);
> + if (ret) {
> + of_node_put(np);
> + return ret;
> + }
> +
> + of_node_put(np);
> +
> + rev_char = (char)FIELD_GET(JHB100_REV_ID_CHAR, rev_id) + 'A';
> + rev_id = (u32)FIELD_GET(JHB100_REV_ID_NUM, rev_id);
> +
> + attrs = kzalloc_obj(*attrs);
> + if (!attrs)
> + return -ENOMEM;
> +
> + np = of_find_node_by_path("/");
> + of_property_read_string(np, "model", &machine);
> + if (machine)
> + attrs->machine = kstrdup(machine, GFP_KERNEL);
> + of_node_put(np);
> +
> + attrs->revision = kasprintf(GFP_KERNEL, "%c%u", rev_char, rev_id);
> + attrs->family = "JH";
> + attrs->soc_id = "JHB100";
> +
> + soc_dev = soc_device_register(attrs);
> + if (IS_ERR(soc_dev)) {
> + kfree(attrs->revision);
> + kfree(attrs->machine);
> + kfree(attrs);
> + return PTR_ERR(soc_dev);
> + }
> +
> + pr_info("StarFive %s SoC rev(%s)\n", attrs->soc_id, attrs->revision);
> +
> + return 0;
> +}
> +
> +early_initcall(starfive_socinfo_init);
Does this really need to be an early initcall btw?
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 12/12] riscv: dts: starfive: jhb100: Add syscon nodes
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (10 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 11/12] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
@ 2026-05-12 8:35 ` Changhuang Liang
2026-05-12 17:40 ` [PATCH v2 00/12] Add StarFive JHB100 syscon modules Conor Dooley
12 siblings, 0 replies; 16+ messages in thread
From: Changhuang Liang @ 2026-05-12 8:35 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Changhuang Liang
Add syscon nodes for JHB100 RISC-V BMC SoC. They contain
pcieep0_ecsr_syscon | host0_syscon | husb0_syscon | husbd0_syscon |
pcieep1_ecsr_syscon | host1_syscon | husb1_syscon | husbd1_syscon |
gpu0_syscon | gpu1_syscon | husbcmn_syscon | b2h_syscon | h2b_syscon |
vout_syscon | pcierp_ecsr_syscon | pcierp_syscon | usb_syscon |
npu_syscon | per0_syscon | per1_syscon | per2_syscon | per3_syscon |
sys0_syscon | sys1_syscon | sys2_syscon | strap_syscon.
Also update the references of pll nodes.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jhb100.dtsi | 180 ++++++++++++++++++-----
1 file changed, 145 insertions(+), 35 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
index 943324b3b2fd..bbdc717399e5 100644
--- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -288,37 +288,7 @@ pll1: clock-pll1 {
clock-frequency = <1000000000>;
};
- pll2: clock-pll2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <903168000>;
- };
-
- pll4: clock-pll4 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100700000>;
- };
-
- pll5: clock-pll5 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100700000>;
- };
-
- pll6: clock-pll6 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <2400000000>;
- };
-
- pll7: clock-pll7 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1950000000>;
- };
-
- per2_gmac2_rgmii_rx: clock-per2-gmac2-rgmii-rx {
+ per2_gmac2_rgmii_rx: clock-per2-gmac2-rgmii-rx {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
@@ -399,6 +369,97 @@ bus_nioc: bus_nioc {
<0x4 0x00000000 0x4 0x00000000 0x2 0x0>;
ranges;
+ pcieep0_ecsr_syscon: syscon@10511000 {
+ compatible = "starfive,jhb100-pcieep-ecsr-syscon", "syscon";
+ reg = <0x0 0x10511000 0x0 0x1000>;
+ };
+
+ host0_syscon: syscon@10519000 {
+ compatible = "starfive,jhb100-host-syscon", "syscon";
+ reg = <0x0 0x10519000 0x0 0x1000>;
+ };
+
+ husb0_syscon: syscon@10695000 {
+ compatible = "starfive,jhb100-husb-syscon", "syscon";
+ reg = <0x0 0x10695000 0x0 0x800>;
+ };
+
+ husbd0_syscon: syscon@10695800 {
+ compatible = "starfive,jhb100-husbd-syscon", "syscon";
+ reg = <0x0 0x10695800 0x0 0x800>;
+ };
+
+ gpu0_syscon: syscon@10745000 {
+ compatible = "starfive,jhb100-gpu-syscon", "syscon";
+ reg = <0x0 0x10745000 0x0 0x1000>;
+ };
+
+ pcieep1_ecsr_syscon: syscon@10d11000 {
+ compatible = "starfive,jhb100-pcieep-ecsr-syscon", "syscon";
+ reg = <0x0 0x10d11000 0x0 0x1000>;
+ };
+
+ host1_syscon: syscon@10d19000 {
+ compatible = "starfive,jhb100-host-syscon", "syscon";
+ reg = <0x0 0x10d19000 0x0 0x1000>;
+ };
+
+ husb1_syscon: syscon@10e95000 {
+ compatible = "starfive,jhb100-husb-syscon", "syscon";
+ reg = <0x0 0x10e95000 0x0 0x800>;
+ };
+
+ husbd1_syscon: syscon@10e95800 {
+ compatible = "starfive,jhb100-husbd-syscon", "syscon";
+ reg = <0x0 0x10e95800 0x0 0x800>;
+ };
+
+ gpu1_syscon: syscon@10f45000 {
+ compatible = "starfive,jhb100-gpu-syscon", "syscon";
+ reg = <0x0 0x10f45000 0x0 0x1000>;
+ };
+
+ husbcmn_syscon: syscon@11045000 {
+ compatible = "starfive,jhb100-husbcmn-syscon", "syscon";
+ reg = <0x0 0x11045000 0x0 0x1000>;
+ };
+
+ b2h_syscon: syscon@11135000 {
+ compatible = "starfive,jhb100-b2h-syscon", "syscon";
+ reg = <0x0 0x11135000 0x0 0x400>;
+ };
+
+ h2b_syscon: syscon@11135400 {
+ compatible = "starfive,jhb100-h2b-syscon", "syscon";
+ reg = <0x0 0x11135400 0x0 0x200>;
+ };
+
+ vout_syscon: syscon@11135800 {
+ compatible = "starfive,jhb100-vout-syscon", "syscon";
+ reg = <0x0 0x11135800 0x0 0x400>;
+ };
+
+ pcierp_ecsr_syscon: syscon@11711000 {
+ compatible = "starfive,jhb100-pcierp-ecsr-syscon", "syscon";
+ reg = <0x0 0x11711000 0x0 0x1000>;
+ };
+
+ pcierp_syscon: syscon@11719000 {
+ compatible = "starfive,jhb100-pcierp-syscon", "syscon";
+ reg = <0x0 0x11719000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ usb_syscon: syscon@11820000 {
+ compatible = "starfive,jhb100-usb-syscon", "syscon";
+ reg = <0x0 0x11820000 0x0 0x10000>;
+ };
+
+ npu_syscon: syscon@118e5000 {
+ compatible = "starfive,jhb100-npu-syscon", "syscon";
+ reg = <0x0 0x118e5000 0x0 0x100>;
+ };
+
uart6: serial@11982000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x11982000 0x0 0x400>;
@@ -416,7 +477,8 @@ uart6: serial@11982000 {
per0crg: clock-controller@11a08000 {
compatible = "starfive,jhb100-per0crg";
reg = <0x0 0x11a08000 0x0 0x1000>;
- clocks = <&osc>, <&pll6>,
+ clocks = <&osc>,
+ <&per0_syscon JHB100_PER0PLL_PLL6_OUT>,
<&sys0crg JHB100_SYS0CLK_BMCPER0_CFG_400>,
<&sys0crg JHB100_SYS0CLK_BMCPER0_CFG_800>,
<&sys0crg JHB100_SYS0CLK_BMCPER0_NCNOC_INIT>,
@@ -428,10 +490,17 @@ per0crg: clock-controller@11a08000 {
#reset-cells = <1>;
};
+ per0_syscon: syscon@11a09000 {
+ compatible = "starfive,jhb100-per0-syscon", "syscon";
+ reg = <0x0 0x11a09000 0x0 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
per1crg: clock-controller@11b40000 {
compatible = "starfive,jhb100-per1crg";
reg = <0x0 0x11b40000 0x0 0x1000>;
- clocks = <&pll7>,
+ clocks = <&per1_syscon JHB100_PER1PLL_PLL7_OUT>,
<&sys0crg JHB100_SYS0CLK_BMCPER1_NCNOC_INIT>,
<&sys0crg JHB100_SYS0CLK_BMCPER1_CFG_800>,
<&sys2crg JHB100_SYS2CLK_BMCPER1_NCNOC_TARG>,
@@ -443,6 +512,13 @@ per1crg: clock-controller@11b40000 {
#reset-cells = <1>;
};
+ per1_syscon: syscon@11b41000 {
+ compatible = "starfive,jhb100-per1-syscon", "syscon";
+ reg = <0x0 0x11b41000 0x0 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
per2crg: clock-controller@11bc0000 {
compatible = "starfive,jhb100-per2crg";
reg = <0x0 0x11bc0000 0x0 0x1000>;
@@ -464,6 +540,11 @@ per2crg: clock-controller@11bc0000 {
#reset-cells = <1>;
};
+ per2_syscon: syscon@11bc1000 {
+ compatible = "starfive,jhb100-per2-syscon", "syscon";
+ reg = <0x0 0x11bc1000 0x0 0x1000>;
+ };
+
per3crg: clock-controller@11c40000 {
compatible = "starfive,jhb100-per3crg";
reg = <0x0 0x11c40000 0x0 0x1000>;
@@ -483,11 +564,16 @@ per3crg: clock-controller@11c40000 {
#reset-cells = <1>;
};
+ per3_syscon: syscon@11c41000 {
+ compatible = "starfive,jhb100-per3-syscon", "syscon";
+ reg = <0x0 0x11c41000 0x0 0x1000>;
+ };
+
sys0crg: clock-controller@13000000 {
compatible = "starfive,jhb100-sys0crg";
reg = <0x0 0x13000000 0x0 0x4000>;
clocks = <&osc>, <&pll0>, <&pll1>,
- <&pll2>;
+ <&sys0_syscon JHB100_SYS0PLL_PLL2_OUT>;
clock-names = "osc", "pll0", "pll1", "pll2";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -497,7 +583,9 @@ sys1crg: clock-controller@13004000 {
compatible = "starfive,jhb100-sys1crg";
reg = <0x0 0x13004000 0x0 0x4000>;
clocks = <&osc>, <&pll0>, <&pll1>,
- <&pll2>, <&pll4>, <&pll5>,
+ <&sys0_syscon JHB100_SYS0PLL_PLL2_OUT>,
+ <&sys0_syscon JHB100_SYS0PLL_PLL4_OUT>,
+ <&sys0_syscon JHB100_SYS0PLL_PLL5_OUT>,
<&sys0crg JHB100_SYS0CLK_NPU_NCNOC_INIT>;
clock-names = "osc", "pll0", "pll1", "pll2",
"pll4", "pll5", "npu_ncnoc_init";
@@ -517,6 +605,28 @@ sys2crg: clock-controller@13008000 {
#reset-cells = <1>;
};
+ sys0_syscon: syscon@13010000 {
+ compatible = "starfive,jhb100-sys0-syscon", "syscon";
+ reg = <0x0 0x13010000 0x0 0x2000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ sys1_syscon: syscon@13014000 {
+ compatible = "starfive,jhb100-sys1-syscon", "syscon";
+ reg = <0x0 0x13014000 0x0 0x4000>;
+ };
+
+ sys2_syscon: syscon@13018000 {
+ compatible = "starfive,jhb100-sys2-syscon", "syscon";
+ reg = <0x0 0x13018000 0x0 0x4000>;
+ };
+
+ strap_syscon: syscon@1301a000 {
+ compatible = "starfive,jhb100-strap-syscon", "syscon";
+ reg = <0x0 0x1301a000 0x0 0x2000>;
+ };
+
intc: interrupt-controller@13220000 {
compatible = "starfive,jhb100-intc";
reg = <0x0 0x13220000 0x0 0x80>;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 00/12] Add StarFive JHB100 syscon modules
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
` (11 preceding siblings ...)
2026-05-12 8:35 ` [PATCH v2 12/12] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
@ 2026-05-12 17:40 ` Conor Dooley
12 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2026-05-12 17:40 UTC (permalink / raw)
To: Changhuang Liang
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Brian Masney, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing,
Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 389 bytes --]
On Tue, May 12, 2026 at 01:35:09AM -0700, Changhuang Liang wrote:
> Changhuang Liang (12):
> dt-bindings: clock: Add system-0 domain PLL clock
> dt-bindings: clock: Add peripheral-0 domain PLL clock
> dt-bindings: clock: Add peripheral-1 domain PLL clock
> dt-bindings: reset: Add StarFive JHB100 reset generator
For these 4,
Acked-by: Conor Dooley <conor.dooley@microchip.com>
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^ permalink raw reply [flat|nested] 16+ messages in thread