* [PATCH] x86/locking: Use sfence for wmb() if SSE is available
@ 2026-08-01 18:29 Yao Zi
2026-08-03 6:22 ` Peter Zijlstra
0 siblings, 1 reply; 2+ messages in thread
From: Yao Zi @ 2026-08-01 18:29 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin, Randy Dunlap, Peter Zijlstra (Intel)
Cc: x86, linux-kernel, Yao Zi, stable
When adding cc clobber to wmb()'s definition, the alternative()
condition to use sfence was incorrectly raised from X86_FEATURE_XMM to
X86_FEATURE_XMM2.
Restore the correct constraint for potential better performance on
machines without SSE2.
Fixes: bd922477d935 ("locking/x86: Add cc clobber for ADDL")
Signed-off-by: Yao Zi <me@ziyao.cc>
Cc: stable@vger.kernel.org
---
arch/x86/include/asm/barrier.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
index b0096b5645a9..e0e59da15748 100644
--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -17,7 +17,7 @@
#define rmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "lfence", \
X86_FEATURE_XMM2) ::: "memory", "cc")
#define wmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "sfence", \
- X86_FEATURE_XMM2) ::: "memory", "cc")
+ X86_FEATURE_XMM) ::: "memory", "cc")
#else
#define __mb() asm volatile("mfence":::"memory")
#define __rmb() asm volatile("lfence":::"memory")
--
2.54.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] x86/locking: Use sfence for wmb() if SSE is available
2026-08-01 18:29 [PATCH] x86/locking: Use sfence for wmb() if SSE is available Yao Zi
@ 2026-08-03 6:22 ` Peter Zijlstra
0 siblings, 0 replies; 2+ messages in thread
From: Peter Zijlstra @ 2026-08-03 6:22 UTC (permalink / raw)
To: Yao Zi
Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin, Randy Dunlap, x86, linux-kernel, stable
On Sat, Aug 01, 2026 at 06:29:53PM +0000, Yao Zi wrote:
> When adding cc clobber to wmb()'s definition, the alternative()
> condition to use sfence was incorrectly raised from X86_FEATURE_XMM to
> X86_FEATURE_XMM2.
>
> Restore the correct constraint for potential better performance on
> machines without SSE2.
So Google tells me that SSE was introduced with P-III, while SSE2 was
introduced with P4, so this affects only P-III.
Anything earlier won't care, and anything later will have DTRT.
I suppose we can do this, for those few people that still care about
P-III... *sigh*.
> Fixes: bd922477d935 ("locking/x86: Add cc clobber for ADDL")
> Signed-off-by: Yao Zi <me@ziyao.cc>
> Cc: stable@vger.kernel.org
> ---
> arch/x86/include/asm/barrier.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
> index b0096b5645a9..e0e59da15748 100644
> --- a/arch/x86/include/asm/barrier.h
> +++ b/arch/x86/include/asm/barrier.h
> @@ -17,7 +17,7 @@
> #define rmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "lfence", \
> X86_FEATURE_XMM2) ::: "memory", "cc")
> #define wmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "sfence", \
> - X86_FEATURE_XMM2) ::: "memory", "cc")
> + X86_FEATURE_XMM) ::: "memory", "cc")
> #else
> #define __mb() asm volatile("mfence":::"memory")
> #define __rmb() asm volatile("lfence":::"memory")
> --
> 2.54.0
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2026-08-03 6:22 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-01 18:29 [PATCH] x86/locking: Use sfence for wmb() if SSE is available Yao Zi
2026-08-03 6:22 ` Peter Zijlstra
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox