From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Leo Yan <leo.yan@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [PATCH v2 8/9] coresight: Make clock sequence consistent
Date: Fri, 2 May 2025 12:26:22 +0530 [thread overview]
Message-ID: <2b39dd04-9b3a-4b50-99d5-e3a45cc3f374@arm.com> (raw)
In-Reply-To: <20250423151726.372561-9-leo.yan@arm.com>
On 4/23/25 20:47, Leo Yan wrote:
> Since atclk is enabled after pclk during the probe phase, this commit
> maintains the same sequence for the runtime resume flow.
which is also the exact opposite of the suspend flow as expected.
>
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-funnel.c | 6 +++---
> drivers/hwtracing/coresight/coresight-replicator.c | 6 +++---
> drivers/hwtracing/coresight/coresight-stm.c | 6 +++---
> drivers/hwtracing/coresight/coresight-tpiu.c | 6 +++---
> 4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
> index 173fee3aaa6e..62e5125c37ad 100644
> --- a/drivers/hwtracing/coresight/coresight-funnel.c
> +++ b/drivers/hwtracing/coresight/coresight-funnel.c
> @@ -296,11 +296,11 @@ static int funnel_runtime_resume(struct device *dev)
> {
> struct funnel_drvdata *drvdata = dev_get_drvdata(dev);
>
> - if (drvdata && !IS_ERR(drvdata->atclk))
> - clk_prepare_enable(drvdata->atclk);
> -
> if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
> clk_prepare_enable(drvdata->pclk);
> +
> + if (drvdata && !IS_ERR(drvdata->atclk))
> + clk_prepare_enable(drvdata->atclk);
> return 0;
> }
> #endif
> diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
> index 7250a2174145..56b03e6d8336 100644
> --- a/drivers/hwtracing/coresight/coresight-replicator.c
> +++ b/drivers/hwtracing/coresight/coresight-replicator.c
> @@ -334,11 +334,11 @@ static int replicator_runtime_resume(struct device *dev)
> {
> struct replicator_drvdata *drvdata = dev_get_drvdata(dev);
>
> - if (drvdata && !IS_ERR(drvdata->atclk))
> - clk_prepare_enable(drvdata->atclk);
> -
> if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
> clk_prepare_enable(drvdata->pclk);
> +
> + if (drvdata && !IS_ERR(drvdata->atclk))
> + clk_prepare_enable(drvdata->atclk);
> return 0;
> }
> #endif
> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
> index 89e90e7f54de..f17986edac00 100644
> --- a/drivers/hwtracing/coresight/coresight-stm.c
> +++ b/drivers/hwtracing/coresight/coresight-stm.c
> @@ -969,11 +969,11 @@ static int stm_runtime_resume(struct device *dev)
> {
> struct stm_drvdata *drvdata = dev_get_drvdata(dev);
>
> - if (drvdata && !IS_ERR(drvdata->atclk))
> - clk_prepare_enable(drvdata->atclk);
> -
> if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
> clk_prepare_enable(drvdata->pclk);
> +
> + if (drvdata && !IS_ERR(drvdata->atclk))
> + clk_prepare_enable(drvdata->atclk);
> return 0;
> }
> #endif
> diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
> index b3d0db0e53b9..4701b34778bd 100644
> --- a/drivers/hwtracing/coresight/coresight-tpiu.c
> +++ b/drivers/hwtracing/coresight/coresight-tpiu.c
> @@ -218,11 +218,11 @@ static int tpiu_runtime_resume(struct device *dev)
> {
> struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
>
> - if (drvdata && !IS_ERR(drvdata->atclk))
> - clk_prepare_enable(drvdata->atclk);
> -
> if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
> clk_prepare_enable(drvdata->pclk);
> +
> + if (drvdata && !IS_ERR(drvdata->atclk))
> + clk_prepare_enable(drvdata->atclk);
> return 0;
> }
> #endif
These also matches the clock initialization sequence during probe()
via the new helper coresight_get_enable_clocks().
LGTM.
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
next prev parent reply other threads:[~2025-05-02 6:56 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-23 15:17 [PATCH v2 0/9] coresight: Fix and improve clock usage Leo Yan
2025-04-23 15:17 ` [PATCH v2 1/9] coresight: tmc: Support atclk Leo Yan
2025-04-23 15:17 ` [PATCH v2 2/9] coresight: catu: " Leo Yan
2025-04-23 15:17 ` [PATCH v2 3/9] coresight: etm4x: " Leo Yan
2025-04-23 15:17 ` [PATCH v2 4/9] coresight: Disable programming clock properly Leo Yan
2025-05-02 6:10 ` Anshuman Khandual
2025-05-06 9:54 ` Leo Yan
2025-05-07 5:59 ` Anshuman Khandual
2025-04-23 15:17 ` [PATCH v2 5/9] coresight: Disable trace bus " Leo Yan
2025-05-02 6:31 ` Anshuman Khandual
2025-04-23 15:17 ` [PATCH v2 6/9] coresight: Avoid enable programming clock duplicately Leo Yan
2025-05-02 6:38 ` Anshuman Khandual
2025-05-06 9:18 ` Leo Yan
2025-05-07 5:55 ` Anshuman Khandual
2025-04-23 15:17 ` [PATCH v2 7/9] coresight: Consolidate clock enabling Leo Yan
2025-05-05 7:28 ` Anshuman Khandual
2025-05-06 10:53 ` Leo Yan
2025-05-07 5:51 ` Anshuman Khandual
2025-04-23 15:17 ` [PATCH v2 8/9] coresight: Make clock sequence consistent Leo Yan
2025-05-02 6:56 ` Anshuman Khandual [this message]
2025-04-23 15:17 ` [PATCH v2 9/9] coresight: Refactor runtime PM Leo Yan
2025-05-02 8:45 ` Anshuman Khandual
2025-05-06 10:16 ` Leo Yan
2025-05-07 5:39 ` Anshuman Khandual
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