From: Yidong Zhang <yidong.zhang@amd.com>
To: Xu Yilun <yilun.xu@linux.intel.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-fpga@vger.kernel.org>,
<mdf@kernel.org>, <hao.wu@intel.com>, <yilun.xu@intel.com>,
<lizhi.hou@amd.com>, DMG Karthik <Karthik.DMG@amd.com>,
Nishad Saraf <nishads@amd.com>,
Prapul Krishnamurthy <prapulk@amd.com>,
Hayden Laccabue <hayden.laccabue@amd.com>
Subject: Re: [PATCH V2 1/4] drivers/fpga/amd: Add new driver amd versal-pci
Date: Sun, 26 Jan 2025 11:46:54 -0800 [thread overview]
Message-ID: <3b520bab-d948-470a-b06f-5494243ebc1a@amd.com> (raw)
In-Reply-To: <Z5YPWHVmL29zuQNm@yilunxu-OptiPlex-7050>
On 1/26/25 02:32, Xu Yilun wrote:
> Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
>
>
> On Tue, Dec 10, 2024 at 10:37:30AM -0800, Yidong Zhang wrote:
>> AMD Versal based PCIe card, including V70, is designed for AI inference
>> efficiency and is tuned for video analytics and natural language processing
>> applications.
>>
>> The driver architecture:
>>
>> +---------+ Communication +---------+ Remote +-----+------+
>> | | Channel | | Queue | | |
>> | User PF | <============> | Mgmt PF | <=======>| FW | FPGA |
>> +---------+ +---------+ +-----+------+
>> PL Data base FW
>> APU FW
>> PL Data (copy)
>> - PL (FPGA Program Logic)
>> - FW (Firmware)
>>
>> There are 2 separate drivers from the original XRT[1] design.
>> - UserPF driver
>> - MgmtPF driver
>>
>> The new AMD versal-pci driver will replace the MgmtPF driver for Versal
>> PCIe card.
>>
>> The XRT[1] is already open-sourced. It includes solution of runtime for
>> many different type of PCIe Based cards. It also provides utilities for
>> managing and programming the devices.
>>
>> The AMD versal-pci stands for AMD Versal brand PCIe device management
>> driver. This driver provides the following functionalities:
>>
>> - module and PCI device initialization
>> this driver will attach to specific device id of V70 card;
>> the driver will initialize itself based on bar resources for
>> - communication channel:
>> a hardware message service between mgmt PF and user PF
>> - remote queue:
>> a hardware queue based ring buffer service between mgmt PF and PCIe
>> hardware firmware for programming FPGA Program Logic, loading
>> firmware and checking card healthy status.
>>
>> - programming FW
>> - The base FW is downloaded onto the flash of the card.
>> - The APU FW is downloaded once after a POR (power on reset).
>> - Reloading the MgmtPF driver will not change any existing hardware.
>>
>> - programming FPGA hardware binaries - PL Data
>> - using fpga framework ops to support re-programing FPGA
>> - the re-programming request will be initiated from the existing UserPF
>> driver only, and the MgmtPF driver load the matched PL Data after
>> receiving request from the communication channel. The matching PL
>
> I think this is not the way the FPGA generic framework should do. A FPGA
> region user (your userPF driver) should not also be the reprogram requester.
> The user driver cannot deal with the unexpected HW change if it happens.
> Maybe after reprogramming, the user driver cannot match the device
> anymore, and if user driver is still working on it, crash.
One thing to clarify. The current design is:
The userPF driver is the only requester. The mgmtPF has no uAPI to
reprogram the FPGA.
>
> The expected behavior is, the FPGA region removes user devices (thus
> detaches user drivers), does reprogramming, re-enumerates/rescans and
> matches new devices with new drivers. And I think that's what Nava is
> working on.
>
Nava's work is different than our current design, our current design is:
the separate userPF driver will detach all services before requesting to
the mgmtPF to program the FPGA, and after the programming is done, the
userPF will re-enumerate/rescan the matching new devices.
The mgmtPF is a util driver which is responsible for communicating with
the mgmtPF PCIe bar resources.
> BTW, AFAICS the expected flow is easier to implement for of-fpga-region,
> but harder for PCI devices. But I think that's the right direction and
> should try to work it out.
Could I recap the suggested design if I understand that correctly...
You are thinking that the mgmtPF (aka. versal-pci) driver should have a
uAPI to trigger the FPGA re-programing; and using Nava's callback ops to
detach the separate userPF driver; after re-programing is done, re-attch
the userPF driver and allow the userPF driver re-enumerate all to match
the new hardware.
I think my understanding is correct, it is doable.
As long as we can keep our userPF driver as separate driver, the code
change won't be too big.
>
> Thanks,
> Yilun
next prev parent reply other threads:[~2025-01-26 19:47 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-10 18:37 [PATCH V2 0/4] Add versal-pci driver Yidong Zhang
2024-12-10 18:37 ` [PATCH V2 1/4] drivers/fpga/amd: Add new driver amd versal-pci Yidong Zhang
2025-01-26 9:24 ` Xu Yilun
2025-01-26 19:50 ` Yidong Zhang
2025-01-26 10:12 ` Christophe JAILLET
2025-01-26 19:56 ` Yidong Zhang
2025-01-26 10:16 ` Christophe JAILLET
2025-01-26 10:32 ` Xu Yilun
2025-01-26 19:46 ` Yidong Zhang [this message]
2025-02-06 4:15 ` Xu Yilun
2025-02-06 4:31 ` Yidong Zhang
2025-02-07 2:19 ` Xu Yilun
2025-02-07 3:16 ` Yidong Zhang
2025-02-07 4:40 ` Xu Yilun
2025-02-10 11:33 ` Yidong Zhang
2025-02-11 9:09 ` Xu Yilun
2025-02-11 11:31 ` Yidong Zhang
2025-03-01 8:20 ` Xu Yilun
2025-03-01 19:03 ` Yidong Zhang
2025-03-03 7:57 ` Xu Yilun
2025-03-03 17:00 ` Yidong Zhang
2024-12-10 18:37 ` [PATCH V2 2/4] drivers/fpga/amd: Add communication channel Yidong Zhang
2025-01-26 10:19 ` Christophe JAILLET
2025-01-26 19:57 ` Yidong Zhang
2024-12-10 18:37 ` [PATCH V2 3/4] drivers/fpga/amd: Add remote queue Yidong Zhang
2025-01-26 10:24 ` Christophe JAILLET
2024-12-10 18:37 ` [PATCH V2 4/4] drivers/fpga/amd: Add load xclbin and load firmware Yidong Zhang
2025-01-26 9:27 ` [PATCH V2 0/4] Add versal-pci driver Xu Yilun
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