From: Xu Yilun <yilun.xu@linux.intel.com>
To: Yidong Zhang <yidong.zhang@amd.com>
Cc: linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org,
mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com,
lizhi.hou@amd.com
Subject: Re: [PATCH V2 0/4] Add versal-pci driver
Date: Sun, 26 Jan 2025 17:27:45 +0800 [thread overview]
Message-ID: <Z5YAEXtUWgB82JD3@yilunxu-OptiPlex-7050> (raw)
In-Reply-To: <20241210183734.30803-1-yidong.zhang@amd.com>
On Tue, Dec 10, 2024 at 10:37:29AM -0800, Yidong Zhang wrote:
> This patchset introduces a new Linux Kernel Driver, versal-pci for AMD
> Alevo Versal based PCIe Card. The driver is based on Linux fpga driver
> framework.
>
> The AMD Alevo Versal based PCIe Card, including V70, is the first Alevo
> production card leveraging AMD XDNA architecture with AI Engines. It is
> designed for AI inference efficiency and is tuned for video analytics and
> natural language processing applications [1].
>
> This versal-pci driver provides services, including:
> - leveraging linux firmware and FPGA framework to download management
> firmware
> - program additional bit-streams for AMD Xilinx specific hardware
> - communicate with PCIe user function
> - communicate with firmware running on the PCIe Card
> - monitor device health
>
> The driver is licensed under GPL-2.0.
>
> The firmware and bit-streams are distributed as a closed binary, delivered
> by AMD. Please see [1] for more information.
>
> [1] https://www.amd.com/en/products/accelerators/alveo/v70.html
>
> Refactor driver to address all comments from v1.
> Changes since v1:
> - Add driver architecture description.
> - Change the driver name to versal-pci
> - Remove unnecessary memcpy in versal-pci-comm-chan.c
> - Keep mod_timer because we need single_threaded_queue with delayed_work.
> - Change the "comms" to "comm_chan".
> - Remove regmap, use base+offset directly.
> - Add skeleton ops with on implementation (TODO) for fpga_manager in early
> patch (0001) and add implementation in later patch(0004).
> - Remove br_ops and FPGA region, no need.
I never said FPGA region is no need. FPGA region is the essential for
managing the reprogramming and re-enumeration.
Thanks,
Yilun
prev parent reply other threads:[~2025-01-26 9:28 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-10 18:37 [PATCH V2 0/4] Add versal-pci driver Yidong Zhang
2024-12-10 18:37 ` [PATCH V2 1/4] drivers/fpga/amd: Add new driver amd versal-pci Yidong Zhang
2025-01-26 9:24 ` Xu Yilun
2025-01-26 19:50 ` Yidong Zhang
2025-01-26 10:12 ` Christophe JAILLET
2025-01-26 19:56 ` Yidong Zhang
2025-01-26 10:16 ` Christophe JAILLET
2025-01-26 10:32 ` Xu Yilun
2025-01-26 19:46 ` Yidong Zhang
2025-02-06 4:15 ` Xu Yilun
2025-02-06 4:31 ` Yidong Zhang
2025-02-07 2:19 ` Xu Yilun
2025-02-07 3:16 ` Yidong Zhang
2025-02-07 4:40 ` Xu Yilun
2025-02-10 11:33 ` Yidong Zhang
2025-02-11 9:09 ` Xu Yilun
2025-02-11 11:31 ` Yidong Zhang
2025-03-01 8:20 ` Xu Yilun
2025-03-01 19:03 ` Yidong Zhang
2025-03-03 7:57 ` Xu Yilun
2025-03-03 17:00 ` Yidong Zhang
2024-12-10 18:37 ` [PATCH V2 2/4] drivers/fpga/amd: Add communication channel Yidong Zhang
2025-01-26 10:19 ` Christophe JAILLET
2025-01-26 19:57 ` Yidong Zhang
2024-12-10 18:37 ` [PATCH V2 3/4] drivers/fpga/amd: Add remote queue Yidong Zhang
2025-01-26 10:24 ` Christophe JAILLET
2024-12-10 18:37 ` [PATCH V2 4/4] drivers/fpga/amd: Add load xclbin and load firmware Yidong Zhang
2025-01-26 9:27 ` Xu Yilun [this message]
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