From: Thomas Gleixner <tglx@kernel.org>
To: Michael Kelley <mhklinux@outlook.com>,
LKML <linux-kernel@vger.kernel.org>
Cc: "x86@kernel.org" <x86@kernel.org>,
Dmitry Ilvokhin <d@ilvokhin.com>, Radu Rendec <radu@rendec.net>,
Jan Kiszka <jan.kiszka@siemens.com>,
Kieran Bingham <kbingham@kernel.org>,
Florian Fainelli <florian.fainelli@broadcom.com>,
Marc Zyngier <maz@kernel.org>
Subject: RE: [patch V5 00/15] Improve /proc/interrupts further
Date: Mon, 11 May 2026 17:45:30 +0200 [thread overview]
Message-ID: <87ecji7xwl.ffs@tglx> (raw)
In-Reply-To: <SN6PR02MB415762C7718ECDBD0D127A60D451A@SN6PR02MB4157.namprd02.prod.outlook.com>
On Thu, Apr 02 2026 at 02:32, Michael Kelley wrote:
> On x86, the leftmost column now correctly aligns the "VPMI:" label.
> But the rightmost column does not correctly align the text
> "Perf Guest Mediated PMI". It needs one additional space. Here's my
> output (with some CPU columns removed so it's not so wide):
>
> root@mhkubun:~# cat /proc/interrupts | cut -b 1-30,64-
> CPU0 CPU1 CPU5 CPU6 CPU7
> PIW: 0 0 0 0 0 Posted-interrupt wakeup event
> VPMI: 0 0 0 0 0 Perf Guest Mediated PMI
Right. There is a missing space in the VPMI text.
> On arm64, the leftmost column doesn't align the IPI<n> entries.
> Neither does the rightmost column for the IPI<n> entries. Here's some
> of my output:
>
> 45: 0 0 80 0 0 HV-PCI-MSIX-0817:00:02.0 14 Edge mlx5_comp13@pci:0817:00:02.0
> 46: 0 0 0 10 0 HV-PCI-MSIX-0817:00:02.0 15 Edge mlx5_comp14@pci:0817:00:02.0
> 47: 0 0 0 0 45 HV-PCI-MSIX-0817:00:02.0 16 Edge mlx5_comp15@pci:0817:00:02.0
> IPI0: 906 536 649 495 606 Rescheduling interrupts
> IPI1: 28844 12457 14770 55242 39175 Function call interrupts
> IPI2: 0 0 0 0 0 CPU stop interrupts
> IPI3: 0 0 0 0 0 CPU stop NMIs
> IPI4: 0 0 0 0 0 Timer broadcast interrupts
> IPI5: 11 1 5 0 2 IRQ work interrupts
> IPI6: 0 0 0 0 0 CPU backtrace interrupts
> IPI7: 0 0 0 0 0 KGDB roundup interrupts
That means total_nr_irqs is < 1000, which makes it use precision of
3. That obiously is not enough for the IPIn output and already an issue
today. The IPI text is misaligned on ARM64 already today in pretty much
the same way as with the patches applied. That's trivial to fix.
As a bonus ARM(64) has quite some interrupt chips which have their own
print routine to show the interupt chip name. That makes it even more
randomly aligned. That's also an existing problem and a larger
effort to mop up and as it's already a mess. I leave it so.
x86 suffers from the leftmost column issue as well when you make NR_CPUS
small enough in case that VPMI is emitted because the default precision
in the core is 3 digits.
Thanks,
tglx
prev parent reply other threads:[~2026-05-11 15:45 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260401195625.213446764@kernel.org>
[not found] ` <20260401201348.355938635@kernel.org>
[not found] ` <bb079a11992a63b30b23de438648932182a351ca.camel@rendec.net>
2026-05-11 14:38 ` [patch V5 05/15] x86/irq: Suppress unlikely interrupt stats by default Thomas Gleixner
[not found] ` <SN6PR02MB415762C7718ECDBD0D127A60D451A@SN6PR02MB4157.namprd02.prod.outlook.com>
2026-05-11 15:45 ` Thomas Gleixner [this message]
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