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* [PATCH] x86/cpufeatures: Move the definition of X86_FEATURE_AMX_* to the word 18
@ 2022-01-17  6:23 Like Xu
  2022-01-17  8:24 ` Paolo Bonzini
  2022-01-18 17:11 ` Dave Hansen
  0 siblings, 2 replies; 10+ messages in thread
From: Like Xu @ 2022-01-17  6:23 UTC (permalink / raw)
  To: Thomas Gleixner, Dave Hansen
  Cc: Ingo Molnar, Borislav Petkov, H . Peter Anvin, x86, Paolo Bonzini,
	Jing Liu, linux-kernel

From: Like Xu <likexu@tencent.com>

We have defined the word 18 for Intel-defined CPU features from CPUID level
0x00000007:0 (EDX). Let's move the definitions of X86_FEATURE_AMX_* to the
right entry to prevent misinterpretation. No functional change intended.

Signed-off-by: Like Xu <likexu@tencent.com>
---
 arch/x86/include/asm/cpufeatures.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 6db4e2932b3d..5cd22090e53d 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,9 +299,6 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
-#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */
-#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */
-#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
@@ -390,7 +387,10 @@
 #define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
+#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */
 #define X86_FEATURE_AVX512_FP16		(18*32+23) /* AVX512 FP16 */
+#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */
+#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
 #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */
-- 
2.33.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2022-02-08  9:21 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-01-17  6:23 [PATCH] x86/cpufeatures: Move the definition of X86_FEATURE_AMX_* to the word 18 Like Xu
2022-01-17  8:24 ` Paolo Bonzini
2022-01-18 17:11 ` Dave Hansen
2022-01-18 17:15   ` Paolo Bonzini
2022-01-19  3:41     ` Like Xu
2022-01-29 14:19       ` Borislav Petkov
2022-02-08  8:08         ` Like Xu
2022-02-08  8:51           ` Borislav Petkov
2022-02-08  9:06             ` Like Xu
2022-02-08  9:21               ` Borislav Petkov

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