Re: [PATCH] arm64: dts: qcom: x1e80100: Add the watchdog device

[Abel Vesa <abel.vesa@linaro.org>]

On 25-02-06 11:44:18, Johan Hovold wrote:
> On Thu, Feb 06, 2025 at 12:37:13PM +0200, Abel Vesa wrote:
> > From: Rajendra Nayak <quic_rjendra@quicinc.com>
> > 
> > The X Elite implements Server Base System Architecture (SBSA) specification
> > compliant generic watchdog.
> > 
> > Describe it.
> > 
> > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > index 9d38436763432892ceef95daf0335d4cf446357c..007815699e4b9137c3b5cf72263c9dd3a64e6bb3 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > @@ -3708,6 +3708,13 @@ pcie4_phy: phy@1c0e000 {
> >  			status = "disabled";
> >  		};
> >  
> > +		watchdog@1c840000 {
> 
> Please keep the nodes sorted by unit address. Looks like this ones goes
> much further down.

Oups. Yes, you are right. Will move and respin.

> 
> > +			compatible = "arm,sbsa-gwdt";
> > +			reg = <0 0x1c840000 0 0x1000>,
> > +			      <0 0x1c850000 0 0x1000>;
> > +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > +		};
> > +
> >  		tcsr_mutex: hwlock@1f40000 {
> >  			compatible = "qcom,tcsr-mutex";
> >  			reg = <0 0x01f40000 0 0x20000>;
> 
> Johan

Thanks for reviewing,

Abel