* [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq()
@ 2024-01-22 15:19 Dan Carpenter
2024-01-22 15:21 ` [PATCH v3 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() Dan Carpenter
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Dan Carpenter @ 2024-01-22 15:19 UTC (permalink / raw)
To: Niklas Cassel
Cc: Jingoo Han, Gustavo Pimentel, Manivannan Sadhasivam,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, linux-pci, linux-kernel, kernel-janitors
The "msg_addr" variable is u64. However, the "aligned_offset" is an
unsigned int. This means that when the code does:
msg_addr &= ~aligned_offset;
it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN()
to do the alignment instead.
Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
v2: fix typo in commit message
v3: Use ALIGN_DOWN() instead of ANDing with ~aligned_offset (this is a
style improvement).
drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 5befed2dc02b..51679c6702cf 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -551,7 +551,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
}
aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
- msg_addr &= ~aligned_offset;
+ msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
epc->mem->window.page_size);
if (ret)
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v3 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() 2024-01-22 15:19 [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Dan Carpenter @ 2024-01-22 15:21 ` Dan Carpenter 2024-01-22 20:24 ` Niklas Cassel 2024-01-22 20:00 ` [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Niklas Cassel 2024-01-22 20:29 ` Niklas Cassel 2 siblings, 1 reply; 5+ messages in thread From: Dan Carpenter @ 2024-01-22 15:21 UTC (permalink / raw) To: Jingoo Han Cc: Gustavo Pimentel, Manivannan Sadhasivam, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, linux-pci, linux-kernel, kernel-janitors I recently changed the code in dw_pcie_ep_raise_msix_irq() to use ALIGN_DOWN(). The code in dw_pcie_ep_raise_msi_irq() is similar so update it to match as well. (No effect on runtime, just a cleanup). Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> --- v2: Add this patch v3: Use ALIGN_DOWN() as a style improvement drivers/pci/controller/dwc/pcie-designware-ep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 51679c6702cf..1c8d2e938851 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -483,8 +483,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg); } aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1); - msg_addr = ((u64)msg_addr_upper) << 32 | - (msg_addr_lower & ~aligned_offset); + msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower; + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret) -- 2.43.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() 2024-01-22 15:21 ` [PATCH v3 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() Dan Carpenter @ 2024-01-22 20:24 ` Niklas Cassel 0 siblings, 0 replies; 5+ messages in thread From: Niklas Cassel @ 2024-01-22 20:24 UTC (permalink / raw) To: Dan Carpenter Cc: Jingoo Han, Gustavo Pimentel, Manivannan Sadhasivam, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, linux-pci, linux-kernel, kernel-janitors On Mon, Jan 22, 2024 at 06:21:00PM +0300, Dan Carpenter wrote: > I recently changed the code in dw_pcie_ep_raise_msix_irq() to use > ALIGN_DOWN(). The code in dw_pcie_ep_raise_msi_irq() is similar so > update it to match as well. (No effect on runtime, just a cleanup). > > Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> > --- > v2: Add this patch > v3: Use ALIGN_DOWN() as a style improvement > > drivers/pci/controller/dwc/pcie-designware-ep.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 51679c6702cf..1c8d2e938851 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -483,8 +483,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg); > } > aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1); > - msg_addr = ((u64)msg_addr_upper) << 32 | > - (msg_addr_lower & ~aligned_offset); > + msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower; > + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); > ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, > epc->mem->window.page_size); > if (ret) > -- > 2.43.0 > Reviewed-by: Niklas Cassel <cassel@kernel.org> Although, if I'm being super nitpicky (sorry... and feel free to ignore), I think this is slightly cleaner: --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -482,9 +482,10 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep_func->msi_cap + PCI_MSI_DATA_32; msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg); } - aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1); - msg_addr = ((u64)msg_addr_upper) << 32 | - (msg_addr_lower & ~aligned_offset); + msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower; + + aligned_offset = msg_addr & (epc->mem->window.page_size - 1); + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret) ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() 2024-01-22 15:19 [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Dan Carpenter 2024-01-22 15:21 ` [PATCH v3 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() Dan Carpenter @ 2024-01-22 20:00 ` Niklas Cassel 2024-01-22 20:29 ` Niklas Cassel 2 siblings, 0 replies; 5+ messages in thread From: Niklas Cassel @ 2024-01-22 20:00 UTC (permalink / raw) To: Dan Carpenter Cc: Niklas Cassel, Jingoo Han, Gustavo Pimentel, Manivannan Sadhasivam, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, linux-pci, linux-kernel, kernel-janitors On Mon, Jan 22, 2024 at 06:19:52PM +0300, Dan Carpenter wrote: > The "msg_addr" variable is u64. However, the "aligned_offset" is an > unsigned int. This means that when the code does: > > msg_addr &= ~aligned_offset; > > it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN() > to do the alignment instead. > > Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support") > Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> > --- > v2: fix typo in commit message > v3: Use ALIGN_DOWN() instead of ANDing with ~aligned_offset (this is a > style improvement). > > drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 5befed2dc02b..51679c6702cf 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -551,7 +551,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > } > > aligned_offset = msg_addr & (epc->mem->window.page_size - 1); > - msg_addr &= ~aligned_offset; > + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); > ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, > epc->mem->window.page_size); > if (ret) > -- > 2.43.0 > Reviewed-by: Niklas Cassel <cassel@kernel.org> ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() 2024-01-22 15:19 [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Dan Carpenter 2024-01-22 15:21 ` [PATCH v3 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() Dan Carpenter 2024-01-22 20:00 ` [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Niklas Cassel @ 2024-01-22 20:29 ` Niklas Cassel 2 siblings, 0 replies; 5+ messages in thread From: Niklas Cassel @ 2024-01-22 20:29 UTC (permalink / raw) To: Dan Carpenter Cc: Niklas Cassel, Jingoo Han, Gustavo Pimentel, Manivannan Sadhasivam, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, linux-pci, linux-kernel, kernel-janitors On Mon, Jan 22, 2024 at 06:19:52PM +0300, Dan Carpenter wrote: > The "msg_addr" variable is u64. However, the "aligned_offset" is an > unsigned int. This means that when the code does: > > msg_addr &= ~aligned_offset; > > it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN() > to do the alignment instead. > > Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support") > Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> > --- > v2: fix typo in commit message > v3: Use ALIGN_DOWN() instead of ANDing with ~aligned_offset (this is a > style improvement). > > drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 5befed2dc02b..51679c6702cf 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -551,7 +551,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > } > > aligned_offset = msg_addr & (epc->mem->window.page_size - 1); > - msg_addr &= ~aligned_offset; > + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); > ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, > epc->mem->window.page_size); > if (ret) > -- > 2.43.0 > Oh.. I just got emails that the patch that this fixes has been backported, so perhaps we should add: Cc: stable@vger.kernel.org as well...? Kind regards, Niklas ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-01-22 20:29 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-01-22 15:19 [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Dan Carpenter 2024-01-22 15:21 ` [PATCH v3 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() Dan Carpenter 2024-01-22 20:24 ` Niklas Cassel 2024-01-22 20:00 ` [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Niklas Cassel 2024-01-22 20:29 ` Niklas Cassel
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox