[PATCH 1/1] iommu/vt-d: Draining PRQ in sva unbind path when FPD bit set

[PATCH 1/1] iommu/vt-d: Draining PRQ in sva unbind path when FPD bit set

[Lu Baolu]

When a device uses a PASID for SVA (Shared Virtual Address), it's possible
that the PASID entry is marked as non-present and FPD bit set before the
device flushes all ongoing DMA requests and removes the SVA domain. This
can occur when an exception happens and the process terminates before the
device driver stops DMA and calls the iommu driver to unbind the PASID.

There's no need to drain the PRQ in the mm release path. Instead, the PRQ
will be drained in the SVA unbind path. But in such case,
intel_pasid_tear_down_entry() only checks the presence of the pasid entry
and returns directly.

Add the code to clear the FPD bit and drain the PRQ.

Suggested-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel/pasid.c | 22 +++++++++++++++++++++-
 drivers/iommu/intel/pasid.h |  6 ++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 5b7d85f1e143..fb59a7d35958 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -244,11 +244,31 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev,
 
 	spin_lock(&iommu->lock);
 	pte = intel_pasid_get_entry(dev, pasid);
-	if (WARN_ON(!pte) || !pasid_pte_is_present(pte)) {
+	if (WARN_ON(!pte)) {
 		spin_unlock(&iommu->lock);
 		return;
 	}
 
+	if (!pasid_pte_is_present(pte)) {
+		if (!pasid_pte_is_fault_disabled(pte)) {
+			WARN_ON(READ_ONCE(pte->val[0]) != 0);
+			spin_unlock(&iommu->lock);
+			return;
+		}
+
+		/*
+		 * When a PASID is used for SVA by a device, it's possible
+		 * that the pasid entry is non-present with the Fault
+		 * Processing Disabled bit set. Clear the pasid entry and
+		 * drain the PRQ for the PASID before return.
+		 */
+		pasid_clear_entry(pte);
+		spin_unlock(&iommu->lock);
+		intel_iommu_drain_pasid_prq(dev, pasid);
+
+		return;
+	}
+
 	did = pasid_get_domain_id(pte);
 	pgtt = pasid_pte_get_pgtt(pte);
 	intel_pasid_clear_entry(dev, pasid, fault_ignore);
diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index 082f4fe20216..668d8ece6b14 100644
--- a/drivers/iommu/intel/pasid.h
+++ b/drivers/iommu/intel/pasid.h
@@ -73,6 +73,12 @@ static inline bool pasid_pte_is_present(struct pasid_entry *pte)
 	return READ_ONCE(pte->val[0]) & PASID_PTE_PRESENT;
 }
 
+/* Get FPD(Fault Processing Disable) bit of a PASID table entry */
+static inline bool pasid_pte_is_fault_disabled(struct pasid_entry *pte)
+{
+	return READ_ONCE(pte->val[0]) & PASID_PTE_FPD;
+}
+
 /* Get PGTT field of a PASID table entry */
 static inline u16 pasid_pte_get_pgtt(struct pasid_entry *pte)
 {
-- 
2.43.0

RE: [PATCH 1/1] iommu/vt-d: Draining PRQ in sva unbind path when FPD bit set

[Tian, Kevin]

> From: Lu Baolu <baolu.lu@linux.intel.com>
> Sent: Tuesday, December 17, 2024 10:43 AM
> 
> When a device uses a PASID for SVA (Shared Virtual Address), it's possible
> that the PASID entry is marked as non-present and FPD bit set before the
> device flushes all ongoing DMA requests and removes the SVA domain. This
> can occur when an exception happens and the process terminates before the
> device driver stops DMA and calls the iommu driver to unbind the PASID.
> 
> There's no need to drain the PRQ in the mm release path. Instead, the PRQ
> will be drained in the SVA unbind path. But in such case,
> intel_pasid_tear_down_entry() only checks the presence of the pasid entry
> and returns directly.
> 
> Add the code to clear the FPD bit and drain the PRQ.
> 
> Suggested-by: Kevin Tian <kevin.tian@intel.com>
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>

Need a fix tag given the old code doesn't work correctly?

Reviewed-by: Kevin Tian <kevin.tian@intel.com>

Re: [PATCH 1/1] iommu/vt-d: Draining PRQ in sva unbind path when FPD bit set

[Baolu Lu]

On 2024/12/17 15:39, Tian, Kevin wrote:
>> From: Lu Baolu<baolu.lu@linux.intel.com>
>> Sent: Tuesday, December 17, 2024 10:43 AM
>>
>> When a device uses a PASID for SVA (Shared Virtual Address), it's possible
>> that the PASID entry is marked as non-present and FPD bit set before the
>> device flushes all ongoing DMA requests and removes the SVA domain. This
>> can occur when an exception happens and the process terminates before the
>> device driver stops DMA and calls the iommu driver to unbind the PASID.
>>
>> There's no need to drain the PRQ in the mm release path. Instead, the PRQ
>> will be drained in the SVA unbind path. But in such case,
>> intel_pasid_tear_down_entry() only checks the presence of the pasid entry
>> and returns directly.
>>
>> Add the code to clear the FPD bit and drain the PRQ.
>>
>> Suggested-by: Kevin Tian<kevin.tian@intel.com>
>> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>
> Need a fix tag given the old code doesn't work correctly?

Yes.

Fixes: c43e1ccdebf2 ("iommu/vt-d: Drain PRQs when domain removed from RID")

Re: [PATCH 1/1] iommu/vt-d: Draining PRQ in sva unbind path when FPD bit set

[Baolu Lu]

On 12/17/24 10:42, Lu Baolu wrote:
> When a device uses a PASID for SVA (Shared Virtual Address), it's possible
> that the PASID entry is marked as non-present and FPD bit set before the
> device flushes all ongoing DMA requests and removes the SVA domain. This
> can occur when an exception happens and the process terminates before the
> device driver stops DMA and calls the iommu driver to unbind the PASID.
> 
> There's no need to drain the PRQ in the mm release path. Instead, the PRQ
> will be drained in the SVA unbind path. But in such case,
> intel_pasid_tear_down_entry() only checks the presence of the pasid entry
> and returns directly.
> 
> Add the code to clear the FPD bit and drain the PRQ.
> 
> Suggested-by: Kevin Tian<kevin.tian@intel.com>
> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>
> ---
>   drivers/iommu/intel/pasid.c | 22 +++++++++++++++++++++-
>   drivers/iommu/intel/pasid.h |  6 ++++++
>   2 files changed, 27 insertions(+), 1 deletion(-)

Queued for v6.14.