* [PATCH v4 01/11] dt-bindings: display/msm: qcom,kaanapali-dpu: Add Kaanapali
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-22 10:23 ` [PATCH v4 02/11] dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHY yuanjie yang
` (10 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Add DPU version 13.0 for Qualcomm Kaanapali Soc. The Kaanapali
DPU and SM8750 have significant differences, including additions
and removals of registers, as well as changes in register addresses.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
.../devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
index fe296e3186d0..e29c4687c3a2 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
@@ -16,6 +16,7 @@ properties:
oneOf:
- enum:
- qcom,glymur-dpu
+ - qcom,kaanapali-dpu
- qcom,sa8775p-dpu
- qcom,sm8650-dpu
- qcom,sm8750-dpu
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 02/11] dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHY
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
2025-12-22 10:23 ` [PATCH v4 01/11] dt-bindings: display/msm: qcom,kaanapali-dpu: Add Kaanapali yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-22 10:23 ` [PATCH v4 03/11] dt-bindings: display/msm: dsi-controller-main: Add Kaanapali yuanjie yang
` (9 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou, Krzysztof Kozlowski
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
The DSI PHY registers on the Kaanapali platform differ from those
on SM8750. So add DSI PHY for Kaanapali to compatible these changes.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
index 1ca820a500b7..a6e044eed3df 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
@@ -17,6 +17,7 @@ properties:
enum:
- qcom,dsi-phy-7nm
- qcom,dsi-phy-7nm-8150
+ - qcom,kaanapali-dsi-phy-3nm
- qcom,sa8775p-dsi-phy-5nm
- qcom,sar2130p-dsi-phy-5nm
- qcom,sc7280-dsi-phy-7nm
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 03/11] dt-bindings: display/msm: dsi-controller-main: Add Kaanapali
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
2025-12-22 10:23 ` [PATCH v4 01/11] dt-bindings: display/msm: qcom,kaanapali-dpu: Add Kaanapali yuanjie yang
2025-12-22 10:23 ` [PATCH v4 02/11] dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHY yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-22 10:23 ` [PATCH v4 04/11] dt-bindings: display/msm: qcom,kaanapali-mdss: " yuanjie yang
` (8 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou, Krzysztof Kozlowski
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
The DSI registers on the Kaanapali platform differ from those on SM8750.
So add DSI for Kaanapali to compatible these changes.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
.../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 4400d4cce072..536ebf331828 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -15,6 +15,7 @@ properties:
- items:
- enum:
- qcom,apq8064-dsi-ctrl
+ - qcom,kaanapali-dsi-ctrl
- qcom,msm8226-dsi-ctrl
- qcom,msm8916-dsi-ctrl
- qcom,msm8953-dsi-ctrl
@@ -369,6 +370,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,kaanapali-dsi-ctrl
- qcom,sm8750-dsi-ctrl
then:
properties:
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 04/11] dt-bindings: display/msm: qcom,kaanapali-mdss: Add Kaanapali
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
` (2 preceding siblings ...)
2025-12-22 10:23 ` [PATCH v4 03/11] dt-bindings: display/msm: dsi-controller-main: Add Kaanapali yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-24 9:39 ` Krzysztof Kozlowski
2025-12-22 10:23 ` [PATCH v4 05/11] drm/msm/mdss: Add support for Kaanapali yuanjie yang
` (7 subsequent siblings)
11 siblings, 1 reply; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Kaanapali introduces DPU 13.0.0 and DSI 2.10. Compared to SM8750,
Kaanapali has significant register changes, making it incompatible
with SM8750. So add MDSS/MDP display subsystem for Qualcomm Kaanapali.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
.../display/msm/qcom,kaanapali-mdss.yaml | 297 ++++++++++++++++++
1 file changed, 297 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml
new file mode 100644
index 000000000000..9f935defd6b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml
@@ -0,0 +1,297 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Kaanapali Display MDSS
+
+maintainers:
+ - Yongxing Mou <yongxing.mou@oss.qualcomm.com>
+ - Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
+
+description:
+ Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,kaanapali-mdss
+
+ clocks:
+ items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+ - description: Display AHB SWI
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
+
+ interconnect-names:
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,kaanapali-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ contains:
+ const: qcom,kaanapali-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,kaanapali-dsi-phy-3nm
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/phy/phy-qcom-qmp.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-subsystem@9800000 {
+ compatible = "qcom,kaanapali-mdss";
+ reg = <0x09800000 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&disp_cc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&disp_cc_mdss_mdp_clk>,
+ <&disp_cc_mdss_ahb_swi_clk>;
+ resets = <&disp_cc_mdss_core_bcr>;
+
+ power-domains = <&mdss_gdsc>;
+
+ iommus = <&apps_smmu 0x800 0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@9801000 {
+ compatible = "qcom,kaanapali-dpu";
+ reg = <0x09801000 0x1c8000>,
+ <0x09b16000 0x3000>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupts-extended = <&mdss 0>;
+
+ clocks = <&gcc_disp_hf_axi_clk>,
+ <&disp_cc_mdss_ahb_clk>,
+ <&disp_cc_mdss_mdp_lut_clk>,
+ <&disp_cc_mdss_mdp_clk>,
+ <&disp_cc_mdss_vsync_clk>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&disp_cc_mdss_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-156000000 {
+ opp-hz = /bits/ 64 <156000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-207000000 {
+ opp-hz = /bits/ 64 <207000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-337000000 {
+ opp-hz = /bits/ 64 <337000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-417000000 {
+ opp-hz = /bits/ 64 <417000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-532000000 {
+ opp-hz = /bits/ 64 <532000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+ };
+ };
+
+ dsi@9ac0000 {
+ compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x09ac0000 0x1000>;
+ reg-names = "dsi_ctrl";
+
+ interrupts-extended = <&mdss 4>;
+
+ clocks = <&disp_cc_mdss_byte0_clk>,
+ <&disp_cc_mdss_byte0_intf_clk>,
+ <&disp_cc_mdss_pclk0_clk>,
+ <&disp_cc_mdss_esc0_clk>,
+ <&disp_cc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>,
+ <&disp_cc_esync0_clk>,
+ <&disp_cc_osc_clk>,
+ <&disp_cc_mdss_byte0_clk_src>,
+ <&disp_cc_mdss_pclk0_clk_src>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus",
+ "dsi_pll_pixel",
+ "dsi_pll_byte",
+ "esync",
+ "osc",
+ "byte_src",
+ "pixel_src";
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+
+ mdss_dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-312500000 {
+ opp-hz = /bits/ 64 <312500000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@9ac1000 {
+ compatible = "qcom,kaanapali-dsi-phy-3nm";
+ reg = <0x09ac1000 0x1cc>,
+ <0x09ac1200 0x80>,
+ <0x09ac1500 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&disp_cc_mdss_ahb_clk>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 04/11] dt-bindings: display/msm: qcom,kaanapali-mdss: Add Kaanapali
2025-12-22 10:23 ` [PATCH v4 04/11] dt-bindings: display/msm: qcom,kaanapali-mdss: " yuanjie yang
@ 2025-12-24 9:39 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-24 9:39 UTC (permalink / raw)
To: yuanjie yang
Cc: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, tingwei.zhang, aiqun.yu,
yongxing.mou
On Mon, Dec 22, 2025 at 06:23:53PM +0800, yuanjie yang wrote:
> From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
>
> Kaanapali introduces DPU 13.0.0 and DSI 2.10. Compared to SM8750,
> Kaanapali has significant register changes, making it incompatible
> with SM8750. So add MDSS/MDP display subsystem for Qualcomm Kaanapali.
>
> Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> ---
> .../display/msm/qcom,kaanapali-mdss.yaml | 297 ++++++++++++++++++
> 1 file changed, 297 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 05/11] drm/msm/mdss: Add support for Kaanapali
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
` (3 preceding siblings ...)
2025-12-22 10:23 ` [PATCH v4 04/11] dt-bindings: display/msm: qcom,kaanapali-mdss: " yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-22 15:46 ` Dmitry Baryshkov
2025-12-22 10:23 ` [PATCH v4 06/11] drm/msm/dsi/phy: " yuanjie yang
` (6 subsequent siblings)
11 siblings, 1 reply; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Add mdss support for the Qualcomm Kaanapali platform.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
drivers/gpu/drm/msm/msm_mdss.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index bf9a33e925ac..7d78d16f8802 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -239,7 +239,11 @@ static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss)
writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
- writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
+ if (data->ubwc_dec_version == UBWC_6_0)
+ writel_relaxed(5, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
+ else
+ writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
+
writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
}
@@ -296,6 +300,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
case UBWC_5_0:
msm_mdss_setup_ubwc_dec_50(msm_mdss);
break;
+ case UBWC_6_0:
+ msm_mdss_setup_ubwc_dec_50(msm_mdss);
+ break;
default:
dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",
msm_mdss->mdss_data->ubwc_dec_version);
@@ -554,6 +561,7 @@ static const struct msm_mdss_data data_153k6 = {
static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss", .data = &data_153k6 },
{ .compatible = "qcom,glymur-mdss", .data = &data_57k },
+ { .compatible = "qcom,kaanapali-mdss", .data = &data_57k },
{ .compatible = "qcom,msm8998-mdss", .data = &data_76k8 },
{ .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 },
{ .compatible = "qcom,qcs8300-mdss", .data = &data_74k },
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 05/11] drm/msm/mdss: Add support for Kaanapali
2025-12-22 10:23 ` [PATCH v4 05/11] drm/msm/mdss: Add support for Kaanapali yuanjie yang
@ 2025-12-22 15:46 ` Dmitry Baryshkov
0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2025-12-22 15:46 UTC (permalink / raw)
To: yuanjie yang
Cc: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, tingwei.zhang, aiqun.yu,
yongxing.mou
On Mon, Dec 22, 2025 at 06:23:54PM +0800, yuanjie yang wrote:
> From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
>
> Add mdss support for the Qualcomm Kaanapali platform.
>
> Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 06/11] drm/msm/dsi/phy: Add support for Kaanapali
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
` (4 preceding siblings ...)
2025-12-22 10:23 ` [PATCH v4 05/11] drm/msm/mdss: Add support for Kaanapali yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-22 10:23 ` [PATCH v4 07/11] drm/msm/dsi: " yuanjie yang
` (5 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou, Dmitry Baryshkov
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Add DSI PHY support for the Kaanapali platform, Kaanapali introduce
addition of DSI2/DSI2_phy compared to SM8650. However, based on the
HPG diagram, only DSI0_phy and DSI1_phy works.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 4ea681130dba..7937266de1d2 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -577,6 +577,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_4nm_8650_cfgs },
{ .compatible = "qcom,sm8750-dsi-phy-3nm",
.data = &dsi_phy_3nm_8750_cfgs },
+ { .compatible = "qcom,kaanapali-dsi-phy-3nm",
+ .data = &dsi_phy_3nm_kaanapali_cfgs },
#endif
{}
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 3cbf08231492..c01784ca38ed 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -64,6 +64,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs;
struct msm_dsi_dphy_timing {
u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index c5e1d2016bcc..8cb0db3a9880 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -1504,3 +1504,26 @@ const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = {
.num_dsi_phy = 2,
.quirks = DSI_PHY_7NM_QUIRK_V7_0,
};
+
+const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs = {
+ .has_phy_lane = true,
+ .regulator_data = dsi_phy_7nm_98000uA_regulators,
+ .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
+ .ops = {
+ .enable = dsi_7nm_phy_enable,
+ .disable = dsi_7nm_phy_disable,
+ .pll_init = dsi_pll_7nm_init,
+ .save_pll_state = dsi_7nm_pll_save_state,
+ .restore_pll_state = dsi_7nm_pll_restore_state,
+ .set_continuous_clock = dsi_7nm_set_continuous_clock,
+ },
+ .min_pll_rate = 600000000UL,
+#ifdef CONFIG_64BIT
+ .max_pll_rate = 5000000000UL,
+#else
+ .max_pll_rate = ULONG_MAX,
+#endif
+ .io_start = { 0x9ac1000, 0x9ac4000 },
+ .num_dsi_phy = 2,
+ .quirks = DSI_PHY_7NM_QUIRK_V7_0,
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 07/11] drm/msm/dsi: Add support for Kaanapali
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
` (5 preceding siblings ...)
2025-12-22 10:23 ` [PATCH v4 06/11] drm/msm/dsi/phy: " yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-22 10:23 ` [PATCH v4 08/11] drm/msm/dpu: Add interrupt registers for DPU 13.0.0 yuanjie yang
` (4 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou, Dmitry Baryshkov
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Add DSI Controller version 2.10.0 support for DSI on Qualcomm
Kaanapali SoC.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 13 +++++++++++++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index fed8e9b67011..bd3c51c350e7 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -205,6 +205,17 @@ static const struct msm_dsi_config sm8650_dsi_cfg = {
},
};
+static const struct msm_dsi_config kaanapali_dsi_cfg = {
+ .io_offset = DSI_6G_REG_SHIFT,
+ .regulator_data = sm8650_dsi_regulators,
+ .num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),
+ .bus_clk_names = dsi_v2_4_clk_names,
+ .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
+ .io_start = {
+ { 0x9ac0000, 0x9ac3000 },
+ },
+};
+
static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
{ .supply = "vdda", .init_load_uA = 8350 }, /* 1.2 V */
{ .supply = "refgen" },
@@ -332,6 +343,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0,
&sm8650_dsi_cfg, &msm_dsi_6g_v2_9_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_10_0,
+ &kaanapali_dsi_cfg, &msm_dsi_6g_v2_9_host_ops},
};
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 38f303f2ed04..5dc812028bd5 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -32,6 +32,7 @@
#define MSM_DSI_6G_VER_MINOR_V2_7_0 0x20070000
#define MSM_DSI_6G_VER_MINOR_V2_8_0 0x20080000
#define MSM_DSI_6G_VER_MINOR_V2_9_0 0x20090000
+#define MSM_DSI_6G_VER_MINOR_V2_10_0 0x200a0000
#define MSM_DSI_V2_VER_MINOR_8064 0x0
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 08/11] drm/msm/dpu: Add interrupt registers for DPU 13.0.0
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
` (6 preceding siblings ...)
2025-12-22 10:23 ` [PATCH v4 07/11] drm/msm/dsi: " yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-22 10:23 ` [PATCH v4 09/11] drm/msm/dpu: Refactor SSPP to compatible " yuanjie yang
` (3 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou, Dmitry Baryshkov
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
DPU version 13.0.0 introduces changes to the interrupt register
layout. Update the driver to support these modifications for
proper interrupt handling.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 89 ++++++++++++++++++-
1 file changed, 88 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 49bd77a755aa..5b7cd5241f45 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -40,6 +40,15 @@
#define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x004)
#define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x008)
+#define MDP_INTF_REV_13xx_OFF(intf) (0x18d000 + 0x1000 * (intf))
+#define MDP_INTF_REV_13xx_INTR_EN(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0x1c0)
+#define MDP_INTF_REV_13xx_INTR_STATUS(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0x1c4)
+#define MDP_INTF_REV_13xx_INTR_CLEAR(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0x1c8)
+#define MDP_INTF_REV_13xx_TEAR_OFF(intf) (0x18d800 + 0x1000 * (intf))
+#define MDP_INTF_REV_13xx_INTR_TEAR_EN(intf) (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x000)
+#define MDP_INTF_REV_13xx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x004)
+#define MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x008)
+
/**
* struct dpu_intr_reg - array of DPU register sets
* @clr_off: offset to CLEAR reg
@@ -199,6 +208,82 @@ static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
},
};
+/*
+ * dpu_intr_set_13xx - List of DPU interrupt registers for DPU >= 13.0
+ */
+static const struct dpu_intr_reg dpu_intr_set_13xx[] = {
+ [MDP_SSPP_TOP0_INTR] = {
+ INTR_CLEAR,
+ INTR_EN,
+ INTR_STATUS
+ },
+ [MDP_SSPP_TOP0_INTR2] = {
+ INTR2_CLEAR,
+ INTR2_EN,
+ INTR2_STATUS
+ },
+ [MDP_SSPP_TOP0_HIST_INTR] = {
+ HIST_INTR_CLEAR,
+ HIST_INTR_EN,
+ HIST_INTR_STATUS
+ },
+ [MDP_INTF0_INTR] = {
+ MDP_INTF_REV_13xx_INTR_CLEAR(0),
+ MDP_INTF_REV_13xx_INTR_EN(0),
+ MDP_INTF_REV_13xx_INTR_STATUS(0)
+ },
+ [MDP_INTF1_INTR] = {
+ MDP_INTF_REV_13xx_INTR_CLEAR(1),
+ MDP_INTF_REV_13xx_INTR_EN(1),
+ MDP_INTF_REV_13xx_INTR_STATUS(1)
+ },
+ [MDP_INTF1_TEAR_INTR] = {
+ MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(1),
+ MDP_INTF_REV_13xx_INTR_TEAR_EN(1),
+ MDP_INTF_REV_13xx_INTR_TEAR_STATUS(1)
+ },
+ [MDP_INTF2_INTR] = {
+ MDP_INTF_REV_13xx_INTR_CLEAR(2),
+ MDP_INTF_REV_13xx_INTR_EN(2),
+ MDP_INTF_REV_13xx_INTR_STATUS(2)
+ },
+ [MDP_INTF2_TEAR_INTR] = {
+ MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(2),
+ MDP_INTF_REV_13xx_INTR_TEAR_EN(2),
+ MDP_INTF_REV_13xx_INTR_TEAR_STATUS(2)
+ },
+ [MDP_INTF3_INTR] = {
+ MDP_INTF_REV_13xx_INTR_CLEAR(3),
+ MDP_INTF_REV_13xx_INTR_EN(3),
+ MDP_INTF_REV_13xx_INTR_STATUS(3)
+ },
+ [MDP_INTF4_INTR] = {
+ MDP_INTF_REV_13xx_INTR_CLEAR(4),
+ MDP_INTF_REV_13xx_INTR_EN(4),
+ MDP_INTF_REV_13xx_INTR_STATUS(4)
+ },
+ [MDP_INTF5_INTR] = {
+ MDP_INTF_REV_13xx_INTR_CLEAR(5),
+ MDP_INTF_REV_13xx_INTR_EN(5),
+ MDP_INTF_REV_13xx_INTR_STATUS(5)
+ },
+ [MDP_INTF6_INTR] = {
+ MDP_INTF_REV_13xx_INTR_CLEAR(6),
+ MDP_INTF_REV_13xx_INTR_EN(6),
+ MDP_INTF_REV_13xx_INTR_STATUS(6)
+ },
+ [MDP_INTF7_INTR] = {
+ MDP_INTF_REV_13xx_INTR_CLEAR(7),
+ MDP_INTF_REV_13xx_INTR_EN(7),
+ MDP_INTF_REV_13xx_INTR_STATUS(7)
+ },
+ [MDP_INTF8_INTR] = {
+ MDP_INTF_REV_13xx_INTR_CLEAR(8),
+ MDP_INTF_REV_13xx_INTR_EN(8),
+ MDP_INTF_REV_13xx_INTR_STATUS(8)
+ },
+};
+
#define DPU_IRQ_MASK(irq_idx) (BIT(DPU_IRQ_BIT(irq_idx)))
static inline bool dpu_core_irq_is_valid(unsigned int irq_idx)
@@ -507,7 +592,9 @@ struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device *dev,
if (!intr)
return ERR_PTR(-ENOMEM);
- if (m->mdss_ver->core_major_ver >= 7)
+ if (m->mdss_ver->core_major_ver >= 13)
+ intr->intr_set = dpu_intr_set_13xx;
+ else if (m->mdss_ver->core_major_ver >= 7)
intr->intr_set = dpu_intr_set_7xxx;
else
intr->intr_set = dpu_intr_set_legacy;
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 09/11] drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
` (7 preceding siblings ...)
2025-12-22 10:23 ` [PATCH v4 08/11] drm/msm/dpu: Add interrupt registers for DPU 13.0.0 yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-23 20:26 ` Dmitry Baryshkov
2025-12-22 10:23 ` [PATCH v4 10/11] drm/msm/dpu: Add Kaanapali SSPP sub-block support yuanjie yang
` (2 subsequent siblings)
11 siblings, 1 reply; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou
From: Yuanjie Yang <yuanjiey@qti.qualcomm.com>
DPU version 13.0.0 introduces structural changes including
register additions, removals, and relocations.
Refactor SSPP-related code to be compatible with DPU 13.0.0
modifications.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 14 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 110 ++++++++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 +++++++++
3 files changed, 130 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 336757103b5a..b03fea1b9cbd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -208,6 +208,18 @@ struct dpu_dsc_blk {
u32 len;
};
+/**
+ * struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information
+ * @name: string name for debug purposes
+ * @base: offset of this sub-block relative to the block offset
+ * @len: register block length of this sub-block
+ */
+struct dpu_sspp_v13_rec_blk {
+ char name[DPU_HW_BLK_NAME_LEN];
+ u32 base;
+ u32 len;
+};
+
/**
* enum dpu_qos_lut_usage - define QoS LUT use cases
*/
@@ -294,6 +306,8 @@ struct dpu_sspp_sub_blks {
u32 qseed_ver;
struct dpu_scaler_blk scaler_blk;
struct dpu_pp_blk csc_blk;
+ struct dpu_sspp_v13_rec_blk sspp_rec0_blk;
+ struct dpu_sspp_v13_rec_blk sspp_rec1_blk;
const u32 *format_list;
u32 num_formats;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 6f1fc790ad6d..197a2c584c73 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -145,11 +145,18 @@
static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- u32 mode_mask;
if (!ctx)
return;
+ dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE);
+}
+
+void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_sspp *ctx, u32 op_mode_off)
+{
+ u32 mode_mask;
+
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
/**
* if rect index is RECT_SOLO, we cannot expect a
@@ -158,7 +165,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
*/
mode_mask = 0;
} else {
- mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE);
+ mode_mask = DPU_REG_READ(&ctx->hw, op_mode_off);
mode_mask |= pipe->multirect_index;
if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
mode_mask |= BIT(2);
@@ -166,10 +173,10 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
mode_mask &= ~BIT(2);
}
- DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask);
+ DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask);
}
-static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
+void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en)
{
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
@@ -189,7 +196,7 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);
}
-static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
+void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en)
{
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
@@ -211,10 +218,6 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
const struct msm_format *fmt, u32 flags)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- struct dpu_hw_blk_reg_map *c;
- u32 chroma_samp, unpack, src_format;
- u32 opmode = 0;
- u32 fast_clear = 0;
u32 op_mode_off, unpack_pat_off, format_off;
if (!ctx || !fmt)
@@ -231,6 +234,21 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
format_off = SSPP_SRC_FORMAT_REC1;
}
+ dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
+ unpack_pat_off, format_off,
+ SSPP_UBWC_STATIC_CTRL, SSPP_UBWC_ERROR_STATUS);
+}
+
+void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
+ u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off,
+ u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off,
+ u32 ubwc_err_off)
+{
+ struct dpu_hw_blk_reg_map *c;
+ u32 chroma_samp, unpack, src_format;
+ u32 opmode;
+ u32 fast_clear;
+
c = &ctx->hw;
opmode = DPU_REG_READ(c, op_mode_off);
opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
@@ -279,24 +297,24 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
switch (ctx->ubwc->ubwc_enc_version) {
case UBWC_1_0:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ DPU_REG_WRITE(c, ubwc_ctrl_off,
fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
BIT(8) |
(ctx->ubwc->highest_bank_bit << 4));
break;
case UBWC_2_0:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ DPU_REG_WRITE(c, ubwc_ctrl_off,
fast_clear | (ctx->ubwc->ubwc_swizzle) |
(ctx->ubwc->highest_bank_bit << 4));
break;
case UBWC_3_0:
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ DPU_REG_WRITE(c, ubwc_ctrl_off,
BIT(30) | (ctx->ubwc->ubwc_swizzle) |
(ctx->ubwc->highest_bank_bit << 4));
break;
case UBWC_4_0:
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ DPU_REG_WRITE(c, ubwc_ctrl_off,
MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
break;
}
@@ -313,10 +331,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
/* update scaler opmode, if appropriate */
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
- _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
+ dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
MSM_FORMAT_IS_YUV(fmt));
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
- _sspp_setup_csc10_opmode(ctx,
+ dpu_hw_sspp_setup_csc10_opmode(ctx,
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
MSM_FORMAT_IS_YUV(fmt));
@@ -325,7 +343,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
DPU_REG_WRITE(c, op_mode_off, opmode);
/* clear previous UBWC error */
- DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
+ DPU_REG_WRITE(c, ubwc_err_off, BIT(31));
}
static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
@@ -385,7 +403,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
tot_req_pixels[3]);
}
-static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
+void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
const struct msm_format *format)
{
@@ -405,15 +423,11 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *cfg)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- struct dpu_hw_blk_reg_map *c;
- u32 src_size, src_xy, dst_size, dst_xy;
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
if (!ctx || !cfg)
return;
- c = &ctx->hw;
-
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
pipe->multirect_index == DPU_SSPP_RECT_0) {
src_size_off = SSPP_SRC_SIZE;
@@ -427,20 +441,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
out_xy_off = SSPP_OUT_XY_REC1;
}
-
- /* src and dest rect programming */
- src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
- src_size = (drm_rect_height(&cfg->src_rect) << 16) |
- drm_rect_width(&cfg->src_rect);
- dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
- dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
- drm_rect_width(&cfg->dst_rect);
-
- /* rectangle register programming */
- DPU_REG_WRITE(c, src_size_off, src_size);
- DPU_REG_WRITE(c, src_xy_off, src_xy);
- DPU_REG_WRITE(c, out_size_off, dst_size);
- DPU_REG_WRITE(c, out_xy_off, dst_xy);
+ dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
+ src_xy_off, out_size_off, out_xy_off);
}
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
@@ -497,7 +499,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);
}
-static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
+void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
const struct dpu_csc_cfg *data)
{
u32 offset;
@@ -519,21 +521,31 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- struct dpu_hw_fmt_layout cfg;
+ u32 const_clr_off;
if (!ctx)
return;
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0)
+ const_clr_off = SSPP_SRC_CONSTANT_COLOR;
+ else
+ const_clr_off = SSPP_SRC_CONSTANT_COLOR_REC1;
+
+ dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
+}
+
+void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
+ u32 color, struct dpu_hw_sspp *ctx,
+ u32 const_clr_off)
+{
+ struct dpu_hw_fmt_layout cfg;
+
/* cleanup source addresses */
memset(&cfg, 0, sizeof(cfg));
ctx->ops.setup_sourceaddress(pipe, &cfg);
- if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
- pipe->multirect_index == DPU_SSPP_RECT_0)
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color);
- else
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1,
- color);
+ DPU_REG_WRITE(&ctx->hw, const_clr_off, color);
}
static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
@@ -547,14 +559,20 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
cfg);
}
+void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
+ bool danger_safe_en, u32 ctrl_off)
+{
+ DPU_REG_WRITE(&ctx->hw, ctrl_off,
+ danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
+}
+
static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
bool danger_safe_en)
{
if (!ctx)
return;
- DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
- danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
+ dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL);
}
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
@@ -609,7 +627,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c,
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
- c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
+ c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
if (test_bit(DPU_SSPP_CDP, &features))
c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index bdac5c04bf79..c6b19cb4d158 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -331,5 +331,57 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
struct dentry *entry);
+void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
+ u32 mask, u8 en);
+
+void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
+ u32 mask, u8 en);
+
+void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
+ struct dpu_hw_scaler3_cfg *scaler3_cfg,
+ const struct msm_format *format);
+
+void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
+ const struct dpu_csc_cfg *data);
+
+void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_sspp *ctx,
+ u32 op_mode_off);
+
+void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
+ u32 flags, struct dpu_hw_sspp *ctx,
+ u32 op_mode_off, u32 unpack_pat_off, u32 format_off,
+ u32 ubwc_ctrl_off, u32 ubwc_err_off);
+
+static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *cfg,
+ struct dpu_hw_sspp *ctx, u32 src_size_off,
+ u32 src_xy_off, u32 out_size_off, u32 out_xy_off)
+{
+ struct dpu_hw_blk_reg_map *c;
+ u32 src_size, src_xy, dst_size, dst_xy;
+
+ c = &ctx->hw;
+
+ /* src and dest rect programming */
+ src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
+ src_size = (drm_rect_height(&cfg->src_rect) << 16) |
+ drm_rect_width(&cfg->src_rect);
+ dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
+ dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
+ drm_rect_width(&cfg->dst_rect);
+
+ /* rectangle register programming */
+ DPU_REG_WRITE(c, src_size_off, src_size);
+ DPU_REG_WRITE(c, src_xy_off, src_xy);
+ DPU_REG_WRITE(c, out_size_off, dst_size);
+ DPU_REG_WRITE(c, out_xy_off, dst_xy);
+}
+
+void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
+ u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off);
+
+void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
+ bool danger_safe_en, u32 ctrl_off);
+
#endif /*_DPU_HW_SSPP_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 09/11] drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0
2025-12-22 10:23 ` [PATCH v4 09/11] drm/msm/dpu: Refactor SSPP to compatible " yuanjie yang
@ 2025-12-23 20:26 ` Dmitry Baryshkov
2025-12-24 2:18 ` yuanjiey
0 siblings, 1 reply; 20+ messages in thread
From: Dmitry Baryshkov @ 2025-12-23 20:26 UTC (permalink / raw)
To: yuanjie yang
Cc: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, tingwei.zhang, aiqun.yu,
yongxing.mou
On Mon, Dec 22, 2025 at 06:23:58PM +0800, yuanjie yang wrote:
> From: Yuanjie Yang <yuanjiey@qti.qualcomm.com>
>
> DPU version 13.0.0 introduces structural changes including
> register additions, removals, and relocations.
>
> Refactor SSPP-related code to be compatible with DPU 13.0.0
> modifications.
>
> Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 14 +++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 110 ++++++++++--------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 +++++++++
> 3 files changed, 130 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 336757103b5a..b03fea1b9cbd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -208,6 +208,18 @@ struct dpu_dsc_blk {
> u32 len;
> };
>
> +/**
> + * struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information
> + * @name: string name for debug purposes
> + * @base: offset of this sub-block relative to the block offset
> + * @len: register block length of this sub-block
> + */
> +struct dpu_sspp_v13_rec_blk {
> + char name[DPU_HW_BLK_NAME_LEN];
> + u32 base;
> + u32 len;
> +};
> +
> /**
> * enum dpu_qos_lut_usage - define QoS LUT use cases
> */
> @@ -294,6 +306,8 @@ struct dpu_sspp_sub_blks {
> u32 qseed_ver;
> struct dpu_scaler_blk scaler_blk;
> struct dpu_pp_blk csc_blk;
> + struct dpu_sspp_v13_rec_blk sspp_rec0_blk;
> + struct dpu_sspp_v13_rec_blk sspp_rec1_blk;
This is a refactoring patch. Don't add fields (and structs) which are
not used inside the patch.
>
> const u32 *format_list;
> u32 num_formats;
Other than that, LGTM.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v4 09/11] drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0
2025-12-23 20:26 ` Dmitry Baryshkov
@ 2025-12-24 2:18 ` yuanjiey
0 siblings, 0 replies; 20+ messages in thread
From: yuanjiey @ 2025-12-24 2:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, tingwei.zhang, aiqun.yu,
yongxing.mou
On Tue, Dec 23, 2025 at 10:26:03PM +0200, Dmitry Baryshkov wrote:
> On Mon, Dec 22, 2025 at 06:23:58PM +0800, yuanjie yang wrote:
> > From: Yuanjie Yang <yuanjiey@qti.qualcomm.com>
> >
> > DPU version 13.0.0 introduces structural changes including
> > register additions, removals, and relocations.
> >
> > Refactor SSPP-related code to be compatible with DPU 13.0.0
> > modifications.
> >
> > Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > ---
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 14 +++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 110 ++++++++++--------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 +++++++++
> > 3 files changed, 130 insertions(+), 46 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index 336757103b5a..b03fea1b9cbd 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -208,6 +208,18 @@ struct dpu_dsc_blk {
> > u32 len;
> > };
> >
> > +/**
> > + * struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information
> > + * @name: string name for debug purposes
> > + * @base: offset of this sub-block relative to the block offset
> > + * @len: register block length of this sub-block
> > + */
> > +struct dpu_sspp_v13_rec_blk {
> > + char name[DPU_HW_BLK_NAME_LEN];
> > + u32 base;
> > + u32 len;
> > +};
> > +
> > /**
> > * enum dpu_qos_lut_usage - define QoS LUT use cases
> > */
> > @@ -294,6 +306,8 @@ struct dpu_sspp_sub_blks {
> > u32 qseed_ver;
> > struct dpu_scaler_blk scaler_blk;
> > struct dpu_pp_blk csc_blk;
> > + struct dpu_sspp_v13_rec_blk sspp_rec0_blk;
> > + struct dpu_sspp_v13_rec_blk sspp_rec1_blk;
>
> This is a refactoring patch. Don't add fields (and structs) which are
> not used inside the patch.
OK, will add in Kaanapali SSPP v13 patch in next patch.
Thanks,
Yuanjie
> >
> > const u32 *format_list;
> > u32 num_formats;
>
> Other than that, LGTM.
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 10/11] drm/msm/dpu: Add Kaanapali SSPP sub-block support
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
` (8 preceding siblings ...)
2025-12-22 10:23 ` [PATCH v4 09/11] drm/msm/dpu: Refactor SSPP to compatible " yuanjie yang
@ 2025-12-22 10:23 ` yuanjie yang
2025-12-23 20:30 ` Dmitry Baryshkov
2025-12-22 10:24 ` [PATCH v4 11/11] drm/msm/dpu: Add support for Kaanapali DPU yuanjie yang
2025-12-22 12:02 ` [PATCH v4 00/11] drm/msm: Add support for Kaanapali Dmitry Baryshkov
11 siblings, 1 reply; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:23 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Add support for Kaanapali platform SSPP sub-blocks, which
introduce structural changes including register additions,
removals, and relocations. Add the new common and rectangle
blocks, and update register definitions and handling to
ensure compatibility with DPU v13.0.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 13 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
7 files changed, 371 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 8aa7d07303fb..8b94c5f1cb68 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -86,6 +86,7 @@ msm-display-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_hw_lm.o \
disp/dpu1/dpu_hw_pingpong.o \
disp/dpu1/dpu_hw_sspp.o \
+ disp/dpu1/dpu_hw_sspp_v13.o \
disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_merge3d.o \
disp/dpu1/dpu_hw_top.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 197a2c584c73..c6d8d7fb3880 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -248,6 +248,7 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format
u32 chroma_samp, unpack, src_format;
u32 opmode;
u32 fast_clear;
+ u8 core_major_ver = ctx->mdss_ver->core_major_ver;
c = &ctx->hw;
opmode = DPU_REG_READ(c, op_mode_off);
@@ -291,9 +292,10 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format
if (MSM_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
- DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
- DPU_FETCH_CONFIG_RESET_VALUE |
- ctx->ubwc->highest_bank_bit << 18);
+ if (core_major_ver < 13)
+ DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
+ DPU_FETCH_CONFIG_RESET_VALUE |
+ ctx->ubwc->highest_bank_bit << 18);
switch (ctx->ubwc->ubwc_enc_version) {
case UBWC_1_0:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
@@ -724,7 +726,10 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
hw_pipe->mdss_ver = mdss_rev;
- _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
+ if (mdss_rev->core_major_ver >= 13)
+ dpu_hw_sspp_init_v13(hw_pipe, hw_pipe->cap->features, mdss_rev);
+ else
+ _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
return hw_pipe;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index c6b19cb4d158..309af4183ba3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -383,5 +383,9 @@ void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
bool danger_safe_en, u32 ctrl_off);
+void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
+ unsigned long features,
+ const struct dpu_mdss_version *mdss_rev);
+
#endif /*_DPU_HW_SSPP_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
new file mode 100644
index 000000000000..e78a20b45300
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/printk.h>
+#include <linux/soc/qcom/ubwc.h>
+
+#include "dpu_hw_sspp.h"
+
+/* >= v13 DPU */
+/* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */
+/* Name Offset */
+#define SSPP_CMN_CLK_CTRL 0x0
+#define SSPP_CMN_CLK_STATUS 0x4
+#define SSPP_CMN_MULTI_REC_OP_MODE 0x10
+#define SSPP_CMN_ADDR_CONFIG 0x14
+#define SSPP_CMN_CAC_CTRL 0x20
+#define SSPP_CMN_SYS_CACHE_MODE 0x24
+#define SSPP_CMN_QOS_CTRL 0x28
+
+#define SSPP_CMN_FILL_LEVEL_SCALE 0x3c
+#define SSPP_CMN_FILL_LEVELS 0x40
+#define SSPP_CMN_STATUS 0x44
+#define SSPP_CMN_FETCH_DMA_RD_OTS 0x48
+#define SSPP_CMN_FETCH_DTB_WR_PLANE0 0x4c
+#define SSPP_CMN_FETCH_DTB_WR_PLANE1 0x50
+#define SSPP_CMN_FETCH_DTB_WR_PLANE2 0x54
+#define SSPP_CMN_DTB_UNPACK_RD_PLANE0 0x58
+#define SSPP_CMN_DTB_UNPACK_RD_PLANE1 0x5c
+#define SSPP_CMN_DTB_UNPACK_RD_PLANE2 0x60
+#define SSPP_CMN_UNPACK_LINE_COUNT 0x64
+#define SSPP_CMN_TPG_CONTROL 0x68
+#define SSPP_CMN_TPG_CONFIG 0x6c
+#define SSPP_CMN_TPG_COMPONENT_LIMITS 0x70
+#define SSPP_CMN_TPG_RECTANGLE 0x74
+#define SSPP_CMN_TPG_BLACK_WHITE_PATTERN_FRAMES 0x78
+#define SSPP_CMN_TPG_RGB_MAPPING 0x7c
+#define SSPP_CMN_TPG_PATTERN_GEN_INIT_VAL 0x80
+
+/*RECRegisterset*/
+/*Name Offset*/
+#define SSPP_REC_SRC_FORMAT 0x0
+#define SSPP_REC_SRC_UNPACK_PATTERN 0x4
+#define SSPP_REC_SRC_OP_MODE 0x8
+#define SSPP_REC_SRC_CONSTANT_COLOR 0xc
+#define SSPP_REC_SRC_IMG_SIZE 0x10
+#define SSPP_REC_SRC_SIZE 0x14
+#define SSPP_REC_SRC_XY 0x18
+#define SSPP_REC_OUT_SIZE 0x1c
+#define SSPP_REC_OUT_XY 0x20
+#define SSPP_REC_SW_PIX_EXT_LR 0x24
+#define SSPP_REC_SW_PIX_EXT_TB 0x28
+#define SSPP_REC_SRC_SIZE_ODX 0x30
+#define SSPP_REC_SRC_XY_ODX 0x34
+#define SSPP_REC_OUT_SIZE_ODX 0x38
+#define SSPP_REC_OUT_XY_ODX 0x3c
+#define SSPP_REC_SW_PIX_EXT_LR_ODX 0x40
+#define SSPP_REC_SW_PIX_EXT_TB_ODX 0x44
+#define SSPP_REC_PRE_DOWN_SCALE 0x48
+#define SSPP_REC_SRC0_ADDR 0x4c
+#define SSPP_REC_SRC1_ADDR 0x50
+#define SSPP_REC_SRC2_ADDR 0x54
+#define SSPP_REC_SRC3_ADDR 0x58
+#define SSPP_REC_SRC_YSTRIDE0 0x5c
+#define SSPP_REC_SRC_YSTRIDE1 0x60
+#define SSPP_REC_CURRENT_SRC0_ADDR 0x64
+#define SSPP_REC_CURRENT_SRC1_ADDR 0x68
+#define SSPP_REC_CURRENT_SRC2_ADDR 0x6c
+#define SSPP_REC_CURRENT_SRC3_ADDR 0x70
+#define SSPP_REC_SRC_ADDR_SW_STATUS 0x74
+#define SSPP_REC_CDP_CNTL 0x78
+#define SSPP_REC_TRAFFIC_SHAPER 0x7c
+#define SSPP_REC_TRAFFIC_SHAPER_PREFILL 0x80
+#define SSPP_REC_PD_MEM_ALLOC 0x84
+#define SSPP_REC_QOS_CLAMP 0x88
+#define SSPP_REC_UIDLE_CTRL_VALUE 0x8c
+#define SSPP_REC_UBWC_STATIC_CTRL 0x90
+#define SSPP_REC_UBWC_STATIC_CTRL_OVERRIDE 0x94
+#define SSPP_REC_UBWC_STATS_ROI 0x98
+#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI0 0x9c
+#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI0 0xa0
+#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI1 0xa4
+#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI1 0xa8
+#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI2 0xac
+#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI2 0xb0
+#define SSPP_REC_EXCL_REC_CTRL 0xb4
+#define SSPP_REC_EXCL_REC_SIZE 0xb8
+#define SSPP_REC_EXCL_REC_XY 0xbc
+#define SSPP_REC_LINE_INSERTION_CTRL 0xc0
+#define SSPP_REC_LINE_INSERTION_OUT_SIZE 0xc4
+#define SSPP_REC_FETCH_PIPE_ACTIVE 0xc8
+#define SSPP_REC_META_ERROR_STATUS 0xcc
+#define SSPP_REC_UBWC_ERROR_STATUS 0xd0
+#define SSPP_REC_FLUSH_CTRL 0xd4
+#define SSPP_REC_INTR_EN 0xd8
+#define SSPP_REC_INTR_STATUS 0xdc
+#define SSPP_REC_INTR_CLEAR 0xe0
+#define SSPP_REC_HSYNC_STATUS 0xe4
+#define SSPP_REC_FP16_CONFIG 0x150
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_0 0x154
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_1 0x158
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_0 0x15c
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_1 0x160
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_0 0x164
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_1 0x168
+#define SSPP_REC_FP16_CSC_PRE_CLAMP_R 0x16c
+#define SSPP_REC_FP16_CSC_PRE_CLAMP_G 0x170
+#define SSPP_REC_FP16_CSC_PRE_CLAMP_B 0x174
+#define SSPP_REC_FP16_CSC_POST_CLAMP 0x178
+
+static inline u32 dpu_hw_sspp_calculate_rect_off(enum dpu_sspp_multirect_index rect_index,
+ struct dpu_hw_sspp *ctx)
+{
+ return (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) ?
+ ctx->cap->sblk->sspp_rec0_blk.base : ctx->cap->sblk->sspp_rec1_blk.base;
+}
+
+static void dpu_hw_sspp_setup_multirect_v13(struct dpu_sw_pipe *pipe)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+
+ if (!ctx)
+ return;
+
+ dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_CMN_MULTI_REC_OP_MODE);
+}
+
+static void dpu_hw_sspp_setup_format_v13(struct dpu_sw_pipe *pipe,
+ const struct msm_format *fmt, u32 flags)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 op_mode_off, unpack_pat_off, format_off;
+ u32 ubwc_ctrl_off, ubwc_err_off;
+ u32 offset;
+
+ if (!ctx || !fmt)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+
+ op_mode_off = offset + SSPP_REC_SRC_OP_MODE;
+ unpack_pat_off = offset + SSPP_REC_SRC_UNPACK_PATTERN;
+ format_off = offset + SSPP_REC_SRC_FORMAT;
+ ubwc_ctrl_off = offset + SSPP_REC_UBWC_STATIC_CTRL;
+ ubwc_err_off = offset + SSPP_REC_UBWC_ERROR_STATUS;
+
+ dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
+ unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_err_off);
+}
+
+static void dpu_hw_sspp_setup_pe_config_v13(struct dpu_hw_sspp *ctx,
+ struct dpu_hw_pixel_ext *pe_ext)
+{
+ struct dpu_hw_blk_reg_map *c;
+ u8 color;
+ u32 lr_pe[4], tb_pe[4];
+ const u32 bytemask = 0xff;
+ u32 offset = ctx->cap->sblk->sspp_rec0_blk.base;
+
+ if (!ctx || !pe_ext)
+ return;
+
+ c = &ctx->hw;
+ /* program SW pixel extension override for all pipes*/
+ for (color = 0; color < DPU_MAX_PLANES; color++) {
+ /* color 2 has the same set of registers as color 1 */
+ if (color == 2)
+ continue;
+
+ lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24) |
+ ((pe_ext->right_rpt[color] & bytemask) << 16) |
+ ((pe_ext->left_ftch[color] & bytemask) << 8) |
+ (pe_ext->left_rpt[color] & bytemask);
+
+ tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24) |
+ ((pe_ext->btm_rpt[color] & bytemask) << 16) |
+ ((pe_ext->top_ftch[color] & bytemask) << 8) |
+ (pe_ext->top_rpt[color] & bytemask);
+ }
+
+ /* color 0 */
+ DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR + offset, lr_pe[0]);
+ DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB + offset, tb_pe[0]);
+
+ /* color 1 and color 2 */
+ DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR_ODX + offset, lr_pe[1]);
+ DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB_ODX + offset, tb_pe[1]);
+}
+
+static void dpu_hw_sspp_setup_rects_v13(struct dpu_sw_pipe *pipe,
+ struct dpu_sw_pipe_cfg *cfg)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
+ u32 offset;
+
+ if (!ctx || !cfg)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+
+ src_size_off = offset + SSPP_REC_SRC_SIZE;
+ src_xy_off = offset + SSPP_REC_SRC_XY;
+ out_size_off = offset + SSPP_REC_OUT_SIZE;
+ out_xy_off = offset + SSPP_REC_OUT_XY;
+
+ dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
+ src_xy_off, out_size_off, out_xy_off);
+}
+
+static void dpu_hw_sspp_setup_sourceaddress_v13(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_fmt_layout *layout)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ int i;
+ u32 offset, ystride0, ystride1;
+
+ if (!ctx)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+
+ for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
+ DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC0_ADDR + i * 0x4,
+ layout->plane_addr[i]);
+
+ ystride0 = (layout->plane_pitch[0]) | (layout->plane_pitch[2] << 16);
+ ystride1 = (layout->plane_pitch[1]) | (layout->plane_pitch[3] << 16);
+
+ DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE0, ystride0);
+ DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE1, ystride1);
+}
+
+static void dpu_hw_sspp_setup_solidfill_v13(struct dpu_sw_pipe *pipe, u32 color)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 const_clr_off;
+ u32 offset;
+
+ if (!ctx)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+ const_clr_off = offset + SSPP_REC_SRC_CONSTANT_COLOR;
+
+ dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
+}
+
+static void dpu_hw_sspp_setup_qos_lut_v13(struct dpu_hw_sspp *ctx,
+ struct dpu_hw_qos_cfg *cfg)
+{
+ if (!ctx || !cfg)
+ return;
+
+ _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
+}
+
+static void dpu_hw_sspp_setup_qos_ctrl_v13(struct dpu_hw_sspp *ctx,
+ bool danger_safe_en)
+{
+ if (!ctx)
+ return;
+
+ dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_CMN_QOS_CTRL);
+}
+
+static void dpu_hw_sspp_setup_cdp_v13(struct dpu_sw_pipe *pipe,
+ const struct msm_format *fmt,
+ bool enable)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 offset = 0;
+
+ if (!ctx)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+ dpu_setup_cdp(&ctx->hw, offset + SSPP_REC_CDP_CNTL, fmt, enable);
+}
+
+static bool dpu_hw_sspp_setup_clk_force_ctrl_v13(struct dpu_hw_sspp *ctx, bool enable)
+{
+ static const struct dpu_clk_ctrl_reg sspp_clk_ctrl = {
+ .reg_off = SSPP_CMN_CLK_CTRL,
+ .bit_off = 0
+ };
+
+ return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable);
+}
+
+void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
+ unsigned long features, const struct dpu_mdss_version *mdss_rev)
+{
+ c->ops.setup_format = dpu_hw_sspp_setup_format_v13;
+ c->ops.setup_rects = dpu_hw_sspp_setup_rects_v13;
+ c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress_v13;
+ c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill_v13;
+ c->ops.setup_pe = dpu_hw_sspp_setup_pe_config_v13;
+
+ if (test_bit(DPU_SSPP_QOS, &features)) {
+ c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut_v13;
+ c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl_v13;
+ }
+
+ if (test_bit(DPU_SSPP_CSC, &features) ||
+ test_bit(DPU_SSPP_CSC_10BIT, &features))
+ c->ops.setup_csc = dpu_hw_sspp_setup_csc;
+
+ if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
+ test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
+ c->ops.setup_multirect = dpu_hw_sspp_setup_multirect_v13;
+
+ if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
+ c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
+
+ if (test_bit(DPU_SSPP_CDP, &features))
+ c->ops.setup_cdp = dpu_hw_sspp_setup_cdp_v13;
+
+ c->ops.setup_clk_force_ctrl = dpu_hw_sspp_setup_clk_force_ctrl_v13;
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 486be346d40d..3cf22ec62792 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -81,6 +81,13 @@ static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE;
#define QOS_CREQ_LUT_0 0x14
#define QOS_CREQ_LUT_1 0x18
+/* CMN_QOS_LUT */
+#define SSPP_CMN_QOS_CTRL 0x28
+#define SSPP_CMN_DANGER_LUT 0x2c
+#define SSPP_CMN_SAFE_LUT 0x30
+#define SSPP_CMN_CREQ_LUT_0 0x34
+#define SSPP_CMN_CREQ_LUT_1 0x38
+
/* QOS_QOS_CTRL */
#define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0)
#define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4)
@@ -475,6 +482,17 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
}
+void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
+ const struct dpu_hw_qos_cfg *cfg)
+{
+ DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut);
+ DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut);
+ DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut);
+ DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32);
+ DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL,
+ cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
+}
+
/*
* note: Aside from encoders, input_sel should be set to 0x0 by default
*/
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 67b08e99335d..1822ac699757 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -360,6 +360,9 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
bool qos_8lvl,
const struct dpu_hw_qos_cfg *cfg);
+void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
+ const struct dpu_hw_qos_cfg *cfg);
+
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
u32 misr_ctrl_offset, u8 input_sel);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 478a091aeccf..006dcc4a0dcc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -148,6 +148,15 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
cfg);
}
+static void dpu_hw_wb_setup_qos_lut_v13(struct dpu_hw_wb *ctx,
+ struct dpu_hw_qos_cfg *cfg)
+{
+ if (!ctx || !cfg)
+ return;
+
+ _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
+}
+
static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
const struct msm_format *fmt,
bool enable)
@@ -202,8 +211,12 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
if (test_bit(DPU_WB_XY_ROI_OFFSET, &features))
ops->setup_roi = dpu_hw_wb_roi;
- if (test_bit(DPU_WB_QOS, &features))
- ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
+ if (test_bit(DPU_WB_QOS, &features)) {
+ if (mdss_rev->core_major_ver >= 13)
+ ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut_v13;
+ else
+ ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
+ }
if (test_bit(DPU_WB_CDP, &features))
ops->setup_cdp = dpu_hw_wb_setup_cdp;
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 10/11] drm/msm/dpu: Add Kaanapali SSPP sub-block support
2025-12-22 10:23 ` [PATCH v4 10/11] drm/msm/dpu: Add Kaanapali SSPP sub-block support yuanjie yang
@ 2025-12-23 20:30 ` Dmitry Baryshkov
2025-12-24 2:25 ` yuanjiey
0 siblings, 1 reply; 20+ messages in thread
From: Dmitry Baryshkov @ 2025-12-23 20:30 UTC (permalink / raw)
To: yuanjie yang
Cc: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, tingwei.zhang, aiqun.yu,
yongxing.mou
On Mon, Dec 22, 2025 at 06:23:59PM +0800, yuanjie yang wrote:
> From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
>
> Add support for Kaanapali platform SSPP sub-blocks, which
> introduce structural changes including register additions,
> removals, and relocations. Add the new common and rectangle
> blocks, and update register definitions and handling to
> ensure compatibility with DPU v13.0.
>
> Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 13 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +
> .../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
> 7 files changed, 371 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
>
> @@ -291,9 +292,10 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format
> if (MSM_FORMAT_IS_UBWC(fmt))
> opmode |= MDSS_MDP_OP_BWC_EN;
> src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
> - DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
> - DPU_FETCH_CONFIG_RESET_VALUE |
> - ctx->ubwc->highest_bank_bit << 18);
> + if (core_major_ver < 13)
> + DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
> + DPU_FETCH_CONFIG_RESET_VALUE |
> + ctx->ubwc->highest_bank_bit << 18);
I'd prefer if this is pulled into dpu_hw_sspp_setup_format().
> switch (ctx->ubwc->ubwc_enc_version) {
> case UBWC_1_0:
> fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> index 478a091aeccf..006dcc4a0dcc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
This commit was about SSPPs. Why are you touching WB?
> @@ -148,6 +148,15 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
> cfg);
> }
>
> +static void dpu_hw_wb_setup_qos_lut_v13(struct dpu_hw_wb *ctx,
> + struct dpu_hw_qos_cfg *cfg)
> +{
> + if (!ctx || !cfg)
> + return;
> +
> + _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
> +}
> +
> static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
> const struct msm_format *fmt,
> bool enable)
> @@ -202,8 +211,12 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
> if (test_bit(DPU_WB_XY_ROI_OFFSET, &features))
> ops->setup_roi = dpu_hw_wb_roi;
>
> - if (test_bit(DPU_WB_QOS, &features))
> - ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
> + if (test_bit(DPU_WB_QOS, &features)) {
> + if (mdss_rev->core_major_ver >= 13)
> + ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut_v13;
> + else
> + ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
> + }
>
> if (test_bit(DPU_WB_CDP, &features))
> ops->setup_cdp = dpu_hw_wb_setup_cdp;
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v4 10/11] drm/msm/dpu: Add Kaanapali SSPP sub-block support
2025-12-23 20:30 ` Dmitry Baryshkov
@ 2025-12-24 2:25 ` yuanjiey
0 siblings, 0 replies; 20+ messages in thread
From: yuanjiey @ 2025-12-24 2:25 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, tingwei.zhang, aiqun.yu,
yongxing.mou
On Tue, Dec 23, 2025 at 10:30:56PM +0200, Dmitry Baryshkov wrote:
> On Mon, Dec 22, 2025 at 06:23:59PM +0800, yuanjie yang wrote:
> > From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> >
> > Add support for Kaanapali platform SSPP sub-blocks, which
> > introduce structural changes including register additions,
> > removals, and relocations. Add the new common and rectangle
> > blocks, and update register definitions and handling to
> > ensure compatibility with DPU v13.0.
> >
> > Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > ---
> > drivers/gpu/drm/msm/Makefile | 1 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 13 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
> > 7 files changed, 371 insertions(+), 6 deletions(-)
> > create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
> >
>
> > @@ -291,9 +292,10 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format
> > if (MSM_FORMAT_IS_UBWC(fmt))
> > opmode |= MDSS_MDP_OP_BWC_EN;
> > src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
> > - DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
> > - DPU_FETCH_CONFIG_RESET_VALUE |
> > - ctx->ubwc->highest_bank_bit << 18);
> > + if (core_major_ver < 13)
> > + DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
> > + DPU_FETCH_CONFIG_RESET_VALUE |
> > + ctx->ubwc->highest_bank_bit << 18);
>
> I'd prefer if this is pulled into dpu_hw_sspp_setup_format().
OK, will put this part in dpu_hw_sspp_setup_format.
> > switch (ctx->ubwc->ubwc_enc_version) {
> > case UBWC_1_0:
> > fast_clear = fmt->alpha_enable ? BIT(31) : 0;
>
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> > index 478a091aeccf..006dcc4a0dcc 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
>
> This commit was about SSPPs. Why are you touching WB?
Look like I should drop WB part in current patch,
and add a new patch just "add qos V13 in WB".
make it more clear for each patch function.
Thank,
Yuanjie
> > @@ -148,6 +148,15 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
> > cfg);
> > }
> >
> > +static void dpu_hw_wb_setup_qos_lut_v13(struct dpu_hw_wb *ctx,
> > + struct dpu_hw_qos_cfg *cfg)
> > +{
> > + if (!ctx || !cfg)
> > + return;
> > +
> > + _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
> > +}
> > +
> > static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
> > const struct msm_format *fmt,
> > bool enable)
> > @@ -202,8 +211,12 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
> > if (test_bit(DPU_WB_XY_ROI_OFFSET, &features))
> > ops->setup_roi = dpu_hw_wb_roi;
> >
> > - if (test_bit(DPU_WB_QOS, &features))
> > - ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
> > + if (test_bit(DPU_WB_QOS, &features)) {
> > + if (mdss_rev->core_major_ver >= 13)
> > + ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut_v13;
> > + else
> > + ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
> > + }
> >
> > if (test_bit(DPU_WB_CDP, &features))
> > ops->setup_cdp = dpu_hw_wb_setup_cdp;
> > --
> > 2.34.1
> >
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 11/11] drm/msm/dpu: Add support for Kaanapali DPU
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
` (9 preceding siblings ...)
2025-12-22 10:23 ` [PATCH v4 10/11] drm/msm/dpu: Add Kaanapali SSPP sub-block support yuanjie yang
@ 2025-12-22 10:24 ` yuanjie yang
2025-12-22 12:02 ` [PATCH v4 00/11] drm/msm: Add support for Kaanapali Dmitry Baryshkov
11 siblings, 0 replies; 20+ messages in thread
From: yuanjie yang @ 2025-12-22 10:24 UTC (permalink / raw)
To: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
tingwei.zhang, aiqun.yu, yongxing.mou, Dmitry Baryshkov
From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Add support for Display Processing Unit (DPU) version 13.0
on the Kaanapali platform. This version introduces changes
to the SSPP sub-block structure. Add common block and rectangle
blocks to accommodate these structural modifications for
compatibility.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
.../disp/dpu1/catalog/dpu_13_0_kaanapali.h | 492 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 41 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 535 insertions(+)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
new file mode 100644
index 000000000000..0b20401b04cf
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
@@ -0,0 +1,492 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DPU_13_0_KAANAPALI_H
+#define _DPU_13_0_KAANAPALI_H
+
+static const struct dpu_caps kaanapali_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 8192,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg kaanapali_mdp = {
+ .name = "top_0",
+ .base = 0, .len = 0x494,
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg kaanapali_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1f000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x20000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x21000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x22000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x23000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x24000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg kaanapali_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x2b000, .len = 0x84,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_5,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x34000, .len = 0x84,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_5,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x3d000, .len = 0x84,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_5,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0x46000, .len = 0x84,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_5,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x97000, .len = 0x84,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0xa0000, .len = 0x84,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0xa9000, .len = 0x84,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0xb2000, .len = 0x84,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_12", .id = SSPP_DMA4,
+ .base = 0xbb000, .len = 0x84,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 14,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_13", .id = SSPP_DMA5,
+ .base = 0xc4000, .len = 0x84,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 15,
+ .type = SSPP_TYPE_DMA,
+ },
+};
+
+static const struct dpu_lm_cfg kaanapali_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x103000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sm8750_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x10b000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sm8750_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x113000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sm8750_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ .dspp = DSPP_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x11b000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sm8750_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ .dspp = DSPP_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x123000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sm8750_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_4,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x12b000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sm8750_lm_sblk,
+ .lm_pair = LM_4,
+ .pingpong = PINGPONG_5,
+ }, {
+ .name = "lm_6", .id = LM_6,
+ .base = 0x133000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sm8750_lm_sblk,
+ .lm_pair = LM_7,
+ .pingpong = PINGPONG_6,
+ }, {
+ .name = "lm_7", .id = LM_7,
+ .base = 0x13b000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sm8750_lm_sblk,
+ .lm_pair = LM_6,
+ .pingpong = PINGPONG_7,
+ },
+};
+
+static const struct dpu_dspp_cfg kaanapali_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x105000, .len = 0x1800,
+ .sblk = &sm8750_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x10d000, .len = 0x1800,
+ .sblk = &sm8750_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x115000, .len = 0x1800,
+ .sblk = &sm8750_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x11d000, .len = 0x1800,
+ .sblk = &sm8750_dspp_sblk,
+ },
+};
+
+static const struct dpu_pingpong_cfg kaanapali_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x108000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x110000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x118000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x120000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ }, {
+ .name = "pingpong_4", .id = PINGPONG_4,
+ .base = 0x128000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ }, {
+ .name = "pingpong_5", .id = PINGPONG_5,
+ .base = 0x130000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ }, {
+ .name = "pingpong_6", .id = PINGPONG_6,
+ .base = 0x138000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_3,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),
+ }, {
+ .name = "pingpong_7", .id = PINGPONG_7,
+ .base = 0x140000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_3,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),
+ }, {
+ .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
+ .base = 0x169000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_4,
+ }, {
+ .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
+ .base = 0x169400, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_4,
+ }, {
+ .name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
+ .base = 0x16a000, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_5,
+ }, {
+ .name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
+ .base = 0x16a400, .len = 0,
+ .sblk = &kaanapali_pp_sblk,
+ .merge_3d = MERGE_3D_5,
+ },
+};
+
+static const struct dpu_merge_3d_cfg kaanapali_merge_3d[] = {
+ {
+ .name = "merge_3d_0", .id = MERGE_3D_0,
+ .base = 0x163000, .len = 0x1c,
+ }, {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x164000, .len = 0x1c,
+ }, {
+ .name = "merge_3d_2", .id = MERGE_3D_2,
+ .base = 0x165000, .len = 0x1c,
+ }, {
+ .name = "merge_3d_3", .id = MERGE_3D_3,
+ .base = 0x166000, .len = 0x1c,
+ }, {
+ .name = "merge_3d_4", .id = MERGE_3D_4,
+ .base = 0x169700, .len = 0x1c,
+ }, {
+ .name = "merge_3d_5", .id = MERGE_3D_5,
+ .base = 0x16a700, .len = 0x1c,
+ },
+};
+
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
+ * slice DSC encoders so both share same base address but with
+ * its own different sub block address.
+ */
+static const struct dpu_dsc_cfg kaanapali_dsc[] = {
+ {
+ .name = "dce_0_0", .id = DSC_0,
+ .base = 0x181000, .len = 0x8,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &sm8750_dsc_sblk_0,
+ }, {
+ .name = "dce_0_1", .id = DSC_1,
+ .base = 0x181000, .len = 0x8,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &sm8750_dsc_sblk_1,
+ }, {
+ .name = "dce_1_0", .id = DSC_2,
+ .base = 0x183000, .len = 0x8,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &sm8750_dsc_sblk_0,
+ }, {
+ .name = "dce_1_1", .id = DSC_3,
+ .base = 0x183000, .len = 0x8,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &sm8750_dsc_sblk_1,
+ }, {
+ .name = "dce_2_0", .id = DSC_4,
+ .base = 0x185000, .len = 0x8,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &sm8750_dsc_sblk_0,
+ }, {
+ .name = "dce_2_1", .id = DSC_5,
+ .base = 0x185000, .len = 0x8,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &sm8750_dsc_sblk_1,
+ }, {
+ .name = "dce_3_0", .id = DSC_6,
+ .base = 0x187000, .len = 0x8,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &sm8750_dsc_sblk_0,
+ }, {
+ .name = "dce_3_1", .id = DSC_7,
+ .base = 0x187000, .len = 0x8,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &sm8750_dsc_sblk_1,
+ },
+};
+
+static const struct dpu_wb_cfg kaanapali_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x16e000, .len = 0x2c8,
+ .features = WB_SDM845_MASK,
+ .format_list = wb2_formats_rgb_yuv,
+ .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
+static const struct dpu_cwb_cfg kaanapali_cwb[] = {
+ {
+ .name = "cwb_0", .id = CWB_0,
+ .base = 0x169200, .len = 0x20,
+ },
+ {
+ .name = "cwb_1", .id = CWB_1,
+ .base = 0x169600, .len = 0x20,
+ },
+ {
+ .name = "cwb_2", .id = CWB_2,
+ .base = 0x16a200, .len = 0x20,
+ },
+ {
+ .name = "cwb_3", .id = CWB_3,
+ .base = 0x16a600, .len = 0x20,
+ },
+};
+
+static const struct dpu_intf_cfg kaanapali_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x18d000, .len = 0x4bc,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x18e000, .len = 0x4bc,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x18f000, .len = 0x4bc,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x190000, .len = 0x4bc,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ },
+};
+
+static const struct dpu_perf_cfg kaanapali_perf_data = {
+ .max_bw_low = 21400000,
+ .max_bw_high = 30200000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 800000,
+ .min_prefill_lines = 35,
+ .danger_lut_tbl = {0x0ffff, 0x0ffff, 0x0},
+ .safe_lut_tbl = {0xff00, 0xff00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(kaanapali_qos_linear),
+ .entries = kaanapali_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(kaanapali_qos_macrotile),
+ .entries = kaanapali_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version kaanapali_mdss_ver = {
+ .core_major_ver = 13,
+ .core_minor_ver = 0,
+};
+
+const struct dpu_mdss_cfg dpu_kaanapali_cfg = {
+ .mdss_ver = &kaanapali_mdss_ver,
+ .caps = &kaanapali_dpu_caps,
+ .mdp = &kaanapali_mdp,
+ .cdm = &dpu_cdm_13_x,
+ .ctl_count = ARRAY_SIZE(kaanapali_ctl),
+ .ctl = kaanapali_ctl,
+ .sspp_count = ARRAY_SIZE(kaanapali_sspp),
+ .sspp = kaanapali_sspp,
+ .mixer_count = ARRAY_SIZE(kaanapali_lm),
+ .mixer = kaanapali_lm,
+ .dspp_count = ARRAY_SIZE(kaanapali_dspp),
+ .dspp = kaanapali_dspp,
+ .pingpong_count = ARRAY_SIZE(kaanapali_pp),
+ .pingpong = kaanapali_pp,
+ .dsc_count = ARRAY_SIZE(kaanapali_dsc),
+ .dsc = kaanapali_dsc,
+ .merge_3d_count = ARRAY_SIZE(kaanapali_merge_3d),
+ .merge_3d = kaanapali_merge_3d,
+ .wb_count = ARRAY_SIZE(kaanapali_wb),
+ .wb = kaanapali_wb,
+ .cwb_count = ARRAY_SIZE(kaanapali_cwb),
+ .cwb = sm8650_cwb,
+ .intf_count = ARRAY_SIZE(kaanapali_intf),
+ .intf = kaanapali_intf,
+ .vbif_count = ARRAY_SIZE(sm8650_vbif),
+ .vbif = sm8650_vbif,
+ .perf = &kaanapali_perf_data,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 23bb39b471b7..be3492df8bde 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -241,6 +241,23 @@ static const u32 wb2_formats_rgb_yuv[] = {
.rotation_cfg = NULL, \
}
+/* kaanapali SSPP common configuration */
+#define _VIG_SBLK_REC0_REC1(scaler_ver) \
+ { \
+ .sspp_rec0_blk = {.name = "sspp_rec0", \
+ .base = 0x1000, .len = 0x180,}, \
+ .csc_blk = {.name = "csc", \
+ .base = 0x1800, .len = 0x100,}, \
+ .scaler_blk = {.name = "scaler", \
+ .version = scaler_ver, \
+ .base = 0x2000, .len = 0xec,}, \
+ .sspp_rec1_blk = {.name = "sspp_rec1", \
+ .base = 0x3000, .len = 0x180,}, \
+ .format_list = plane_formats_yuv, \
+ .num_formats = ARRAY_SIZE(plane_formats_yuv), \
+ .rotation_cfg = NULL, \
+ }
+
#define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \
{ \
.scaler_blk = {.name = "scaler", \
@@ -329,6 +346,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =
static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =
_VIG_SBLK(SSPP_SCALER_VER(3, 4));
+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_5 =
+ _VIG_SBLK_REC0_REC1(SSPP_SCALER_VER(3, 5));
+
static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK();
static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
@@ -412,6 +432,11 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
.len = 0x20, .version = 0x20000},
};
+static const struct dpu_pingpong_sub_blks kaanapali_pp_sblk = {
+ .dither = {.name = "dither", .base = 0xc0,
+ .len = 0x40, .version = 0x30000},
+};
+
/*************************************************************
* DSC sub blocks config
*************************************************************/
@@ -452,6 +477,13 @@ static const struct dpu_cdm_cfg dpu_cdm_5_x = {
.base = 0x79200,
};
+static const struct dpu_cdm_cfg dpu_cdm_13_x = {
+ .name = "cdm_0",
+ .id = CDM_0,
+ .len = 0x240,
+ .base = 0x19e000,
+};
+
/*************************************************************
* VBIF sub blocks config
*************************************************************/
@@ -639,6 +671,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222335777},
};
+static const struct dpu_qos_lut_entry kaanapali_qos_linear[] = {
+ {.fl = 0, .lut = 0x0011223344556666},
+};
+
static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
{.fl = 0, .lut = 0x0011223445566777 },
};
@@ -668,6 +704,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
{.fl = 0, .lut = 0x0011223344556677},
};
+static const struct dpu_qos_lut_entry kaanapali_qos_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223344556666},
+};
+
static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
{.fl = 10, .lut = 0x0000000344556677},
};
@@ -727,3 +767,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_10_0_sm8650.h"
#include "catalog/dpu_12_0_sm8750.h"
#include "catalog/dpu_12_2_glymur.h"
+#include "catalog/dpu_13_0_kaanapali.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index b03fea1b9cbd..83870e84d789 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -764,6 +764,7 @@ struct dpu_mdss_cfg {
};
extern const struct dpu_mdss_cfg dpu_glymur_cfg;
+extern const struct dpu_mdss_cfg dpu_kaanapali_cfg;
extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
extern const struct dpu_mdss_cfg dpu_msm8937_cfg;
extern const struct dpu_mdss_cfg dpu_msm8953_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index f4c9767c418d..0623f1dbed97 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1506,6 +1506,7 @@ static const struct dev_pm_ops dpu_pm_ops = {
static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,glymur-dpu", .data = &dpu_glymur_cfg, },
+ { .compatible = "qcom,kaanapali-dpu", .data = &dpu_kaanapali_cfg, },
{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
{ .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
{ .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 00/11] drm/msm: Add support for Kaanapali
2025-12-22 10:23 [PATCH v4 00/11] drm/msm: Add support for Kaanapali yuanjie yang
` (10 preceding siblings ...)
2025-12-22 10:24 ` [PATCH v4 11/11] drm/msm/dpu: Add support for Kaanapali DPU yuanjie yang
@ 2025-12-22 12:02 ` Dmitry Baryshkov
2025-12-23 3:24 ` yuanjiey
11 siblings, 1 reply; 20+ messages in thread
From: Dmitry Baryshkov @ 2025-12-22 12:02 UTC (permalink / raw)
To: yuanjie yang
Cc: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, tingwei.zhang, aiqun.yu,
yongxing.mou
On Mon, 22 Dec 2025 at 12:24, yuanjie yang
<yuanjie.yang@oss.qualcomm.com> wrote:
>
> From: Yuanjie Yang <yuanjiey@qti.qualcomm.com>
>
> The Kaanapali MDSS has some differences compared to the SM8750 MDSS:
> - DSI PHY/DSI base address have some changes.
> - DPU 13.0:
> - SSPP layout has a great change.
> - interrupt INTF layout has some changes.
>
> This patchset contains DSI PHY, DSI Controller, DPU & MDSS bindings
> in addition to the driver changes.
>
> We have already tested the display functionality using the Kaanapali-mtp
> device on the Kaanapali branch of kernel-qcom repository.
> Test command: "modetest -r -v"
> kernel-qcom repository: https://git.codelinaro.org/clo/linux-kernel/kernel-qcom/-/tree/kaanapali
>
> [PATCH v4 05/11] drm/msm/mdss: Add support for Kaanapali
> compile depend on qcom-soc tree patch: https://lore.kernel.org/lkml/20250930-kaana-gpu-support-v1-1-73530b0700ed@oss.qualcomm.com/
>
> Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> ---
> Changes in v4:
> - fix qcom,kaanapali-mdss.yaml compile error
> - reorganize SSPP patch order
> - fix Dmitry ohter comment
Which 'comment'? Please be specific in the changelog.
> - rebase on top of msm-next
> - Link to v3: https://lore.kernel.org/all/20251215083854.577-1-yuanjie.yang@oss.qualcomm.com/
>
> Changes in v3:
> - split SSPP refactor patch
> - add devicetree email list
> - fix Dmitry comment
> - rebase on top of msm-next
> - Link to v2: https://lore.kernel.org/all/20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com/
>
> Changes in v2:
> - Drop panel patch
> - adjust patch order (bindings then drivers)
> - add dpu_hw_ssppv13.c to complete kaanapali SSPP function
> - fix bindings example dts compile error
> - fix other comment
> - rebase on top of msm-next
> - Link to v1: https://lore.kernel.org/all/20251023075401.1148-1-yuanjie.yang@oss.qualcomm.com/
>
> ---
> Yuanjie Yang (11):
> dt-bindings: display/msm: qcom,kaanapali-dpu: Add Kaanapali
> dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHY
> dt-bindings: display/msm: dsi-controller-main: Add Kaanapali
> dt-bindings: display/msm: qcom,kaanapali-mdss: Add Kaanapali
> drm/msm/mdss: Add support for Kaanapali
> drm/msm/dsi/phy: Add support for Kaanapali
> drm/msm/dsi: Add support for Kaanapali
> drm/msm/dpu: Add interrupt registers for DPU 13.0.0
> drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0
> drm/msm/dpu: Add Kaanapali SSPP sub-block support
> drm/msm/dpu: Add support for Kaanapali DPU
>
> .../display/msm/dsi-controller-main.yaml | 2 +
> .../bindings/display/msm/dsi-phy-7nm.yaml | 1 +
> .../display/msm/qcom,kaanapali-mdss.yaml | 297 +++++++++++
> .../bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
> drivers/gpu/drm/msm/Makefile | 1 +
> .../disp/dpu1/catalog/dpu_13_0_kaanapali.h | 492 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 41 ++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 15 +
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 89 +++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 123 +++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 56 ++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 13 +
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +
> drivers/gpu/drm/msm/msm_mdss.c | 10 +-
> 22 files changed, 1474 insertions(+), 54 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
>
>
> base-commit: 06aa394d58c11406569bcbd4a69b81290edf3f63
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v4 00/11] drm/msm: Add support for Kaanapali
2025-12-22 12:02 ` [PATCH v4 00/11] drm/msm: Add support for Kaanapali Dmitry Baryshkov
@ 2025-12-23 3:24 ` yuanjiey
0 siblings, 0 replies; 20+ messages in thread
From: yuanjiey @ 2025-12-23 3:24 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: robin.clark, lumag, jesszhan0024, sean, marijn.suijten, airlied,
simona, maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt,
conor+dt, neil.armstrong, konrad.dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, tingwei.zhang, aiqun.yu,
yongxing.mou
On Mon, Dec 22, 2025 at 02:02:52PM +0200, Dmitry Baryshkov wrote:
> On Mon, 22 Dec 2025 at 12:24, yuanjie yang
> <yuanjie.yang@oss.qualcomm.com> wrote:
> >
> > From: Yuanjie Yang <yuanjiey@qti.qualcomm.com>
> >
> > The Kaanapali MDSS has some differences compared to the SM8750 MDSS:
> > - DSI PHY/DSI base address have some changes.
> > - DPU 13.0:
> > - SSPP layout has a great change.
> > - interrupt INTF layout has some changes.
> >
> > This patchset contains DSI PHY, DSI Controller, DPU & MDSS bindings
> > in addition to the driver changes.
> >
> > We have already tested the display functionality using the Kaanapali-mtp
> > device on the Kaanapali branch of kernel-qcom repository.
> > Test command: "modetest -r -v"
> > kernel-qcom repository: https://git.codelinaro.org/clo/linux-kernel/kernel-qcom/-/tree/kaanapali
> >
> > [PATCH v4 05/11] drm/msm/mdss: Add support for Kaanapali
> > compile depend on qcom-soc tree patch: https://lore.kernel.org/lkml/20250930-kaana-gpu-support-v1-1-73530b0700ed@oss.qualcomm.com/
> >
> > Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > ---
> > Changes in v4:
> > - fix qcom,kaanapali-mdss.yaml compile error
> > - reorganize SSPP patch order
> > - fix Dmitry ohter comment
>
> Which 'comment'? Please be specific in the changelog.
fix SSPP space issue.
fix MDSS UBWC issue.
fix commit msg kaanapali -> Kaanapali.
clean refactor SSPP patch and SSPP V13 patch.
will be careful later.
Thanks,
Yuanjie
> > - rebase on top of msm-next
> > - Link to v3: https://lore.kernel.org/all/20251215083854.577-1-yuanjie.yang@oss.qualcomm.com/
> >
> > Changes in v3:
> > - split SSPP refactor patch
> > - add devicetree email list
> > - fix Dmitry comment
> > - rebase on top of msm-next
> > - Link to v2: https://lore.kernel.org/all/20251125064758.7207-1-yuanjie.yang@oss.qualcomm.com/
> >
> > Changes in v2:
> > - Drop panel patch
> > - adjust patch order (bindings then drivers)
> > - add dpu_hw_ssppv13.c to complete kaanapali SSPP function
> > - fix bindings example dts compile error
> > - fix other comment
> > - rebase on top of msm-next
> > - Link to v1: https://lore.kernel.org/all/20251023075401.1148-1-yuanjie.yang@oss.qualcomm.com/
> >
> > ---
> > Yuanjie Yang (11):
> > dt-bindings: display/msm: qcom,kaanapali-dpu: Add Kaanapali
> > dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHY
> > dt-bindings: display/msm: dsi-controller-main: Add Kaanapali
> > dt-bindings: display/msm: qcom,kaanapali-mdss: Add Kaanapali
> > drm/msm/mdss: Add support for Kaanapali
> > drm/msm/dsi/phy: Add support for Kaanapali
> > drm/msm/dsi: Add support for Kaanapali
> > drm/msm/dpu: Add interrupt registers for DPU 13.0.0
> > drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0
> > drm/msm/dpu: Add Kaanapali SSPP sub-block support
> > drm/msm/dpu: Add support for Kaanapali DPU
> >
> > .../display/msm/dsi-controller-main.yaml | 2 +
> > .../bindings/display/msm/dsi-phy-7nm.yaml | 1 +
> > .../display/msm/qcom,kaanapali-mdss.yaml | 297 +++++++++++
> > .../bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
> > drivers/gpu/drm/msm/Makefile | 1 +
> > .../disp/dpu1/catalog/dpu_13_0_kaanapali.h | 492 ++++++++++++++++++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 41 ++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 15 +
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 89 +++-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 123 +++--
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 56 ++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 13 +
> > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
> > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +
> > drivers/gpu/drm/msm/msm_mdss.c | 10 +-
> > 22 files changed, 1474 insertions(+), 54 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml
> > create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
> > create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
> >
> >
> > base-commit: 06aa394d58c11406569bcbd4a69b81290edf3f63
> > --
> > 2.34.1
> >
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread