* [PATCH 01/32] thermal/intel: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
@ 2026-06-29 6:04 ` Juergen Gross
2026-07-02 9:31 ` Ingo Molnar
2026-06-29 6:04 ` [PATCH 02/32] powercap: " Juergen Gross
` (31 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:04 UTC (permalink / raw)
To: linux-kernel, linux-pm
Cc: Juergen Gross, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba
The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and
wrmsr_safe() are planned to be removed. Use the related 64-bit variants
instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/thermal/intel/intel_tcc.c | 10 +--
drivers/thermal/intel/therm_throt.c | 68 +++++++++-----------
drivers/thermal/intel/x86_pkg_temp_thermal.c | 32 +++++----
3 files changed, 52 insertions(+), 58 deletions(-)
diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/intel_tcc.c
index 59f70bb5ffa5..d1fa3c63d554 100644
--- a/drivers/thermal/intel/intel_tcc.c
+++ b/drivers/thermal/intel/intel_tcc.c
@@ -185,7 +185,7 @@ int intel_tcc_get_tjmax(int cpu)
int val, err;
if (cpu < 0)
- err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msrval.l, &msrval.h);
+ err = rdmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, &msrval.q);
else
err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval.q);
if (err)
@@ -212,7 +212,7 @@ int intel_tcc_get_offset(int cpu)
int err;
if (cpu < 0)
- err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h);
+ err = rdmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, &val.q);
else
err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q);
if (err)
@@ -245,7 +245,7 @@ int intel_tcc_set_offset(int cpu, int offset)
return -EINVAL;
if (cpu < 0)
- err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h);
+ err = rdmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, &val.q);
else
err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q);
if (err)
@@ -259,7 +259,7 @@ int intel_tcc_set_offset(int cpu, int offset)
val.l |= offset << 24;
if (cpu < 0)
- return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, val.l, val.h);
+ return wrmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, val.q);
else
return wrmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.q);
}
@@ -288,7 +288,7 @@ int intel_tcc_get_temp(int cpu, int *temp, bool pkg)
return tjmax;
if (cpu < 0)
- err = rdmsr_safe(msr, &val.l, &val.h);
+ err = rdmsrq_safe(msr, &val.q);
else
err = rdmsrq_safe_on_cpu(cpu, msr, &val.q);
if (err)
diff --git a/drivers/thermal/intel/therm_throt.c b/drivers/thermal/intel/therm_throt.c
index 45a8ef4a608b..0b46a727ca7a 100644
--- a/drivers/thermal/intel/therm_throt.c
+++ b/drivers/thermal/intel/therm_throt.c
@@ -722,8 +722,8 @@ void __init therm_lvt_init(void)
void intel_init_thermal(struct cpuinfo_x86 *c)
{
unsigned int cpu = smp_processor_id();
+ struct msr val;
int tm2 = 0;
- u32 l, h;
if (!intel_thermal_supported(c))
return;
@@ -733,9 +733,9 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
* be some SMM goo which handles it, so we can't even put a handler
* since it might be delivered via SMI already:
*/
- rdmsr(MSR_IA32_MISC_ENABLE, l, h);
+ rdmsrq(MSR_IA32_MISC_ENABLE, val.q);
- h = lvtthmr_init;
+ val.h = lvtthmr_init;
/*
* The initial value of thermal LVT entries on all APs always reads
* 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
@@ -746,11 +746,11 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
* BIOS has programmed on AP based on BSP's info we saved since BIOS
* is always setting the same value for all threads/cores.
*/
- if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
+ if ((val.h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
apic_write(APIC_LVTTHMR, lvtthmr_init);
- if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
+ if ((val.l & MSR_IA32_MISC_ENABLE_TM1) && (val.h & APIC_DM_SMI)) {
if (system_state == SYSTEM_BOOTING)
pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu);
return;
@@ -759,59 +759,55 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
/* early Pentium M models use different method for enabling TM2 */
if (cpu_has(c, X86_FEATURE_TM2)) {
if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
- rdmsr(MSR_THERM2_CTL, l, h);
- if (l & MSR_THERM2_CTL_TM_SELECT)
+ rdmsrq(MSR_THERM2_CTL, val.q);
+ if (val.l & MSR_THERM2_CTL_TM_SELECT)
tm2 = 1;
- } else if (l & MSR_IA32_MISC_ENABLE_TM2)
+ } else if (val.l & MSR_IA32_MISC_ENABLE_TM2)
tm2 = 1;
}
/* We'll mask the thermal vector in the lapic till we're ready: */
- h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
- apic_write(APIC_LVTTHMR, h);
+ val.h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
+ apic_write(APIC_LVTTHMR, val.h);
thermal_intr_init_core_clear_mask();
thermal_intr_init_pkg_clear_mask();
- rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
+ rdmsrq(MSR_IA32_THERM_INTERRUPT, val.q);
if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
- wrmsr(MSR_IA32_THERM_INTERRUPT,
- (l | (THERM_INT_LOW_ENABLE
- | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
+ val.l = (val.l | THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE) &
+ ~THERM_INT_PLN_ENABLE;
else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
- wrmsr(MSR_IA32_THERM_INTERRUPT,
- l | (THERM_INT_LOW_ENABLE
- | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
+ val.l |= THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE |
+ THERM_INT_PLN_ENABLE;
else
- wrmsr(MSR_IA32_THERM_INTERRUPT,
- l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
+ val.l |= THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE;
+ wrmsrq(MSR_IA32_THERM_INTERRUPT, val.q);
if (cpu_has(c, X86_FEATURE_PTS)) {
- rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
+ rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
- wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
- (l | (PACKAGE_THERM_INT_LOW_ENABLE
- | PACKAGE_THERM_INT_HIGH_ENABLE))
- & ~PACKAGE_THERM_INT_PLN_ENABLE, h);
+ val.l = (val.l | PACKAGE_THERM_INT_LOW_ENABLE |
+ PACKAGE_THERM_INT_HIGH_ENABLE) &
+ ~PACKAGE_THERM_INT_PLN_ENABLE;
else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
- wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
- l | (PACKAGE_THERM_INT_LOW_ENABLE
- | PACKAGE_THERM_INT_HIGH_ENABLE
- | PACKAGE_THERM_INT_PLN_ENABLE), h);
+ val.l |= PACKAGE_THERM_INT_LOW_ENABLE |
+ PACKAGE_THERM_INT_HIGH_ENABLE |
+ PACKAGE_THERM_INT_PLN_ENABLE;
else
- wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
- l | (PACKAGE_THERM_INT_LOW_ENABLE
- | PACKAGE_THERM_INT_HIGH_ENABLE), h);
+ val.l |= PACKAGE_THERM_INT_LOW_ENABLE |
+ PACKAGE_THERM_INT_HIGH_ENABLE;
+ wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
if (cpu_has(c, X86_FEATURE_HFI)) {
- rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
- wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
- l | PACKAGE_THERM_INT_HFI_ENABLE, h);
+ rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
+ wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT,
+ val.q | PACKAGE_THERM_INT_HFI_ENABLE);
}
}
- rdmsr(MSR_IA32_MISC_ENABLE, l, h);
- wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
+ rdmsrq(MSR_IA32_MISC_ENABLE, val.q);
+ wrmsrq(MSR_IA32_MISC_ENABLE, val.q | MSR_IA32_MISC_ENABLE_TM1);
pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
tm2 ? "TM2" : "TM1");
diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c
index 688e04c63761..43fd5bdf1d8d 100644
--- a/drivers/thermal/intel/x86_pkg_temp_thermal.c
+++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c
@@ -51,8 +51,7 @@ MODULE_PARM_DESC(notify_delay_ms,
struct zone_device {
int cpu;
bool work_scheduled;
- u32 msr_pkg_therm_low;
- u32 msr_pkg_therm_high;
+ u64 msr_pkg_therm;
struct delayed_work work;
struct thermal_zone_device *tzone;
struct cpumask cpumask;
@@ -186,28 +185,28 @@ static bool pkg_thermal_rate_control(void)
static inline void enable_pkg_thres_interrupt(void)
{
u8 thres_0, thres_1;
- u32 l, h;
+ struct msr val;
- rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
+ rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
/* only enable/disable if it had valid threshold value */
- thres_0 = (l & THERM_MASK_THRESHOLD0) >> THERM_SHIFT_THRESHOLD0;
- thres_1 = (l & THERM_MASK_THRESHOLD1) >> THERM_SHIFT_THRESHOLD1;
+ thres_0 = (val.l & THERM_MASK_THRESHOLD0) >> THERM_SHIFT_THRESHOLD0;
+ thres_1 = (val.l & THERM_MASK_THRESHOLD1) >> THERM_SHIFT_THRESHOLD1;
if (thres_0)
- l |= THERM_INT_THRESHOLD0_ENABLE;
+ val.l |= THERM_INT_THRESHOLD0_ENABLE;
if (thres_1)
- l |= THERM_INT_THRESHOLD1_ENABLE;
- wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
+ val.l |= THERM_INT_THRESHOLD1_ENABLE;
+ wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
}
/* Disable threshold interrupt on local package/cpu */
static inline void disable_pkg_thres_interrupt(void)
{
- u32 l, h;
+ struct msr val;
- rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
+ rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
- l &= ~(THERM_INT_THRESHOLD0_ENABLE | THERM_INT_THRESHOLD1_ENABLE);
- wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
+ val.l &= ~(THERM_INT_THRESHOLD0_ENABLE | THERM_INT_THRESHOLD1_ENABLE);
+ wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
}
static void pkg_temp_thermal_threshold_work_fn(struct work_struct *work)
@@ -357,8 +356,7 @@ static int pkg_temp_thermal_device_add(unsigned int cpu)
goto out_unregister_tz;
/* Store MSR value for package thermal interrupt, to restore at exit */
- rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, zonedev->msr_pkg_therm_low,
- zonedev->msr_pkg_therm_high);
+ rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, zonedev->msr_pkg_therm);
cpumask_set_cpu(cpu, &zonedev->cpumask);
raw_spin_lock_irq(&pkg_temp_lock);
@@ -426,8 +424,8 @@ static int pkg_thermal_cpu_offline(unsigned int cpu)
if (lastcpu) {
zones[topology_logical_die_id(cpu)] = NULL;
/* After this point nothing touches the MSR anymore. */
- wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
- zonedev->msr_pkg_therm_low, zonedev->msr_pkg_therm_high);
+ wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT,
+ zonedev->msr_pkg_therm);
}
/*
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 01/32] thermal/intel: Stop using 32-bit MSR interfaces
2026-06-29 6:04 ` [PATCH 01/32] thermal/intel: Stop using " Juergen Gross
@ 2026-07-02 9:31 ` Ingo Molnar
2026-07-02 11:18 ` Jürgen Groß
0 siblings, 1 reply; 80+ messages in thread
From: Ingo Molnar @ 2026-07-02 9:31 UTC (permalink / raw)
To: Juergen Gross
Cc: linux-kernel, linux-pm, Rafael J. Wysocki, Daniel Lezcano,
Zhang Rui, Lukasz Luba
* Juergen Gross <jgross@suse.com> wrote:
> - rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
> + rdmsrq(MSR_IA32_THERM_INTERRUPT, val.q);
> if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
> - wrmsr(MSR_IA32_THERM_INTERRUPT,
> - (l | (THERM_INT_LOW_ENABLE
> - | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
> + val.l = (val.l | THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE) &
> + ~THERM_INT_PLN_ENABLE;
This could be written as something like:
val.l |= THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE;
val.l &= ~THERM_INT_PLN_ENABLE;
Which would be far more readable than the multi-line statement.
> + val.l = (val.l | PACKAGE_THERM_INT_LOW_ENABLE |
> + PACKAGE_THERM_INT_HIGH_ENABLE) &
> + ~PACKAGE_THERM_INT_PLN_ENABLE;
Ditto.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 01/32] thermal/intel: Stop using 32-bit MSR interfaces
2026-07-02 9:31 ` Ingo Molnar
@ 2026-07-02 11:18 ` Jürgen Groß
0 siblings, 0 replies; 80+ messages in thread
From: Jürgen Groß @ 2026-07-02 11:18 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-pm, Rafael J. Wysocki, Daniel Lezcano,
Zhang Rui, Lukasz Luba
[-- Attachment #1.1.1: Type: text/plain, Size: 880 bytes --]
On 02.07.26 11:31, Ingo Molnar wrote:
>
> * Juergen Gross <jgross@suse.com> wrote:
>
>> - rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
>> + rdmsrq(MSR_IA32_THERM_INTERRUPT, val.q);
>> if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
>> - wrmsr(MSR_IA32_THERM_INTERRUPT,
>> - (l | (THERM_INT_LOW_ENABLE
>> - | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
>> + val.l = (val.l | THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE) &
>> + ~THERM_INT_PLN_ENABLE;
>
> This could be written as something like:
>
> val.l |= THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE;
> val.l &= ~THERM_INT_PLN_ENABLE;
>
> Which would be far more readable than the multi-line statement.
>
>> + val.l = (val.l | PACKAGE_THERM_INT_LOW_ENABLE |
>> + PACKAGE_THERM_INT_HIGH_ENABLE) &
>> + ~PACKAGE_THERM_INT_PLN_ENABLE;
Okay, will change.
Juergen
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^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 02/32] powercap: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
2026-06-29 6:04 ` [PATCH 01/32] thermal/intel: Stop using " Juergen Gross
@ 2026-06-29 6:04 ` Juergen Gross
2026-06-29 11:25 ` Ingo Molnar
2026-06-29 6:04 ` [PATCH 03/32] edac: " Juergen Gross
` (30 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:04 UTC (permalink / raw)
To: linux-kernel, linux-pm; +Cc: Juergen Gross, Rafael J. Wysocki
The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to
be removed. Use the related 64-bit variants instead.
Drop a pointless initializer.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/powercap/intel_rapl_common.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 1006d183d508..3cee4ccb7997 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -752,17 +752,17 @@ EXPORT_SYMBOL_NS_GPL(rapl_default_check_unit, "INTEL_RAPL");
static void power_limit_irq_save_cpu(void *info)
{
- u32 l, h = 0;
+ struct msr val;
struct rapl_package *rp = (struct rapl_package *)info;
/* save the state of PLN irq mask bit before disabling it */
- rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
+ rdmsrq_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &val.q);
if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
- rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
+ rp->power_limit_irq = val.l & PACKAGE_THERM_INT_PLN_ENABLE;
rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
}
- l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
- wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
+ val.l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
+ wrmsrq_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
}
/* REVISIT:
@@ -792,7 +792,7 @@ static void package_power_limit_irq_save(struct rapl_package *rp)
*/
static void package_power_limit_irq_restore(struct rapl_package *rp)
{
- u32 l, h;
+ struct msr val;
if (rp->lead_cpu < 0)
return;
@@ -804,14 +804,14 @@ static void package_power_limit_irq_restore(struct rapl_package *rp)
if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
return;
- rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
+ rdmsrq_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &val.q);
if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
- l |= PACKAGE_THERM_INT_PLN_ENABLE;
+ val.l |= PACKAGE_THERM_INT_PLN_ENABLE;
else
- l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
+ val.l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
- wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
+ wrmsrq_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
}
void rapl_default_set_floor_freq(struct rapl_domain *rd, bool mode)
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 02/32] powercap: Stop using 32-bit MSR interfaces
2026-06-29 6:04 ` [PATCH 02/32] powercap: " Juergen Gross
@ 2026-06-29 11:25 ` Ingo Molnar
2026-06-29 11:33 ` Jürgen Groß
0 siblings, 1 reply; 80+ messages in thread
From: Ingo Molnar @ 2026-06-29 11:25 UTC (permalink / raw)
To: Juergen Gross; +Cc: linux-kernel, linux-pm, Rafael J. Wysocki
* Juergen Gross <jgross@suse.com> wrote:
> The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to
> be removed. Use the related 64-bit variants instead.
>
> Drop a pointless initializer.
Was the initializer really 'pointless'? IIRC it suppressed a build warning
on 32-bit builds, at least in some past iterations of these APIs.
So maybe this should say: 'Drop initializer that became pointless'?
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/32] powercap: Stop using 32-bit MSR interfaces
2026-06-29 11:25 ` Ingo Molnar
@ 2026-06-29 11:33 ` Jürgen Groß
2026-06-29 12:31 ` Ingo Molnar
0 siblings, 1 reply; 80+ messages in thread
From: Jürgen Groß @ 2026-06-29 11:33 UTC (permalink / raw)
To: Ingo Molnar; +Cc: linux-kernel, linux-pm, Rafael J. Wysocki
[-- Attachment #1.1.1: Type: text/plain, Size: 979 bytes --]
On 29.06.26 13:25, Ingo Molnar wrote:
>
> * Juergen Gross <jgross@suse.com> wrote:
>
>> The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to
>> be removed. Use the related 64-bit variants instead.
>>
>> Drop a pointless initializer.
>
> Was the initializer really 'pointless'? IIRC it suppressed a build warning
> on 32-bit builds, at least in some past iterations of these APIs.
I don't see the connection to 32-bit builds. Either the uninitialized
variable is a problem or not. And I don't see why "l" didn't need an initial
value (it is modified in this function only via a "&=" operation, so some
bits would still be random in case it is seen not to be set by rdmsr_safe()).
In reality it should never be a problem, as rdmsr_safe() will always set both
output variables to a value (0 in case of error, MSR contents else).
>
> So maybe this should say: 'Drop initializer that became pointless'?
I don't think so.
Juergen
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^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/32] powercap: Stop using 32-bit MSR interfaces
2026-06-29 11:33 ` Jürgen Groß
@ 2026-06-29 12:31 ` Ingo Molnar
2026-06-29 12:52 ` Jürgen Groß
0 siblings, 1 reply; 80+ messages in thread
From: Ingo Molnar @ 2026-06-29 12:31 UTC (permalink / raw)
To: Jürgen Groß; +Cc: linux-kernel, linux-pm, Rafael J. Wysocki
* Jürgen Groß <jgross@suse.com> wrote:
> On 29.06.26 13:25, Ingo Molnar wrote:
> >
> > * Juergen Gross <jgross@suse.com> wrote:
> >
> > > The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to
> > > be removed. Use the related 64-bit variants instead.
> > >
> > > Drop a pointless initializer.
> >
> > Was the initializer really 'pointless'? IIRC it suppressed a build warning
> > on 32-bit builds, at least in some past iterations of these APIs.
>
> I don't see the connection to 32-bit builds. Either the uninitialized
> variable is a problem or not. And I don't see why "l" didn't need an initial
> value (it is modified in this function only via a "&=" operation, so some
> bits would still be random in case it is seen not to be set by rdmsr_safe()).
>
> In reality it should never be a problem, as rdmsr_safe() will always set both
> output variables to a value (0 in case of error, MSR contents else).
So it's not rdmsr_safe() but rdmsr(), but we had this:
10a5d65856b9 ("x86/process: Convert rdmsr() to rdmsrq() in arch_post_acpi_subsys_init() to address W=1 warning")
Which addressed this W=1 warning:
arch/x86/kernel/process.c: In function 'arch_post_acpi_subsys_init':
arch/x86/kernel/process.c:972:17: warning: variable 'hi' set but not used
By the pattern the 'pointless' hi=0 initialization looks similar
and may not be as pointless as it seems. :-)
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 02/32] powercap: Stop using 32-bit MSR interfaces
2026-06-29 12:31 ` Ingo Molnar
@ 2026-06-29 12:52 ` Jürgen Groß
0 siblings, 0 replies; 80+ messages in thread
From: Jürgen Groß @ 2026-06-29 12:52 UTC (permalink / raw)
To: Ingo Molnar; +Cc: linux-kernel, linux-pm, Rafael J. Wysocki
[-- Attachment #1.1.1: Type: text/plain, Size: 2173 bytes --]
On 29.06.26 14:31, Ingo Molnar wrote:
>
> * Jürgen Groß <jgross@suse.com> wrote:
>
>> On 29.06.26 13:25, Ingo Molnar wrote:
>>>
>>> * Juergen Gross <jgross@suse.com> wrote:
>>>
>>>> The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to
>>>> be removed. Use the related 64-bit variants instead.
>>>>
>>>> Drop a pointless initializer.
>>>
>>> Was the initializer really 'pointless'? IIRC it suppressed a build warning
>>> on 32-bit builds, at least in some past iterations of these APIs.
>>
>> I don't see the connection to 32-bit builds. Either the uninitialized
>> variable is a problem or not. And I don't see why "l" didn't need an initial
>> value (it is modified in this function only via a "&=" operation, so some
>> bits would still be random in case it is seen not to be set by rdmsr_safe()).
>>
>> In reality it should never be a problem, as rdmsr_safe() will always set both
>> output variables to a value (0 in case of error, MSR contents else).
>
> So it's not rdmsr_safe() but rdmsr(), but we had this:
>
> 10a5d65856b9 ("x86/process: Convert rdmsr() to rdmsrq() in arch_post_acpi_subsys_init() to address W=1 warning")
>
> Which addressed this W=1 warning:
>
> arch/x86/kernel/process.c: In function 'arch_post_acpi_subsys_init':
> arch/x86/kernel/process.c:972:17: warning: variable 'hi' set but not used
>
> By the pattern the 'pointless' hi=0 initialization looks similar
> and may not be as pointless as it seems. :-)
Maybe I'm not getting something here, but 10a5d65856b9 was not about a
missing initializer, but about "hi" just not being consumed after setting it.
"hi" wasn't initialized before 10a5d65856b9 and it was removed by this commit.
I don't see how a pointless initializer would help in such a case.
It would mean that setting a variable twice fixes a "variable set but not
used" warning, which sounds a little bit weird.
BTW, the "hi=0" initializer was added _before_ rdmsr() would return with the
value being set in case of an error. So at the time of the patch setting hi
to 0 it was correct, but this reason vanished only 2 months later.
Juergen
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3743 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 495 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 03/32] edac: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
2026-06-29 6:04 ` [PATCH 01/32] thermal/intel: Stop using " Juergen Gross
2026-06-29 6:04 ` [PATCH 02/32] powercap: " Juergen Gross
@ 2026-06-29 6:04 ` Juergen Gross
2026-06-30 1:50 ` Zhuo, Qiuxu
2026-07-02 10:15 ` [tip: x86/msr] EDAC: " tip-bot2 for Juergen Gross
2026-06-29 6:04 ` [PATCH 04/32] acpi: " Juergen Gross
` (29 subsequent siblings)
32 siblings, 2 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:04 UTC (permalink / raw)
To: linux-kernel, linux-edac
Cc: Juergen Gross, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam
The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to
be removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/edac/ie31200_edac.c | 10 +++++-----
drivers/edac/mce_amd.c | 8 ++++----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
index e3bd6436669b..94ab80197c2e 100644
--- a/drivers/edac/ie31200_edac.c
+++ b/drivers/edac/ie31200_edac.c
@@ -261,11 +261,11 @@ static void ie31200_clear_error_info(struct mem_ctl_info *mci)
* the ECC error log registers in all memory controllers.
*/
if (cfg->msr_clear_eccerrlog_offset) {
- if (wrmsr_safe(cfg->msr_clear_eccerrlog_offset,
- cfg->reg_eccerrlog_ce_mask |
- cfg->reg_eccerrlog_ce_ovfl_mask |
- cfg->reg_eccerrlog_ue_mask |
- cfg->reg_eccerrlog_ue_ovfl_mask, 0) < 0)
+ if (wrmsrq_safe(cfg->msr_clear_eccerrlog_offset,
+ cfg->reg_eccerrlog_ce_mask |
+ cfg->reg_eccerrlog_ce_ovfl_mask |
+ cfg->reg_eccerrlog_ue_mask |
+ cfg->reg_eccerrlog_ue_ovfl_mask) < 0)
ie31200_printk(KERN_ERR, "Failed to wrmsr.\n");
return;
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index bd252cb3c38e..7aee57a25b68 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -806,7 +806,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
struct mce *m = (struct mce *)data;
struct mce_hw_err *err = to_mce_hw_err(m);
unsigned int fam = x86_family(m->cpuid);
- u32 mca_config_lo = 0, dummy;
+ u64 mca_config = 0;
int ecc;
if (m->kflags & MCE_HANDLED_CEC)
@@ -826,9 +826,9 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
((m->status & MCI_STATUS_PCC) ? "PCC" : "-"));
if (boot_cpu_has(X86_FEATURE_SMCA)) {
- rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), &mca_config_lo, &dummy);
+ rdmsrq_safe(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), &mca_config);
- if (mca_config_lo & MCI_CONFIG_MCAX)
+ if (mca_config & MCI_CONFIG_MCAX)
pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
@@ -863,7 +863,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
if (m->status & MCI_STATUS_SYNDV) {
pr_cont(", Syndrome: 0x%016llx\n", m->synd);
- if (mca_config_lo & MCI_CONFIG_FRUTEXT) {
+ if (mca_config & MCI_CONFIG_FRUTEXT) {
char frutext[17];
frutext[16] = '\0';
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* RE: [PATCH 03/32] edac: Stop using 32-bit MSR interfaces
2026-06-29 6:04 ` [PATCH 03/32] edac: " Juergen Gross
@ 2026-06-30 1:50 ` Zhuo, Qiuxu
2026-07-02 10:15 ` [tip: x86/msr] EDAC: " tip-bot2 for Juergen Gross
1 sibling, 0 replies; 80+ messages in thread
From: Zhuo, Qiuxu @ 2026-06-30 1:50 UTC (permalink / raw)
To: Juergen Gross, linux-kernel@vger.kernel.org,
linux-edac@vger.kernel.org
Cc: Jason Baron, Borislav Petkov, Luck, Tony, Yazen Ghannam
> From: Juergen Gross <jgross@suse.com>
> Sent: Monday, June 29, 2026 2:05 PM
> To: linux-kernel@vger.kernel.org; linux-edac@vger.kernel.org
> Cc: Juergen Gross <jgross@suse.com>; Jason Baron <jbaron@akamai.com>;
> Borislav Petkov <bp@alien8.de>; Luck, Tony <tony.luck@intel.com>; Yazen
> Ghannam <yazen.ghannam@amd.com>
> Subject: [PATCH 03/32] edac: Stop using 32-bit MSR interfaces
>
> The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to be
> removed. Use the related 64-bit variants instead.
>
> Signed-off-by: Juergen Gross <jgross@suse.com>
> ---
> drivers/edac/ie31200_edac.c | 10 +++++-----
> drivers/edac/mce_amd.c | 8 ++++----
> 2 files changed, 9 insertions(+), 9 deletions(-)
For this patch, LGTM.
Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
^ permalink raw reply [flat|nested] 80+ messages in thread
* [tip: x86/msr] EDAC: Stop using 32-bit MSR interfaces
2026-06-29 6:04 ` [PATCH 03/32] edac: " Juergen Gross
2026-06-30 1:50 ` Zhuo, Qiuxu
@ 2026-07-02 10:15 ` tip-bot2 for Juergen Gross
1 sibling, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:15 UTC (permalink / raw)
To: linux-tip-commits
Cc: Juergen Gross, Ingo Molnar, Qiuxu Zhuo, Jason Baron, Tony Luck,
Yazen Ghannam, linux-edac, x86, linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: 3e8ca6691e9d6695e36cafa84217bb8b955face1
Gitweb: https://git.kernel.org/tip/3e8ca6691e9d6695e36cafa84217bb8b955face1
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:04:54 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:53 +02:00
EDAC: Stop using 32-bit MSR interfaces
The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to
be removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: Jason Baron <jbaron@akamai.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: linux-edac@vger.kernel.org
Link: https://patch.msgid.link/20260629060526.3638272-4-jgross@suse.com
---
drivers/edac/ie31200_edac.c | 10 +++++-----
drivers/edac/mce_amd.c | 8 ++++----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
index e3bd643..94ab801 100644
--- a/drivers/edac/ie31200_edac.c
+++ b/drivers/edac/ie31200_edac.c
@@ -261,11 +261,11 @@ static void ie31200_clear_error_info(struct mem_ctl_info *mci)
* the ECC error log registers in all memory controllers.
*/
if (cfg->msr_clear_eccerrlog_offset) {
- if (wrmsr_safe(cfg->msr_clear_eccerrlog_offset,
- cfg->reg_eccerrlog_ce_mask |
- cfg->reg_eccerrlog_ce_ovfl_mask |
- cfg->reg_eccerrlog_ue_mask |
- cfg->reg_eccerrlog_ue_ovfl_mask, 0) < 0)
+ if (wrmsrq_safe(cfg->msr_clear_eccerrlog_offset,
+ cfg->reg_eccerrlog_ce_mask |
+ cfg->reg_eccerrlog_ce_ovfl_mask |
+ cfg->reg_eccerrlog_ue_mask |
+ cfg->reg_eccerrlog_ue_ovfl_mask) < 0)
ie31200_printk(KERN_ERR, "Failed to wrmsr.\n");
return;
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index bd252cb..7aee57a 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -806,7 +806,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
struct mce *m = (struct mce *)data;
struct mce_hw_err *err = to_mce_hw_err(m);
unsigned int fam = x86_family(m->cpuid);
- u32 mca_config_lo = 0, dummy;
+ u64 mca_config = 0;
int ecc;
if (m->kflags & MCE_HANDLED_CEC)
@@ -826,9 +826,9 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
((m->status & MCI_STATUS_PCC) ? "PCC" : "-"));
if (boot_cpu_has(X86_FEATURE_SMCA)) {
- rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), &mca_config_lo, &dummy);
+ rdmsrq_safe(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), &mca_config);
- if (mca_config_lo & MCI_CONFIG_MCAX)
+ if (mca_config & MCI_CONFIG_MCAX)
pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
@@ -863,7 +863,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
if (m->status & MCI_STATUS_SYNDV) {
pr_cont(", Syndrome: 0x%016llx\n", m->synd);
- if (mca_config_lo & MCI_CONFIG_FRUTEXT) {
+ if (mca_config & MCI_CONFIG_FRUTEXT) {
char frutext[17];
frutext[16] = '\0';
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 04/32] acpi: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (2 preceding siblings ...)
2026-06-29 6:04 ` [PATCH 03/32] edac: " Juergen Gross
@ 2026-06-29 6:04 ` Juergen Gross
2026-06-30 12:30 ` Rafael J. Wysocki (Intel)
2026-06-29 6:04 ` [PATCH 05/32] x86/mtrr: " Juergen Gross
` (28 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:04 UTC (permalink / raw)
To: linux-kernel, x86, linux-pm, linux-acpi
Cc: Juergen Gross, Rafael J. Wysocki, Len Brown, Pavel Machek,
Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin
The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and
wrmsr_safe() are planned to be removed. Use the related 64-bit variants
instead.
In processor_throttling.c drop needless initializers.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kernel/acpi/sleep.c | 20 ++++++++------------
drivers/acpi/processor_perflib.c | 11 ++++++-----
drivers/acpi/processor_throttling.c | 14 ++------------
3 files changed, 16 insertions(+), 29 deletions(-)
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 91fa262f0e30..8dfe98784bf9 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -61,6 +61,7 @@ int x86_acpi_suspend_lowlevel(void)
{
struct wakeup_header *header =
(struct wakeup_header *) __va(real_mode_header->wakeup_header);
+ struct msr val;
if (header->signature != WAKEUP_HEADER_SIGNATURE) {
printk(KERN_ERR "wakeup header does not match\n");
@@ -82,13 +83,10 @@ int x86_acpi_suspend_lowlevel(void)
* with 2-MB L2 Cache and Intel® Processor A100 and A110 on 90
* nm process with 512-KB L2 Cache Specification Update".
*/
- if (!rdmsr_safe(MSR_EFER,
- &header->pmode_efer_low,
- &header->pmode_efer_high) &&
- !wrmsr_safe(MSR_EFER,
- header->pmode_efer_low,
- header->pmode_efer_high))
+ if (!rdmsrq_safe(MSR_EFER, &val.q) && !wrmsrq_safe(MSR_EFER, val.q))
header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER);
+ header->pmode_efer_low = val.l;
+ header->pmode_efer_high = val.h;
#endif /* !CONFIG_64BIT */
header->pmode_cr0 = read_cr0();
@@ -96,14 +94,12 @@ int x86_acpi_suspend_lowlevel(void)
header->pmode_cr4 = __read_cr4();
header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_CR4);
}
- if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
- &header->pmode_misc_en_low,
- &header->pmode_misc_en_high) &&
- !wrmsr_safe(MSR_IA32_MISC_ENABLE,
- header->pmode_misc_en_low,
- header->pmode_misc_en_high))
+ if (!rdmsrq_safe(MSR_IA32_MISC_ENABLE, &val.q) &&
+ !wrmsrq_safe(MSR_IA32_MISC_ENABLE, val.q))
header->pmode_behavior |=
(1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE);
+ header->pmode_misc_en_low = val.l;
+ header->pmode_misc_en_high = val.h;
header->realmode_flags = acpi_realmode_flags;
header->real_magic = 0x12345678;
diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c
index fdf55c285c9a..9e25d6124efd 100644
--- a/drivers/acpi/processor_perflib.c
+++ b/drivers/acpi/processor_perflib.c
@@ -287,7 +287,8 @@ static int acpi_processor_get_performance_control(struct acpi_processor *pr)
*/
static void amd_fixup_frequency(struct acpi_processor_px *px, int i)
{
- u32 hi, lo, fid, did;
+ struct msr val;
+ u32 fid, did;
int index = px->control & 0x00000007;
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
@@ -295,16 +296,16 @@ static void amd_fixup_frequency(struct acpi_processor_px *px, int i)
if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10) ||
boot_cpu_data.x86 == 0x11) {
- rdmsr(MSR_AMD_PSTATE_DEF_BASE + index, lo, hi);
+ rdmsrq(MSR_AMD_PSTATE_DEF_BASE + index, val.q);
/*
* MSR C001_0064+:
* Bit 63: PstateEn. Read-write. If set, the P-state is valid.
*/
- if (!(hi & BIT(31)))
+ if (!(val.h & BIT(31)))
return;
- fid = lo & 0x3f;
- did = (lo >> 6) & 7;
+ fid = val.l & 0x3f;
+ did = (val.l >> 6) & 7;
if (boot_cpu_data.x86 == 0x10)
px->core_frequency = (100 * (fid + 0x10)) >> did;
else
diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c
index c0f92b93747d..d1605e0ab61f 100644
--- a/drivers/acpi/processor_throttling.c
+++ b/drivers/acpi/processor_throttling.c
@@ -698,20 +698,13 @@ static int acpi_processor_get_throttling_fadt(struct acpi_processor *pr)
#ifdef CONFIG_X86
static int acpi_throttling_rdmsr(u64 *value)
{
- u64 msr_high, msr_low;
- u64 msr = 0;
int ret = -1;
if ((this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_INTEL) ||
!this_cpu_has(X86_FEATURE_ACPI)) {
pr_err("HARDWARE addr space,NOT supported yet\n");
} else {
- msr_low = 0;
- msr_high = 0;
- rdmsr_safe(MSR_IA32_THERM_CONTROL,
- (u32 *)&msr_low, (u32 *) &msr_high);
- msr = (msr_high << 32) | msr_low;
- *value = (u64) msr;
+ rdmsrq_safe(MSR_IA32_THERM_CONTROL, value);
ret = 0;
}
return ret;
@@ -720,15 +713,12 @@ static int acpi_throttling_rdmsr(u64 *value)
static int acpi_throttling_wrmsr(u64 value)
{
int ret = -1;
- u64 msr;
if ((this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_INTEL) ||
!this_cpu_has(X86_FEATURE_ACPI)) {
pr_err("HARDWARE addr space,NOT supported yet\n");
} else {
- msr = value;
- wrmsr_safe(MSR_IA32_THERM_CONTROL,
- msr & 0xffffffff, msr >> 32);
+ wrmsrq_safe(MSR_IA32_THERM_CONTROL, value);
ret = 0;
}
return ret;
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 04/32] acpi: Stop using 32-bit MSR interfaces
2026-06-29 6:04 ` [PATCH 04/32] acpi: " Juergen Gross
@ 2026-06-30 12:30 ` Rafael J. Wysocki (Intel)
2026-06-30 12:42 ` Jürgen Groß
2026-07-02 9:17 ` Ingo Molnar
0 siblings, 2 replies; 80+ messages in thread
From: Rafael J. Wysocki (Intel) @ 2026-06-30 12:30 UTC (permalink / raw)
To: Juergen Gross
Cc: linux-kernel, x86, linux-pm, linux-acpi, Rafael J. Wysocki,
Len Brown, Pavel Machek, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin
On Mon, Jun 29, 2026 at 8:05 AM Juergen Gross <jgross@suse.com> wrote:
>
> The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and
> wrmsr_safe() are planned to be removed. Use the related 64-bit variants
> instead.
>
> In processor_throttling.c drop needless initializers.
>
> Signed-off-by: Juergen Gross <jgross@suse.com>
LGTM overall.
Do you want me to pick it up or do you prefer to route it along with
the rest of the series?
> ---
> arch/x86/kernel/acpi/sleep.c | 20 ++++++++------------
> drivers/acpi/processor_perflib.c | 11 ++++++-----
> drivers/acpi/processor_throttling.c | 14 ++------------
> 3 files changed, 16 insertions(+), 29 deletions(-)
>
> diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
> index 91fa262f0e30..8dfe98784bf9 100644
> --- a/arch/x86/kernel/acpi/sleep.c
> +++ b/arch/x86/kernel/acpi/sleep.c
> @@ -61,6 +61,7 @@ int x86_acpi_suspend_lowlevel(void)
> {
> struct wakeup_header *header =
> (struct wakeup_header *) __va(real_mode_header->wakeup_header);
> + struct msr val;
>
> if (header->signature != WAKEUP_HEADER_SIGNATURE) {
> printk(KERN_ERR "wakeup header does not match\n");
> @@ -82,13 +83,10 @@ int x86_acpi_suspend_lowlevel(void)
> * with 2-MB L2 Cache and Intel® Processor A100 and A110 on 90
> * nm process with 512-KB L2 Cache Specification Update".
> */
> - if (!rdmsr_safe(MSR_EFER,
> - &header->pmode_efer_low,
> - &header->pmode_efer_high) &&
> - !wrmsr_safe(MSR_EFER,
> - header->pmode_efer_low,
> - header->pmode_efer_high))
> + if (!rdmsrq_safe(MSR_EFER, &val.q) && !wrmsrq_safe(MSR_EFER, val.q))
> header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER);
> + header->pmode_efer_low = val.l;
> + header->pmode_efer_high = val.h;
> #endif /* !CONFIG_64BIT */
>
> header->pmode_cr0 = read_cr0();
> @@ -96,14 +94,12 @@ int x86_acpi_suspend_lowlevel(void)
> header->pmode_cr4 = __read_cr4();
> header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_CR4);
> }
> - if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
> - &header->pmode_misc_en_low,
> - &header->pmode_misc_en_high) &&
> - !wrmsr_safe(MSR_IA32_MISC_ENABLE,
> - header->pmode_misc_en_low,
> - header->pmode_misc_en_high))
> + if (!rdmsrq_safe(MSR_IA32_MISC_ENABLE, &val.q) &&
> + !wrmsrq_safe(MSR_IA32_MISC_ENABLE, val.q))
> header->pmode_behavior |=
> (1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE);
> + header->pmode_misc_en_low = val.l;
> + header->pmode_misc_en_high = val.h;
> header->realmode_flags = acpi_realmode_flags;
> header->real_magic = 0x12345678;
>
> diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c
> index fdf55c285c9a..9e25d6124efd 100644
> --- a/drivers/acpi/processor_perflib.c
> +++ b/drivers/acpi/processor_perflib.c
> @@ -287,7 +287,8 @@ static int acpi_processor_get_performance_control(struct acpi_processor *pr)
> */
> static void amd_fixup_frequency(struct acpi_processor_px *px, int i)
> {
> - u32 hi, lo, fid, did;
> + struct msr val;
> + u32 fid, did;
> int index = px->control & 0x00000007;
>
> if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
> @@ -295,16 +296,16 @@ static void amd_fixup_frequency(struct acpi_processor_px *px, int i)
>
> if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10) ||
> boot_cpu_data.x86 == 0x11) {
> - rdmsr(MSR_AMD_PSTATE_DEF_BASE + index, lo, hi);
> + rdmsrq(MSR_AMD_PSTATE_DEF_BASE + index, val.q);
> /*
> * MSR C001_0064+:
> * Bit 63: PstateEn. Read-write. If set, the P-state is valid.
> */
> - if (!(hi & BIT(31)))
> + if (!(val.h & BIT(31)))
> return;
>
> - fid = lo & 0x3f;
> - did = (lo >> 6) & 7;
> + fid = val.l & 0x3f;
> + did = (val.l >> 6) & 7;
> if (boot_cpu_data.x86 == 0x10)
> px->core_frequency = (100 * (fid + 0x10)) >> did;
> else
> diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c
> index c0f92b93747d..d1605e0ab61f 100644
> --- a/drivers/acpi/processor_throttling.c
> +++ b/drivers/acpi/processor_throttling.c
> @@ -698,20 +698,13 @@ static int acpi_processor_get_throttling_fadt(struct acpi_processor *pr)
> #ifdef CONFIG_X86
> static int acpi_throttling_rdmsr(u64 *value)
> {
> - u64 msr_high, msr_low;
> - u64 msr = 0;
> int ret = -1;
>
> if ((this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_INTEL) ||
> !this_cpu_has(X86_FEATURE_ACPI)) {
> pr_err("HARDWARE addr space,NOT supported yet\n");
> } else {
> - msr_low = 0;
> - msr_high = 0;
> - rdmsr_safe(MSR_IA32_THERM_CONTROL,
> - (u32 *)&msr_low, (u32 *) &msr_high);
> - msr = (msr_high << 32) | msr_low;
> - *value = (u64) msr;
> + rdmsrq_safe(MSR_IA32_THERM_CONTROL, value);
> ret = 0;
> }
> return ret;
> @@ -720,15 +713,12 @@ static int acpi_throttling_rdmsr(u64 *value)
> static int acpi_throttling_wrmsr(u64 value)
> {
> int ret = -1;
> - u64 msr;
>
> if ((this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_INTEL) ||
> !this_cpu_has(X86_FEATURE_ACPI)) {
> pr_err("HARDWARE addr space,NOT supported yet\n");
> } else {
> - msr = value;
> - wrmsr_safe(MSR_IA32_THERM_CONTROL,
> - msr & 0xffffffff, msr >> 32);
> + wrmsrq_safe(MSR_IA32_THERM_CONTROL, value);
> ret = 0;
> }
> return ret;
> --
> 2.54.0
>
>
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 04/32] acpi: Stop using 32-bit MSR interfaces
2026-06-30 12:30 ` Rafael J. Wysocki (Intel)
@ 2026-06-30 12:42 ` Jürgen Groß
2026-07-02 9:17 ` Ingo Molnar
1 sibling, 0 replies; 80+ messages in thread
From: Jürgen Groß @ 2026-06-30 12:42 UTC (permalink / raw)
To: Rafael J. Wysocki (Intel)
Cc: linux-kernel, x86, linux-pm, linux-acpi, Len Brown, Pavel Machek,
Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin
[-- Attachment #1.1.1: Type: text/plain, Size: 586 bytes --]
On 30.06.26 14:30, Rafael J. Wysocki (Intel) wrote:
> On Mon, Jun 29, 2026 at 8:05 AM Juergen Gross <jgross@suse.com> wrote:
>>
>> The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and
>> wrmsr_safe() are planned to be removed. Use the related 64-bit variants
>> instead.
>>
>> In processor_throttling.c drop needless initializers.
>>
>> Signed-off-by: Juergen Gross <jgross@suse.com>
>
> LGTM overall.
Thanks.
> Do you want me to pick it up or do you prefer to route it along with
> the rest of the series?
I'm fine with you picking it up.
Juergen
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3743 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 495 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 04/32] acpi: Stop using 32-bit MSR interfaces
2026-06-30 12:30 ` Rafael J. Wysocki (Intel)
2026-06-30 12:42 ` Jürgen Groß
@ 2026-07-02 9:17 ` Ingo Molnar
2026-07-02 11:33 ` Rafael J. Wysocki (Intel)
1 sibling, 1 reply; 80+ messages in thread
From: Ingo Molnar @ 2026-07-02 9:17 UTC (permalink / raw)
To: Rafael J. Wysocki (Intel)
Cc: Juergen Gross, linux-kernel, x86, linux-pm, linux-acpi, Len Brown,
Pavel Machek, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
* Rafael J. Wysocki (Intel) <rafael@kernel.org> wrote:
> On Mon, Jun 29, 2026 at 8:05 AM Juergen Gross <jgross@suse.com> wrote:
> >
> > The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and
> > wrmsr_safe() are planned to be removed. Use the related 64-bit variants
> > instead.
> >
> > In processor_throttling.c drop needless initializers.
> >
> > Signed-off-by: Juergen Gross <jgross@suse.com>
>
> LGTM overall.
>
> Do you want me to pick it up or do you prefer to route it along with
> the rest of the series?
I'd like to keep this series together if you don't mind, so that
followup changes can be done more easily.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 04/32] acpi: Stop using 32-bit MSR interfaces
2026-07-02 9:17 ` Ingo Molnar
@ 2026-07-02 11:33 ` Rafael J. Wysocki (Intel)
0 siblings, 0 replies; 80+ messages in thread
From: Rafael J. Wysocki (Intel) @ 2026-07-02 11:33 UTC (permalink / raw)
To: Ingo Molnar
Cc: Rafael J. Wysocki (Intel), Juergen Gross, linux-kernel, x86,
linux-pm, linux-acpi, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, H. Peter Anvin
On Thu, Jul 2, 2026 at 11:17 AM Ingo Molnar <mingo@kernel.org> wrote:
>
>
> * Rafael J. Wysocki (Intel) <rafael@kernel.org> wrote:
>
> > On Mon, Jun 29, 2026 at 8:05 AM Juergen Gross <jgross@suse.com> wrote:
> > >
> > > The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and
> > > wrmsr_safe() are planned to be removed. Use the related 64-bit variants
> > > instead.
> > >
> > > In processor_throttling.c drop needless initializers.
> > >
> > > Signed-off-by: Juergen Gross <jgross@suse.com>
> >
> > LGTM overall.
> >
> > Do you want me to pick it up or do you prefer to route it along with
> > the rest of the series?
>
> I'd like to keep this series together if you don't mind, so that
> followup changes can be done more easily.
Sure.
I will be assuming that tip will be taking care of this change going forward.
Thanks!
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 05/32] x86/mtrr: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (3 preceding siblings ...)
2026-06-29 6:04 ` [PATCH 04/32] acpi: " Juergen Gross
@ 2026-06-29 6:04 ` Juergen Gross
2026-06-29 11:33 ` Ingo Molnar
2026-06-29 6:04 ` [PATCH 06/32] x86/msr: Stop using 32-bit MSR interfaces in lib/msr-smp.c Juergen Gross
` (27 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:04 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and
wrmsr_safe() are planned to be removed. Use the related 64-bit variants
instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kernel/cpu/mtrr/amd.c | 36 ++++++-----
arch/x86/kernel/cpu/mtrr/centaur.c | 18 +++---
arch/x86/kernel/cpu/mtrr/cleanup.c | 18 +++---
arch/x86/kernel/cpu/mtrr/generic.c | 97 ++++++++++++++++--------------
arch/x86/kernel/cpu/mtrr/mtrr.c | 4 +-
5 files changed, 93 insertions(+), 80 deletions(-)
diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c
index ef3e8e42b782..fad93cbf6869 100644
--- a/arch/x86/kernel/cpu/mtrr/amd.c
+++ b/arch/x86/kernel/cpu/mtrr/amd.c
@@ -10,20 +10,23 @@ static void
amd_get_mtrr(unsigned int reg, unsigned long *base,
unsigned long *size, mtrr_type *type)
{
- unsigned long low, high;
+ unsigned long val;
+ struct msr msr;
- rdmsr(MSR_K6_UWCCR, low, high);
+ rdmsrq(MSR_K6_UWCCR, msr.q);
/* Upper dword is region 1, lower is region 0 */
if (reg == 1)
- low = high;
+ val = msr.h;
+ else
+ val = msr.l;
/* The base masks off on the right alignment */
- *base = (low & 0xFFFE0000) >> PAGE_SHIFT;
+ *base = (val & 0xFFFE0000) >> PAGE_SHIFT;
*type = 0;
- if (low & 1)
+ if (val & 1)
*type = MTRR_TYPE_UNCACHABLE;
- if (low & 2)
+ if (val & 2)
*type = MTRR_TYPE_WRCOMB;
- if (!(low & 3)) {
+ if (!(val & 3)) {
*size = 0;
return;
}
@@ -42,8 +45,8 @@ amd_get_mtrr(unsigned int reg, unsigned long *base,
* +1 000 0000 0000 0100
* *128K ...
*/
- low = (~low) & 0x1FFFC;
- *size = (low + 4) << (15 - PAGE_SHIFT);
+ val = (~val) & 0x1FFFC;
+ *size = (val + 4) << (15 - PAGE_SHIFT);
}
/**
@@ -59,17 +62,20 @@ amd_get_mtrr(unsigned int reg, unsigned long *base,
static void
amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
{
- u32 regs[2];
+ union {
+ u32 regs[2];
+ u64 val;
+ } msr;
/*
* Low is MTRR0, High MTRR 1
*/
- rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
+ rdmsrq(MSR_K6_UWCCR, msr.val);
/*
* Blank to disable
*/
if (size == 0) {
- regs[reg] = 0;
+ msr.regs[reg] = 0;
} else {
/*
* Set the register to the base, the type (off by one) and an
@@ -80,8 +86,8 @@ amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type
*
* But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!
*/
- regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
- | (base << PAGE_SHIFT) | (type + 1);
+ msr.regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
+ | (base << PAGE_SHIFT) | (type + 1);
}
/*
@@ -89,7 +95,7 @@ amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type
* disable local interrupts, write back the cache, set the mtrr
*/
wbinvd();
- wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
+ wrmsrq(MSR_K6_UWCCR, msr.val);
}
static int
diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/centaur.c
index 6f6c3ae92943..e32cca1caf59 100644
--- a/arch/x86/kernel/cpu/mtrr/centaur.c
+++ b/arch/x86/kernel/cpu/mtrr/centaur.c
@@ -65,26 +65,26 @@ static void
centaur_set_mcr(unsigned int reg, unsigned long base,
unsigned long size, mtrr_type type)
{
- unsigned long low, high;
+ struct msr val;
if (size == 0) {
/* Disable */
- high = low = 0;
+ val.q = 0;
} else {
- high = base << PAGE_SHIFT;
+ val.h = base << PAGE_SHIFT;
if (centaur_mcr_type == 0) {
/* Only support write-combining... */
- low = -size << PAGE_SHIFT | 0x1f;
+ val.l = -size << PAGE_SHIFT | 0x1f;
} else {
if (type == MTRR_TYPE_UNCACHABLE)
- low = -size << PAGE_SHIFT | 0x02; /* NC */
+ val.l = -size << PAGE_SHIFT | 0x02; /* NC */
else
- low = -size << PAGE_SHIFT | 0x09; /* WWO, WC */
+ val.l = -size << PAGE_SHIFT | 0x09; /* WWO, WC */
}
}
- centaur_mcr[reg].high = high;
- centaur_mcr[reg].low = low;
- wrmsr(MSR_IDT_MCR0 + reg, low, high);
+ centaur_mcr[reg].high = val.h;
+ centaur_mcr[reg].low = val.l;
+ wrmsrq(MSR_IDT_MCR0 + reg, val.q);
}
static int
diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
index e3eee9ae4141..cd1a6dec4064 100644
--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
+++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
@@ -658,8 +658,8 @@ static int __init mtrr_search_optimal_index(void)
int __init mtrr_cleanup(void)
{
unsigned long x_remove_base, x_remove_size;
- unsigned long base, size, def, dummy;
- u64 chunk_size, gran_size;
+ u64 def, chunk_size, gran_size;
+ unsigned long base, size;
mtrr_type type;
int index_good;
int i;
@@ -670,7 +670,7 @@ int __init mtrr_cleanup(void)
if (!cpu_feature_enabled(X86_FEATURE_MTRR) || enable_mtrr_cleanup < 1)
return 0;
- rdmsr(MSR_MTRRdefType, def, dummy);
+ rdmsrq(MSR_MTRRdefType, def);
def &= 0xff;
if (def != MTRR_TYPE_UNCACHABLE)
return 0;
@@ -806,7 +806,7 @@ early_param("disable_mtrr_trim", disable_mtrr_trim_setup);
int __init amd_special_default_mtrr(void)
{
- u32 l, h;
+ u64 q;
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
@@ -814,13 +814,13 @@ int __init amd_special_default_mtrr(void)
if (boot_cpu_data.x86 < 0xf)
return 0;
/* In case some hypervisor doesn't pass SYSCFG through: */
- if (rdmsr_safe(MSR_AMD64_SYSCFG, &l, &h) < 0)
+ if (rdmsrq_safe(MSR_AMD64_SYSCFG, &q) < 0)
return 0;
/*
* Memory between 4GB and top of mem is forced WB by this magic bit.
* Reserved before K8RevF, but should be zero there.
*/
- if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) ==
+ if ((q & (Tom2Enabled | Tom2ForceMemTypeWB)) ==
(Tom2Enabled | Tom2ForceMemTypeWB))
return 1;
return 0;
@@ -854,9 +854,9 @@ real_trim_memory(unsigned long start_pfn, unsigned long limit_pfn)
*/
int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
{
- unsigned long i, base, size, highest_pfn = 0, def, dummy;
+ unsigned long i, base, size, highest_pfn = 0;
mtrr_type type;
- u64 total_trim_size;
+ u64 def, total_trim_size;
/* extra one for all 0 */
int num[MTRR_NUM_TYPES + 1];
@@ -870,7 +870,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
if (!cpu_feature_enabled(X86_FEATURE_MTRR) || disable_mtrr_trim)
return 0;
- rdmsr(MSR_MTRRdefType, def, dummy);
+ rdmsrq(MSR_MTRRdefType, def);
def &= MTRR_DEF_TYPE_TYPE;
if (def != MTRR_TYPE_UNCACHABLE)
return 0;
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 3a8317060732..67cf69f24b00 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -103,7 +103,7 @@ u32 phys_hi_rsvd;
*/
static inline void k8_check_syscfg_dram_mod_en(void)
{
- u32 lo, hi;
+ struct msr val;
if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
(boot_cpu_data.x86 >= 0x0f)))
@@ -112,13 +112,13 @@ static inline void k8_check_syscfg_dram_mod_en(void)
if (cc_platform_has(CC_ATTR_HOST_SEV_SNP))
return;
- rdmsr(MSR_AMD64_SYSCFG, lo, hi);
- if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
+ rdmsrq(MSR_AMD64_SYSCFG, val.q);
+ if (val.l & K8_MTRRFIXRANGE_DRAM_MODIFY) {
pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
" not cleared by BIOS, clearing this bit\n",
smp_processor_id());
- lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
- mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi);
+ val.l &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
+ mtrr_wrmsr(MSR_AMD64_SYSCFG, val.l, val.h);
}
}
@@ -557,8 +557,14 @@ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform)
static void
get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
{
- rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
- rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
+ struct msr val;
+
+ rdmsrq(MTRRphysBase_MSR(index), val.q);
+ vr->base_lo = val.l;
+ vr->base_hi = val.h;
+ rdmsrq(MTRRphysMask_MSR(index), val.q);
+ vr->mask_lo = val.l;
+ vr->mask_hi = val.h;
}
/* Fill the MSR pair relating to a var range */
@@ -577,17 +583,17 @@ void fill_mtrr_var_range(unsigned int index,
static void get_fixed_ranges(mtrr_type *frs)
{
- unsigned int *p = (unsigned int *)frs;
+ u64 *p = (u64 *)frs;
int i;
k8_check_syscfg_dram_mod_en();
- rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
+ rdmsrq(MSR_MTRRfix64K_00000, p[0]);
for (i = 0; i < 2; i++)
- rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
+ rdmsrq(MSR_MTRRfix16K_80000 + i, p[1 + i]);
for (i = 0; i < 8; i++)
- rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
+ rdmsrq(MSR_MTRRfix4K_C0000 + i, p[3 + i]);
}
void mtrr_save_fixed_ranges(void *info)
@@ -689,31 +695,26 @@ static void __init print_mtrr_state(void)
bool __init get_mtrr_state(void)
{
struct mtrr_var_range *vrs;
- unsigned lo, dummy;
unsigned int i;
+ u64 q;
vrs = mtrr_state.var_ranges;
- rdmsr(MSR_MTRRcap, lo, dummy);
- mtrr_state.have_fixed = lo & MTRR_CAP_FIX;
+ rdmsrq(MSR_MTRRcap, q);
+ mtrr_state.have_fixed = q & MTRR_CAP_FIX;
for (i = 0; i < num_var_ranges; i++)
get_mtrr_var_range(i, &vrs[i]);
if (mtrr_state.have_fixed)
get_fixed_ranges(mtrr_state.fixed_ranges);
- rdmsr(MSR_MTRRdefType, lo, dummy);
- mtrr_state.def_type = lo & MTRR_DEF_TYPE_TYPE;
- mtrr_state.enabled = (lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT;
+ rdmsrq(MSR_MTRRdefType, q);
+ mtrr_state.def_type = q & MTRR_DEF_TYPE_TYPE;
+ mtrr_state.enabled = (q & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT;
if (amd_special_default_mtrr()) {
- unsigned low, high;
-
/* TOP_MEM2 */
- rdmsr(MSR_K8_TOP_MEM2, low, high);
- mtrr_tom2 = high;
- mtrr_tom2 <<= 32;
- mtrr_tom2 |= low;
+ rdmsrq(MSR_K8_TOP_MEM2, mtrr_tom2);
mtrr_tom2 &= 0xffffff800000ULL;
}
@@ -750,7 +751,9 @@ void __init mtrr_state_warn(void)
*/
void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
{
- if (wrmsr_safe(msr, a, b) < 0) {
+ struct msr val = { .l = a, .h = b };
+
+ if (wrmsrq_safe(msr, val.q) < 0) {
pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
smp_processor_id(), msr, a, b);
}
@@ -765,11 +768,11 @@ void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
*/
static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
{
- unsigned lo, hi;
+ struct msr val;
- rdmsr(msr, lo, hi);
+ rdmsrq(msr, val.q);
- if (lo != msrwords[0] || hi != msrwords[1]) {
+ if (val.l != msrwords[0] || val.h != msrwords[1]) {
mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
*changed = true;
}
@@ -806,9 +809,8 @@ generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
static void generic_get_mtrr(unsigned int reg, unsigned long *base,
unsigned long *size, mtrr_type *type)
{
- u32 mask_lo, mask_hi, base_lo, base_hi;
+ u64 tmp, mask, base_msr;
unsigned int hi;
- u64 tmp, mask;
/*
* get_mtrr doesn't need to update mtrr_state, also it could be called
@@ -816,9 +818,9 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
*/
get_cpu();
- rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
+ rdmsrq(MTRRphysMask_MSR(reg), mask);
- if (!(mask_lo & MTRR_PHYSMASK_V)) {
+ if (!(mask & MTRR_PHYSMASK_V)) {
/* Invalid (i.e. free) range */
*base = 0;
*size = 0;
@@ -826,10 +828,10 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
goto out_put_cpu;
}
- rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
+ rdmsrq(MTRRphysBase_MSR(reg), base_msr);
/* Work out the shifted address mask: */
- tmp = (u64)mask_hi << 32 | (mask_lo & PAGE_MASK);
+ tmp = mask & PAGE_MASK;
mask = (u64)phys_hi_rsvd << 32 | tmp;
/* Expand tmp with high bits to all 1s: */
@@ -849,8 +851,8 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
* contiguous range:
*/
*size = -mask >> PAGE_SHIFT;
- *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
- *type = base_lo & MTRR_PHYSBASE_TYPE;
+ *base = base_msr >> PAGE_SHIFT;
+ *type = base_msr & MTRR_PHYSBASE_TYPE;
out_put_cpu:
put_cpu();
@@ -884,21 +886,21 @@ static int set_fixed_ranges(mtrr_type *frs)
*/
static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
{
- unsigned int lo, hi;
bool changed = false;
+ struct msr val;
- rdmsr(MTRRphysBase_MSR(index), lo, hi);
- if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (lo & ~MTRR_PHYSBASE_RSVD)
- || (vr->base_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) {
+ rdmsrq(MTRRphysBase_MSR(index), val.q);
+ if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (val.l & ~MTRR_PHYSBASE_RSVD)
+ || (vr->base_hi & ~phys_hi_rsvd) != (val.h & ~phys_hi_rsvd)) {
mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
changed = true;
}
- rdmsr(MTRRphysMask_MSR(index), lo, hi);
+ rdmsrq(MTRRphysMask_MSR(index), val.q);
- if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (lo & ~MTRR_PHYSMASK_RSVD)
- || (vr->mask_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) {
+ if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (val.l & ~MTRR_PHYSMASK_RSVD)
+ || (vr->mask_hi & ~phys_hi_rsvd) != (val.h & ~phys_hi_rsvd)) {
mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
changed = true;
}
@@ -947,8 +949,12 @@ static unsigned long set_mtrr_state(void)
void mtrr_disable(void)
{
+ struct msr val;
+
/* Save MTRR state */
- rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
+ rdmsrq(MSR_MTRRdefType, val.q);
+ deftype_lo = val.l;
+ deftype_hi = val.h;
/* Disable MTRRs, and set the default type to uncached */
mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, deftype_hi);
@@ -1057,8 +1063,9 @@ int generic_validate_add_page(unsigned long base, unsigned long size,
static int generic_have_wrcomb(void)
{
- unsigned long config, dummy;
- rdmsr(MSR_MTRRcap, config, dummy);
+ u64 config;
+
+ rdmsrq(MSR_MTRRcap, config);
return config & MTRR_CAP_WC;
}
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
index 4b3d492afe17..468c53b20acf 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
@@ -547,7 +547,7 @@ void __init mtrr_bp_init(void)
{
bool generic_mtrrs = cpu_feature_enabled(X86_FEATURE_MTRR);
const char *why = "(not available)";
- unsigned long config, dummy;
+ unsigned long config;
phys_hi_rsvd = GENMASK(31, boot_cpu_data.x86_phys_bits - 32);
@@ -571,7 +571,7 @@ void __init mtrr_bp_init(void)
if (mtrr_enabled()) {
/* Get the number of variable MTRR ranges. */
if (mtrr_if == &generic_mtrr_ops)
- rdmsr(MSR_MTRRcap, config, dummy);
+ rdmsrq(MSR_MTRRcap, config);
else
config = mtrr_if->var_regs;
num_var_ranges = config & MTRR_CAP_VCNT;
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 05/32] x86/mtrr: Stop using 32-bit MSR interfaces
2026-06-29 6:04 ` [PATCH 05/32] x86/mtrr: " Juergen Gross
@ 2026-06-29 11:33 ` Ingo Molnar
2026-06-29 11:41 ` Jürgen Groß
0 siblings, 1 reply; 80+ messages in thread
From: Ingo Molnar @ 2026-06-29 11:33 UTC (permalink / raw)
To: Juergen Gross
Cc: linux-kernel, x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
* Juergen Gross <jgross@suse.com> wrote:
> amd_get_mtrr(unsigned int reg, unsigned long *base,
> unsigned long *size, mtrr_type *type)
> {
> - unsigned long low, high;
> + unsigned long val;
> + struct msr msr;
So, 'struct msr' is defined in <asm/msr.h>, but:
> static void
> amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
> {
> - u32 regs[2];
> + union {
> + u32 regs[2];
> + u64 val;
> + } msr;
Why do we use a local anonymous union here with overlapping
nomenclature and a confusingly different but (AFAICS) functionally
equivalent definition to 'struct msr'?
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 05/32] x86/mtrr: Stop using 32-bit MSR interfaces
2026-06-29 11:33 ` Ingo Molnar
@ 2026-06-29 11:41 ` Jürgen Groß
2026-06-29 12:27 ` Ingo Molnar
0 siblings, 1 reply; 80+ messages in thread
From: Jürgen Groß @ 2026-06-29 11:41 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
[-- Attachment #1.1.1: Type: text/plain, Size: 1024 bytes --]
On 29.06.26 13:33, Ingo Molnar wrote:
>
> * Juergen Gross <jgross@suse.com> wrote:
>
>> amd_get_mtrr(unsigned int reg, unsigned long *base,
>> unsigned long *size, mtrr_type *type)
>> {
>> - unsigned long low, high;
>> + unsigned long val;
>> + struct msr msr;
>
> So, 'struct msr' is defined in <asm/msr.h>, but:
>
>> static void
>> amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
>> {
>> - u32 regs[2];
>> + union {
>> + u32 regs[2];
>> + u64 val;
>> + } msr;
>
> Why do we use a local anonymous union here with overlapping
> nomenclature and a confusingly different but (AFAICS) functionally
> equivalent definition to 'struct msr'?
This is done in order to avoid having to change the code too much. As an
alternative I could use struct msr by doing:
rdmsrq(MSR_K6_UWCCR, msr.q);
regs[0] = msr.l;
regs[1] = msr.h;
...
msr.l = regs[0];
msr.h = regs[1];
wrmsrq(MSR_K6_UWCCR, msr.q);
Juergen
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^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 05/32] x86/mtrr: Stop using 32-bit MSR interfaces
2026-06-29 11:41 ` Jürgen Groß
@ 2026-06-29 12:27 ` Ingo Molnar
2026-06-29 13:04 ` Jürgen Groß
0 siblings, 1 reply; 80+ messages in thread
From: Ingo Molnar @ 2026-06-29 12:27 UTC (permalink / raw)
To: Jürgen Groß
Cc: linux-kernel, x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
* Jürgen Groß <jgross@suse.com> wrote:
> On 29.06.26 13:33, Ingo Molnar wrote:
> >
> > * Juergen Gross <jgross@suse.com> wrote:
> >
> > > amd_get_mtrr(unsigned int reg, unsigned long *base,
> > > unsigned long *size, mtrr_type *type)
> > > {
> > > - unsigned long low, high;
> > > + unsigned long val;
> > > + struct msr msr;
> >
> > So, 'struct msr' is defined in <asm/msr.h>, but:
> >
> > > static void
> > > amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
> > > {
> > > - u32 regs[2];
> > > + union {
> > > + u32 regs[2];
> > > + u64 val;
> > > + } msr;
> >
> > Why do we use a local anonymous union here with overlapping
> > nomenclature and a confusingly different but (AFAICS) functionally
> > equivalent definition to 'struct msr'?
>
> This is done in order to avoid having to change the code too much.
That's OK, but I'd suggest a followup cleanup in a separate patch:
> alternative I could use struct msr by doing:
>
> rdmsrq(MSR_K6_UWCCR, msr.q);
> regs[0] = msr.l;
> regs[1] = msr.h;
>
> ...
>
> msr.l = regs[0];
> msr.h = regs[1];
> wrmsrq(MSR_K6_UWCCR, msr.q);
Or just move regs[] over to a struct msr variable use?
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 05/32] x86/mtrr: Stop using 32-bit MSR interfaces
2026-06-29 12:27 ` Ingo Molnar
@ 2026-06-29 13:04 ` Jürgen Groß
2026-07-02 9:15 ` Ingo Molnar
0 siblings, 1 reply; 80+ messages in thread
From: Jürgen Groß @ 2026-06-29 13:04 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
[-- Attachment #1.1.1: Type: text/plain, Size: 1581 bytes --]
On 29.06.26 14:27, Ingo Molnar wrote:
>
> * Jürgen Groß <jgross@suse.com> wrote:
>
>> On 29.06.26 13:33, Ingo Molnar wrote:
>>>
>>> * Juergen Gross <jgross@suse.com> wrote:
>>>
>>>> amd_get_mtrr(unsigned int reg, unsigned long *base,
>>>> unsigned long *size, mtrr_type *type)
>>>> {
>>>> - unsigned long low, high;
>>>> + unsigned long val;
>>>> + struct msr msr;
>>>
>>> So, 'struct msr' is defined in <asm/msr.h>, but:
>>>
>>>> static void
>>>> amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
>>>> {
>>>> - u32 regs[2];
>>>> + union {
>>>> + u32 regs[2];
>>>> + u64 val;
>>>> + } msr;
>>>
>>> Why do we use a local anonymous union here with overlapping
>>> nomenclature and a confusingly different but (AFAICS) functionally
>>> equivalent definition to 'struct msr'?
>>
>> This is done in order to avoid having to change the code too much.
>
> That's OK, but I'd suggest a followup cleanup in a separate patch:
>
>> alternative I could use struct msr by doing:
>>
>> rdmsrq(MSR_K6_UWCCR, msr.q);
>> regs[0] = msr.l;
>> regs[1] = msr.h;
>>
>> ...
>>
>> msr.l = regs[0];
>> msr.h = regs[1];
>> wrmsrq(MSR_K6_UWCCR, msr.q);
I think it would be easier to just use that initially. I can change the
patch accordingly.
> Or just move regs[] over to a struct msr variable use?
That would be nasty, as the index used for addressing the correct regs[]
member is _calculated_, so for each access there would need to be an "if".
Juergen
[-- Attachment #1.1.2: OpenPGP public key --]
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[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 495 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 05/32] x86/mtrr: Stop using 32-bit MSR interfaces
2026-06-29 13:04 ` Jürgen Groß
@ 2026-07-02 9:15 ` Ingo Molnar
0 siblings, 0 replies; 80+ messages in thread
From: Ingo Molnar @ 2026-07-02 9:15 UTC (permalink / raw)
To: Jürgen Groß
Cc: linux-kernel, x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
* Jürgen Groß <jgross@suse.com> wrote:
> > > alternative I could use struct msr by doing:
> > >
> > > rdmsrq(MSR_K6_UWCCR, msr.q);
> > > regs[0] = msr.l;
> > > regs[1] = msr.h;
> > >
> > > ...
> > >
> > > msr.l = regs[0];
> > > msr.h = regs[1];
> > > wrmsrq(MSR_K6_UWCCR, msr.q);
>
> I think it would be easier to just use that initially. I can change the
> patch accordingly.
>
> > Or just move regs[] over to a struct msr variable use?
>
> That would be nasty, as the index used for addressing the correct regs[]
> member is _calculated_, so for each access there would need to be an "if".
Ok, fair enough.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 06/32] x86/msr: Stop using 32-bit MSR interfaces in lib/msr-smp.c
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (4 preceding siblings ...)
2026-06-29 6:04 ` [PATCH 05/32] x86/mtrr: " Juergen Gross
@ 2026-06-29 6:04 ` Juergen Gross
2026-07-02 10:16 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
2026-06-29 6:04 ` [PATCH 07/32] x86/msr: Remove wrmsr_safe() Juergen Gross
` (26 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:04 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and
wrmsr_safe() are planned to be removed. Use the related 64-bit variants
instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/lib/msr-smp.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c
index 0c6627773c80..7b6cfc2c0970 100644
--- a/arch/x86/lib/msr-smp.c
+++ b/arch/x86/lib/msr-smp.c
@@ -15,7 +15,7 @@ static void __rdmsr_on_cpu(void *info)
else
reg = &rv->reg;
- rdmsr(rv->msr_no, reg->l, reg->h);
+ rdmsrq(rv->msr_no, reg->q);
}
static void __wrmsr_on_cpu(void *info)
@@ -28,7 +28,7 @@ static void __wrmsr_on_cpu(void *info)
else
reg = &rv->reg;
- wrmsr(rv->msr_no, reg->l, reg->h);
+ wrmsrq(rv->msr_no, reg->q);
}
int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
@@ -121,7 +121,7 @@ static void __rdmsr_safe_on_cpu(void *info)
{
struct msr_info_completion *rv = info;
- rv->msr.err = rdmsr_safe(rv->msr.msr_no, &rv->msr.reg.l, &rv->msr.reg.h);
+ rv->msr.err = rdmsrq_safe(rv->msr.msr_no, &rv->msr.reg.q);
complete(&rv->done);
}
@@ -129,7 +129,7 @@ static void __wrmsr_safe_on_cpu(void *info)
{
struct msr_info *rv = info;
- rv->err = wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h);
+ rv->err = wrmsrq_safe(rv->msr_no, rv->reg.q);
}
int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [tip: x86/msr] x86/msr: Stop using 32-bit MSR interfaces in lib/msr-smp.c
2026-06-29 6:04 ` [PATCH 06/32] x86/msr: Stop using 32-bit MSR interfaces in lib/msr-smp.c Juergen Gross
@ 2026-07-02 10:16 ` tip-bot2 for Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:16 UTC (permalink / raw)
To: linux-tip-commits
Cc: Juergen Gross, Ingo Molnar, H. Peter Anvin, x86, linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: c69d7feb8d124e5f82d502ce0d93d8be6bd80dd1
Gitweb: https://git.kernel.org/tip/c69d7feb8d124e5f82d502ce0d93d8be6bd80dd1
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:04:57 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:51 +02:00
x86/msr: Stop using 32-bit MSR interfaces in lib/msr-smp.c
The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and
wrmsr_safe() are planned to be removed. Use the related 64-bit variants
instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Link: https://patch.msgid.link/20260629060526.3638272-7-jgross@suse.com
---
arch/x86/lib/msr-smp.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c
index 0c66277..7b6cfc2 100644
--- a/arch/x86/lib/msr-smp.c
+++ b/arch/x86/lib/msr-smp.c
@@ -15,7 +15,7 @@ static void __rdmsr_on_cpu(void *info)
else
reg = &rv->reg;
- rdmsr(rv->msr_no, reg->l, reg->h);
+ rdmsrq(rv->msr_no, reg->q);
}
static void __wrmsr_on_cpu(void *info)
@@ -28,7 +28,7 @@ static void __wrmsr_on_cpu(void *info)
else
reg = &rv->reg;
- wrmsr(rv->msr_no, reg->l, reg->h);
+ wrmsrq(rv->msr_no, reg->q);
}
int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
@@ -121,7 +121,7 @@ static void __rdmsr_safe_on_cpu(void *info)
{
struct msr_info_completion *rv = info;
- rv->msr.err = rdmsr_safe(rv->msr.msr_no, &rv->msr.reg.l, &rv->msr.reg.h);
+ rv->msr.err = rdmsrq_safe(rv->msr.msr_no, &rv->msr.reg.q);
complete(&rv->done);
}
@@ -129,7 +129,7 @@ static void __wrmsr_safe_on_cpu(void *info)
{
struct msr_info *rv = info;
- rv->err = wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h);
+ rv->err = wrmsrq_safe(rv->msr_no, rv->reg.q);
}
int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 07/32] x86/msr: Remove wrmsr_safe()
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (5 preceding siblings ...)
2026-06-29 6:04 ` [PATCH 06/32] x86/msr: Stop using 32-bit MSR interfaces in lib/msr-smp.c Juergen Gross
@ 2026-06-29 6:04 ` Juergen Gross
2026-06-29 6:04 ` [PATCH 08/32] x86/mce: Stop using 32-bit MSR interfaces Juergen Gross
` (25 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:04 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
wrmsr_safe() has no users left. Delete it.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/include/asm/msr.h | 8 --------
1 file changed, 8 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 2f41a9289d79..6fb7125608c7 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -242,14 +242,6 @@ static __always_inline void wrmsrns(u32 msr, u64 val)
: : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)));
}
-/*
- * Dual u32 version of wrmsrq_safe():
- */
-static inline int wrmsr_safe(u32 msr, u32 low, u32 high)
-{
- return wrmsrq_safe(msr, (u64)high << 32 | low);
-}
-
struct msr __percpu *msrs_alloc(void);
void msrs_free(struct msr __percpu *msrs);
int msr_set_bit(u32 msr, u8 bit);
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 08/32] x86/mce: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (6 preceding siblings ...)
2026-06-29 6:04 ` [PATCH 07/32] x86/msr: Remove wrmsr_safe() Juergen Gross
@ 2026-06-29 6:04 ` Juergen Gross
2026-07-02 10:16 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
2026-06-29 6:05 ` [PATCH 09/32] KVM/x86: " Juergen Gross
` (24 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:04 UTC (permalink / raw)
To: linux-kernel, x86, linux-edac
Cc: Juergen Gross, Tony Luck, Borislav Petkov, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin
The 32-bit MSR interfaces rdmsr(), wrmsr() and rdmsr_safe() are
planned to be removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kernel/cpu/mce/amd.c | 87 ++++++++++++++++---------------
arch/x86/kernel/cpu/mce/core.c | 2 +-
arch/x86/kernel/cpu/mce/p5.c | 16 +++---
arch/x86/kernel/cpu/mce/winchip.c | 10 ++--
4 files changed, 58 insertions(+), 57 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 36e0df4d1342..f916fb4c5d13 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -280,11 +280,11 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
u8 *bank_counts = this_cpu_ptr(smca_bank_counts);
const struct smca_hwid *s_hwid;
unsigned int i, hwid_mcatype;
- u32 high, low;
+ struct msr val;
u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
/* Set appropriate bits in MCA_CONFIG */
- if (!rdmsr_safe(smca_config, &low, &high)) {
+ if (!rdmsrq_safe(smca_config, &val.q)) {
/*
* OS is required to set the MCAX bit to acknowledge that it is
* now using the new MSR ranges and new registers under each
@@ -294,7 +294,7 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
*
* MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
*/
- high |= BIT(0);
+ val.h |= BIT(0);
/*
* SMCA sets the Deferred Error Interrupt type per bank.
@@ -307,9 +307,9 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
* APIC based interrupt. First, check that no interrupt has been
* set.
*/
- if ((low & BIT(5)) && !((high >> 5) & 0x3) && data->dfr_intr_en) {
+ if ((val.l & BIT(5)) && !((val.h >> 5) & 0x3) && data->dfr_intr_en) {
__set_bit(bank, data->dfr_intr_banks);
- high |= BIT(5);
+ val.h |= BIT(5);
}
/*
@@ -324,33 +324,33 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
* The OS should set this to inform the platform that the OS is ready
* to handle the MCA Thresholding interrupt.
*/
- if ((low & BIT(10)) && data->thr_intr_en) {
+ if ((val.l & BIT(10)) && data->thr_intr_en) {
__set_bit(bank, data->thr_intr_banks);
- high |= BIT(8);
+ val.h |= BIT(8);
}
- this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
+ this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(val.l & BIT(8));
- if (low & MCI_CONFIG_PADDRV)
+ if (val.l & MCI_CONFIG_PADDRV)
this_cpu_ptr(smca_banks)[bank].paddrv = 1;
- wrmsr(smca_config, low, high);
+ wrmsrq(smca_config, val.q);
}
- if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
+ if (rdmsrq_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &val.q)) {
pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
return;
}
- hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
- (high & MCI_IPID_MCATYPE) >> 16);
+ hwid_mcatype = HWID_MCATYPE(val.h & MCI_IPID_HWID,
+ (val.h & MCI_IPID_MCATYPE) >> 16);
for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
s_hwid = &smca_hwid_mcatypes[i];
if (hwid_mcatype == s_hwid->hwid_mcatype) {
this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;
- this_cpu_ptr(smca_banks)[bank].id = low;
+ this_cpu_ptr(smca_banks)[bank].id = val.l;
this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;
break;
}
@@ -432,50 +432,50 @@ static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
static void threshold_restart_block(void *_tr)
{
struct thresh_restart *tr = _tr;
- u32 hi, lo;
+ struct msr val;
/* sysfs write might race against an offline operation */
if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
return;
- rdmsr(tr->b->address, lo, hi);
+ rdmsrq(tr->b->address, val.q);
/*
* Reset error count and overflow bit.
* This is done during init or after handling an interrupt.
*/
- if (hi & MASK_OVERFLOW_HI || tr->set_lvt_off) {
- hi &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI);
- hi |= THRESHOLD_MAX - tr->b->threshold_limit;
+ if (val.h & MASK_OVERFLOW_HI || tr->set_lvt_off) {
+ val.h &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI);
+ val.h |= THRESHOLD_MAX - tr->b->threshold_limit;
} else if (tr->old_limit) { /* change limit w/o reset */
- int new_count = (hi & THRESHOLD_MAX) +
+ int new_count = (val.h & THRESHOLD_MAX) +
(tr->old_limit - tr->b->threshold_limit);
- hi = (hi & ~MASK_ERR_COUNT_HI) |
+ val.h = (val.h & ~MASK_ERR_COUNT_HI) |
(new_count & THRESHOLD_MAX);
}
/* clear IntType */
- hi &= ~MASK_INT_TYPE_HI;
+ val.h &= ~MASK_INT_TYPE_HI;
if (!tr->b->interrupt_capable)
goto done;
if (tr->set_lvt_off) {
- if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
+ if (lvt_off_valid(tr->b, tr->lvt_off, val.l, val.h)) {
/* set new lvt offset */
- hi &= ~MASK_LVTOFF_HI;
- hi |= tr->lvt_off << 20;
+ val.h &= ~MASK_LVTOFF_HI;
+ val.h |= tr->lvt_off << 20;
}
}
if (tr->b->interrupt_enable)
- hi |= INT_TYPE_APIC;
+ val.h |= INT_TYPE_APIC;
done:
- hi |= MASK_COUNT_EN_HI;
- wrmsr(tr->b->address, lo, hi);
+ val.h |= MASK_COUNT_EN_HI;
+ wrmsrq(tr->b->address, val.q);
}
static void threshold_restart_bank(unsigned int bank, bool intr_en)
@@ -726,7 +726,8 @@ static void smca_enable_interrupt_vectors(void)
void mce_amd_feature_init(struct cpuinfo_x86 *c)
{
unsigned int bank, block, cpu = smp_processor_id();
- u32 low = 0, high = 0, address = 0;
+ struct msr val = { .q = 0 };
+ u32 address = 0;
int offset = -1;
amd_apply_cpu_quirks(c);
@@ -746,21 +747,21 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
disable_err_thresholding(c, bank);
for (block = 0; block < NR_BLOCKS; ++block) {
- address = get_block_address(address, low, high, bank, block, cpu);
+ address = get_block_address(address, val.l, val.h, bank, block, cpu);
if (!address)
break;
- if (rdmsr_safe(address, &low, &high))
+ if (rdmsrq_safe(address, &val.q))
break;
- if (!(high & MASK_VALID_HI))
+ if (!(val.h & MASK_VALID_HI))
continue;
- if (!(high & MASK_CNTP_HI) ||
- (high & MASK_LOCKED_HI))
+ if (!(val.h & MASK_CNTP_HI) ||
+ (val.h & MASK_LOCKED_HI))
continue;
- offset = prepare_threshold_block(bank, block, address, offset, high);
+ offset = prepare_threshold_block(bank, block, address, offset, val.h);
}
}
}
@@ -1083,24 +1084,24 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
u32 address)
{
struct threshold_block *b = NULL;
- u32 low, high;
+ struct msr val;
int err;
if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))
return 0;
- if (rdmsr_safe(address, &low, &high))
+ if (rdmsrq_safe(address, &val.q))
return 0;
- if (!(high & MASK_VALID_HI)) {
+ if (!(val.h & MASK_VALID_HI)) {
if (block)
goto recurse;
else
return 0;
}
- if (!(high & MASK_CNTP_HI) ||
- (high & MASK_LOCKED_HI))
+ if (!(val.h & MASK_CNTP_HI) ||
+ (val.h & MASK_LOCKED_HI))
goto recurse;
b = kzalloc_obj(struct threshold_block);
@@ -1112,7 +1113,7 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
b->cpu = cpu;
b->address = address;
b->interrupt_enable = 0;
- b->interrupt_capable = lvt_interrupt_supported(bank, high);
+ b->interrupt_capable = lvt_interrupt_supported(bank, val.h);
b->threshold_limit = get_thr_limit();
if (b->interrupt_capable) {
@@ -1124,13 +1125,13 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
list_add(&b->miscj, &tb->miscj);
- mce_threshold_block_init(b, (high & MASK_LVTOFF_HI) >> 20);
+ mce_threshold_block_init(b, (val.h & MASK_LVTOFF_HI) >> 20);
err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));
if (err)
goto out_free;
recurse:
- address = get_block_address(address, low, high, bank, ++block, cpu);
+ address = get_block_address(address, val.l, val.h, bank, ++block, cpu);
if (!address)
return 0;
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 9bba1e2f03af..017aaf57ba47 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1866,7 +1866,7 @@ static void __mcheck_cpu_init_generic(void)
rdmsrq(MSR_IA32_MCG_CAP, cap);
if (cap & MCG_CTL_P)
- wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+ wrmsrq(MSR_IA32_MCG_CTL, ~0ULL);
}
static void __mcheck_cpu_init_prepare_banks(void)
diff --git a/arch/x86/kernel/cpu/mce/p5.c b/arch/x86/kernel/cpu/mce/p5.c
index 2272ad53fc33..eb99f384d747 100644
--- a/arch/x86/kernel/cpu/mce/p5.c
+++ b/arch/x86/kernel/cpu/mce/p5.c
@@ -23,16 +23,16 @@ int mce_p5_enabled __read_mostly;
/* Machine check handler for Pentium class Intel CPUs: */
noinstr void pentium_machine_check(struct pt_regs *regs)
{
- u32 loaddr, hi, lotype;
+ u64 addr, type;
instrumentation_begin();
- rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
- rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
+ rdmsrq(MSR_IA32_P5_MC_ADDR, addr);
+ rdmsrq(MSR_IA32_P5_MC_TYPE, type);
pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
- smp_processor_id(), loaddr, lotype);
+ smp_processor_id(), (u32)addr, (u32)type);
- if (lotype & (1<<5)) {
+ if (type & (1<<5)) {
pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
smp_processor_id());
}
@@ -44,7 +44,7 @@ noinstr void pentium_machine_check(struct pt_regs *regs)
/* Set up machine check reporting for processors with Intel style MCE: */
void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
{
- u32 l, h;
+ u64 q;
/* Default P5 to off as its often misconnected: */
if (!mce_p5_enabled)
@@ -55,8 +55,8 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
return;
/* Read registers before enabling: */
- rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
- rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
+ rdmsrq(MSR_IA32_P5_MC_ADDR, q);
+ rdmsrq(MSR_IA32_P5_MC_TYPE, q);
pr_info("Intel old style machine check architecture supported.\n");
/* Enable MCE: */
diff --git a/arch/x86/kernel/cpu/mce/winchip.c b/arch/x86/kernel/cpu/mce/winchip.c
index 6c99f2941909..7040243533d9 100644
--- a/arch/x86/kernel/cpu/mce/winchip.c
+++ b/arch/x86/kernel/cpu/mce/winchip.c
@@ -28,12 +28,12 @@ noinstr void winchip_machine_check(struct pt_regs *regs)
/* Set up machine check reporting on the Winchip C6 series */
void winchip_mcheck_init(struct cpuinfo_x86 *c)
{
- u32 lo, hi;
+ struct msr val;
- rdmsr(MSR_IDT_FCR1, lo, hi);
- lo |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
- lo &= ~(1<<4); /* Enable MCE */
- wrmsr(MSR_IDT_FCR1, lo, hi);
+ rdmsrq(MSR_IDT_FCR1, val.q);
+ val.l |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
+ val.l &= ~(1<<4); /* Enable MCE */
+ wrmsrq(MSR_IDT_FCR1, val.q);
cr4_set_bits(X86_CR4_MCE);
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [tip: x86/msr] x86/mce: Stop using 32-bit MSR interfaces
2026-06-29 6:04 ` [PATCH 08/32] x86/mce: Stop using 32-bit MSR interfaces Juergen Gross
@ 2026-07-02 10:16 ` tip-bot2 for Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:16 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Juergen Gross, Ingo Molnar, x86, linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: cff219368bd066d67cc66e8fcdd2c4b13f5101ce
Gitweb: https://git.kernel.org/tip/cff219368bd066d67cc66e8fcdd2c4b13f5101ce
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:04:59 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:51 +02:00
x86/mce: Stop using 32-bit MSR interfaces
The 32-bit MSR interfaces rdmsr(), wrmsr() and rdmsr_safe() are
planned to be removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://patch.msgid.link/20260629060526.3638272-9-jgross@suse.com
---
arch/x86/kernel/cpu/mce/amd.c | 87 +++++++++++++++---------------
arch/x86/kernel/cpu/mce/core.c | 2 +-
arch/x86/kernel/cpu/mce/p5.c | 16 +++---
arch/x86/kernel/cpu/mce/winchip.c | 10 +--
4 files changed, 58 insertions(+), 57 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 36e0df4..f916fb4 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -280,11 +280,11 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
u8 *bank_counts = this_cpu_ptr(smca_bank_counts);
const struct smca_hwid *s_hwid;
unsigned int i, hwid_mcatype;
- u32 high, low;
+ struct msr val;
u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
/* Set appropriate bits in MCA_CONFIG */
- if (!rdmsr_safe(smca_config, &low, &high)) {
+ if (!rdmsrq_safe(smca_config, &val.q)) {
/*
* OS is required to set the MCAX bit to acknowledge that it is
* now using the new MSR ranges and new registers under each
@@ -294,7 +294,7 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
*
* MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
*/
- high |= BIT(0);
+ val.h |= BIT(0);
/*
* SMCA sets the Deferred Error Interrupt type per bank.
@@ -307,9 +307,9 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
* APIC based interrupt. First, check that no interrupt has been
* set.
*/
- if ((low & BIT(5)) && !((high >> 5) & 0x3) && data->dfr_intr_en) {
+ if ((val.l & BIT(5)) && !((val.h >> 5) & 0x3) && data->dfr_intr_en) {
__set_bit(bank, data->dfr_intr_banks);
- high |= BIT(5);
+ val.h |= BIT(5);
}
/*
@@ -324,33 +324,33 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
* The OS should set this to inform the platform that the OS is ready
* to handle the MCA Thresholding interrupt.
*/
- if ((low & BIT(10)) && data->thr_intr_en) {
+ if ((val.l & BIT(10)) && data->thr_intr_en) {
__set_bit(bank, data->thr_intr_banks);
- high |= BIT(8);
+ val.h |= BIT(8);
}
- this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
+ this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(val.l & BIT(8));
- if (low & MCI_CONFIG_PADDRV)
+ if (val.l & MCI_CONFIG_PADDRV)
this_cpu_ptr(smca_banks)[bank].paddrv = 1;
- wrmsr(smca_config, low, high);
+ wrmsrq(smca_config, val.q);
}
- if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
+ if (rdmsrq_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &val.q)) {
pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
return;
}
- hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
- (high & MCI_IPID_MCATYPE) >> 16);
+ hwid_mcatype = HWID_MCATYPE(val.h & MCI_IPID_HWID,
+ (val.h & MCI_IPID_MCATYPE) >> 16);
for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
s_hwid = &smca_hwid_mcatypes[i];
if (hwid_mcatype == s_hwid->hwid_mcatype) {
this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;
- this_cpu_ptr(smca_banks)[bank].id = low;
+ this_cpu_ptr(smca_banks)[bank].id = val.l;
this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;
break;
}
@@ -432,50 +432,50 @@ static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
static void threshold_restart_block(void *_tr)
{
struct thresh_restart *tr = _tr;
- u32 hi, lo;
+ struct msr val;
/* sysfs write might race against an offline operation */
if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
return;
- rdmsr(tr->b->address, lo, hi);
+ rdmsrq(tr->b->address, val.q);
/*
* Reset error count and overflow bit.
* This is done during init or after handling an interrupt.
*/
- if (hi & MASK_OVERFLOW_HI || tr->set_lvt_off) {
- hi &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI);
- hi |= THRESHOLD_MAX - tr->b->threshold_limit;
+ if (val.h & MASK_OVERFLOW_HI || tr->set_lvt_off) {
+ val.h &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI);
+ val.h |= THRESHOLD_MAX - tr->b->threshold_limit;
} else if (tr->old_limit) { /* change limit w/o reset */
- int new_count = (hi & THRESHOLD_MAX) +
+ int new_count = (val.h & THRESHOLD_MAX) +
(tr->old_limit - tr->b->threshold_limit);
- hi = (hi & ~MASK_ERR_COUNT_HI) |
+ val.h = (val.h & ~MASK_ERR_COUNT_HI) |
(new_count & THRESHOLD_MAX);
}
/* clear IntType */
- hi &= ~MASK_INT_TYPE_HI;
+ val.h &= ~MASK_INT_TYPE_HI;
if (!tr->b->interrupt_capable)
goto done;
if (tr->set_lvt_off) {
- if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
+ if (lvt_off_valid(tr->b, tr->lvt_off, val.l, val.h)) {
/* set new lvt offset */
- hi &= ~MASK_LVTOFF_HI;
- hi |= tr->lvt_off << 20;
+ val.h &= ~MASK_LVTOFF_HI;
+ val.h |= tr->lvt_off << 20;
}
}
if (tr->b->interrupt_enable)
- hi |= INT_TYPE_APIC;
+ val.h |= INT_TYPE_APIC;
done:
- hi |= MASK_COUNT_EN_HI;
- wrmsr(tr->b->address, lo, hi);
+ val.h |= MASK_COUNT_EN_HI;
+ wrmsrq(tr->b->address, val.q);
}
static void threshold_restart_bank(unsigned int bank, bool intr_en)
@@ -726,7 +726,8 @@ static void smca_enable_interrupt_vectors(void)
void mce_amd_feature_init(struct cpuinfo_x86 *c)
{
unsigned int bank, block, cpu = smp_processor_id();
- u32 low = 0, high = 0, address = 0;
+ struct msr val = { .q = 0 };
+ u32 address = 0;
int offset = -1;
amd_apply_cpu_quirks(c);
@@ -746,21 +747,21 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
disable_err_thresholding(c, bank);
for (block = 0; block < NR_BLOCKS; ++block) {
- address = get_block_address(address, low, high, bank, block, cpu);
+ address = get_block_address(address, val.l, val.h, bank, block, cpu);
if (!address)
break;
- if (rdmsr_safe(address, &low, &high))
+ if (rdmsrq_safe(address, &val.q))
break;
- if (!(high & MASK_VALID_HI))
+ if (!(val.h & MASK_VALID_HI))
continue;
- if (!(high & MASK_CNTP_HI) ||
- (high & MASK_LOCKED_HI))
+ if (!(val.h & MASK_CNTP_HI) ||
+ (val.h & MASK_LOCKED_HI))
continue;
- offset = prepare_threshold_block(bank, block, address, offset, high);
+ offset = prepare_threshold_block(bank, block, address, offset, val.h);
}
}
}
@@ -1083,24 +1084,24 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
u32 address)
{
struct threshold_block *b = NULL;
- u32 low, high;
+ struct msr val;
int err;
if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))
return 0;
- if (rdmsr_safe(address, &low, &high))
+ if (rdmsrq_safe(address, &val.q))
return 0;
- if (!(high & MASK_VALID_HI)) {
+ if (!(val.h & MASK_VALID_HI)) {
if (block)
goto recurse;
else
return 0;
}
- if (!(high & MASK_CNTP_HI) ||
- (high & MASK_LOCKED_HI))
+ if (!(val.h & MASK_CNTP_HI) ||
+ (val.h & MASK_LOCKED_HI))
goto recurse;
b = kzalloc_obj(struct threshold_block);
@@ -1112,7 +1113,7 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
b->cpu = cpu;
b->address = address;
b->interrupt_enable = 0;
- b->interrupt_capable = lvt_interrupt_supported(bank, high);
+ b->interrupt_capable = lvt_interrupt_supported(bank, val.h);
b->threshold_limit = get_thr_limit();
if (b->interrupt_capable) {
@@ -1124,13 +1125,13 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
list_add(&b->miscj, &tb->miscj);
- mce_threshold_block_init(b, (high & MASK_LVTOFF_HI) >> 20);
+ mce_threshold_block_init(b, (val.h & MASK_LVTOFF_HI) >> 20);
err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));
if (err)
goto out_free;
recurse:
- address = get_block_address(address, low, high, bank, ++block, cpu);
+ address = get_block_address(address, val.l, val.h, bank, ++block, cpu);
if (!address)
return 0;
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 9bba1e2..017aaf5 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1866,7 +1866,7 @@ static void __mcheck_cpu_init_generic(void)
rdmsrq(MSR_IA32_MCG_CAP, cap);
if (cap & MCG_CTL_P)
- wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+ wrmsrq(MSR_IA32_MCG_CTL, ~0ULL);
}
static void __mcheck_cpu_init_prepare_banks(void)
diff --git a/arch/x86/kernel/cpu/mce/p5.c b/arch/x86/kernel/cpu/mce/p5.c
index 2272ad5..eb99f38 100644
--- a/arch/x86/kernel/cpu/mce/p5.c
+++ b/arch/x86/kernel/cpu/mce/p5.c
@@ -23,16 +23,16 @@ int mce_p5_enabled __read_mostly;
/* Machine check handler for Pentium class Intel CPUs: */
noinstr void pentium_machine_check(struct pt_regs *regs)
{
- u32 loaddr, hi, lotype;
+ u64 addr, type;
instrumentation_begin();
- rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
- rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
+ rdmsrq(MSR_IA32_P5_MC_ADDR, addr);
+ rdmsrq(MSR_IA32_P5_MC_TYPE, type);
pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
- smp_processor_id(), loaddr, lotype);
+ smp_processor_id(), (u32)addr, (u32)type);
- if (lotype & (1<<5)) {
+ if (type & (1<<5)) {
pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
smp_processor_id());
}
@@ -44,7 +44,7 @@ noinstr void pentium_machine_check(struct pt_regs *regs)
/* Set up machine check reporting for processors with Intel style MCE: */
void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
{
- u32 l, h;
+ u64 q;
/* Default P5 to off as its often misconnected: */
if (!mce_p5_enabled)
@@ -55,8 +55,8 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
return;
/* Read registers before enabling: */
- rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
- rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
+ rdmsrq(MSR_IA32_P5_MC_ADDR, q);
+ rdmsrq(MSR_IA32_P5_MC_TYPE, q);
pr_info("Intel old style machine check architecture supported.\n");
/* Enable MCE: */
diff --git a/arch/x86/kernel/cpu/mce/winchip.c b/arch/x86/kernel/cpu/mce/winchip.c
index 6c99f29..7040243 100644
--- a/arch/x86/kernel/cpu/mce/winchip.c
+++ b/arch/x86/kernel/cpu/mce/winchip.c
@@ -28,12 +28,12 @@ noinstr void winchip_machine_check(struct pt_regs *regs)
/* Set up machine check reporting on the Winchip C6 series */
void winchip_mcheck_init(struct cpuinfo_x86 *c)
{
- u32 lo, hi;
+ struct msr val;
- rdmsr(MSR_IDT_FCR1, lo, hi);
- lo |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
- lo &= ~(1<<4); /* Enable MCE */
- wrmsr(MSR_IDT_FCR1, lo, hi);
+ rdmsrq(MSR_IDT_FCR1, val.q);
+ val.l |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
+ val.l &= ~(1<<4); /* Enable MCE */
+ wrmsrq(MSR_IDT_FCR1, val.q);
cr4_set_bits(X86_CR4_MCE);
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 09/32] KVM/x86: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (7 preceding siblings ...)
2026-06-29 6:04 ` [PATCH 08/32] x86/mce: Stop using 32-bit MSR interfaces Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 10/32] x86/hygon: " Juergen Gross
` (23 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86, kvm, linux-coco
Cc: Juergen Gross, Sean Christopherson, Paolo Bonzini,
Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin, Kiryl Shutsemau, Rick Edgecombe
The 32-bit MSR interfaces rdmsr(), wrmsr() and rdmsr_safe() are
planned to be removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kvm/vmx/vmx.c | 24 +++++++++++++-----------
arch/x86/kvm/x86.c | 4 ++--
arch/x86/virt/vmx/tdx/tdx.c | 6 ++++--
3 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 2325be57d3d7..49948bbaf2de 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2676,13 +2676,13 @@ static bool cpu_has_sgx(void)
static int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, u32 msr, u32 *result)
{
- u32 vmx_msr_low, vmx_msr_high;
+ struct msr vmx_msr;
u32 ctl = ctl_min | ctl_opt;
- rdmsr(msr, vmx_msr_low, vmx_msr_high);
+ rdmsrq(msr, vmx_msr.q);
- ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
- ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
+ ctl &= vmx_msr.h; /* bit == 0 in high word ==> must be zero */
+ ctl |= vmx_msr.l; /* bit == 1 in low word ==> must be one */
/* Ensure minimum (required) set of control bits are supported. */
if (ctl_min & ~ctl)
@@ -2738,6 +2738,7 @@ static int setup_vmcs_config(struct vmcs_config *vmcs_conf,
u64 _cpu_based_3rd_exec_control = 0;
u32 _vmexit_control = 0;
u32 _vmentry_control = 0;
+ struct msr val;
u64 basic_msr;
u64 misc_msr;
@@ -2787,8 +2788,9 @@ static int setup_vmcs_config(struct vmcs_config *vmcs_conf,
SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
- rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
- &vmx_cap->ept, &vmx_cap->vpid);
+ rdmsrq_safe(MSR_IA32_VMX_EPT_VPID_CAP, &val.q);
+ vmx_cap->ept = val.l;
+ vmx_cap->vpid = val.h;
if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
vmx_cap->ept) {
@@ -4435,7 +4437,7 @@ void vmx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,
*/
void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
{
- u32 low32, high32;
+ struct msr val;
unsigned long tmpl;
unsigned long cr0, cr3, cr4;
@@ -4476,8 +4478,8 @@ void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
- rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
- vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
+ rdmsrq(MSR_IA32_SYSENTER_CS, val.q);
+ vmcs_write32(HOST_IA32_SYSENTER_CS, val.l);
/*
* SYSENTER is used for 32-bit system calls on either 32-bit or
@@ -4492,8 +4494,8 @@ void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
- rdmsr(MSR_IA32_CR_PAT, low32, high32);
- vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
+ rdmsrq(MSR_IA32_CR_PAT, val.q);
+ vmcs_write64(HOST_IA32_PAT, val.q);
}
if (cpu_has_load_ia32_efer())
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index afcac1042947..9b645563ece9 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -7633,9 +7633,9 @@ static void kvm_probe_feature_msr(u32 msr_index)
static void kvm_probe_msr_to_save(u32 msr_index)
{
- u32 dummy[2];
+ u64 dummy;
- if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
+ if (rdmsrq_safe(msr_index, &dummy))
return;
/*
diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c
index 42df8ea464c4..1b9ff749dd8e 100644
--- a/arch/x86/virt/vmx/tdx/tdx.c
+++ b/arch/x86/virt/vmx/tdx/tdx.c
@@ -1430,6 +1430,7 @@ static __init int record_keyid_partitioning(u32 *tdx_keyid_start,
u32 *nr_tdx_keyids)
{
u32 _nr_mktme_keyids, _tdx_keyid_start, _nr_tdx_keyids;
+ struct msr val;
int ret;
/*
@@ -1437,8 +1438,9 @@ static __init int record_keyid_partitioning(u32 *tdx_keyid_start,
* Bit [31:0]: Number of MKTME KeyIDs.
* Bit [63:32]: Number of TDX private KeyIDs.
*/
- ret = rdmsr_safe(MSR_IA32_MKTME_KEYID_PARTITIONING, &_nr_mktme_keyids,
- &_nr_tdx_keyids);
+ ret = rdmsrq_safe(MSR_IA32_MKTME_KEYID_PARTITIONING, &val.q);
+ _nr_mktme_keyids = val.l;
+ _nr_tdx_keyids = val.h;
if (ret || !_nr_tdx_keyids)
return -EINVAL;
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 10/32] x86/hygon: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (8 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 09/32] KVM/x86: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-07-02 10:16 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
2026-06-29 6:05 ` [PATCH 11/32] x86/pci: " Juergen Gross
` (22 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Pu Wen, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin
The 32-bit MSR interface rdmsr_safe()is planned to be removed. Use the
related 64-bit variant instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kernel/cpu/hygon.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 3e8891a9caf2..ec51c2b9a257 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -125,11 +125,12 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c)
static void early_init_hygon(struct cpuinfo_x86 *c)
{
- u32 dummy;
+ u64 val;
set_cpu_cap(c, X86_FEATURE_K8);
- rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
+ rdmsrq_safe(MSR_AMD64_PATCH_LEVEL, &val);
+ c->microcode = (u32)val;
/*
* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [tip: x86/msr] x86/hygon: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 10/32] x86/hygon: " Juergen Gross
@ 2026-07-02 10:16 ` tip-bot2 for Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:16 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Juergen Gross, Ingo Molnar, Pu Wen, x86, linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: c36c3d7e5dc49f0085e26ee4bcd2cb6493b0120e
Gitweb: https://git.kernel.org/tip/c36c3d7e5dc49f0085e26ee4bcd2cb6493b0120e
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:05:01 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:51 +02:00
x86/hygon: Stop using 32-bit MSR interfaces
The 32-bit MSR interface rdmsr_safe()is planned to be removed. Use the
related 64-bit variant instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Pu Wen <puwen@hygon.cn>
Link: https://patch.msgid.link/20260629060526.3638272-11-jgross@suse.com
---
arch/x86/kernel/cpu/hygon.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 3e8891a..ec51c2b 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -125,11 +125,12 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c)
static void early_init_hygon(struct cpuinfo_x86 *c)
{
- u32 dummy;
+ u64 val;
set_cpu_cap(c, X86_FEATURE_K8);
- rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
+ rdmsrq_safe(MSR_AMD64_PATCH_LEVEL, &val);
+ c->microcode = (u32)val;
/*
* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 11/32] x86/pci: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (9 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 10/32] x86/hygon: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-07-02 10:16 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
2026-06-29 6:05 ` [PATCH 12/32] x86/amd: " Juergen Gross
` (21 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86, linux-pci
Cc: Juergen Gross, Bjorn Helgaas, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin
The 32-bit MSR interface rdmsr_safe()is planned to be removed. Use the
related 64-bit variant instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/pci/mmconfig-shared.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index acdb8dcaeb52..9749820f68f7 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -189,7 +189,7 @@ static const char *__init pci_mmcfg_intel_945(void)
static const char *__init pci_mmcfg_amd_fam10h(void)
{
- u32 low, high, address;
+ u32 address;
u64 base, msr;
int i;
unsigned segnbits = 0, busnbits, end_bus;
@@ -198,13 +198,9 @@ static const char *__init pci_mmcfg_amd_fam10h(void)
return NULL;
address = MSR_FAM10H_MMIO_CONF_BASE;
- if (rdmsr_safe(address, &low, &high))
+ if (rdmsrq_safe(address, &msr))
return NULL;
- msr = high;
- msr <<= 32;
- msr |= low;
-
/* ECAM is not enabled */
if (!(msr & FAM10H_MMIO_CONF_ENABLE))
return NULL;
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [tip: x86/msr] x86/pci: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 11/32] x86/pci: " Juergen Gross
@ 2026-07-02 10:16 ` tip-bot2 for Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:16 UTC (permalink / raw)
To: linux-tip-commits
Cc: Juergen Gross, Ingo Molnar, linux-pci, Bjorn Helgaas, x86,
linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: b67096f9dbbb4295c892e266a80b816f24c32f7c
Gitweb: https://git.kernel.org/tip/b67096f9dbbb4295c892e266a80b816f24c32f7c
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:05:02 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:52 +02:00
x86/pci: Stop using 32-bit MSR interfaces
The 32-bit MSR interface rdmsr_safe()is planned to be removed. Use the
related 64-bit variant instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: linux-pci@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260629060526.3638272-12-jgross@suse.com
---
arch/x86/pci/mmconfig-shared.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index acdb8dc..9749820 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -189,7 +189,7 @@ static const char *__init pci_mmcfg_intel_945(void)
static const char *__init pci_mmcfg_amd_fam10h(void)
{
- u32 low, high, address;
+ u32 address;
u64 base, msr;
int i;
unsigned segnbits = 0, busnbits, end_bus;
@@ -198,13 +198,9 @@ static const char *__init pci_mmcfg_amd_fam10h(void)
return NULL;
address = MSR_FAM10H_MMIO_CONF_BASE;
- if (rdmsr_safe(address, &low, &high))
+ if (rdmsrq_safe(address, &msr))
return NULL;
- msr = high;
- msr <<= 32;
- msr |= low;
-
/* ECAM is not enabled */
if (!(msr & FAM10H_MMIO_CONF_ENABLE))
return NULL;
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 12/32] x86/amd: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (10 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 11/32] x86/pci: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-07-02 10:16 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
2026-06-29 6:05 ` [PATCH 13/32] x86/featctl: " Juergen Gross
` (20 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
The 32-bit MSR interfaces rdmsr(), wrmsr() and rdmsr_safe() are
planned to be removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kernel/cpu/amd.c | 34 ++++++++++++++++++----------------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 487ac147e11f..169e373418bb 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -113,7 +113,7 @@ static void init_amd_k5(struct cpuinfo_x86 *c)
static void init_amd_k6(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
- u32 l, h;
+ struct msr val;
int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
if (c->x86_model < 6) {
@@ -160,13 +160,13 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
if (mbytes > 508)
mbytes = 508;
- rdmsr(MSR_K6_WHCR, l, h);
- if ((l&0x0000FFFF) == 0) {
+ rdmsrq(MSR_K6_WHCR, val.q);
+ if ((val.l & 0x0000FFFF) == 0) {
unsigned long flags;
- l = (1<<0)|((mbytes/4)<<1);
+ val.l = (1 << 0) | ((mbytes / 4) << 1);
local_irq_save(flags);
wbinvd();
- wrmsr(MSR_K6_WHCR, l, h);
+ wrmsrq(MSR_K6_WHCR, val.q);
local_irq_restore(flags);
pr_info("Enabling old style K6 write allocation for %d Mb\n",
mbytes);
@@ -181,13 +181,13 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
if (mbytes > 4092)
mbytes = 4092;
- rdmsr(MSR_K6_WHCR, l, h);
- if ((l&0xFFFF0000) == 0) {
+ rdmsrq(MSR_K6_WHCR, val.q);
+ if ((val.l & 0xFFFF0000) == 0) {
unsigned long flags;
- l = ((mbytes>>2)<<22)|(1<<16);
+ val.l = ((mbytes >> 2) << 22) | (1 << 16);
local_irq_save(flags);
wbinvd();
- wrmsr(MSR_K6_WHCR, l, h);
+ wrmsrq(MSR_K6_WHCR, val.q);
local_irq_restore(flags);
pr_info("Enabling new style K6 write allocation for %d Mb\n",
mbytes);
@@ -207,7 +207,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
static void init_amd_k7(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
- u32 l, h;
+ struct msr val;
/*
* Bit 15 of Athlon specific MSR 15, needs to be 0
@@ -228,11 +228,12 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
* As per AMD technical note 27212 0.2
*/
if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
- rdmsr(MSR_K7_CLK_CTL, l, h);
- if ((l & 0xfff00000) != 0x20000000) {
+ rdmsrq(MSR_K7_CLK_CTL, val.q);
+ if ((val.l & 0xfff00000) != 0x20000000) {
pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
- l, ((l & 0x000fffff)|0x20000000));
- wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
+ val.l, ((val.l & 0x000fffff) | 0x20000000));
+ val.l = (val.l & 0x000fffff) | 0x20000000;
+ wrmsrq(MSR_K7_CLK_CTL, val.q);
}
}
@@ -614,12 +615,13 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
static void early_init_amd(struct cpuinfo_x86 *c)
{
- u32 dummy;
+ u64 val;
if (c->x86 >= 0xf)
set_cpu_cap(c, X86_FEATURE_K8);
- rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
+ rdmsrq_safe(MSR_AMD64_PATCH_LEVEL, &val);
+ c->microcode = (u32)val;
/*
* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [tip: x86/msr] x86/amd: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 12/32] x86/amd: " Juergen Gross
@ 2026-07-02 10:16 ` tip-bot2 for Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:16 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Juergen Gross, Ingo Molnar, x86, linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: 9c6be5e789818f6577507ce42fc4b70f0fd44303
Gitweb: https://git.kernel.org/tip/9c6be5e789818f6577507ce42fc4b70f0fd44303
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:05:03 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:52 +02:00
x86/amd: Stop using 32-bit MSR interfaces
The 32-bit MSR interfaces rdmsr(), wrmsr() and rdmsr_safe() are
planned to be removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://patch.msgid.link/20260629060526.3638272-13-jgross@suse.com
---
arch/x86/kernel/cpu/amd.c | 34 ++++++++++++++++++----------------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 487ac14..169e373 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -113,7 +113,7 @@ static void init_amd_k5(struct cpuinfo_x86 *c)
static void init_amd_k6(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
- u32 l, h;
+ struct msr val;
int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
if (c->x86_model < 6) {
@@ -160,13 +160,13 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
if (mbytes > 508)
mbytes = 508;
- rdmsr(MSR_K6_WHCR, l, h);
- if ((l&0x0000FFFF) == 0) {
+ rdmsrq(MSR_K6_WHCR, val.q);
+ if ((val.l & 0x0000FFFF) == 0) {
unsigned long flags;
- l = (1<<0)|((mbytes/4)<<1);
+ val.l = (1 << 0) | ((mbytes / 4) << 1);
local_irq_save(flags);
wbinvd();
- wrmsr(MSR_K6_WHCR, l, h);
+ wrmsrq(MSR_K6_WHCR, val.q);
local_irq_restore(flags);
pr_info("Enabling old style K6 write allocation for %d Mb\n",
mbytes);
@@ -181,13 +181,13 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
if (mbytes > 4092)
mbytes = 4092;
- rdmsr(MSR_K6_WHCR, l, h);
- if ((l&0xFFFF0000) == 0) {
+ rdmsrq(MSR_K6_WHCR, val.q);
+ if ((val.l & 0xFFFF0000) == 0) {
unsigned long flags;
- l = ((mbytes>>2)<<22)|(1<<16);
+ val.l = ((mbytes >> 2) << 22) | (1 << 16);
local_irq_save(flags);
wbinvd();
- wrmsr(MSR_K6_WHCR, l, h);
+ wrmsrq(MSR_K6_WHCR, val.q);
local_irq_restore(flags);
pr_info("Enabling new style K6 write allocation for %d Mb\n",
mbytes);
@@ -207,7 +207,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
static void init_amd_k7(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
- u32 l, h;
+ struct msr val;
/*
* Bit 15 of Athlon specific MSR 15, needs to be 0
@@ -228,11 +228,12 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
* As per AMD technical note 27212 0.2
*/
if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
- rdmsr(MSR_K7_CLK_CTL, l, h);
- if ((l & 0xfff00000) != 0x20000000) {
+ rdmsrq(MSR_K7_CLK_CTL, val.q);
+ if ((val.l & 0xfff00000) != 0x20000000) {
pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
- l, ((l & 0x000fffff)|0x20000000));
- wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
+ val.l, ((val.l & 0x000fffff) | 0x20000000));
+ val.l = (val.l & 0x000fffff) | 0x20000000;
+ wrmsrq(MSR_K7_CLK_CTL, val.q);
}
}
@@ -614,12 +615,13 @@ clear_sev:
static void early_init_amd(struct cpuinfo_x86 *c)
{
- u32 dummy;
+ u64 val;
if (c->x86 >= 0xf)
set_cpu_cap(c, X86_FEATURE_K8);
- rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
+ rdmsrq_safe(MSR_AMD64_PATCH_LEVEL, &val);
+ c->microcode = (u32)val;
/*
* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 13/32] x86/featctl: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (11 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 12/32] x86/amd: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-07-02 9:39 ` Ingo Molnar
2026-06-29 6:05 ` [PATCH 14/32] x86/tsc: " Juergen Gross
` (19 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
The 32-bit MSR interfaces rdmsr() and rdmsr_safe() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kernel/cpu/feat_ctl.c | 27 ++++++++++++++++-----------
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c
index d69757246bde..1ce30a5c26ce 100644
--- a/arch/x86/kernel/cpu/feat_ctl.c
+++ b/arch/x86/kernel/cpu/feat_ctl.c
@@ -25,7 +25,8 @@ enum vmx_feature_leafs {
static void init_vmx_capabilities(struct cpuinfo_x86 *c)
{
- u32 supported, funcs, ept, vpid, ign, low, high;
+ struct msr val;
+ u32 supported, funcs, ept, vpid;
BUILD_BUG_ON(NVMXINTS != NR_VMX_FEATURE_WORDS);
@@ -39,25 +40,29 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c)
* as they exist on any CPU that supports VMX, i.e. we want the WARN if
* the RDMSR faults.
*/
- rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, ign, supported);
- c->vmx_capability[PRIMARY_CTLS] = supported;
+ rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS, val.q);
+ c->vmx_capability[PRIMARY_CTLS] = val.h;
- rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported);
- c->vmx_capability[SECONDARY_CTLS] = supported;
+ rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &val.q);
+ c->vmx_capability[SECONDARY_CTLS] = val.h;
/* All 64 bits of tertiary controls MSR are allowed-1 settings. */
- rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &low, &high);
- c->vmx_capability[TERTIARY_CTLS_LOW] = low;
- c->vmx_capability[TERTIARY_CTLS_HIGH] = high;
+ rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &val.q);
+ c->vmx_capability[TERTIARY_CTLS_LOW] = val.l;
+ c->vmx_capability[TERTIARY_CTLS_HIGH] = val.h;
- rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported);
- rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs);
+ rdmsrq(MSR_IA32_VMX_PINBASED_CTLS, val.q);
+ supported = val.h;
+ rdmsrq_safe(MSR_IA32_VMX_VMFUNC, &val.q);
+ funcs = val.h;
/*
* Except for EPT+VPID, which enumerates support for both in a single
* MSR, low for EPT, high for VPID.
*/
- rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, &ept, &vpid);
+ rdmsrq_safe(MSR_IA32_VMX_EPT_VPID_CAP, &val.q);
+ ept = val.l;
+ vpid = val.h;
/* Pin, EPT, VPID and VM-Func are merged into a single word. */
WARN_ON_ONCE(supported >> 16);
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 13/32] x86/featctl: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 13/32] x86/featctl: " Juergen Gross
@ 2026-07-02 9:39 ` Ingo Molnar
2026-07-02 11:19 ` Jürgen Groß
0 siblings, 1 reply; 80+ messages in thread
From: Ingo Molnar @ 2026-07-02 9:39 UTC (permalink / raw)
To: Juergen Gross
Cc: linux-kernel, x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
* Juergen Gross <jgross@suse.com> wrote:
> - rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, ign, supported);
> - c->vmx_capability[PRIMARY_CTLS] = supported;
> + rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS, val.q);
> + c->vmx_capability[PRIMARY_CTLS] = val.h;
Please keep the original assignment that puts this into the
'supported' variable - which semi-documents the meaning of this
field - even though its use is arguably minimal:
rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS, val.q);
supported = val.h;
c->vmx_capability[PRIMARY_CTLS] = supported;
> - rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported);
> - c->vmx_capability[SECONDARY_CTLS] = supported;
> + rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &val.q);
> + c->vmx_capability[SECONDARY_CTLS] = val.h;
Ditto.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 13/32] x86/featctl: Stop using 32-bit MSR interfaces
2026-07-02 9:39 ` Ingo Molnar
@ 2026-07-02 11:19 ` Jürgen Groß
0 siblings, 0 replies; 80+ messages in thread
From: Jürgen Groß @ 2026-07-02 11:19 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
[-- Attachment #1.1.1: Type: text/plain, Size: 866 bytes --]
On 02.07.26 11:39, Ingo Molnar wrote:
>
> * Juergen Gross <jgross@suse.com> wrote:
>
>> - rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, ign, supported);
>> - c->vmx_capability[PRIMARY_CTLS] = supported;
>> + rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS, val.q);
>> + c->vmx_capability[PRIMARY_CTLS] = val.h;
>
> Please keep the original assignment that puts this into the
> 'supported' variable - which semi-documents the meaning of this
> field - even though its use is arguably minimal:
>
> rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS, val.q);
> supported = val.h;
> c->vmx_capability[PRIMARY_CTLS] = supported;
>
>> - rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported);
>> - c->vmx_capability[SECONDARY_CTLS] = supported;
>> + rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &val.q);
>> + c->vmx_capability[SECONDARY_CTLS] = val.h;
Fine with me.
Juergen
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3743 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 495 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 14/32] x86/tsc: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (12 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 13/32] x86/featctl: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-07-02 10:15 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
2026-06-29 6:05 ` [PATCH 15/32] x86/msr: Remove rdmsr_safe() Juergen Gross
` (18 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
The 32-bit MSR interfaces rdmsr() and rdmsr_safe() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kernel/tsc.c | 6 +++---
arch/x86/kernel/tsc_msr.c | 15 ++++++++-------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index ce10ae4b298b..723347e2cf7f 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1221,11 +1221,11 @@ static void __init check_system_tsc_reliable(void)
if (is_geode_lx()) {
/* RTSC counts during suspend */
#define RTSC_SUSP 0x100
- unsigned long res_low, res_high;
+ u64 res;
- rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
+ rdmsrq_safe(MSR_GEODE_BUSCONT_CONF0, &res);
/* Geode_LX - the OLPC CPU has a very reliable TSC */
- if (res_low & RTSC_SUSP)
+ if (res & RTSC_SUSP)
tsc_clocksource_reliable = 1;
}
#endif
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 48e6cc1cb017..d74743c8d2a4 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -165,7 +165,8 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
*/
unsigned long cpu_khz_from_msr(void)
{
- u32 lo, hi, ratio, freq, tscref;
+ u32 ratio, freq, tscref;
+ struct msr val;
const struct freq_desc *freq_desc;
const struct x86_cpu_id *id;
const struct muldiv *md;
@@ -178,16 +179,16 @@ unsigned long cpu_khz_from_msr(void)
freq_desc = (struct freq_desc *)id->driver_data;
if (freq_desc->use_msr_plat) {
- rdmsr(MSR_PLATFORM_INFO, lo, hi);
- ratio = (lo >> 8) & 0xff;
+ rdmsrq(MSR_PLATFORM_INFO, val.q);
+ ratio = (val.l >> 8) & 0xff;
} else {
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
- ratio = (hi >> 8) & 0x1f;
+ rdmsrq(MSR_IA32_PERF_STATUS, val.q);
+ ratio = (val.h >> 8) & 0x1f;
}
/* Get FSB FREQ ID */
- rdmsr(MSR_FSB_FREQ, lo, hi);
- index = lo & freq_desc->mask;
+ rdmsrq(MSR_FSB_FREQ, val.q);
+ index = val.l & freq_desc->mask;
md = &freq_desc->muldiv[index];
/*
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [tip: x86/msr] x86/tsc: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 14/32] x86/tsc: " Juergen Gross
@ 2026-07-02 10:15 ` tip-bot2 for Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:15 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Juergen Gross, Ingo Molnar, x86, linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: 4ff91f7b8fbfb56424f3b63a3b69286df961bb75
Gitweb: https://git.kernel.org/tip/4ff91f7b8fbfb56424f3b63a3b69286df961bb75
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:05:05 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:52 +02:00
x86/tsc: Stop using 32-bit MSR interfaces
The 32-bit MSR interfaces rdmsr() and rdmsr_safe() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://patch.msgid.link/20260629060526.3638272-15-jgross@suse.com
---
arch/x86/kernel/tsc.c | 6 +++---
arch/x86/kernel/tsc_msr.c | 15 ++++++++-------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index ce10ae4..723347e 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1221,11 +1221,11 @@ static void __init check_system_tsc_reliable(void)
if (is_geode_lx()) {
/* RTSC counts during suspend */
#define RTSC_SUSP 0x100
- unsigned long res_low, res_high;
+ u64 res;
- rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
+ rdmsrq_safe(MSR_GEODE_BUSCONT_CONF0, &res);
/* Geode_LX - the OLPC CPU has a very reliable TSC */
- if (res_low & RTSC_SUSP)
+ if (res & RTSC_SUSP)
tsc_clocksource_reliable = 1;
}
#endif
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 48e6cc1..d74743c 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -165,7 +165,8 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
*/
unsigned long cpu_khz_from_msr(void)
{
- u32 lo, hi, ratio, freq, tscref;
+ u32 ratio, freq, tscref;
+ struct msr val;
const struct freq_desc *freq_desc;
const struct x86_cpu_id *id;
const struct muldiv *md;
@@ -178,16 +179,16 @@ unsigned long cpu_khz_from_msr(void)
freq_desc = (struct freq_desc *)id->driver_data;
if (freq_desc->use_msr_plat) {
- rdmsr(MSR_PLATFORM_INFO, lo, hi);
- ratio = (lo >> 8) & 0xff;
+ rdmsrq(MSR_PLATFORM_INFO, val.q);
+ ratio = (val.l >> 8) & 0xff;
} else {
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
- ratio = (hi >> 8) & 0x1f;
+ rdmsrq(MSR_IA32_PERF_STATUS, val.q);
+ ratio = (val.h >> 8) & 0x1f;
}
/* Get FSB FREQ ID */
- rdmsr(MSR_FSB_FREQ, lo, hi);
- index = lo & freq_desc->mask;
+ rdmsrq(MSR_FSB_FREQ, val.q);
+ index = val.l & freq_desc->mask;
md = &freq_desc->muldiv[index];
/*
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 15/32] x86/msr: Remove rdmsr_safe()
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (13 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 14/32] x86/tsc: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 16/32] cpufreq: Stop using 32-bit MSR interfaces Juergen Gross
` (17 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86, virtualization
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list
rdmsr_safe() has no users left. Delete it.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/include/asm/msr.h | 10 ----------
arch/x86/include/asm/paravirt.h | 10 ----------
2 files changed, 20 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 6fb7125608c7..776a2daa2ba2 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -205,16 +205,6 @@ static inline int wrmsrq_safe(u32 msr, u64 val)
return native_write_msr_safe(msr, val);
}
-/* rdmsr with exception handling */
-#define rdmsr_safe(msr, low, high) \
-({ \
- u64 __val; \
- int __err = native_read_msr_safe((msr), &__val); \
- (*low) = (u32)__val; \
- (*high) = (u32)(__val >> 32); \
- __err; \
-})
-
static inline int rdmsrq_safe(u32 msr, u64 *p)
{
return native_read_msr_safe(msr, p);
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 0591aa38fd85..97b082095572 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -177,16 +177,6 @@ static inline int wrmsrq_safe(u32 msr, u64 val)
return paravirt_write_msr_safe(msr, val);
}
-/* rdmsr with exception handling */
-#define rdmsr_safe(msr, a, b) \
-({ \
- u64 _l; \
- int _err = paravirt_read_msr_safe((msr), &_l); \
- (*a) = (u32)_l; \
- (*b) = (u32)(_l >> 32); \
- _err; \
-})
-
static __always_inline int rdmsrq_safe(u32 msr, u64 *p)
{
return paravirt_read_msr_safe(msr, p);
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 16/32] cpufreq: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (14 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 15/32] x86/msr: Remove rdmsr_safe() Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 14:55 ` Zhongqiu Han
2026-06-29 6:05 ` [PATCH 17/32] x86/resctrl: " Juergen Gross
` (16 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, linux-pm; +Cc: Juergen Gross, Rafael J. Wysocki, Viresh Kumar
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/cpufreq/acpi-cpufreq.c | 22 ++++----
drivers/cpufreq/e_powersaver.c | 48 ++++++++---------
drivers/cpufreq/longhaul.c | 15 +++---
drivers/cpufreq/longrun.c | 78 +++++++++++++++-------------
drivers/cpufreq/powernow-k6.c | 12 ++---
drivers/cpufreq/powernow-k8.c | 67 ++++++++++++------------
drivers/cpufreq/speedstep-centrino.c | 16 +++---
drivers/cpufreq/speedstep-lib.c | 63 +++++++++++-----------
8 files changed, 166 insertions(+), 155 deletions(-)
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 21639d9ac753..b40fa99b5ab2 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -246,32 +246,32 @@ static unsigned extract_freq(struct cpufreq_policy *policy, u32 val)
static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used)
{
- u32 val, dummy __always_unused;
+ u64 val;
- rdmsr(MSR_IA32_PERF_CTL, val, dummy);
- return val;
+ rdmsrq(MSR_IA32_PERF_CTL, val);
+ return (u32)val;
}
static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val)
{
- u32 lo, hi;
+ struct msr msrval;
- rdmsr(MSR_IA32_PERF_CTL, lo, hi);
- lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
- wrmsr(MSR_IA32_PERF_CTL, lo, hi);
+ rdmsrq(MSR_IA32_PERF_CTL, msrval.q);
+ msrval.h = (msrval.h & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
+ wrmsrq(MSR_IA32_PERF_CTL, msrval.q);
}
static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used)
{
- u32 val, dummy __always_unused;
+ u64 val;
- rdmsr(MSR_AMD_PERF_CTL, val, dummy);
- return val;
+ rdmsrq(MSR_AMD_PERF_CTL, val);
+ return (u32)val;
}
static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val)
{
- wrmsr(MSR_AMD_PERF_CTL, val, 0);
+ wrmsrq(MSR_AMD_PERF_CTL, val);
}
static u32 cpu_freq_read_io(struct acpi_pct_register *reg)
diff --git a/drivers/cpufreq/e_powersaver.c b/drivers/cpufreq/e_powersaver.c
index eb5a9209d828..13709f9667ea 100644
--- a/drivers/cpufreq/e_powersaver.c
+++ b/drivers/cpufreq/e_powersaver.c
@@ -90,7 +90,7 @@ static int eps_acpi_exit(struct cpufreq_policy *policy)
static unsigned int eps_get(unsigned int cpu)
{
struct eps_cpu_data *centaur;
- u32 lo, hi;
+ u64 val;
if (cpu)
return 0;
@@ -99,35 +99,35 @@ static unsigned int eps_get(unsigned int cpu)
return 0;
/* Return current frequency */
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
- return centaur->fsb * ((lo >> 8) & 0xff);
+ rdmsrq(MSR_IA32_PERF_STATUS, val);
+ return centaur->fsb * ((val >> 8) & 0xff);
}
static int eps_set_state(struct eps_cpu_data *centaur,
struct cpufreq_policy *policy,
u32 dest_state)
{
- u32 lo, hi;
+ u64 val;
int i;
/* Wait while CPU is busy */
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ rdmsrq(MSR_IA32_PERF_STATUS, val);
i = 0;
- while (lo & ((1 << 16) | (1 << 17))) {
+ while (val & ((1 << 16) | (1 << 17))) {
udelay(16);
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ rdmsrq(MSR_IA32_PERF_STATUS, val);
i++;
if (unlikely(i > 64)) {
return -ENODEV;
}
}
/* Set new multiplier and voltage */
- wrmsr(MSR_IA32_PERF_CTL, dest_state & 0xffff, 0);
+ wrmsrq(MSR_IA32_PERF_CTL, dest_state & 0xffff);
/* Wait until transition end */
i = 0;
do {
udelay(16);
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ rdmsrq(MSR_IA32_PERF_STATUS, val);
i++;
if (unlikely(i > 64)) {
return -ENODEV;
@@ -139,10 +139,10 @@ static int eps_set_state(struct eps_cpu_data *centaur,
u8 current_multiplier, current_voltage;
/* Print voltage and multiplier */
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
- current_voltage = lo & 0xff;
+ rdmsrq(MSR_IA32_PERF_STATUS, val);
+ current_voltage = val & 0xff;
pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
- current_multiplier = (lo >> 8) & 0xff;
+ current_multiplier = (val >> 8) & 0xff;
pr_info("Current multiplier = %d\n", current_multiplier);
}
#endif
@@ -171,8 +171,8 @@ static int eps_target(struct cpufreq_policy *policy, unsigned int index)
static int eps_cpu_init(struct cpufreq_policy *policy)
{
unsigned int i;
- u32 lo, hi;
u64 val;
+ struct msr status;
u8 current_multiplier, current_voltage;
u8 max_multiplier, max_voltage;
u8 min_multiplier, min_voltage;
@@ -195,13 +195,13 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
switch (c->x86_model) {
case 10:
- rdmsr(0x1153, lo, hi);
- brand = (((lo >> 2) ^ lo) >> 18) & 3;
+ rdmsrq(0x1153, val);
+ brand = (((val >> 2) ^ val) >> 18) & 3;
pr_cont("Model A ");
break;
case 13:
- rdmsr(0x1154, lo, hi);
- brand = (((lo >> 4) ^ (lo >> 2))) & 0x000000ff;
+ rdmsrq(0x1154, val);
+ brand = (((val >> 4) ^ (val >> 2))) & 0x000000ff;
pr_cont("Model D ");
break;
}
@@ -237,20 +237,20 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
}
/* Print voltage and multiplier */
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
- current_voltage = lo & 0xff;
+ rdmsrq(MSR_IA32_PERF_STATUS, status.q);
+ current_voltage = status.l & 0xff;
pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
- current_multiplier = (lo >> 8) & 0xff;
+ current_multiplier = (status.l >> 8) & 0xff;
pr_info("Current multiplier = %d\n", current_multiplier);
/* Print limits */
- max_voltage = hi & 0xff;
+ max_voltage = status.h & 0xff;
pr_info("Highest voltage = %dmV\n", max_voltage * 16 + 700);
- max_multiplier = (hi >> 8) & 0xff;
+ max_multiplier = (status.h >> 8) & 0xff;
pr_info("Highest multiplier = %d\n", max_multiplier);
- min_voltage = (hi >> 16) & 0xff;
+ min_voltage = (status.h >> 16) & 0xff;
pr_info("Lowest voltage = %dmV\n", min_voltage * 16 + 700);
- min_multiplier = (hi >> 24) & 0xff;
+ min_multiplier = (status.h >> 24) & 0xff;
pr_info("Lowest multiplier = %d\n", min_multiplier);
/* Sanity checks */
diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
index a18d1d11725f..4c2599264333 100644
--- a/drivers/cpufreq/longhaul.c
+++ b/drivers/cpufreq/longhaul.c
@@ -118,13 +118,14 @@ static unsigned int calc_speed(int mult)
static int longhaul_get_cpu_mult(void)
{
- unsigned long invalue = 0, lo, hi;
+ unsigned long invalue = 0;
+ u64 val;
- rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
- invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22;
+ rdmsrq(MSR_IA32_EBL_CR_POWERON, val);
+ invalue = (val & (1<<22|1<<23|1<<24|1<<25))>>22;
if (longhaul_version == TYPE_LONGHAUL_V2 ||
longhaul_version == TYPE_POWERSAVER) {
- if (lo & (1<<27))
+ if (val & (1<<27))
invalue += 16;
}
return eblcr[invalue];
@@ -761,7 +762,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
struct cpuinfo_x86 *c = &cpu_data(0);
char *cpuname = NULL;
int ret;
- u32 lo, hi;
+ u64 val;
/* Check what we have on this motherboard */
switch (c->x86_model) {
@@ -835,8 +836,8 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
}
/* Check Longhaul ver. 2 */
if (longhaul_version == TYPE_LONGHAUL_V2) {
- rdmsr(MSR_VIA_LONGHAUL, lo, hi);
- if (lo == 0 && hi == 0)
+ rdmsrq(MSR_VIA_LONGHAUL, val);
+ if (val == 0)
/* Looks like MSR isn't present */
longhaul_version = TYPE_LONGHAUL_V1;
}
diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c
index f3aaca0496a4..99abef32e7e5 100644
--- a/drivers/cpufreq/longrun.c
+++ b/drivers/cpufreq/longrun.c
@@ -35,27 +35,27 @@ static unsigned int longrun_low_freq, longrun_high_freq;
*/
static void longrun_get_policy(struct cpufreq_policy *policy)
{
- u32 msr_lo, msr_hi;
+ struct msr msr;
- rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
- pr_debug("longrun flags are %x - %x\n", msr_lo, msr_hi);
- if (msr_lo & 0x01)
+ rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
+ pr_debug("longrun flags are %x - %x\n", msr.l, msr.h);
+ if (msr.l & 0x01)
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
else
policy->policy = CPUFREQ_POLICY_POWERSAVE;
- rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
- pr_debug("longrun ctrl is %x - %x\n", msr_lo, msr_hi);
- msr_lo &= 0x0000007F;
- msr_hi &= 0x0000007F;
+ rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
+ pr_debug("longrun ctrl is %x - %x\n", msr.l, msr.h);
+ msr.l &= 0x0000007F;
+ msr.h &= 0x0000007F;
if (longrun_high_freq <= longrun_low_freq) {
/* Assume degenerate Longrun table */
policy->min = policy->max = longrun_high_freq;
} else {
- policy->min = longrun_low_freq + msr_lo *
+ policy->min = longrun_low_freq + msr.l *
((longrun_high_freq - longrun_low_freq) / 100);
- policy->max = longrun_low_freq + msr_hi *
+ policy->max = longrun_low_freq + msr.h *
((longrun_high_freq - longrun_low_freq) / 100);
}
policy->cpu = 0;
@@ -71,7 +71,7 @@ static void longrun_get_policy(struct cpufreq_policy *policy)
*/
static int longrun_set_policy(struct cpufreq_policy *policy)
{
- u32 msr_lo, msr_hi;
+ struct msr msr;
u32 pctg_lo, pctg_hi;
if (!policy)
@@ -93,24 +93,24 @@ static int longrun_set_policy(struct cpufreq_policy *policy)
pctg_lo = pctg_hi;
/* performance or economy mode */
- rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
- msr_lo &= 0xFFFFFFFE;
+ rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
+ msr.l &= 0xFFFFFFFE;
switch (policy->policy) {
case CPUFREQ_POLICY_PERFORMANCE:
- msr_lo |= 0x00000001;
+ msr.l |= 0x00000001;
break;
case CPUFREQ_POLICY_POWERSAVE:
break;
}
- wrmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
+ wrmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
/* lower and upper boundary */
- rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
- msr_lo &= 0xFFFFFF80;
- msr_hi &= 0xFFFFFF80;
- msr_lo |= pctg_lo;
- msr_hi |= pctg_hi;
- wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
+ rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
+ msr.l &= 0xFFFFFF80;
+ msr.h &= 0xFFFFFF80;
+ msr.l |= pctg_lo;
+ msr.h |= pctg_hi;
+ wrmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
return 0;
}
@@ -160,7 +160,7 @@ static unsigned int longrun_get(unsigned int cpu)
static int longrun_determine_freqs(unsigned int *low_freq,
unsigned int *high_freq)
{
- u32 msr_lo, msr_hi;
+ struct msr msr;
u32 save_lo, save_hi;
u32 eax, ebx, ecx, edx;
u32 try_hi;
@@ -178,15 +178,17 @@ static int longrun_determine_freqs(unsigned int *low_freq,
* For maximum frequency, read out level zero.
*/
/* minimum */
- rdmsr(MSR_TMTA_LRTI_READOUT, msr_lo, msr_hi);
- wrmsr(MSR_TMTA_LRTI_READOUT, msr_hi, msr_hi);
- rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
- *low_freq = msr_lo * 1000; /* to kHz */
+ rdmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
+ msr.l = msr.h;
+ wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
+ rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
+ *low_freq = msr.l * 1000; /* to kHz */
/* maximum */
- wrmsr(MSR_TMTA_LRTI_READOUT, 0, msr_hi);
- rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
- *high_freq = msr_lo * 1000; /* to kHz */
+ msr.l = 0;
+ wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
+ rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
+ *high_freq = msr.l * 1000; /* to kHz */
pr_debug("longrun table interface told %u - %u kHz\n",
*low_freq, *high_freq);
@@ -202,9 +204,9 @@ static int longrun_determine_freqs(unsigned int *low_freq,
pr_debug("high frequency is %u kHz\n", *high_freq);
/* get current borders */
- rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
- save_lo = msr_lo & 0x0000007F;
- save_hi = msr_hi & 0x0000007F;
+ rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
+ save_lo = msr.l & 0x0000007F;
+ save_hi = msr.h & 0x0000007F;
/* if current perf_pctg is larger than 90%, we need to decrease the
* upper limit to make the calculation more accurate.
@@ -214,16 +216,18 @@ static int longrun_determine_freqs(unsigned int *low_freq,
* on some barrier values */
for (try_hi = 80; try_hi > 0 && ecx > 90; try_hi -= 10) {
/* set to 0 to try_hi perf_pctg */
- msr_lo &= 0xFFFFFF80;
- msr_hi &= 0xFFFFFF80;
- msr_hi |= try_hi;
- wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
+ msr.l &= 0xFFFFFF80;
+ msr.h &= 0xFFFFFF80;
+ msr.h |= try_hi;
+ wrmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
/* read out current core MHz and current perf_pctg */
cpuid(0x80860007, &eax, &ebx, &ecx, &edx);
/* restore values */
- wrmsr(MSR_TMTA_LONGRUN_CTRL, save_lo, save_hi);
+ msr.l = save_lo;
+ msr.h = save_hi;
+ wrmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
}
pr_debug("percentage is %u %%, freq is %u MHz\n", ecx, eax);
diff --git a/drivers/cpufreq/powernow-k6.c b/drivers/cpufreq/powernow-k6.c
index 99d2244e03b0..2044e8a336ec 100644
--- a/drivers/cpufreq/powernow-k6.c
+++ b/drivers/cpufreq/powernow-k6.c
@@ -83,15 +83,15 @@ static const struct {
static int powernow_k6_get_cpu_multiplier(void)
{
unsigned long invalue = 0;
- u32 msrval;
+ u64 msrval;
local_irq_disable();
msrval = POWERNOW_IOPORT + 0x1;
- wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
+ wrmsrq(MSR_K6_EPMR, msrval); /* enable the PowerNow port */
invalue = inl(POWERNOW_IOPORT + 0x8);
msrval = POWERNOW_IOPORT + 0x0;
- wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
+ wrmsrq(MSR_K6_EPMR, msrval); /* disable it again */
local_irq_enable();
@@ -101,8 +101,8 @@ static int powernow_k6_get_cpu_multiplier(void)
static void powernow_k6_set_cpu_multiplier(unsigned int best_i)
{
unsigned long outvalue, invalue;
- unsigned long msrval;
unsigned long cr0;
+ u64 msrval;
/* we now need to transform best_i to the BVC format, see AMD#23446 */
@@ -118,13 +118,13 @@ static void powernow_k6_set_cpu_multiplier(unsigned int best_i)
outvalue = (1<<12) | (1<<10) | (1<<9) | (index_to_register[best_i]<<5);
msrval = POWERNOW_IOPORT + 0x1;
- wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
+ wrmsrq(MSR_K6_EPMR, msrval); /* enable the PowerNow port */
invalue = inl(POWERNOW_IOPORT + 0x8);
invalue = invalue & 0x1f;
outvalue = outvalue | invalue;
outl(outvalue, (POWERNOW_IOPORT + 0x8));
msrval = POWERNOW_IOPORT + 0x0;
- wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
+ wrmsrq(MSR_K6_EPMR, msrval); /* disable it again */
write_cr0(cr0);
local_irq_enable();
diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c
index 2b791f1ec51b..fe1f499b4fc0 100644
--- a/drivers/cpufreq/powernow-k8.c
+++ b/drivers/cpufreq/powernow-k8.c
@@ -87,10 +87,10 @@ static u32 convert_fid_to_vco_fid(u32 fid)
*/
static int pending_bit_stuck(void)
{
- u32 lo, hi __always_unused;
+ u64 msr;
- rdmsr(MSR_FIDVID_STATUS, lo, hi);
- return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0;
+ rdmsrq(MSR_FIDVID_STATUS, msr);
+ return msr & MSR_S_LO_CHANGE_PENDING ? 1 : 0;
}
/*
@@ -99,7 +99,7 @@ static int pending_bit_stuck(void)
*/
static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
{
- u32 lo, hi;
+ struct msr msr;
u32 i = 0;
do {
@@ -107,11 +107,11 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
pr_debug("detected change pending stuck\n");
return 1;
}
- rdmsr(MSR_FIDVID_STATUS, lo, hi);
- } while (lo & MSR_S_LO_CHANGE_PENDING);
+ rdmsrq(MSR_FIDVID_STATUS, msr.q);
+ } while (msr.l & MSR_S_LO_CHANGE_PENDING);
- data->currvid = hi & MSR_S_HI_CURRENT_VID;
- data->currfid = lo & MSR_S_LO_CURRENT_FID;
+ data->currvid = msr.h & MSR_S_HI_CURRENT_VID;
+ data->currfid = msr.l & MSR_S_LO_CURRENT_FID;
return 0;
}
@@ -131,22 +131,22 @@ static void count_off_vst(struct powernow_k8_data *data)
/* need to init the control msr to a safe value (for each cpu) */
static void fidvid_msr_init(void)
{
- u32 lo, hi;
+ struct msr msr;
u8 fid, vid;
- rdmsr(MSR_FIDVID_STATUS, lo, hi);
- vid = hi & MSR_S_HI_CURRENT_VID;
- fid = lo & MSR_S_LO_CURRENT_FID;
- lo = fid | (vid << MSR_C_LO_VID_SHIFT);
- hi = MSR_C_HI_STP_GNT_BENIGN;
- pr_debug("cpu%d, init lo 0x%x, hi 0x%x\n", smp_processor_id(), lo, hi);
- wrmsr(MSR_FIDVID_CTL, lo, hi);
+ rdmsrq(MSR_FIDVID_STATUS, msr.q);
+ vid = msr.h & MSR_S_HI_CURRENT_VID;
+ fid = msr.l & MSR_S_LO_CURRENT_FID;
+ msr.l = fid | (vid << MSR_C_LO_VID_SHIFT);
+ msr.h = MSR_C_HI_STP_GNT_BENIGN;
+ pr_debug("cpu%d, init lo 0x%x, hi 0x%x\n", smp_processor_id(), msr.l, msr.h);
+ wrmsrq(MSR_FIDVID_CTL, msr.q);
}
/* write the new fid value along with the other control fields to the msr */
static int write_new_fid(struct powernow_k8_data *data, u32 fid)
{
- u32 lo;
+ struct msr msr;
u32 savevid = data->currvid;
u32 i = 0;
@@ -155,15 +155,15 @@ static int write_new_fid(struct powernow_k8_data *data, u32 fid)
return 1;
}
- lo = fid;
- lo |= (data->currvid << MSR_C_LO_VID_SHIFT);
- lo |= MSR_C_LO_INIT_FID_VID;
+ msr.l = fid;
+ msr.l |= (data->currvid << MSR_C_LO_VID_SHIFT);
+ msr.l |= MSR_C_LO_INIT_FID_VID;
+ msr.h = data->plllock * PLL_LOCK_CONVERSION;
- pr_debug("writing fid 0x%x, lo 0x%x, hi 0x%x\n",
- fid, lo, data->plllock * PLL_LOCK_CONVERSION);
+ pr_debug("writing fid 0x%x, lo 0x%x, hi 0x%x\n", fid, msr.l, msr.h);
do {
- wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION);
+ wrmsrq(MSR_FIDVID_CTL, msr.q);
if (i++ > 100) {
pr_err("Hardware error - pending bit very stuck - no further pstate changes possible\n");
return 1;
@@ -190,7 +190,7 @@ static int write_new_fid(struct powernow_k8_data *data, u32 fid)
/* Write a new vid to the hardware */
static int write_new_vid(struct powernow_k8_data *data, u32 vid)
{
- u32 lo;
+ struct msr msr;
u32 savefid = data->currfid;
int i = 0;
@@ -199,15 +199,15 @@ static int write_new_vid(struct powernow_k8_data *data, u32 vid)
return 1;
}
- lo = data->currfid;
- lo |= (vid << MSR_C_LO_VID_SHIFT);
- lo |= MSR_C_LO_INIT_FID_VID;
+ msr.l = data->currfid;
+ msr.l |= (vid << MSR_C_LO_VID_SHIFT);
+ msr.l |= MSR_C_LO_INIT_FID_VID;
+ msr.h = STOP_GRANT_5NS;
- pr_debug("writing vid 0x%x, lo 0x%x, hi 0x%x\n",
- vid, lo, STOP_GRANT_5NS);
+ pr_debug("writing vid 0x%x, lo 0x%x, hi 0x%x\n", vid, msr.l, msr.h);
do {
- wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS);
+ wrmsrq(MSR_FIDVID_CTL, msr.q);
if (i++ > 100) {
pr_err("internal error - pending bit very stuck - no further pstate changes possible\n");
return 1;
@@ -281,9 +281,10 @@ static int transition_fid_vid(struct powernow_k8_data *data,
static int core_voltage_pre_transition(struct powernow_k8_data *data,
u32 reqvid, u32 reqfid)
{
+ struct msr msr;
u32 rvosteps = data->rvo;
u32 savefid = data->currfid;
- u32 maxvid, lo __always_unused, rvomult = 1;
+ u32 maxvid, rvomult = 1;
pr_debug("ph1 (cpu%d): start, currfid 0x%x, currvid 0x%x, reqvid 0x%x, rvo 0x%x\n",
smp_processor_id(),
@@ -292,8 +293,8 @@ static int core_voltage_pre_transition(struct powernow_k8_data *data,
if ((savefid < LO_FID_TABLE_TOP) && (reqfid < LO_FID_TABLE_TOP))
rvomult = 2;
rvosteps *= rvomult;
- rdmsr(MSR_FIDVID_STATUS, lo, maxvid);
- maxvid = 0x1f & (maxvid >> 16);
+ rdmsrq(MSR_FIDVID_STATUS, msr.q);
+ maxvid = 0x1f & (msr.h >> 16);
pr_debug("ph1 maxvid=0x%x\n", maxvid);
if (reqvid < maxvid) /* lower numbers are higher voltages */
reqvid = maxvid;
diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
index 9237ed8f2b1f..de50fb367c6b 100644
--- a/drivers/cpufreq/speedstep-centrino.c
+++ b/drivers/cpufreq/speedstep-centrino.c
@@ -345,7 +345,7 @@ static unsigned int get_cur_freq(unsigned int cpu)
static int centrino_cpu_init(struct cpufreq_policy *policy)
{
struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
- unsigned l, h;
+ u64 q;
int i;
/* Only Intel makes Enhanced Speedstep-capable CPUs */
@@ -378,16 +378,16 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
/* Check to see if Enhanced SpeedStep is enabled, and try to
enable it if not. */
- rdmsr(MSR_IA32_MISC_ENABLE, l, h);
+ rdmsrq(MSR_IA32_MISC_ENABLE, q);
- if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
- l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
- pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
- wrmsr(MSR_IA32_MISC_ENABLE, l, h);
+ if (!(q & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
+ q |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
+ pr_debug("trying to enable Enhanced SpeedStep (%x)\n", (u32)q);
+ wrmsrq(MSR_IA32_MISC_ENABLE, q);
/* check to see if it stuck */
- rdmsr(MSR_IA32_MISC_ENABLE, l, h);
- if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
+ rdmsrq(MSR_IA32_MISC_ENABLE, q);
+ if (!(q & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
pr_info("couldn't enable Enhanced SpeedStep\n");
return -ENODEV;
}
diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
index 973716c1c29c..2afc3f177a29 100644
--- a/drivers/cpufreq/speedstep-lib.c
+++ b/drivers/cpufreq/speedstep-lib.c
@@ -69,13 +69,14 @@ static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
{ 0, 0xff}
};
+ struct msr msr;
u32 msr_lo, msr_tmp;
int i = 0, j = 0;
/* read MSR 0x2a - we only need the low 32 bits */
- rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
- pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
- msr_tmp = msr_lo;
+ rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h);
+ msr_tmp = msr_lo = msr.l;
/* decode the FSB */
msr_tmp &= 0x00c0000;
@@ -108,19 +109,20 @@ static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
static unsigned int pentiumM_get_frequency(void)
{
- u32 msr_lo, msr_tmp;
+ struct msr msr;
+ u32 msr_tmp;
- rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
- pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
+ rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h);
/* see table B-2 of 24547212.pdf */
- if (msr_lo & 0x00040000) {
+ if (msr.l & 0x00040000) {
printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
- msr_lo, msr_tmp);
+ msr.l, msr.h);
return 0;
}
- msr_tmp = (msr_lo >> 22) & 0x1f;
+ msr_tmp = (msr.l >> 22) & 0x1f;
pr_debug("bits 22-26 are 0x%x, speed is %u\n",
msr_tmp, (msr_tmp * 100 * 1000));
@@ -129,13 +131,14 @@ static unsigned int pentiumM_get_frequency(void)
static unsigned int pentium_core_get_frequency(void)
{
+ struct msr msr;
u32 fsb = 0;
- u32 msr_lo, msr_tmp;
+ u32 msr_tmp;
int ret;
- rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
+ rdmsrq(MSR_FSB_FREQ, msr.q);
/* see table B-2 of 25366920.pdf */
- switch (msr_lo & 0x07) {
+ switch (msr.l & 0x07) {
case 5:
fsb = 100000;
break;
@@ -158,11 +161,11 @@ static unsigned int pentium_core_get_frequency(void)
pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
}
- rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
+ rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
- msr_lo, msr_tmp);
+ msr.l, msr.h);
- msr_tmp = (msr_lo >> 22) & 0x1f;
+ msr_tmp = (msr.l >> 22) & 0x1f;
pr_debug("bits 22-26 are 0x%x, speed is %u\n",
msr_tmp, (msr_tmp * fsb));
@@ -174,7 +177,8 @@ static unsigned int pentium_core_get_frequency(void)
static unsigned int pentium4_get_frequency(void)
{
struct cpuinfo_x86 *c = &boot_cpu_data;
- u32 msr_lo, msr_hi, mult;
+ struct msr msr;
+ u32 mult;
unsigned int fsb = 0;
unsigned int ret;
u8 fsb_code;
@@ -187,16 +191,16 @@ static unsigned int pentium4_get_frequency(void)
if (c->x86_model < 2)
return cpu_khz;
- rdmsr(0x2c, msr_lo, msr_hi);
+ rdmsrq(0x2c, msr.q);
- pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
+ pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr.l, msr.h);
/* decode the FSB: see IA-32 Intel (C) Architecture Software
* Developer's Manual, Volume 3: System Prgramming Guide,
* revision #12 in Table B-1: MSRs in the Pentium 4 and
* Intel Xeon Processors, on page B-4 and B-5.
*/
- fsb_code = (msr_lo >> 16) & 0x7;
+ fsb_code = (msr.l >> 16) & 0x7;
switch (fsb_code) {
case 0:
fsb = 100 * 1000;
@@ -214,7 +218,7 @@ static unsigned int pentium4_get_frequency(void)
"Please send an e-mail to <linux@brodo.de>\n");
/* Multiplier. */
- mult = msr_lo >> 24;
+ mult = msr.l >> 24;
pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
fsb, mult, (fsb * mult));
@@ -255,7 +259,8 @@ EXPORT_SYMBOL_GPL(speedstep_get_frequency);
enum speedstep_processor speedstep_detect_processor(void)
{
struct cpuinfo_x86 *c = &cpu_data(0);
- u32 ebx, msr_lo, msr_hi;
+ struct msr msr;
+ u32 ebx;
pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
@@ -343,11 +348,11 @@ enum speedstep_processor speedstep_detect_processor(void)
/* all mobile PIII Coppermines have FSB 100 MHz
* ==> sort out a few desktop PIIIs. */
- rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
+ rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
- msr_lo, msr_hi);
- msr_lo &= 0x00c0000;
- if (msr_lo != 0x0080000)
+ msr.l, msr.h);
+ msr.l &= 0x00c0000;
+ if (msr.l != 0x0080000)
return 0;
/*
@@ -356,11 +361,11 @@ enum speedstep_processor speedstep_detect_processor(void)
* it has SpeedStep technology if either
* bit 56 or 57 is set
*/
- rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
+ rdmsrq(MSR_IA32_PLATFORM_ID, msr.q);
pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
- msr_lo, msr_hi);
- if ((msr_hi & (1<<18)) &&
- (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
+ msr.l, msr.h);
+ if ((msr.h & (1<<18)) &&
+ (relaxed_check ? 1 : (msr.h & (3<<24)))) {
if (c->x86_stepping == 0x01) {
pr_debug("early PIII version\n");
return SPEEDSTEP_CPU_PIII_C_EARLY;
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 16/32] cpufreq: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 16/32] cpufreq: Stop using 32-bit MSR interfaces Juergen Gross
@ 2026-06-29 14:55 ` Zhongqiu Han
2026-06-30 6:38 ` Juergen Gross
0 siblings, 1 reply; 80+ messages in thread
From: Zhongqiu Han @ 2026-06-29 14:55 UTC (permalink / raw)
To: Juergen Gross, linux-kernel, linux-pm
Cc: Rafael J. Wysocki, Viresh Kumar, zhongqiu.han
On 6/29/2026 2:05 PM, Juergen Gross wrote:
> The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
> removed. Use the related 64-bit variants instead.
Hello Juergen,
>
> Signed-off-by: Juergen Gross <jgross@suse.com>
> ---
> drivers/cpufreq/acpi-cpufreq.c | 22 ++++----
> drivers/cpufreq/e_powersaver.c | 48 ++++++++---------
> drivers/cpufreq/longhaul.c | 15 +++---
> drivers/cpufreq/longrun.c | 78 +++++++++++++++-------------
> drivers/cpufreq/powernow-k6.c | 12 ++---
> drivers/cpufreq/powernow-k8.c | 67 ++++++++++++------------
> drivers/cpufreq/speedstep-centrino.c | 16 +++---
> drivers/cpufreq/speedstep-lib.c | 63 +++++++++++-----------
> 8 files changed, 166 insertions(+), 155 deletions(-)
>
> diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
> index 21639d9ac753..b40fa99b5ab2 100644
> --- a/drivers/cpufreq/acpi-cpufreq.c
> +++ b/drivers/cpufreq/acpi-cpufreq.c
> @@ -246,32 +246,32 @@ static unsigned extract_freq(struct cpufreq_policy *policy, u32 val)
>
> static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used)
> {
> - u32 val, dummy __always_unused;
> + u64 val;
>
> - rdmsr(MSR_IA32_PERF_CTL, val, dummy);
> - return val;
> + rdmsrq(MSR_IA32_PERF_CTL, val);
> + return (u32)val;
> }
>
> static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val)
> {
> - u32 lo, hi;
> + struct msr msrval;
>
> - rdmsr(MSR_IA32_PERF_CTL, lo, hi);
> - lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
> - wrmsr(MSR_IA32_PERF_CTL, lo, hi);
> + rdmsrq(MSR_IA32_PERF_CTL, msrval.q);
> + msrval.h = (msrval.h & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
msrval.l？
please feel free to correct me if there is any misunderstanding.
how about using u64 directly?
u64 msrval;
rdmsrq(MSR_IA32_PERF_CTL, msrval);
msrval = (msrval & ~(u64)INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
wrmsrq(MSR_IA32_PERF_CTL, msrval);
As per my understanding, we can use u64 instead of struct msr in many
other places in this patch as well.
> + wrmsrq(MSR_IA32_PERF_CTL, msrval.q);
> }
>
> static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used)
> {
> - u32 val, dummy __always_unused;
> + u64 val;
>
> - rdmsr(MSR_AMD_PERF_CTL, val, dummy);
> - return val;
> + rdmsrq(MSR_AMD_PERF_CTL, val);
> + return (u32)val;
> }
>
> static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val)
> {
> - wrmsr(MSR_AMD_PERF_CTL, val, 0);
> + wrmsrq(MSR_AMD_PERF_CTL, val);
> }
>
> static u32 cpu_freq_read_io(struct acpi_pct_register *reg)
> diff --git a/drivers/cpufreq/e_powersaver.c b/drivers/cpufreq/e_powersaver.c
> index eb5a9209d828..13709f9667ea 100644
> --- a/drivers/cpufreq/e_powersaver.c
> +++ b/drivers/cpufreq/e_powersaver.c
> @@ -90,7 +90,7 @@ static int eps_acpi_exit(struct cpufreq_policy *policy)
> static unsigned int eps_get(unsigned int cpu)
> {
> struct eps_cpu_data *centaur;
> - u32 lo, hi;
> + u64 val;
>
> if (cpu)
> return 0;
> @@ -99,35 +99,35 @@ static unsigned int eps_get(unsigned int cpu)
> return 0;
>
> /* Return current frequency */
> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
> - return centaur->fsb * ((lo >> 8) & 0xff);
> + rdmsrq(MSR_IA32_PERF_STATUS, val);
> + return centaur->fsb * ((val >> 8) & 0xff);
> }
>
> static int eps_set_state(struct eps_cpu_data *centaur,
> struct cpufreq_policy *policy,
> u32 dest_state)
> {
> - u32 lo, hi;
> + u64 val;
> int i;
>
> /* Wait while CPU is busy */
> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
> + rdmsrq(MSR_IA32_PERF_STATUS, val);
> i = 0;
> - while (lo & ((1 << 16) | (1 << 17))) {
> + while (val & ((1 << 16) | (1 << 17))) {
> udelay(16);
> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
> + rdmsrq(MSR_IA32_PERF_STATUS, val);
> i++;
> if (unlikely(i > 64)) {
> return -ENODEV;
> }
> }
> /* Set new multiplier and voltage */
> - wrmsr(MSR_IA32_PERF_CTL, dest_state & 0xffff, 0);
> + wrmsrq(MSR_IA32_PERF_CTL, dest_state & 0xffff);
> /* Wait until transition end */
> i = 0;
> do {
> udelay(16);
> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
> + rdmsrq(MSR_IA32_PERF_STATUS, val);
> i++;
> if (unlikely(i > 64)) {
> return -ENODEV;
do {
udelay(16);
rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
i++;
if (unlikely(i > 64)) {
return -ENODEV;
}
} while (lo & ((1 << 16) | (1 << 17)));-->lo has been deleted?
> @@ -139,10 +139,10 @@ static int eps_set_state(struct eps_cpu_data *centaur,
> u8 current_multiplier, current_voltage;
>
> /* Print voltage and multiplier */
> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
> - current_voltage = lo & 0xff;
> + rdmsrq(MSR_IA32_PERF_STATUS, val);
> + current_voltage = val & 0xff;
> pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
> - current_multiplier = (lo >> 8) & 0xff;
> + current_multiplier = (val >> 8) & 0xff;
> pr_info("Current multiplier = %d\n", current_multiplier);
> }
> #endif
> @@ -171,8 +171,8 @@ static int eps_target(struct cpufreq_policy *policy, unsigned int index)
> static int eps_cpu_init(struct cpufreq_policy *policy)
> {
> unsigned int i;
> - u32 lo, hi;
> u64 val;
> + struct msr status;
> u8 current_multiplier, current_voltage;
> u8 max_multiplier, max_voltage;
> u8 min_multiplier, min_voltage;
> @@ -195,13 +195,13 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
>
> switch (c->x86_model) {
> case 10:
> - rdmsr(0x1153, lo, hi);
> - brand = (((lo >> 2) ^ lo) >> 18) & 3;
> + rdmsrq(0x1153, val);
> + brand = (((val >> 2) ^ val) >> 18) & 3;
> pr_cont("Model A ");
> break;
> case 13:
> - rdmsr(0x1154, lo, hi);
> - brand = (((lo >> 4) ^ (lo >> 2))) & 0x000000ff;
> + rdmsrq(0x1154, val);
> + brand = (((val >> 4) ^ (val >> 2))) & 0x000000ff;
> pr_cont("Model D ");
> break;
> }
> @@ -237,20 +237,20 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
> }
>
> /* Print voltage and multiplier */
> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
> - current_voltage = lo & 0xff;
> + rdmsrq(MSR_IA32_PERF_STATUS, status.q);
> + current_voltage = status.l & 0xff;
> pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
> - current_multiplier = (lo >> 8) & 0xff;
> + current_multiplier = (status.l >> 8) & 0xff;
> pr_info("Current multiplier = %d\n", current_multiplier);
>
> /* Print limits */
> - max_voltage = hi & 0xff;
> + max_voltage = status.h & 0xff;
> pr_info("Highest voltage = %dmV\n", max_voltage * 16 + 700);
> - max_multiplier = (hi >> 8) & 0xff;
> + max_multiplier = (status.h >> 8) & 0xff;
> pr_info("Highest multiplier = %d\n", max_multiplier);
> - min_voltage = (hi >> 16) & 0xff;
> + min_voltage = (status.h >> 16) & 0xff;
> pr_info("Lowest voltage = %dmV\n", min_voltage * 16 + 700);
> - min_multiplier = (hi >> 24) & 0xff;
> + min_multiplier = (status.h >> 24) & 0xff;
> pr_info("Lowest multiplier = %d\n", min_multiplier);
>
> /* Sanity checks */
> diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
> index a18d1d11725f..4c2599264333 100644
> --- a/drivers/cpufreq/longhaul.c
> +++ b/drivers/cpufreq/longhaul.c
> @@ -118,13 +118,14 @@ static unsigned int calc_speed(int mult)
>
> static int longhaul_get_cpu_mult(void)
> {
> - unsigned long invalue = 0, lo, hi;
> + unsigned long invalue = 0;
> + u64 val;
>
> - rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
> - invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22;
> + rdmsrq(MSR_IA32_EBL_CR_POWERON, val);
> + invalue = (val & (1<<22|1<<23|1<<24|1<<25))>>22;
> if (longhaul_version == TYPE_LONGHAUL_V2 ||
> longhaul_version == TYPE_POWERSAVER) {
> - if (lo & (1<<27))
> + if (val & (1<<27))
> invalue += 16;
> }
> return eblcr[invalue];
> @@ -761,7 +762,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
> struct cpuinfo_x86 *c = &cpu_data(0);
> char *cpuname = NULL;
> int ret;
> - u32 lo, hi;
> + u64 val;
>
> /* Check what we have on this motherboard */
> switch (c->x86_model) {
> @@ -835,8 +836,8 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
> }
> /* Check Longhaul ver. 2 */
> if (longhaul_version == TYPE_LONGHAUL_V2) {
> - rdmsr(MSR_VIA_LONGHAUL, lo, hi);
> - if (lo == 0 && hi == 0)
> + rdmsrq(MSR_VIA_LONGHAUL, val);
> + if (val == 0)
> /* Looks like MSR isn't present */
> longhaul_version = TYPE_LONGHAUL_V1;
> }
> diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c
> index f3aaca0496a4..99abef32e7e5 100644
> --- a/drivers/cpufreq/longrun.c
> +++ b/drivers/cpufreq/longrun.c
> @@ -35,27 +35,27 @@ static unsigned int longrun_low_freq, longrun_high_freq;
> */
> static void longrun_get_policy(struct cpufreq_policy *policy)
> {
> - u32 msr_lo, msr_hi;
> + struct msr msr;
>
> - rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
> - pr_debug("longrun flags are %x - %x\n", msr_lo, msr_hi);
> - if (msr_lo & 0x01)
> + rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
> + pr_debug("longrun flags are %x - %x\n", msr.l, msr.h);
> + if (msr.l & 0x01)
> policy->policy = CPUFREQ_POLICY_PERFORMANCE;
> else
> policy->policy = CPUFREQ_POLICY_POWERSAVE;
>
> - rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
> - pr_debug("longrun ctrl is %x - %x\n", msr_lo, msr_hi);
> - msr_lo &= 0x0000007F;
> - msr_hi &= 0x0000007F;
> + rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
> + pr_debug("longrun ctrl is %x - %x\n", msr.l, msr.h);
> + msr.l &= 0x0000007F;
> + msr.h &= 0x0000007F;
>
> if (longrun_high_freq <= longrun_low_freq) {
> /* Assume degenerate Longrun table */
> policy->min = policy->max = longrun_high_freq;
> } else {
> - policy->min = longrun_low_freq + msr_lo *
> + policy->min = longrun_low_freq + msr.l *
> ((longrun_high_freq - longrun_low_freq) / 100);
> - policy->max = longrun_low_freq + msr_hi *
> + policy->max = longrun_low_freq + msr.h *
> ((longrun_high_freq - longrun_low_freq) / 100);
> }
> policy->cpu = 0;
> @@ -71,7 +71,7 @@ static void longrun_get_policy(struct cpufreq_policy *policy)
> */
> static int longrun_set_policy(struct cpufreq_policy *policy)
> {
> - u32 msr_lo, msr_hi;
> + struct msr msr;
> u32 pctg_lo, pctg_hi;
>
> if (!policy)
> @@ -93,24 +93,24 @@ static int longrun_set_policy(struct cpufreq_policy *policy)
> pctg_lo = pctg_hi;
>
> /* performance or economy mode */
> - rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
> - msr_lo &= 0xFFFFFFFE;
> + rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
> + msr.l &= 0xFFFFFFFE;
> switch (policy->policy) {
> case CPUFREQ_POLICY_PERFORMANCE:
> - msr_lo |= 0x00000001;
> + msr.l |= 0x00000001;
> break;
> case CPUFREQ_POLICY_POWERSAVE:
> break;
> }
> - wrmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
> + wrmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
>
> /* lower and upper boundary */
> - rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
> - msr_lo &= 0xFFFFFF80;
> - msr_hi &= 0xFFFFFF80;
> - msr_lo |= pctg_lo;
> - msr_hi |= pctg_hi;
> - wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
> + rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
> + msr.l &= 0xFFFFFF80;
> + msr.h &= 0xFFFFFF80;
> + msr.l |= pctg_lo;
> + msr.h |= pctg_hi;
> + wrmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
>
> return 0;
> }
> @@ -160,7 +160,7 @@ static unsigned int longrun_get(unsigned int cpu)
> static int longrun_determine_freqs(unsigned int *low_freq,
> unsigned int *high_freq)
> {
> - u32 msr_lo, msr_hi;
> + struct msr msr;
> u32 save_lo, save_hi;
> u32 eax, ebx, ecx, edx;
> u32 try_hi;
> @@ -178,15 +178,17 @@ static int longrun_determine_freqs(unsigned int *low_freq,
> * For maximum frequency, read out level zero.
> */
> /* minimum */
> - rdmsr(MSR_TMTA_LRTI_READOUT, msr_lo, msr_hi);
> - wrmsr(MSR_TMTA_LRTI_READOUT, msr_hi, msr_hi);
> - rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
> - *low_freq = msr_lo * 1000; /* to kHz */
> + rdmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
> + msr.l = msr.h;
> + wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
> + rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
> + *low_freq = msr.l * 1000; /* to kHz */
>
> /* maximum */
> - wrmsr(MSR_TMTA_LRTI_READOUT, 0, msr_hi);
> - rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
> - *high_freq = msr_lo * 1000; /* to kHz */
> + msr.l = 0;
> + wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
> + rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
> + *high_freq = msr.l * 1000; /* to kHz */
>
> pr_debug("longrun table interface told %u - %u kHz\n",
> *low_freq, *high_freq);
> @@ -202,9 +204,9 @@ static int longrun_determine_freqs(unsigned int *low_freq,
> pr_debug("high frequency is %u kHz\n", *high_freq);
>
> /* get current borders */
> - rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
> - save_lo = msr_lo & 0x0000007F;
> - save_hi = msr_hi & 0x0000007F;
> + rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
> + save_lo = msr.l & 0x0000007F;
> + save_hi = msr.h & 0x0000007F;
>
> /* if current perf_pctg is larger than 90%, we need to decrease the
> * upper limit to make the calculation more accurate.
> @@ -214,16 +216,18 @@ static int longrun_determine_freqs(unsigned int *low_freq,
> * on some barrier values */
> for (try_hi = 80; try_hi > 0 && ecx > 90; try_hi -= 10) {
> /* set to 0 to try_hi perf_pctg */
> - msr_lo &= 0xFFFFFF80;
> - msr_hi &= 0xFFFFFF80;
> - msr_hi |= try_hi;
> - wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
> + msr.l &= 0xFFFFFF80;
> + msr.h &= 0xFFFFFF80;
> + msr.h |= try_hi;
> + wrmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
>
> /* read out current core MHz and current perf_pctg */
> cpuid(0x80860007, &eax, &ebx, &ecx, &edx);
>
> /* restore values */
> - wrmsr(MSR_TMTA_LONGRUN_CTRL, save_lo, save_hi);
> + msr.l = save_lo;
> + msr.h = save_hi;
> + wrmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
> }
As sashiko.dev pointed, from the second iter, this patch code
will clear upper 25 bits to zero.
https://sashiko.dev/#/patchset/20260629060526.3638272-1-jgross%40suse.com
for (try_hi = 80; ...; ...) {
- msr_lo &= 0xFFFFFF80; /* iter 1: X.lo[31:7]; iter 2+: same */
- msr_hi &= 0xFFFFFF80;
- msr_hi |= try_hi;
- wrmsr(reg, msr_lo, msr_hi);/* writes X.hi[31:7] | try_hi */
+ msr.l &= 0xFFFFFF80; /* iter 2+: locals=0 -> mask = 0 */
+ msr.h &= 0xFFFFFF80;
+ msr.h |= try_hi;
+ wrmsrq(reg, msr.q); /* <-- iter 2+ writes 0 (vs X.hi[31:7])*/
cpuid(...);
/* restore */
- wrmsr(reg, save_lo, save_hi); /* locals untouched */
+ msr.l = save_lo; /* poisons locals ->next iter bug */
+ msr.h = save_hi;
+ wrmsrq(reg, msr.q);
}
I'm not sure whether the upper 25 bits are reserved, but the original
code preserved them across iterations. It might be safer to keep that
behavior unchanged.
> pr_debug("percentage is %u %%, freq is %u MHz\n", ecx, eax);
>
> diff --git a/drivers/cpufreq/powernow-k6.c b/drivers/cpufreq/powernow-k6.c
> index 99d2244e03b0..2044e8a336ec 100644
> --- a/drivers/cpufreq/powernow-k6.c
> +++ b/drivers/cpufreq/powernow-k6.c
> @@ -83,15 +83,15 @@ static const struct {
> static int powernow_k6_get_cpu_multiplier(void)
> {
> unsigned long invalue = 0;
> - u32 msrval;
> + u64 msrval;
>
> local_irq_disable();
>
> msrval = POWERNOW_IOPORT + 0x1;
> - wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
> + wrmsrq(MSR_K6_EPMR, msrval); /* enable the PowerNow port */
> invalue = inl(POWERNOW_IOPORT + 0x8);
> msrval = POWERNOW_IOPORT + 0x0;
> - wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
> + wrmsrq(MSR_K6_EPMR, msrval); /* disable it again */
>
> local_irq_enable();
>
> @@ -101,8 +101,8 @@ static int powernow_k6_get_cpu_multiplier(void)
> static void powernow_k6_set_cpu_multiplier(unsigned int best_i)
> {
> unsigned long outvalue, invalue;
> - unsigned long msrval;
> unsigned long cr0;
> + u64 msrval;
>
> /* we now need to transform best_i to the BVC format, see AMD#23446 */
>
> @@ -118,13 +118,13 @@ static void powernow_k6_set_cpu_multiplier(unsigned int best_i)
> outvalue = (1<<12) | (1<<10) | (1<<9) | (index_to_register[best_i]<<5);
>
> msrval = POWERNOW_IOPORT + 0x1;
> - wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
> + wrmsrq(MSR_K6_EPMR, msrval); /* enable the PowerNow port */
> invalue = inl(POWERNOW_IOPORT + 0x8);
> invalue = invalue & 0x1f;
> outvalue = outvalue | invalue;
> outl(outvalue, (POWERNOW_IOPORT + 0x8));
> msrval = POWERNOW_IOPORT + 0x0;
> - wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
> + wrmsrq(MSR_K6_EPMR, msrval); /* disable it again */
>
> write_cr0(cr0);
> local_irq_enable();
> diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c
> index 2b791f1ec51b..fe1f499b4fc0 100644
> --- a/drivers/cpufreq/powernow-k8.c
> +++ b/drivers/cpufreq/powernow-k8.c
> @@ -87,10 +87,10 @@ static u32 convert_fid_to_vco_fid(u32 fid)
> */
> static int pending_bit_stuck(void)
> {
> - u32 lo, hi __always_unused;
> + u64 msr;
>
> - rdmsr(MSR_FIDVID_STATUS, lo, hi);
> - return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0;
> + rdmsrq(MSR_FIDVID_STATUS, msr);
> + return msr & MSR_S_LO_CHANGE_PENDING ? 1 : 0;
> }
>
> /*
> @@ -99,7 +99,7 @@ static int pending_bit_stuck(void)
> */
> static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
> {
> - u32 lo, hi;
> + struct msr msr;
msrval?
> u32 i = 0;
>
> do {
> @@ -107,11 +107,11 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
> pr_debug("detected change pending stuck\n");
> return 1;
> }
> - rdmsr(MSR_FIDVID_STATUS, lo, hi);
> - } while (lo & MSR_S_LO_CHANGE_PENDING);
> + rdmsrq(MSR_FIDVID_STATUS, msr.q);
> + } while (msr.l & MSR_S_LO_CHANGE_PENDING);
>
> - data->currvid = hi & MSR_S_HI_CURRENT_VID;
> - data->currfid = lo & MSR_S_LO_CURRENT_FID;
> + data->currvid = msr.h & MSR_S_HI_CURRENT_VID;
> + data->currfid = msr.l & MSR_S_LO_CURRENT_FID;
>
> return 0;
> }
> @@ -131,22 +131,22 @@ static void count_off_vst(struct powernow_k8_data *data)
> /* need to init the control msr to a safe value (for each cpu) */
> static void fidvid_msr_init(void)
> {
> - u32 lo, hi;
> + struct msr msr;
> u8 fid, vid;
>
> - rdmsr(MSR_FIDVID_STATUS, lo, hi);
> - vid = hi & MSR_S_HI_CURRENT_VID;
> - fid = lo & MSR_S_LO_CURRENT_FID;
> - lo = fid | (vid << MSR_C_LO_VID_SHIFT);
> - hi = MSR_C_HI_STP_GNT_BENIGN;
> - pr_debug("cpu%d, init lo 0x%x, hi 0x%x\n", smp_processor_id(), lo, hi);
> - wrmsr(MSR_FIDVID_CTL, lo, hi);
> + rdmsrq(MSR_FIDVID_STATUS, msr.q);
> + vid = msr.h & MSR_S_HI_CURRENT_VID;
> + fid = msr.l & MSR_S_LO_CURRENT_FID;
> + msr.l = fid | (vid << MSR_C_LO_VID_SHIFT);
> + msr.h = MSR_C_HI_STP_GNT_BENIGN;
> + pr_debug("cpu%d, init lo 0x%x, hi 0x%x\n", smp_processor_id(), msr.l, msr.h);
> + wrmsrq(MSR_FIDVID_CTL, msr.q);
> }
>
> /* write the new fid value along with the other control fields to the msr */
> static int write_new_fid(struct powernow_k8_data *data, u32 fid)
> {
> - u32 lo;
> + struct msr msr;
> u32 savevid = data->currvid;
> u32 i = 0;
>
> @@ -155,15 +155,15 @@ static int write_new_fid(struct powernow_k8_data *data, u32 fid)
> return 1;
> }
>
> - lo = fid;
> - lo |= (data->currvid << MSR_C_LO_VID_SHIFT);
> - lo |= MSR_C_LO_INIT_FID_VID;
> + msr.l = fid;
> + msr.l |= (data->currvid << MSR_C_LO_VID_SHIFT);
> + msr.l |= MSR_C_LO_INIT_FID_VID;
> + msr.h = data->plllock * PLL_LOCK_CONVERSION;
>
> - pr_debug("writing fid 0x%x, lo 0x%x, hi 0x%x\n",
> - fid, lo, data->plllock * PLL_LOCK_CONVERSION);
> + pr_debug("writing fid 0x%x, lo 0x%x, hi 0x%x\n", fid, msr.l, msr.h);
>
> do {
> - wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION);
> + wrmsrq(MSR_FIDVID_CTL, msr.q);
> if (i++ > 100) {
> pr_err("Hardware error - pending bit very stuck - no further pstate changes possible\n");
> return 1;
> @@ -190,7 +190,7 @@ static int write_new_fid(struct powernow_k8_data *data, u32 fid)
> /* Write a new vid to the hardware */
> static int write_new_vid(struct powernow_k8_data *data, u32 vid)
> {
> - u32 lo;
> + struct msr msr;
> u32 savefid = data->currfid;
> int i = 0;
>
> @@ -199,15 +199,15 @@ static int write_new_vid(struct powernow_k8_data *data, u32 vid)
> return 1;
> }
>
> - lo = data->currfid;
> - lo |= (vid << MSR_C_LO_VID_SHIFT);
> - lo |= MSR_C_LO_INIT_FID_VID;
> + msr.l = data->currfid;
> + msr.l |= (vid << MSR_C_LO_VID_SHIFT);
> + msr.l |= MSR_C_LO_INIT_FID_VID;
> + msr.h = STOP_GRANT_5NS;
>
> - pr_debug("writing vid 0x%x, lo 0x%x, hi 0x%x\n",
> - vid, lo, STOP_GRANT_5NS);
> + pr_debug("writing vid 0x%x, lo 0x%x, hi 0x%x\n", vid, msr.l, msr.h);
>
> do {
> - wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS);
> + wrmsrq(MSR_FIDVID_CTL, msr.q);
> if (i++ > 100) {
> pr_err("internal error - pending bit very stuck - no further pstate changes possible\n");
> return 1;
> @@ -281,9 +281,10 @@ static int transition_fid_vid(struct powernow_k8_data *data,
> static int core_voltage_pre_transition(struct powernow_k8_data *data,
> u32 reqvid, u32 reqfid)
> {
> + struct msr msr;
> u32 rvosteps = data->rvo;
> u32 savefid = data->currfid;
> - u32 maxvid, lo __always_unused, rvomult = 1;
> + u32 maxvid, rvomult = 1;
>
> pr_debug("ph1 (cpu%d): start, currfid 0x%x, currvid 0x%x, reqvid 0x%x, rvo 0x%x\n",
> smp_processor_id(),
> @@ -292,8 +293,8 @@ static int core_voltage_pre_transition(struct powernow_k8_data *data,
> if ((savefid < LO_FID_TABLE_TOP) && (reqfid < LO_FID_TABLE_TOP))
> rvomult = 2;
> rvosteps *= rvomult;
> - rdmsr(MSR_FIDVID_STATUS, lo, maxvid);
> - maxvid = 0x1f & (maxvid >> 16);
> + rdmsrq(MSR_FIDVID_STATUS, msr.q);
> + maxvid = 0x1f & (msr.h >> 16);
> pr_debug("ph1 maxvid=0x%x\n", maxvid);
> if (reqvid < maxvid) /* lower numbers are higher voltages */
> reqvid = maxvid;
> diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
> index 9237ed8f2b1f..de50fb367c6b 100644
> --- a/drivers/cpufreq/speedstep-centrino.c
> +++ b/drivers/cpufreq/speedstep-centrino.c
> @@ -345,7 +345,7 @@ static unsigned int get_cur_freq(unsigned int cpu)
> static int centrino_cpu_init(struct cpufreq_policy *policy)
> {
> struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
> - unsigned l, h;
> + u64 q;
> int i;
>
> /* Only Intel makes Enhanced Speedstep-capable CPUs */
> @@ -378,16 +378,16 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
>
> /* Check to see if Enhanced SpeedStep is enabled, and try to
> enable it if not. */
> - rdmsr(MSR_IA32_MISC_ENABLE, l, h);
> + rdmsrq(MSR_IA32_MISC_ENABLE, q);
>
> - if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
> - l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
> - pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
> - wrmsr(MSR_IA32_MISC_ENABLE, l, h);
> + if (!(q & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
> + q |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
> + pr_debug("trying to enable Enhanced SpeedStep (%x)\n", (u32)q);
> + wrmsrq(MSR_IA32_MISC_ENABLE, q);
>
> /* check to see if it stuck */
> - rdmsr(MSR_IA32_MISC_ENABLE, l, h);
> - if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
> + rdmsrq(MSR_IA32_MISC_ENABLE, q);
> + if (!(q & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
> pr_info("couldn't enable Enhanced SpeedStep\n");
> return -ENODEV;
> }
> diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
> index 973716c1c29c..2afc3f177a29 100644
> --- a/drivers/cpufreq/speedstep-lib.c
> +++ b/drivers/cpufreq/speedstep-lib.c
> @@ -69,13 +69,14 @@ static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
> { 0, 0xff}
> };
>
> + struct msr msr;
> u32 msr_lo, msr_tmp;
> int i = 0, j = 0;
>
> /* read MSR 0x2a - we only need the low 32 bits */
> - rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
> - pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
> - msr_tmp = msr_lo;
> + rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
> + pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h);
> + msr_tmp = msr_lo = msr.l;
>
> /* decode the FSB */
> msr_tmp &= 0x00c0000;
> @@ -108,19 +109,20 @@ static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
>
> static unsigned int pentiumM_get_frequency(void)
> {
> - u32 msr_lo, msr_tmp;
> + struct msr msr;
> + u32 msr_tmp;
>
> - rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
> - pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
> + rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
> + pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h);
>
> /* see table B-2 of 24547212.pdf */
> - if (msr_lo & 0x00040000) {
> + if (msr.l & 0x00040000) {
> printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
> - msr_lo, msr_tmp);
> + msr.l, msr.h);
> return 0;
> }
>
> - msr_tmp = (msr_lo >> 22) & 0x1f;
> + msr_tmp = (msr.l >> 22) & 0x1f;
> pr_debug("bits 22-26 are 0x%x, speed is %u\n",
> msr_tmp, (msr_tmp * 100 * 1000));
>
> @@ -129,13 +131,14 @@ static unsigned int pentiumM_get_frequency(void)
>
> static unsigned int pentium_core_get_frequency(void)
> {
> + struct msr msr;
> u32 fsb = 0;
> - u32 msr_lo, msr_tmp;
> + u32 msr_tmp;
> int ret;
>
> - rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
> + rdmsrq(MSR_FSB_FREQ, msr.q);
> /* see table B-2 of 25366920.pdf */
> - switch (msr_lo & 0x07) {
> + switch (msr.l & 0x07) {
> case 5:
> fsb = 100000;
> break;
> @@ -158,11 +161,11 @@ static unsigned int pentium_core_get_frequency(void)
> pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
> }
>
> - rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
> + rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
> pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
> - msr_lo, msr_tmp);
> + msr.l, msr.h);
>
> - msr_tmp = (msr_lo >> 22) & 0x1f;
> + msr_tmp = (msr.l >> 22) & 0x1f;
> pr_debug("bits 22-26 are 0x%x, speed is %u\n",
> msr_tmp, (msr_tmp * fsb));
>
> @@ -174,7 +177,8 @@ static unsigned int pentium_core_get_frequency(void)
> static unsigned int pentium4_get_frequency(void)
> {
> struct cpuinfo_x86 *c = &boot_cpu_data;
> - u32 msr_lo, msr_hi, mult;
> + struct msr msr;
> + u32 mult;
> unsigned int fsb = 0;
> unsigned int ret;
> u8 fsb_code;
> @@ -187,16 +191,16 @@ static unsigned int pentium4_get_frequency(void)
> if (c->x86_model < 2)
> return cpu_khz;
>
> - rdmsr(0x2c, msr_lo, msr_hi);
> + rdmsrq(0x2c, msr.q);
>
> - pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
> + pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr.l, msr.h);
>
> /* decode the FSB: see IA-32 Intel (C) Architecture Software
> * Developer's Manual, Volume 3: System Prgramming Guide,
> * revision #12 in Table B-1: MSRs in the Pentium 4 and
> * Intel Xeon Processors, on page B-4 and B-5.
> */
> - fsb_code = (msr_lo >> 16) & 0x7;
> + fsb_code = (msr.l >> 16) & 0x7;
> switch (fsb_code) {
> case 0:
> fsb = 100 * 1000;
> @@ -214,7 +218,7 @@ static unsigned int pentium4_get_frequency(void)
> "Please send an e-mail to <linux@brodo.de>\n");
>
> /* Multiplier. */
> - mult = msr_lo >> 24;
> + mult = msr.l >> 24;
>
> pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
> fsb, mult, (fsb * mult));
> @@ -255,7 +259,8 @@ EXPORT_SYMBOL_GPL(speedstep_get_frequency);
> enum speedstep_processor speedstep_detect_processor(void)
> {
> struct cpuinfo_x86 *c = &cpu_data(0);
> - u32 ebx, msr_lo, msr_hi;
> + struct msr msr;
> + u32 ebx;
>
> pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
>
> @@ -343,11 +348,11 @@ enum speedstep_processor speedstep_detect_processor(void)
>
> /* all mobile PIII Coppermines have FSB 100 MHz
> * ==> sort out a few desktop PIIIs. */
> - rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
> + rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
> pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
> - msr_lo, msr_hi);
> - msr_lo &= 0x00c0000;
> - if (msr_lo != 0x0080000)
> + msr.l, msr.h);
> + msr.l &= 0x00c0000;
> + if (msr.l != 0x0080000)
> return 0;
>
> /*
> @@ -356,11 +361,11 @@ enum speedstep_processor speedstep_detect_processor(void)
> * it has SpeedStep technology if either
> * bit 56 or 57 is set
> */
> - rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
> + rdmsrq(MSR_IA32_PLATFORM_ID, msr.q);
> pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
> - msr_lo, msr_hi);
> - if ((msr_hi & (1<<18)) &&
> - (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
> + msr.l, msr.h);
> + if ((msr.h & (1<<18)) &&
> + (relaxed_check ? 1 : (msr.h & (3<<24)))) {
> if (c->x86_stepping == 0x01) {
> pr_debug("early PIII version\n");
> return SPEEDSTEP_CPU_PIII_C_EARLY;
--
Thx and BRs,
Zhongqiu Han
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 16/32] cpufreq: Stop using 32-bit MSR interfaces
2026-06-29 14:55 ` Zhongqiu Han
@ 2026-06-30 6:38 ` Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-30 6:38 UTC (permalink / raw)
To: Zhongqiu Han, linux-kernel, linux-pm; +Cc: Rafael J. Wysocki, Viresh Kumar
[-- Attachment #1.1.1: Type: text/plain, Size: 18896 bytes --]
On 29.06.26 16:55, Zhongqiu Han wrote:
> On 6/29/2026 2:05 PM, Juergen Gross wrote:
>> The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
>> removed. Use the related 64-bit variants instead.
>
> Hello Juergen,
>
>>
>> Signed-off-by: Juergen Gross <jgross@suse.com>
>> ---
>> drivers/cpufreq/acpi-cpufreq.c | 22 ++++----
>> drivers/cpufreq/e_powersaver.c | 48 ++++++++---------
>> drivers/cpufreq/longhaul.c | 15 +++---
>> drivers/cpufreq/longrun.c | 78 +++++++++++++++-------------
>> drivers/cpufreq/powernow-k6.c | 12 ++---
>> drivers/cpufreq/powernow-k8.c | 67 ++++++++++++------------
>> drivers/cpufreq/speedstep-centrino.c | 16 +++---
>> drivers/cpufreq/speedstep-lib.c | 63 +++++++++++-----------
>> 8 files changed, 166 insertions(+), 155 deletions(-)
>>
>> diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
>> index 21639d9ac753..b40fa99b5ab2 100644
>> --- a/drivers/cpufreq/acpi-cpufreq.c
>> +++ b/drivers/cpufreq/acpi-cpufreq.c
>> @@ -246,32 +246,32 @@ static unsigned extract_freq(struct cpufreq_policy
>> *policy, u32 val)
>> static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used)
>> {
>> - u32 val, dummy __always_unused;
>> + u64 val;
>> - rdmsr(MSR_IA32_PERF_CTL, val, dummy);
>> - return val;
>> + rdmsrq(MSR_IA32_PERF_CTL, val);
>> + return (u32)val;
>> }
>> static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val)
>> {
>> - u32 lo, hi;
>> + struct msr msrval;
>> - rdmsr(MSR_IA32_PERF_CTL, lo, hi);
>> - lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
>> - wrmsr(MSR_IA32_PERF_CTL, lo, hi);
>> + rdmsrq(MSR_IA32_PERF_CTL, msrval.q);
>> + msrval.h = (msrval.h & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
>
> msrval.l
Oh, indeed.
>
> please feel free to correct me if there is any misunderstanding.
>
> how about using u64 directly?
>
> u64 msrval;
> rdmsrq(MSR_IA32_PERF_CTL, msrval);
> msrval = (msrval & ~(u64)INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
> wrmsrq(MSR_IA32_PERF_CTL, msrval);
>
> As per my understanding, we can use u64 instead of struct msr in many
> other places in this patch as well.
I didn't look at all the MSR definitions to find out whether a plain u64 would
work.
Will look into this in more detail.
>
>> + wrmsrq(MSR_IA32_PERF_CTL, msrval.q);
>> }
>> static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used)
>> {
>> - u32 val, dummy __always_unused;
>> + u64 val;
>> - rdmsr(MSR_AMD_PERF_CTL, val, dummy);
>> - return val;
>> + rdmsrq(MSR_AMD_PERF_CTL, val);
>> + return (u32)val;
>> }
>> static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val)
>> {
>> - wrmsr(MSR_AMD_PERF_CTL, val, 0);
>> + wrmsrq(MSR_AMD_PERF_CTL, val);
>> }
>> static u32 cpu_freq_read_io(struct acpi_pct_register *reg)
>> diff --git a/drivers/cpufreq/e_powersaver.c b/drivers/cpufreq/e_powersaver.c
>> index eb5a9209d828..13709f9667ea 100644
>> --- a/drivers/cpufreq/e_powersaver.c
>> +++ b/drivers/cpufreq/e_powersaver.c
>> @@ -90,7 +90,7 @@ static int eps_acpi_exit(struct cpufreq_policy *policy)
>> static unsigned int eps_get(unsigned int cpu)
>> {
>> struct eps_cpu_data *centaur;
>> - u32 lo, hi;
>> + u64 val;
>> if (cpu)
>> return 0;
>> @@ -99,35 +99,35 @@ static unsigned int eps_get(unsigned int cpu)
>> return 0;
>> /* Return current frequency */
>> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
>> - return centaur->fsb * ((lo >> 8) & 0xff);
>> + rdmsrq(MSR_IA32_PERF_STATUS, val);
>> + return centaur->fsb * ((val >> 8) & 0xff);
>> }
>> static int eps_set_state(struct eps_cpu_data *centaur,
>> struct cpufreq_policy *policy,
>> u32 dest_state)
>> {
>> - u32 lo, hi;
>> + u64 val;
>> int i;
>> /* Wait while CPU is busy */
>> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
>> + rdmsrq(MSR_IA32_PERF_STATUS, val);
>> i = 0;
>> - while (lo & ((1 << 16) | (1 << 17))) {
>> + while (val & ((1 << 16) | (1 << 17))) {
>> udelay(16);
>> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
>> + rdmsrq(MSR_IA32_PERF_STATUS, val);
>> i++;
>> if (unlikely(i > 64)) {
>> return -ENODEV;
>> }
>> }
>> /* Set new multiplier and voltage */
>> - wrmsr(MSR_IA32_PERF_CTL, dest_state & 0xffff, 0);
>> + wrmsrq(MSR_IA32_PERF_CTL, dest_state & 0xffff);
>> /* Wait until transition end */
>> i = 0;
>> do {
>> udelay(16);
>> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
>> + rdmsrq(MSR_IA32_PERF_STATUS, val);
>> i++;
>> if (unlikely(i > 64)) {
>> return -ENODEV;
>
>
> do {
> udelay(16);
> rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
> i++;
> if (unlikely(i > 64)) {
> return -ENODEV;
> }
> } while (lo & ((1 << 16) | (1 << 17)));-->lo has been deleted?
Thanks for spotting that. Seems by 32-bit allyesconfig tree lost the config
entry needed for building this source.
Will fix this.
>
>
>
>
>
>> @@ -139,10 +139,10 @@ static int eps_set_state(struct eps_cpu_data *centaur,
>> u8 current_multiplier, current_voltage;
>> /* Print voltage and multiplier */
>> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
>> - current_voltage = lo & 0xff;
>> + rdmsrq(MSR_IA32_PERF_STATUS, val);
>> + current_voltage = val & 0xff;
>> pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
>> - current_multiplier = (lo >> 8) & 0xff;
>> + current_multiplier = (val >> 8) & 0xff;
>> pr_info("Current multiplier = %d\n", current_multiplier);
>> }
>> #endif
>> @@ -171,8 +171,8 @@ static int eps_target(struct cpufreq_policy *policy,
>> unsigned int index)
>> static int eps_cpu_init(struct cpufreq_policy *policy)
>> {
>> unsigned int i;
>> - u32 lo, hi;
>> u64 val;
>> + struct msr status;
>> u8 current_multiplier, current_voltage;
>> u8 max_multiplier, max_voltage;
>> u8 min_multiplier, min_voltage;
>> @@ -195,13 +195,13 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
>> switch (c->x86_model) {
>> case 10:
>> - rdmsr(0x1153, lo, hi);
>> - brand = (((lo >> 2) ^ lo) >> 18) & 3;
>> + rdmsrq(0x1153, val);
>> + brand = (((val >> 2) ^ val) >> 18) & 3;
>> pr_cont("Model A ");
>> break;
>> case 13:
>> - rdmsr(0x1154, lo, hi);
>> - brand = (((lo >> 4) ^ (lo >> 2))) & 0x000000ff;
>> + rdmsrq(0x1154, val);
>> + brand = (((val >> 4) ^ (val >> 2))) & 0x000000ff;
>> pr_cont("Model D ");
>> break;
>> }
>> @@ -237,20 +237,20 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
>> }
>> /* Print voltage and multiplier */
>> - rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
>> - current_voltage = lo & 0xff;
>> + rdmsrq(MSR_IA32_PERF_STATUS, status.q);
>> + current_voltage = status.l & 0xff;
>> pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
>> - current_multiplier = (lo >> 8) & 0xff;
>> + current_multiplier = (status.l >> 8) & 0xff;
>> pr_info("Current multiplier = %d\n", current_multiplier);
>> /* Print limits */
>> - max_voltage = hi & 0xff;
>> + max_voltage = status.h & 0xff;
>> pr_info("Highest voltage = %dmV\n", max_voltage * 16 + 700);
>> - max_multiplier = (hi >> 8) & 0xff;
>> + max_multiplier = (status.h >> 8) & 0xff;
>> pr_info("Highest multiplier = %d\n", max_multiplier);
>> - min_voltage = (hi >> 16) & 0xff;
>> + min_voltage = (status.h >> 16) & 0xff;
>> pr_info("Lowest voltage = %dmV\n", min_voltage * 16 + 700);
>> - min_multiplier = (hi >> 24) & 0xff;
>> + min_multiplier = (status.h >> 24) & 0xff;
>> pr_info("Lowest multiplier = %d\n", min_multiplier);
>> /* Sanity checks */
>> diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
>> index a18d1d11725f..4c2599264333 100644
>> --- a/drivers/cpufreq/longhaul.c
>> +++ b/drivers/cpufreq/longhaul.c
>> @@ -118,13 +118,14 @@ static unsigned int calc_speed(int mult)
>> static int longhaul_get_cpu_mult(void)
>> {
>> - unsigned long invalue = 0, lo, hi;
>> + unsigned long invalue = 0;
>> + u64 val;
>> - rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
>> - invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22;
>> + rdmsrq(MSR_IA32_EBL_CR_POWERON, val);
>> + invalue = (val & (1<<22|1<<23|1<<24|1<<25))>>22;
>> if (longhaul_version == TYPE_LONGHAUL_V2 ||
>> longhaul_version == TYPE_POWERSAVER) {
>> - if (lo & (1<<27))
>> + if (val & (1<<27))
>> invalue += 16;
>> }
>> return eblcr[invalue];
>> @@ -761,7 +762,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
>> struct cpuinfo_x86 *c = &cpu_data(0);
>> char *cpuname = NULL;
>> int ret;
>> - u32 lo, hi;
>> + u64 val;
>> /* Check what we have on this motherboard */
>> switch (c->x86_model) {
>> @@ -835,8 +836,8 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
>> }
>> /* Check Longhaul ver. 2 */
>> if (longhaul_version == TYPE_LONGHAUL_V2) {
>> - rdmsr(MSR_VIA_LONGHAUL, lo, hi);
>> - if (lo == 0 && hi == 0)
>> + rdmsrq(MSR_VIA_LONGHAUL, val);
>> + if (val == 0)
>> /* Looks like MSR isn't present */
>> longhaul_version = TYPE_LONGHAUL_V1;
>> }
>> diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c
>> index f3aaca0496a4..99abef32e7e5 100644
>> --- a/drivers/cpufreq/longrun.c
>> +++ b/drivers/cpufreq/longrun.c
>> @@ -35,27 +35,27 @@ static unsigned int longrun_low_freq, longrun_high_freq;
>> */
>> static void longrun_get_policy(struct cpufreq_policy *policy)
>> {
>> - u32 msr_lo, msr_hi;
>> + struct msr msr;
>> - rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
>> - pr_debug("longrun flags are %x - %x\n", msr_lo, msr_hi);
>> - if (msr_lo & 0x01)
>> + rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
>> + pr_debug("longrun flags are %x - %x\n", msr.l, msr.h);
>> + if (msr.l & 0x01)
>> policy->policy = CPUFREQ_POLICY_PERFORMANCE;
>> else
>> policy->policy = CPUFREQ_POLICY_POWERSAVE;
>> - rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
>> - pr_debug("longrun ctrl is %x - %x\n", msr_lo, msr_hi);
>> - msr_lo &= 0x0000007F;
>> - msr_hi &= 0x0000007F;
>> + rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
>> + pr_debug("longrun ctrl is %x - %x\n", msr.l, msr.h);
>> + msr.l &= 0x0000007F;
>> + msr.h &= 0x0000007F;
>> if (longrun_high_freq <= longrun_low_freq) {
>> /* Assume degenerate Longrun table */
>> policy->min = policy->max = longrun_high_freq;
>> } else {
>> - policy->min = longrun_low_freq + msr_lo *
>> + policy->min = longrun_low_freq + msr.l *
>> ((longrun_high_freq - longrun_low_freq) / 100);
>> - policy->max = longrun_low_freq + msr_hi *
>> + policy->max = longrun_low_freq + msr.h *
>> ((longrun_high_freq - longrun_low_freq) / 100);
>> }
>> policy->cpu = 0;
>> @@ -71,7 +71,7 @@ static void longrun_get_policy(struct cpufreq_policy *policy)
>> */
>> static int longrun_set_policy(struct cpufreq_policy *policy)
>> {
>> - u32 msr_lo, msr_hi;
>> + struct msr msr;
>> u32 pctg_lo, pctg_hi;
>> if (!policy)
>> @@ -93,24 +93,24 @@ static int longrun_set_policy(struct cpufreq_policy *policy)
>> pctg_lo = pctg_hi;
>> /* performance or economy mode */
>> - rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
>> - msr_lo &= 0xFFFFFFFE;
>> + rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
>> + msr.l &= 0xFFFFFFFE;
>> switch (policy->policy) {
>> case CPUFREQ_POLICY_PERFORMANCE:
>> - msr_lo |= 0x00000001;
>> + msr.l |= 0x00000001;
>> break;
>> case CPUFREQ_POLICY_POWERSAVE:
>> break;
>> }
>> - wrmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
>> + wrmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
>> /* lower and upper boundary */
>> - rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
>> - msr_lo &= 0xFFFFFF80;
>> - msr_hi &= 0xFFFFFF80;
>> - msr_lo |= pctg_lo;
>> - msr_hi |= pctg_hi;
>> - wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
>> + rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
>> + msr.l &= 0xFFFFFF80;
>> + msr.h &= 0xFFFFFF80;
>> + msr.l |= pctg_lo;
>> + msr.h |= pctg_hi;
>> + wrmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
>> return 0;
>> }
>> @@ -160,7 +160,7 @@ static unsigned int longrun_get(unsigned int cpu)
>> static int longrun_determine_freqs(unsigned int *low_freq,
>> unsigned int *high_freq)
>> {
>> - u32 msr_lo, msr_hi;
>> + struct msr msr;
>> u32 save_lo, save_hi;
>> u32 eax, ebx, ecx, edx;
>> u32 try_hi;
>> @@ -178,15 +178,17 @@ static int longrun_determine_freqs(unsigned int *low_freq,
>> * For maximum frequency, read out level zero.
>> */
>> /* minimum */
>> - rdmsr(MSR_TMTA_LRTI_READOUT, msr_lo, msr_hi);
>> - wrmsr(MSR_TMTA_LRTI_READOUT, msr_hi, msr_hi);
>> - rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
>> - *low_freq = msr_lo * 1000; /* to kHz */
>> + rdmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
>> + msr.l = msr.h;
>> + wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
>> + rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
>> + *low_freq = msr.l * 1000; /* to kHz */
>> /* maximum */
>> - wrmsr(MSR_TMTA_LRTI_READOUT, 0, msr_hi);
>> - rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
>> - *high_freq = msr_lo * 1000; /* to kHz */
>> + msr.l = 0;
>> + wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
>> + rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
>> + *high_freq = msr.l * 1000; /* to kHz */
>> pr_debug("longrun table interface told %u - %u kHz\n",
>> *low_freq, *high_freq);
>> @@ -202,9 +204,9 @@ static int longrun_determine_freqs(unsigned int *low_freq,
>> pr_debug("high frequency is %u kHz\n", *high_freq);
>> /* get current borders */
>> - rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
>> - save_lo = msr_lo & 0x0000007F;
>> - save_hi = msr_hi & 0x0000007F;
>> + rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
>> + save_lo = msr.l & 0x0000007F;
>> + save_hi = msr.h & 0x0000007F;
>> /* if current perf_pctg is larger than 90%, we need to decrease the
>> * upper limit to make the calculation more accurate.
>> @@ -214,16 +216,18 @@ static int longrun_determine_freqs(unsigned int *low_freq,
>> * on some barrier values */
>> for (try_hi = 80; try_hi > 0 && ecx > 90; try_hi -= 10) {
>> /* set to 0 to try_hi perf_pctg */
>> - msr_lo &= 0xFFFFFF80;
>> - msr_hi &= 0xFFFFFF80;
>> - msr_hi |= try_hi;
>> - wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
>> + msr.l &= 0xFFFFFF80;
>> + msr.h &= 0xFFFFFF80;
>> + msr.h |= try_hi;
>> + wrmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
>> /* read out current core MHz and current perf_pctg */
>> cpuid(0x80860007, &eax, &ebx, &ecx, &edx);
>> /* restore values */
>> - wrmsr(MSR_TMTA_LONGRUN_CTRL, save_lo, save_hi);
>> + msr.l = save_lo;
>> + msr.h = save_hi;
>> + wrmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
>> }
>
> As sashiko.dev pointed, from the second iter, this patch code
> will clear upper 25 bits to zero.
>
> https://sashiko.dev/#/patchset/20260629060526.3638272-1-jgross%40suse.com
>
> for (try_hi = 80; ...; ...) {
> - msr_lo &= 0xFFFFFF80; /* iter 1: X.lo[31:7]; iter 2+: same */
> - msr_hi &= 0xFFFFFF80;
> - msr_hi |= try_hi;
> - wrmsr(reg, msr_lo, msr_hi);/* writes X.hi[31:7] | try_hi */
> + msr.l &= 0xFFFFFF80; /* iter 2+: locals=0 -> mask = 0 */
> + msr.h &= 0xFFFFFF80;
> + msr.h |= try_hi;
> + wrmsrq(reg, msr.q); /* <-- iter 2+ writes 0 (vs X.hi[31:7])*/
>
> cpuid(...);
>
> /* restore */
> - wrmsr(reg, save_lo, save_hi); /* locals untouched */
> + msr.l = save_lo; /* poisons locals ->next iter bug */
> + msr.h = save_hi;
> + wrmsrq(reg, msr.q);
> }
>
> I'm not sure whether the upper 25 bits are reserved, but the original
> code preserved them across iterations. It might be safer to keep that
> behavior unchanged.
Will fix that.
Juergen
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3743 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 495 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 17/32] x86/resctrl: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (15 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 16/32] cpufreq: Stop using 32-bit MSR interfaces Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-07-01 16:49 ` Reinette Chatre
2026-07-02 10:15 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
2026-06-29 6:05 ` [PATCH 18/32] x86/apic: " Juergen Gross
` (15 subsequent siblings)
32 siblings, 2 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Tony Luck, Reinette Chatre, Dave Martin,
James Morse, Babu Moger, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/include/asm/resctrl.h | 5 ++++-
arch/x86/kernel/cpu/resctrl/core.c | 7 ++++--
arch/x86/kernel/cpu/resctrl/monitor.c | 27 +++++++++++++----------
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 12 +++++-----
4 files changed, 30 insertions(+), 21 deletions(-)
diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h
index 575f8408a9e7..8f6edcdcfd87 100644
--- a/arch/x86/include/asm/resctrl.h
+++ b/arch/x86/include/asm/resctrl.h
@@ -102,6 +102,7 @@ static inline void __resctrl_sched_in(struct task_struct *tsk)
struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state);
u32 closid = READ_ONCE(state->default_closid);
u32 rmid = READ_ONCE(state->default_rmid);
+ struct msr val;
u32 tmp;
/*
@@ -123,7 +124,9 @@ static inline void __resctrl_sched_in(struct task_struct *tsk)
if (closid != state->cur_closid || rmid != state->cur_rmid) {
state->cur_closid = closid;
state->cur_rmid = rmid;
- wrmsr(MSR_IA32_PQR_ASSOC, rmid, closid);
+ val.l = rmid;
+ val.h = closid;
+ wrmsrq(MSR_IA32_PQR_ASSOC, val.q);
}
}
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 9c01d2562b7a..f452e8ce4cef 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -725,13 +725,16 @@ static void domain_remove_cpu(int cpu, struct rdt_resource *r)
static void clear_closid_rmid(int cpu)
{
struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state);
+ struct msr val = {
+ .l = RESCTRL_RESERVED_RMID,
+ .h = RESCTRL_RESERVED_CLOSID
+ };
state->default_closid = RESCTRL_RESERVED_CLOSID;
state->default_rmid = RESCTRL_RESERVED_RMID;
state->cur_closid = RESCTRL_RESERVED_CLOSID;
state->cur_rmid = RESCTRL_RESERVED_RMID;
- wrmsr(MSR_IA32_PQR_ASSOC, RESCTRL_RESERVED_RMID,
- RESCTRL_RESERVED_CLOSID);
+ wrmsrq(MSR_IA32_PQR_ASSOC, val.q);
}
static int resctrl_arch_online_cpu(unsigned int cpu)
diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
index 03ee6102ab07..153dc5a268a4 100644
--- a/arch/x86/kernel/cpu/resctrl/monitor.c
+++ b/arch/x86/kernel/cpu/resctrl/monitor.c
@@ -136,7 +136,7 @@ static int logical_rmid_to_physical_rmid(int cpu, int lrmid)
static int __rmid_read_phys(u32 prmid, enum resctrl_event_id eventid, u64 *val)
{
- u64 msr_val;
+ struct msr msr_val = { .l = eventid, .h = prmid };
/*
* As per the SDM, when IA32_QM_EVTSEL.EvtID (bits 7:0) is configured
@@ -146,15 +146,15 @@ static int __rmid_read_phys(u32 prmid, enum resctrl_event_id eventid, u64 *val)
* IA32_QM_CTR.Error (bit 63) and IA32_QM_CTR.Unavailable (bit 62)
* are error bits.
*/
- wrmsr(MSR_IA32_QM_EVTSEL, eventid, prmid);
- rdmsrq(MSR_IA32_QM_CTR, msr_val);
+ wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q);
+ rdmsrq(MSR_IA32_QM_CTR, msr_val.q);
- if (msr_val & RMID_VAL_ERROR)
+ if (msr_val.q & RMID_VAL_ERROR)
return -EIO;
- if (msr_val & RMID_VAL_UNAVAIL)
+ if (msr_val.q & RMID_VAL_UNAVAIL)
return -EINVAL;
- *val = msr_val;
+ *val = msr_val.q;
return 0;
}
@@ -278,7 +278,10 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *hdr,
static int __cntr_id_read(u32 cntr_id, u64 *val)
{
- u64 msr_val;
+ struct msr msr_val = {
+ .l = ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID,
+ .h = cntr_id
+ };
/*
* QM_EVTSEL Register definition:
@@ -301,15 +304,15 @@ static int __cntr_id_read(u32 cntr_id, u64 *val)
* ID is set in the QM_EVTSEL.RMID field. The RMID_VAL_UNAVAIL bit
* is set if the counter data is unavailable.
*/
- wrmsr(MSR_IA32_QM_EVTSEL, ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, cntr_id);
- rdmsrq(MSR_IA32_QM_CTR, msr_val);
+ wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q);
+ rdmsrq(MSR_IA32_QM_CTR, msr_val.q);
- if (msr_val & RMID_VAL_ERROR)
+ if (msr_val.q & RMID_VAL_ERROR)
return -EIO;
- if (msr_val & RMID_VAL_UNAVAIL)
+ if (msr_val.q & RMID_VAL_UNAVAIL)
return -EINVAL;
- *val = msr_val;
+ *val = msr_val.q;
return 0;
}
diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index de580eca3363..d7caab0409b6 100644
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -241,16 +241,16 @@ int resctrl_arch_pseudo_lock_fn(void *_plr)
int resctrl_arch_measure_cycles_lat_fn(void *_plr)
{
struct pseudo_lock_region *plr = _plr;
- u32 saved_low, saved_high;
unsigned long i;
u64 start, end;
void *mem_r;
+ u64 saved;
local_irq_disable();
/*
* Disable hardware prefetchers.
*/
- rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ rdmsrq(MSR_MISC_FEATURE_CONTROL, saved);
wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
mem_r = READ_ONCE(plr->kmem);
/*
@@ -267,7 +267,7 @@ int resctrl_arch_measure_cycles_lat_fn(void *_plr)
end = rdtsc_ordered();
trace_pseudo_lock_mem_latency((u32)(end - start));
}
- wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ wrmsrq(MSR_MISC_FEATURE_CONTROL, saved);
local_irq_enable();
plr->thread_done = 1;
wake_up_interruptible(&plr->lock_thread_wq);
@@ -312,11 +312,11 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
u64 hits_before = 0, hits_after = 0, miss_before = 0, miss_after = 0;
struct perf_event *miss_event, *hit_event;
int hit_pmcnum, miss_pmcnum;
- u32 saved_low, saved_high;
unsigned int line_size;
unsigned int size;
unsigned long i;
void *mem_r;
+ u64 saved;
u64 tmp;
miss_event = perf_event_create_kernel_counter(miss_attr, plr->cpu,
@@ -346,7 +346,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
/*
* Disable hardware prefetchers.
*/
- rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ rdmsrq(MSR_MISC_FEATURE_CONTROL, saved);
wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
/* Initialize rest of local variables */
@@ -405,7 +405,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
*/
rmb();
/* Re-enable hardware prefetchers */
- wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ wrmsrq(MSR_MISC_FEATURE_CONTROL, saved);
local_irq_enable();
out_hit:
perf_event_release_kernel(hit_event);
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 17/32] x86/resctrl: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 17/32] x86/resctrl: " Juergen Gross
@ 2026-07-01 16:49 ` Reinette Chatre
2026-07-02 10:15 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
1 sibling, 0 replies; 80+ messages in thread
From: Reinette Chatre @ 2026-07-01 16:49 UTC (permalink / raw)
To: Juergen Gross, linux-kernel, x86
Cc: Tony Luck, Dave Martin, James Morse, Babu Moger, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, H. Peter Anvin
On 6/28/26 11:05 PM, Juergen Gross wrote:
> The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
> removed. Use the related 64-bit variants instead.
>
> Signed-off-by: Juergen Gross <jgross@suse.com>
> ---
Thank you.
Acked-by: Reinette Chatre <reinette.chatre@intel.com>
Reinette
^ permalink raw reply [flat|nested] 80+ messages in thread
* [tip: x86/msr] x86/resctrl: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 17/32] x86/resctrl: " Juergen Gross
2026-07-01 16:49 ` Reinette Chatre
@ 2026-07-02 10:15 ` tip-bot2 for Juergen Gross
1 sibling, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:15 UTC (permalink / raw)
To: linux-tip-commits
Cc: Juergen Gross, Ingo Molnar, Reinette Chatre, x86, linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: 4967c466ca3860fcc3ae70fee286f220020774fe
Gitweb: https://git.kernel.org/tip/4967c466ca3860fcc3ae70fee286f220020774fe
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:05:08 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:52 +02:00
x86/resctrl: Stop using 32-bit MSR interfaces
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/20260629060526.3638272-18-jgross@suse.com
---
arch/x86/include/asm/resctrl.h | 5 +++-
arch/x86/kernel/cpu/resctrl/core.c | 7 ++++--
arch/x86/kernel/cpu/resctrl/monitor.c | 27 ++++++++++++----------
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 12 +++++-----
4 files changed, 30 insertions(+), 21 deletions(-)
diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h
index 575f840..8f6edcd 100644
--- a/arch/x86/include/asm/resctrl.h
+++ b/arch/x86/include/asm/resctrl.h
@@ -102,6 +102,7 @@ static inline void __resctrl_sched_in(struct task_struct *tsk)
struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state);
u32 closid = READ_ONCE(state->default_closid);
u32 rmid = READ_ONCE(state->default_rmid);
+ struct msr val;
u32 tmp;
/*
@@ -123,7 +124,9 @@ static inline void __resctrl_sched_in(struct task_struct *tsk)
if (closid != state->cur_closid || rmid != state->cur_rmid) {
state->cur_closid = closid;
state->cur_rmid = rmid;
- wrmsr(MSR_IA32_PQR_ASSOC, rmid, closid);
+ val.l = rmid;
+ val.h = closid;
+ wrmsrq(MSR_IA32_PQR_ASSOC, val.q);
}
}
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 9c01d25..f452e8c 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -725,13 +725,16 @@ static void domain_remove_cpu(int cpu, struct rdt_resource *r)
static void clear_closid_rmid(int cpu)
{
struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state);
+ struct msr val = {
+ .l = RESCTRL_RESERVED_RMID,
+ .h = RESCTRL_RESERVED_CLOSID
+ };
state->default_closid = RESCTRL_RESERVED_CLOSID;
state->default_rmid = RESCTRL_RESERVED_RMID;
state->cur_closid = RESCTRL_RESERVED_CLOSID;
state->cur_rmid = RESCTRL_RESERVED_RMID;
- wrmsr(MSR_IA32_PQR_ASSOC, RESCTRL_RESERVED_RMID,
- RESCTRL_RESERVED_CLOSID);
+ wrmsrq(MSR_IA32_PQR_ASSOC, val.q);
}
static int resctrl_arch_online_cpu(unsigned int cpu)
diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
index 03ee610..153dc5a 100644
--- a/arch/x86/kernel/cpu/resctrl/monitor.c
+++ b/arch/x86/kernel/cpu/resctrl/monitor.c
@@ -136,7 +136,7 @@ static int logical_rmid_to_physical_rmid(int cpu, int lrmid)
static int __rmid_read_phys(u32 prmid, enum resctrl_event_id eventid, u64 *val)
{
- u64 msr_val;
+ struct msr msr_val = { .l = eventid, .h = prmid };
/*
* As per the SDM, when IA32_QM_EVTSEL.EvtID (bits 7:0) is configured
@@ -146,15 +146,15 @@ static int __rmid_read_phys(u32 prmid, enum resctrl_event_id eventid, u64 *val)
* IA32_QM_CTR.Error (bit 63) and IA32_QM_CTR.Unavailable (bit 62)
* are error bits.
*/
- wrmsr(MSR_IA32_QM_EVTSEL, eventid, prmid);
- rdmsrq(MSR_IA32_QM_CTR, msr_val);
+ wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q);
+ rdmsrq(MSR_IA32_QM_CTR, msr_val.q);
- if (msr_val & RMID_VAL_ERROR)
+ if (msr_val.q & RMID_VAL_ERROR)
return -EIO;
- if (msr_val & RMID_VAL_UNAVAIL)
+ if (msr_val.q & RMID_VAL_UNAVAIL)
return -EINVAL;
- *val = msr_val;
+ *val = msr_val.q;
return 0;
}
@@ -278,7 +278,10 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *hdr,
static int __cntr_id_read(u32 cntr_id, u64 *val)
{
- u64 msr_val;
+ struct msr msr_val = {
+ .l = ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID,
+ .h = cntr_id
+ };
/*
* QM_EVTSEL Register definition:
@@ -301,15 +304,15 @@ static int __cntr_id_read(u32 cntr_id, u64 *val)
* ID is set in the QM_EVTSEL.RMID field. The RMID_VAL_UNAVAIL bit
* is set if the counter data is unavailable.
*/
- wrmsr(MSR_IA32_QM_EVTSEL, ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, cntr_id);
- rdmsrq(MSR_IA32_QM_CTR, msr_val);
+ wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q);
+ rdmsrq(MSR_IA32_QM_CTR, msr_val.q);
- if (msr_val & RMID_VAL_ERROR)
+ if (msr_val.q & RMID_VAL_ERROR)
return -EIO;
- if (msr_val & RMID_VAL_UNAVAIL)
+ if (msr_val.q & RMID_VAL_UNAVAIL)
return -EINVAL;
- *val = msr_val;
+ *val = msr_val.q;
return 0;
}
diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index de580ec..d7caab0 100644
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -241,16 +241,16 @@ int resctrl_arch_pseudo_lock_fn(void *_plr)
int resctrl_arch_measure_cycles_lat_fn(void *_plr)
{
struct pseudo_lock_region *plr = _plr;
- u32 saved_low, saved_high;
unsigned long i;
u64 start, end;
void *mem_r;
+ u64 saved;
local_irq_disable();
/*
* Disable hardware prefetchers.
*/
- rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ rdmsrq(MSR_MISC_FEATURE_CONTROL, saved);
wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
mem_r = READ_ONCE(plr->kmem);
/*
@@ -267,7 +267,7 @@ int resctrl_arch_measure_cycles_lat_fn(void *_plr)
end = rdtsc_ordered();
trace_pseudo_lock_mem_latency((u32)(end - start));
}
- wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ wrmsrq(MSR_MISC_FEATURE_CONTROL, saved);
local_irq_enable();
plr->thread_done = 1;
wake_up_interruptible(&plr->lock_thread_wq);
@@ -312,11 +312,11 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
u64 hits_before = 0, hits_after = 0, miss_before = 0, miss_after = 0;
struct perf_event *miss_event, *hit_event;
int hit_pmcnum, miss_pmcnum;
- u32 saved_low, saved_high;
unsigned int line_size;
unsigned int size;
unsigned long i;
void *mem_r;
+ u64 saved;
u64 tmp;
miss_event = perf_event_create_kernel_counter(miss_attr, plr->cpu,
@@ -346,7 +346,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
/*
* Disable hardware prefetchers.
*/
- rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ rdmsrq(MSR_MISC_FEATURE_CONTROL, saved);
wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
/* Initialize rest of local variables */
@@ -405,7 +405,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
*/
rmb();
/* Re-enable hardware prefetchers */
- wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
+ wrmsrq(MSR_MISC_FEATURE_CONTROL, saved);
local_irq_enable();
out_hit:
perf_event_release_kernel(hit_event);
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 18/32] x86/apic: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (16 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 17/32] x86/resctrl: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-07-02 10:15 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
2026-06-29 6:05 ` [PATCH 19/32] x86/cpu: " Juergen Gross
` (14 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kernel/apic/apic.c | 39 +++++++++++++++++++------------------
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index aa1e19979aa8..90025451ace2 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1191,11 +1191,11 @@ void disable_local_APIC(void)
* restore the disabled state.
*/
if (enabled_via_apicbase) {
- unsigned int l, h;
+ struct msr val;
- rdmsr(MSR_IA32_APICBASE, l, h);
- l &= ~MSR_IA32_APICBASE_ENABLE;
- wrmsr(MSR_IA32_APICBASE, l, h);
+ rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.l &= ~MSR_IA32_APICBASE_ENABLE;
+ wrmsrq(MSR_IA32_APICBASE, val.q);
}
#endif
}
@@ -1960,7 +1960,8 @@ static bool __init detect_init_APIC(void)
static bool __init apic_verify(unsigned long addr)
{
- u32 features, h, l;
+ struct msr val;
+ u32 features;
/*
* The APIC feature bit should now be enabled
@@ -1975,9 +1976,9 @@ static bool __init apic_verify(unsigned long addr)
/* The BIOS may have set up the APIC at some other address */
if (boot_cpu_data.x86 >= 6) {
- rdmsr(MSR_IA32_APICBASE, l, h);
- if (l & MSR_IA32_APICBASE_ENABLE)
- addr = l & MSR_IA32_APICBASE_BASE;
+ rdmsrq(MSR_IA32_APICBASE, val.q);
+ if (val.l & MSR_IA32_APICBASE_ENABLE)
+ addr = val.l & MSR_IA32_APICBASE_BASE;
}
register_lapic_address(addr);
@@ -1987,7 +1988,7 @@ static bool __init apic_verify(unsigned long addr)
bool __init apic_force_enable(unsigned long addr)
{
- u32 h, l;
+ struct msr val;
if (apic_is_disabled)
return false;
@@ -1998,12 +1999,12 @@ bool __init apic_force_enable(unsigned long addr)
* and AMD K7 (Model > 1) or later.
*/
if (boot_cpu_data.x86 >= 6) {
- rdmsr(MSR_IA32_APICBASE, l, h);
- if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+ rdmsrq(MSR_IA32_APICBASE, val.q);
+ if (!(val.l & MSR_IA32_APICBASE_ENABLE)) {
pr_info("Local APIC disabled by BIOS -- reenabling.\n");
- l &= ~MSR_IA32_APICBASE_BASE;
- l |= MSR_IA32_APICBASE_ENABLE | addr;
- wrmsr(MSR_IA32_APICBASE, l, h);
+ val.l &= ~MSR_IA32_APICBASE_BASE;
+ val.l |= MSR_IA32_APICBASE_ENABLE | addr;
+ wrmsrq(MSR_IA32_APICBASE, val.q);
enabled_via_apicbase = 1;
}
}
@@ -2442,7 +2443,7 @@ static int lapic_suspend(void *data)
static void lapic_resume(void *data)
{
- unsigned int l, h;
+ struct msr val;
unsigned long flags;
int maxlvt;
@@ -2475,10 +2476,10 @@ static void lapic_resume(void *data)
* SMP! We'll need to do this as part of the CPU restore!
*/
if (boot_cpu_data.x86 >= 6) {
- rdmsr(MSR_IA32_APICBASE, l, h);
- l &= ~MSR_IA32_APICBASE_BASE;
- l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
- wrmsr(MSR_IA32_APICBASE, l, h);
+ rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.l &= ~MSR_IA32_APICBASE_BASE;
+ val.l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+ wrmsrq(MSR_IA32_APICBASE, val.q);
}
}
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [tip: x86/msr] x86/apic: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 18/32] x86/apic: " Juergen Gross
@ 2026-07-02 10:15 ` tip-bot2 for Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:15 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Juergen Gross, Ingo Molnar, x86, linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: 7920900e53dd9cff1f95a8edfeac3f7c24a1b723
Gitweb: https://git.kernel.org/tip/7920900e53dd9cff1f95a8edfeac3f7c24a1b723
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:05:09 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:52 +02:00
x86/apic: Stop using 32-bit MSR interfaces
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://patch.msgid.link/20260629060526.3638272-19-jgross@suse.com
---
arch/x86/kernel/apic/apic.c | 39 ++++++++++++++++++------------------
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index aa1e199..9002545 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1191,11 +1191,11 @@ void disable_local_APIC(void)
* restore the disabled state.
*/
if (enabled_via_apicbase) {
- unsigned int l, h;
+ struct msr val;
- rdmsr(MSR_IA32_APICBASE, l, h);
- l &= ~MSR_IA32_APICBASE_ENABLE;
- wrmsr(MSR_IA32_APICBASE, l, h);
+ rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.l &= ~MSR_IA32_APICBASE_ENABLE;
+ wrmsrq(MSR_IA32_APICBASE, val.q);
}
#endif
}
@@ -1960,7 +1960,8 @@ static bool __init detect_init_APIC(void)
static bool __init apic_verify(unsigned long addr)
{
- u32 features, h, l;
+ struct msr val;
+ u32 features;
/*
* The APIC feature bit should now be enabled
@@ -1975,9 +1976,9 @@ static bool __init apic_verify(unsigned long addr)
/* The BIOS may have set up the APIC at some other address */
if (boot_cpu_data.x86 >= 6) {
- rdmsr(MSR_IA32_APICBASE, l, h);
- if (l & MSR_IA32_APICBASE_ENABLE)
- addr = l & MSR_IA32_APICBASE_BASE;
+ rdmsrq(MSR_IA32_APICBASE, val.q);
+ if (val.l & MSR_IA32_APICBASE_ENABLE)
+ addr = val.l & MSR_IA32_APICBASE_BASE;
}
register_lapic_address(addr);
@@ -1987,7 +1988,7 @@ static bool __init apic_verify(unsigned long addr)
bool __init apic_force_enable(unsigned long addr)
{
- u32 h, l;
+ struct msr val;
if (apic_is_disabled)
return false;
@@ -1998,12 +1999,12 @@ bool __init apic_force_enable(unsigned long addr)
* and AMD K7 (Model > 1) or later.
*/
if (boot_cpu_data.x86 >= 6) {
- rdmsr(MSR_IA32_APICBASE, l, h);
- if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+ rdmsrq(MSR_IA32_APICBASE, val.q);
+ if (!(val.l & MSR_IA32_APICBASE_ENABLE)) {
pr_info("Local APIC disabled by BIOS -- reenabling.\n");
- l &= ~MSR_IA32_APICBASE_BASE;
- l |= MSR_IA32_APICBASE_ENABLE | addr;
- wrmsr(MSR_IA32_APICBASE, l, h);
+ val.l &= ~MSR_IA32_APICBASE_BASE;
+ val.l |= MSR_IA32_APICBASE_ENABLE | addr;
+ wrmsrq(MSR_IA32_APICBASE, val.q);
enabled_via_apicbase = 1;
}
}
@@ -2442,7 +2443,7 @@ static int lapic_suspend(void *data)
static void lapic_resume(void *data)
{
- unsigned int l, h;
+ struct msr val;
unsigned long flags;
int maxlvt;
@@ -2475,10 +2476,10 @@ static void lapic_resume(void *data)
* SMP! We'll need to do this as part of the CPU restore!
*/
if (boot_cpu_data.x86 >= 6) {
- rdmsr(MSR_IA32_APICBASE, l, h);
- l &= ~MSR_IA32_APICBASE_BASE;
- l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
- wrmsr(MSR_IA32_APICBASE, l, h);
+ rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.l &= ~MSR_IA32_APICBASE_BASE;
+ val.l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+ wrmsrq(MSR_IA32_APICBASE, val.q);
}
}
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 19/32] x86/cpu: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (17 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 18/32] x86/apic: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-07-02 10:15 ` [tip: x86/msr] " tip-bot2 for Juergen Gross
2026-06-29 6:05 ` [PATCH 20/32] drivers/ata: " Juergen Gross
` (13 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Tony W Wang-oc
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/kernel/cpu/centaur.c | 35 +++++++++++++++++----------------
arch/x86/kernel/cpu/common.c | 12 ++++++-----
arch/x86/kernel/cpu/intel.c | 8 ++++----
arch/x86/kernel/cpu/transmeta.c | 9 +++++----
arch/x86/kernel/cpu/zhaoxin.c | 12 +++++------
5 files changed, 39 insertions(+), 37 deletions(-)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 681d2da49341..513fa1f640f9 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -22,7 +22,7 @@
static void init_c3(struct cpuinfo_x86 *c)
{
- u32 lo, hi;
+ u64 msr;
/* Test for Centaur Extended Feature Flags presence */
if (cpuid_eax(0xC0000000) >= 0xC0000001) {
@@ -30,17 +30,17 @@ static void init_c3(struct cpuinfo_x86 *c)
/* enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsr(MSR_VIA_FCR, lo, hi);
- lo |= ACE_FCR; /* enable ACE unit */
- wrmsr(MSR_VIA_FCR, lo, hi);
+ rdmsrq(MSR_VIA_FCR, msr);
+ /* enable ACE unit */
+ wrmsrq(MSR_VIA_FCR, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
}
/* enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsr(MSR_VIA_RNG, lo, hi);
- lo |= RNG_ENABLE; /* enable RNG unit */
- wrmsr(MSR_VIA_RNG, lo, hi);
+ rdmsrq(MSR_VIA_RNG, msr);
+ /* enable RNG unit */
+ wrmsrq(MSR_VIA_RNG, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
}
@@ -52,9 +52,8 @@ static void init_c3(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_32
/* Cyrix III family needs CX8 & PGE explicitly enabled. */
if (c->x86_model >= 6 && c->x86_model <= 13) {
- rdmsr(MSR_VIA_FCR, lo, hi);
- lo |= (1<<1 | 1<<7);
- wrmsr(MSR_VIA_FCR, lo, hi);
+ rdmsrq(MSR_VIA_FCR, msr);
+ wrmsrq(MSR_VIA_FCR, msr | (1 << 1 | 1 << 7));
set_cpu_cap(c, X86_FEATURE_CX8);
}
@@ -115,8 +114,9 @@ static void init_centaur(struct cpuinfo_x86 *c)
char *name;
u32 fcr_set = 0;
u32 fcr_clr = 0;
- u32 lo, hi, newlo;
+ u32 newlo;
u32 aa, bb, cc, dd;
+ struct msr val;
#endif
early_init_centaur(c);
init_intel_cacheinfo(c);
@@ -169,15 +169,16 @@ static void init_centaur(struct cpuinfo_x86 *c)
name = "??";
}
- rdmsr(MSR_IDT_FCR1, lo, hi);
- newlo = (lo|fcr_set) & (~fcr_clr);
+ rdmsrq(MSR_IDT_FCR1, val.q);
+ newlo = (val.l | fcr_set) & (~fcr_clr);
- if (newlo != lo) {
+ if (newlo != val.l) {
pr_info("Centaur FCR was 0x%X now 0x%X\n",
- lo, newlo);
- wrmsr(MSR_IDT_FCR1, newlo, hi);
+ val.l, newlo);
+ val.l = newlo;
+ wrmsrq(MSR_IDT_FCR1, val.q);
} else {
- pr_info("Centaur FCR is 0x%X\n", lo);
+ pr_info("Centaur FCR is 0x%X\n", val.l);
}
/* Emulate MTRRs using Centaur's MCR. */
set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index a3df21d26460..cbef2c6c8478 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -339,16 +339,16 @@ bool cpuid_feature(void)
static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
{
- unsigned long lo, hi;
+ struct msr val;
if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
return;
/* Disable processor serial number: */
- rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
- lo |= 0x200000;
- wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
+ rdmsrq(MSR_IA32_BBL_CR_CTL, val.q);
+ val.l |= 0x200000;
+ wrmsrq(MSR_IA32_BBL_CR_CTL, val.q);
pr_notice("CPU serial number disabled.\n");
clear_cpu_cap(c, X86_FEATURE_PN);
@@ -2299,8 +2299,10 @@ static inline void idt_syscall_init(void)
/* May not be marked __init: used by software suspend */
void syscall_init(void)
{
+ struct msr val = { .h = (__USER32_CS << 16) | __KERNEL_CS };
+
/* The default user and kernel segments */
- wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
+ wrmsrq(MSR_STAR, val.q);
/*
* Except the IA32_STAR MSR, there is NO need to setup SYSCALL and
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index abb3984336eb..076bdd0d3f85 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -542,12 +542,12 @@ static void init_intel(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
if (boot_cpu_has(X86_FEATURE_DS)) {
- unsigned int l1, l2;
+ u64 l;
- rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
- if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
+ rdmsrq(MSR_IA32_MISC_ENABLE, l);
+ if (!(l & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_BTS);
- if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
+ if (!(l & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_PEBS);
}
diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index 1fdcd69c625c..c670fbb6ee50 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -24,7 +24,8 @@ static void early_init_transmeta(struct cpuinfo_x86 *c)
static void init_transmeta(struct cpuinfo_x86 *c)
{
- unsigned int cap_mask, uk, max, dummy;
+ u64 msr;
+ unsigned int max, dummy;
unsigned int cms_rev1, cms_rev2;
unsigned int cpu_rev, cpu_freq = 0, cpu_flags, new_cpu_rev;
char cpu_info[65];
@@ -86,10 +87,10 @@ static void init_transmeta(struct cpuinfo_x86 *c)
}
/* Unhide possibly hidden capability flags */
- rdmsr(0x80860004, cap_mask, uk);
- wrmsr(0x80860004, ~0, uk);
+ rdmsrq(0x80860004, msr);
+ wrmsrq(0x80860004, msr | ~0U);
c->x86_capability[CPUID_1_EDX] = cpuid_edx(0x00000001);
- wrmsr(0x80860004, cap_mask, uk);
+ wrmsrq(0x80860004, msr);
/* All Transmeta CPUs have a constant TSC */
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 761aef5590ac..fe504fd43c77 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -21,7 +21,7 @@
static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
{
- u32 lo, hi;
+ u64 msr;
/* Test for Extended Feature Flags presence */
if (cpuid_eax(0xC0000000) >= 0xC0000001) {
@@ -29,19 +29,17 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
/* Enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ rdmsrq(MSR_ZHAOXIN_FCR57, msr);
/* Enable ACE unit */
- lo |= ACE_FCR;
- wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ wrmsrq(MSR_ZHAOXIN_FCR57, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
}
/* Enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ rdmsrq(MSR_ZHAOXIN_FCR57, msr);
/* Enable RNG unit */
- lo |= RNG_ENABLE;
- wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ wrmsrq(MSR_ZHAOXIN_FCR57, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
}
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [tip: x86/msr] x86/cpu: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 19/32] x86/cpu: " Juergen Gross
@ 2026-07-02 10:15 ` tip-bot2 for Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: tip-bot2 for Juergen Gross @ 2026-07-02 10:15 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Juergen Gross, Ingo Molnar, x86, linux-kernel
The following commit has been merged into the x86/msr branch of tip:
Commit-ID: 2e9e6edbad45fe9078dfb2d35d1213c9969de49d
Gitweb: https://git.kernel.org/tip/2e9e6edbad45fe9078dfb2d35d1213c9969de49d
Author: Juergen Gross <jgross@suse.com>
AuthorDate: Mon, 29 Jun 2026 08:05:10 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 02 Jul 2026 11:54:52 +02:00
x86/cpu: Stop using 32-bit MSR interfaces
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://patch.msgid.link/20260629060526.3638272-20-jgross@suse.com
---
arch/x86/kernel/cpu/centaur.c | 35 ++++++++++++++++----------------
arch/x86/kernel/cpu/common.c | 12 ++++++-----
arch/x86/kernel/cpu/intel.c | 8 +++----
arch/x86/kernel/cpu/transmeta.c | 9 ++++----
arch/x86/kernel/cpu/zhaoxin.c | 12 ++++-------
5 files changed, 39 insertions(+), 37 deletions(-)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 681d2da..513fa1f 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -22,7 +22,7 @@
static void init_c3(struct cpuinfo_x86 *c)
{
- u32 lo, hi;
+ u64 msr;
/* Test for Centaur Extended Feature Flags presence */
if (cpuid_eax(0xC0000000) >= 0xC0000001) {
@@ -30,17 +30,17 @@ static void init_c3(struct cpuinfo_x86 *c)
/* enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsr(MSR_VIA_FCR, lo, hi);
- lo |= ACE_FCR; /* enable ACE unit */
- wrmsr(MSR_VIA_FCR, lo, hi);
+ rdmsrq(MSR_VIA_FCR, msr);
+ /* enable ACE unit */
+ wrmsrq(MSR_VIA_FCR, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
}
/* enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsr(MSR_VIA_RNG, lo, hi);
- lo |= RNG_ENABLE; /* enable RNG unit */
- wrmsr(MSR_VIA_RNG, lo, hi);
+ rdmsrq(MSR_VIA_RNG, msr);
+ /* enable RNG unit */
+ wrmsrq(MSR_VIA_RNG, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
}
@@ -52,9 +52,8 @@ static void init_c3(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_32
/* Cyrix III family needs CX8 & PGE explicitly enabled. */
if (c->x86_model >= 6 && c->x86_model <= 13) {
- rdmsr(MSR_VIA_FCR, lo, hi);
- lo |= (1<<1 | 1<<7);
- wrmsr(MSR_VIA_FCR, lo, hi);
+ rdmsrq(MSR_VIA_FCR, msr);
+ wrmsrq(MSR_VIA_FCR, msr | (1 << 1 | 1 << 7));
set_cpu_cap(c, X86_FEATURE_CX8);
}
@@ -115,8 +114,9 @@ static void init_centaur(struct cpuinfo_x86 *c)
char *name;
u32 fcr_set = 0;
u32 fcr_clr = 0;
- u32 lo, hi, newlo;
+ u32 newlo;
u32 aa, bb, cc, dd;
+ struct msr val;
#endif
early_init_centaur(c);
init_intel_cacheinfo(c);
@@ -169,15 +169,16 @@ static void init_centaur(struct cpuinfo_x86 *c)
name = "??";
}
- rdmsr(MSR_IDT_FCR1, lo, hi);
- newlo = (lo|fcr_set) & (~fcr_clr);
+ rdmsrq(MSR_IDT_FCR1, val.q);
+ newlo = (val.l | fcr_set) & (~fcr_clr);
- if (newlo != lo) {
+ if (newlo != val.l) {
pr_info("Centaur FCR was 0x%X now 0x%X\n",
- lo, newlo);
- wrmsr(MSR_IDT_FCR1, newlo, hi);
+ val.l, newlo);
+ val.l = newlo;
+ wrmsrq(MSR_IDT_FCR1, val.q);
} else {
- pr_info("Centaur FCR is 0x%X\n", lo);
+ pr_info("Centaur FCR is 0x%X\n", val.l);
}
/* Emulate MTRRs using Centaur's MCR. */
set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index a3df21d..cbef2c6 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -339,16 +339,16 @@ bool cpuid_feature(void)
static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
{
- unsigned long lo, hi;
+ struct msr val;
if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
return;
/* Disable processor serial number: */
- rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
- lo |= 0x200000;
- wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
+ rdmsrq(MSR_IA32_BBL_CR_CTL, val.q);
+ val.l |= 0x200000;
+ wrmsrq(MSR_IA32_BBL_CR_CTL, val.q);
pr_notice("CPU serial number disabled.\n");
clear_cpu_cap(c, X86_FEATURE_PN);
@@ -2299,8 +2299,10 @@ static inline void idt_syscall_init(void)
/* May not be marked __init: used by software suspend */
void syscall_init(void)
{
+ struct msr val = { .h = (__USER32_CS << 16) | __KERNEL_CS };
+
/* The default user and kernel segments */
- wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
+ wrmsrq(MSR_STAR, val.q);
/*
* Except the IA32_STAR MSR, there is NO need to setup SYSCALL and
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index abb3984..076bdd0 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -542,12 +542,12 @@ static void init_intel(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
if (boot_cpu_has(X86_FEATURE_DS)) {
- unsigned int l1, l2;
+ u64 l;
- rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
- if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
+ rdmsrq(MSR_IA32_MISC_ENABLE, l);
+ if (!(l & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_BTS);
- if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
+ if (!(l & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_PEBS);
}
diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index 1fdcd69..c670fbb 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -24,7 +24,8 @@ static void early_init_transmeta(struct cpuinfo_x86 *c)
static void init_transmeta(struct cpuinfo_x86 *c)
{
- unsigned int cap_mask, uk, max, dummy;
+ u64 msr;
+ unsigned int max, dummy;
unsigned int cms_rev1, cms_rev2;
unsigned int cpu_rev, cpu_freq = 0, cpu_flags, new_cpu_rev;
char cpu_info[65];
@@ -86,10 +87,10 @@ static void init_transmeta(struct cpuinfo_x86 *c)
}
/* Unhide possibly hidden capability flags */
- rdmsr(0x80860004, cap_mask, uk);
- wrmsr(0x80860004, ~0, uk);
+ rdmsrq(0x80860004, msr);
+ wrmsrq(0x80860004, msr | ~0U);
c->x86_capability[CPUID_1_EDX] = cpuid_edx(0x00000001);
- wrmsr(0x80860004, cap_mask, uk);
+ wrmsrq(0x80860004, msr);
/* All Transmeta CPUs have a constant TSC */
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 761aef5..fe504fd 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -21,7 +21,7 @@
static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
{
- u32 lo, hi;
+ u64 msr;
/* Test for Extended Feature Flags presence */
if (cpuid_eax(0xC0000000) >= 0xC0000001) {
@@ -29,19 +29,17 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
/* Enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ rdmsrq(MSR_ZHAOXIN_FCR57, msr);
/* Enable ACE unit */
- lo |= ACE_FCR;
- wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ wrmsrq(MSR_ZHAOXIN_FCR57, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
}
/* Enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ rdmsrq(MSR_ZHAOXIN_FCR57, msr);
/* Enable RNG unit */
- lo |= RNG_ENABLE;
- wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
+ wrmsrq(MSR_ZHAOXIN_FCR57, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
}
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 20/32] drivers/ata: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (18 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 19/32] x86/cpu: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 21/32] agp/nvidia: " Juergen Gross
` (12 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, linux-ide; +Cc: Juergen Gross, Damien Le Moal, Niklas Cassel
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
In drivers/ata/pata_cs5536.c don't redefine rdmsr() and wrmsr() as
empty macros for avoiding misuse, but guard the affected code via
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/ata/pata_cs5535.c | 20 ++++++++++----------
drivers/ata/pata_cs5536.c | 17 ++++++++---------
2 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c
index d793fc441b46..da98390cc49e 100644
--- a/drivers/ata/pata_cs5535.c
+++ b/drivers/ata/pata_cs5535.c
@@ -90,7 +90,7 @@ static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
static const u16 pio_cmd_timings[5] = {
0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
};
- u32 reg, __maybe_unused dummy;
+ u32 reg;
struct ata_device *pair = ata_dev_pair(adev);
int mode = adev->pio_mode - XFER_PIO_0;
@@ -102,16 +102,16 @@ static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
cmdmode = min(mode, pairmode);
/* Write the other drive timing register if it changed */
if (cmdmode < pairmode)
- wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
- pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode], 0);
+ wrmsrq(ATAC_CH0D0_PIO + 2 * pair->devno,
+ pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode]);
}
/* Write the drive timing register */
- wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
- pio_cmd_timings[cmdmode] << 16 | pio_timings[mode], 0);
+ wrmsrq(ATAC_CH0D0_PIO + 2 * adev->devno,
+ pio_cmd_timings[cmdmode] << 16 | pio_timings[mode]);
/* Set the PIO "format 1" bit in the DMA timing register */
- rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
- wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
+ rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg);
+ wrmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL);
}
/**
@@ -129,16 +129,16 @@ static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
static const u32 mwdma_timings[3] = {
0x7F0FFFF3, 0x7F035352, 0x7F024241
};
- u32 reg, __maybe_unused dummy;
+ u32 reg;
int mode = adev->dma_mode;
- rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
+ rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg);
reg &= 0x80000000UL;
if (mode >= XFER_UDMA_0)
reg |= udma_timings[mode - XFER_UDMA_0];
else
reg |= mwdma_timings[mode - XFER_MW_DMA_0];
- wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
+ wrmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg);
}
static const struct scsi_host_template cs5535_sht = {
diff --git a/drivers/ata/pata_cs5536.c b/drivers/ata/pata_cs5536.c
index 73e81e160c91..61d232a82b5e 100644
--- a/drivers/ata/pata_cs5536.c
+++ b/drivers/ata/pata_cs5536.c
@@ -32,11 +32,8 @@
static int use_msr;
module_param_named(msr, use_msr, int, 0644);
MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
+#define MAYBE_USE_MSR
#else
-#undef rdmsr /* avoid accidental MSR usage on, e.g. x86-64 */
-#undef wrmsr
-#define rdmsr(x, y, z) do { } while (0)
-#define wrmsr(x, y, z) do { } while (0)
#define use_msr 0
#endif
@@ -85,22 +82,24 @@ static const struct dmi_system_id udma_quirk_dmi_table[] = {
static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
{
+#ifdef MAYBE_USE_MSR
if (unlikely(use_msr)) {
- u32 dummy __maybe_unused;
-
- rdmsr(MSR_IDE_CFG + reg, *val, dummy);
+ rdmsrq(MSR_IDE_CFG + reg, *val);
return 0;
}
+#endif
return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
}
-static int cs5536_write(struct pci_dev *pdev, int reg, int val)
+static int cs5536_write(struct pci_dev *pdev, int reg, u32 val)
{
+#ifdef MAYBE_USE_MSR
if (unlikely(use_msr)) {
- wrmsr(MSR_IDE_CFG + reg, val, 0);
+ wrmsrq(MSR_IDE_CFG + reg, val);
return 0;
}
+#endif
return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
}
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 21/32] agp/nvidia: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (19 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 20/32] drivers/ata: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 22/32] fbdev/geode: " Juergen Gross
` (11 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, dri-devel; +Cc: Juergen Gross, David Airlie
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/char/agp/nvidia-agp.c | 32 +++++++++++++++-----------------
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index 4787391bb6b4..3e760bc00afa 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -65,22 +65,20 @@ static int nvidia_fetch_size(void)
static int nvidia_init_iorr(u32 base, u32 size)
{
- u32 base_hi, base_lo;
- u32 mask_hi, mask_lo;
- u32 sys_hi, sys_lo;
+ struct msr base_msr, mask_msr, sys_msr;
u32 iorr_addr, free_iorr_addr;
/* Find the iorr that is already used for the base */
/* If not found, determine the uppermost available iorr */
free_iorr_addr = AMD_K7_NUM_IORR;
for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
- rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
- rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
+ rdmsrq(IORR_BASE0 + 2 * iorr_addr, base_msr.q);
+ rdmsrq(IORR_MASK0 + 2 * iorr_addr, mask_msr.q);
- if ((base_lo & 0xfffff000) == (base & 0xfffff000))
+ if ((base_msr.l & 0xfffff000) == (base & 0xfffff000))
break;
- if ((mask_lo & 0x00000800) == 0)
+ if ((mask_msr.l & 0x00000800) == 0)
free_iorr_addr = iorr_addr;
}
@@ -89,16 +87,16 @@ static int nvidia_init_iorr(u32 base, u32 size)
if (iorr_addr >= AMD_K7_NUM_IORR)
return -EINVAL;
}
- base_hi = 0x0;
- base_lo = (base & ~0xfff) | 0x18;
- mask_hi = 0xf;
- mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800;
- wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
- wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
-
- rdmsr(SYSCFG, sys_lo, sys_hi);
- sys_lo |= 0x00100000;
- wrmsr(SYSCFG, sys_lo, sys_hi);
+ base_msr.h = 0x0;
+ base_msr.l = (base & ~0xfff) | 0x18;
+ mask_msr.h = 0xf;
+ mask_msr.l = ((~(size - 1)) & 0xfffff000) | 0x800;
+ wrmsrq(IORR_BASE0 + 2 * iorr_addr, base_msr.q);
+ wrmsrq(IORR_MASK0 + 2 * iorr_addr, mask_msr.q);
+
+ rdmsrq(SYSCFG, sys_msr.q);
+ sys_msr.l |= 0x00100000;
+ wrmsrq(SYSCFG, sys_msr.q);
return 0;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 22/32] fbdev/geode: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (20 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 21/32] agp/nvidia: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 23/32] hw_random/via-rng: " Juergen Gross
` (10 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, linux-fbdev, dri-devel
Cc: Juergen Gross, Helge Deller, linux-geode
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/video/fbdev/geode/display_gx.c | 8 +++---
drivers/video/fbdev/geode/lxfb_ops.c | 38 +++++++++++++-------------
drivers/video/fbdev/geode/suspend_gx.c | 20 ++++++++------
3 files changed, 34 insertions(+), 32 deletions(-)
diff --git a/drivers/video/fbdev/geode/display_gx.c b/drivers/video/fbdev/geode/display_gx.c
index 099322cefce0..b93aa21a1d2b 100644
--- a/drivers/video/fbdev/geode/display_gx.c
+++ b/drivers/video/fbdev/geode/display_gx.c
@@ -23,15 +23,15 @@ unsigned int gx_frame_buffer_size(void)
unsigned int val;
if (!cs5535_has_vsa2()) {
- uint32_t hi, lo;
+ struct msr msr;
/* The number of pages is (PMAX - PMIN)+1 */
- rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
+ rdmsrq(MSR_GLIU_P2D_RO0, msr.q);
/* PMAX */
- val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
+ val = ((msr.h & 0xff) << 12) | ((msr.l & 0xfff00000) >> 20);
/* PMIN */
- val -= (lo & 0x000fffff);
+ val -= (msr.l & 0x000fffff);
val += 1;
/* The page size is 4k */
diff --git a/drivers/video/fbdev/geode/lxfb_ops.c b/drivers/video/fbdev/geode/lxfb_ops.c
index 2e33da9849b0..f5f1134cae9a 100644
--- a/drivers/video/fbdev/geode/lxfb_ops.c
+++ b/drivers/video/fbdev/geode/lxfb_ops.c
@@ -124,19 +124,19 @@ static const struct {
static void lx_set_dotpll(u32 pllval)
{
- u32 dotpll_lo, dotpll_hi;
+ struct msr dotpll;
int i;
- rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+ rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
- if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
+ if ((dotpll.l & MSR_GLCP_DOTPLL_LOCK) && (dotpll.h == pllval))
return;
- dotpll_hi = pllval;
- dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
- dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
+ dotpll.h = pllval;
+ dotpll.l &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
+ dotpll.l |= MSR_GLCP_DOTPLL_DOTRESET;
- wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+ wrmsrq(MSR_GLCP_DOTPLL, dotpll.q);
/* Wait 100us for the PLL to lock */
@@ -145,15 +145,15 @@ static void lx_set_dotpll(u32 pllval)
/* Now, loop for the lock bit */
for (i = 0; i < 1000; i++) {
- rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
- if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
+ rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ if (dotpll.l & MSR_GLCP_DOTPLL_LOCK)
break;
}
/* Clear the reset bit */
- dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
- wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+ dotpll.l &= ~MSR_GLCP_DOTPLL_DOTRESET;
+ wrmsrq(MSR_GLCP_DOTPLL, dotpll.q);
}
/* Set the clock based on the frequency specified by the current mode */
@@ -268,7 +268,7 @@ static void lx_graphics_enable(struct fb_info *info)
config |= VP_DCFG_CRT_VSYNC_POL;
if (par->output & OUTPUT_PANEL) {
- u32 msrlo, msrhi;
+ struct msr val;
write_fp(par, FP_PT1, 0);
temp = FP_PT2_SCRC;
@@ -282,10 +282,10 @@ static void lx_graphics_enable(struct fb_info *info)
write_fp(par, FP_PT2, temp);
write_fp(par, FP_DFC, FP_DFC_BC);
- msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
- msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
+ val.l = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
+ val.h = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
- wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
+ wrmsrq(MSR_LX_MSR_PADSEL, val.q);
}
if (par->output & OUTPUT_CRT) {
@@ -313,15 +313,15 @@ unsigned int lx_framebuffer_size(void)
unsigned int val;
if (!cs5535_has_vsa2()) {
- uint32_t hi, lo;
+ struct msr msr;
/* The number of pages is (PMAX - PMIN)+1 */
- rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
+ rdmsrq(MSR_GLIU_P2D_RO0, msr.q);
/* PMAX */
- val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
+ val = ((msr.h & 0xff) << 12) | ((msr.l & 0xfff00000) >> 20);
/* PMIN */
- val -= (lo & 0x000fffff);
+ val -= (msr.l & 0x000fffff);
val += 1;
/* The page size is 4k */
diff --git a/drivers/video/fbdev/geode/suspend_gx.c b/drivers/video/fbdev/geode/suspend_gx.c
index 73307f42e343..6c0a526ee8a2 100644
--- a/drivers/video/fbdev/geode/suspend_gx.c
+++ b/drivers/video/fbdev/geode/suspend_gx.c
@@ -40,25 +40,27 @@ static void gx_save_regs(struct gxfb_par *par)
static void gx_set_dotpll(uint32_t dotpll_hi)
{
- uint32_t dotpll_lo;
+ struct msr dotpll;
int i;
- rdmsrq(MSR_GLCP_DOTPLL, dotpll_lo);
- dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
- dotpll_lo &= ~MSR_GLCP_DOTPLL_BYPASS;
- wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+ rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ dotpll.l |= MSR_GLCP_DOTPLL_DOTRESET;
+ dotpll.l &= ~MSR_GLCP_DOTPLL_BYPASS;
+ dotpll.h = dotpll_hi;
+ wrmsrq(MSR_GLCP_DOTPLL, dotpll.q);
/* wait for the PLL to lock */
for (i = 0; i < 200; i++) {
- rdmsrq(MSR_GLCP_DOTPLL, dotpll_lo);
- if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
+ rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ if (dotpll.l & MSR_GLCP_DOTPLL_LOCK)
break;
udelay(1);
}
/* PLL set, unlock */
- dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
- wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+ dotpll.l &= ~MSR_GLCP_DOTPLL_DOTRESET;
+ dotpll.h = dotpll_hi;
+ wrmsrq(MSR_GLCP_DOTPLL, dotpll.q);
}
static void gx_restore_gfx_proc(struct gxfb_par *par)
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 23/32] hw_random/via-rng: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (21 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 22/32] fbdev/geode: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 24/32] drivers/gpio: " Juergen Gross
` (9 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, linux-crypto; +Cc: Juergen Gross, Olivia Mackall, Herbert Xu
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/char/hw_random/via-rng.c | 29 +++++++++++++++--------------
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
index a9a0a3b09c8b..b718e78d3c1c 100644
--- a/drivers/char/hw_random/via-rng.c
+++ b/drivers/char/hw_random/via-rng.c
@@ -129,7 +129,8 @@ static int via_rng_data_read(struct hwrng *rng, u32 *data)
static int via_rng_init(struct hwrng *rng)
{
struct cpuinfo_x86 *c = &cpu_data(0);
- u32 lo, hi, old_lo;
+ u32 old_lo;
+ struct msr val;
/* VIA Nano CPUs don't have the MSR_VIA_RNG anymore. The RNG
* is always enabled if CPUID rng_en is set. There is no
@@ -150,32 +151,32 @@ static int via_rng_init(struct hwrng *rng)
* does not say to write them as zero, so I make a guess that
* we restore the values we find in the register.
*/
- rdmsr(MSR_VIA_RNG, lo, hi);
+ rdmsrq(MSR_VIA_RNG, val.q);
- old_lo = lo;
- lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
- lo &= ~VIA_XSTORE_CNT_MASK;
- lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);
- lo |= VIA_RNG_ENABLE;
- lo |= VIA_NOISESRC1;
+ old_lo = val.l;
+ val.l &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
+ val.l &= ~VIA_XSTORE_CNT_MASK;
+ val.l &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);
+ val.l |= VIA_RNG_ENABLE;
+ val.l |= VIA_NOISESRC1;
/* Enable secondary noise source on CPUs where it is present. */
/* Nehemiah stepping 8 and higher */
if ((c->x86_model == 9) && (c->x86_stepping > 7))
- lo |= VIA_NOISESRC2;
+ val.l |= VIA_NOISESRC2;
/* Esther */
if (c->x86_model >= 10)
- lo |= VIA_NOISESRC2;
+ val.l |= VIA_NOISESRC2;
- if (lo != old_lo)
- wrmsr(MSR_VIA_RNG, lo, hi);
+ if (val.l != old_lo)
+ wrmsrq(MSR_VIA_RNG, val.q);
/* perhaps-unnecessary sanity check; remove after testing if
unneeded */
- rdmsr(MSR_VIA_RNG, lo, hi);
- if ((lo & VIA_RNG_ENABLE) == 0) {
+ rdmsrq(MSR_VIA_RNG, val.q);
+ if ((val.l & VIA_RNG_ENABLE) == 0) {
pr_err(PFX "cannot enable VIA C3 RNG, aborting\n");
return -ENODEV;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 24/32] drivers/gpio: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (22 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 23/32] hw_random/via-rng: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 10:33 ` Bartosz Golaszewski
2026-07-01 8:13 ` Linus Walleij
2026-06-29 6:05 ` [PATCH 25/32] drivers/misc: " Juergen Gross
` (8 subsequent siblings)
32 siblings, 2 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, linux-gpio
Cc: Juergen Gross, Linus Walleij, Bartosz Golaszewski
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/gpio/gpio-cs5535.c | 10 +++++-----
include/linux/cs5535.h | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpio-cs5535.c b/drivers/gpio/gpio-cs5535.c
index 5f5373d86397..a97ec7561889 100644
--- a/drivers/gpio/gpio-cs5535.c
+++ b/drivers/gpio/gpio-cs5535.c
@@ -143,17 +143,17 @@ EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
int cs5535_gpio_set_irq(unsigned group, unsigned irq)
{
- uint32_t lo, hi;
+ struct msr val;
if (group > 7 || irq > 15)
return -EINVAL;
- rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
+ rdmsrq(MSR_PIC_ZSEL_HIGH, val.q);
- lo &= ~(0xF << (group * 4));
- lo |= (irq & 0xF) << (group * 4);
+ val.l &= ~(0xF << (group * 4));
+ val.l |= (irq & 0xF) << (group * 4);
- wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
+ wrmsrq(MSR_PIC_ZSEL_HIGH, val.q);
return 0;
}
EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
diff --git a/include/linux/cs5535.h b/include/linux/cs5535.h
index 2be1120174eb..5ec2aca537bb 100644
--- a/include/linux/cs5535.h
+++ b/include/linux/cs5535.h
@@ -49,12 +49,12 @@
static inline int cs5535_pic_unreqz_select_high(unsigned int group,
unsigned int irq)
{
- uint32_t lo, hi;
+ struct msr val;
- rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
- lo &= ~(0xF << (group * 4));
- lo |= (irq & 0xF) << (group * 4);
- wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
+ rdmsrq(MSR_PIC_ZSEL_HIGH, val.q);
+ val.l &= ~(0xF << (group * 4));
+ val.l |= (irq & 0xF) << (group * 4);
+ wrmsrq(MSR_PIC_ZSEL_HIGH, val.q);
return 0;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 24/32] drivers/gpio: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 24/32] drivers/gpio: " Juergen Gross
@ 2026-06-29 10:33 ` Bartosz Golaszewski
2026-07-01 8:13 ` Linus Walleij
1 sibling, 0 replies; 80+ messages in thread
From: Bartosz Golaszewski @ 2026-06-29 10:33 UTC (permalink / raw)
To: Juergen Gross
Cc: linux-kernel, linux-gpio, Linus Walleij, Bartosz Golaszewski
On Mon, 29 Jun 2026 08:05:15 +0200, Juergen Gross <jgross@suse.com> said:
> The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
> removed. Use the related 64-bit variants instead.
>
> Signed-off-by: Juergen Gross <jgross@suse.com>
> ---
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 24/32] drivers/gpio: Stop using 32-bit MSR interfaces
2026-06-29 6:05 ` [PATCH 24/32] drivers/gpio: " Juergen Gross
2026-06-29 10:33 ` Bartosz Golaszewski
@ 2026-07-01 8:13 ` Linus Walleij
2026-07-01 8:32 ` Juergen Gross
1 sibling, 1 reply; 80+ messages in thread
From: Linus Walleij @ 2026-07-01 8:13 UTC (permalink / raw)
To: Juergen Gross; +Cc: linux-kernel, linux-gpio, Bartosz Golaszewski
Hi Jürgen,
On Mon, Jun 29, 2026 at 8:07 AM Juergen Gross <jgross@suse.com> wrote:
> The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
> removed. Use the related 64-bit variants instead.
>
> Signed-off-by: Juergen Gross <jgross@suse.com>
Is this something the subsystem maintainera are supposed to apply
directly on a per-subsystem basis? I was under that impression.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 24/32] drivers/gpio: Stop using 32-bit MSR interfaces
2026-07-01 8:13 ` Linus Walleij
@ 2026-07-01 8:32 ` Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-07-01 8:32 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-kernel, linux-gpio, Bartosz Golaszewski
[-- Attachment #1.1.1: Type: text/plain, Size: 492 bytes --]
On 01.07.26 10:13, Linus Walleij wrote:
> Hi Jürgen,
>
> On Mon, Jun 29, 2026 at 8:07 AM Juergen Gross <jgross@suse.com> wrote:
>
>> The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
>> removed. Use the related 64-bit variants instead.
>>
>> Signed-off-by: Juergen Gross <jgross@suse.com>
>
> Is this something the subsystem maintainera are supposed to apply
> directly on a per-subsystem basis? I was under that impression.
Yes, please do so.
Juergen
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3743 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 495 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 25/32] drivers/misc: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (23 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 24/32] drivers/gpio: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 26/32] x86/msr: Remove wrmsr() Juergen Gross
` (7 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel; +Cc: Juergen Gross, Arnd Bergmann, Greg Kroah-Hartman
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/misc/cs5535-mfgpt.c | 33 ++++++++++++++++-----------------
1 file changed, 16 insertions(+), 17 deletions(-)
diff --git a/drivers/misc/cs5535-mfgpt.c b/drivers/misc/cs5535-mfgpt.c
index cdd0e7bda68d..9abfc44f70f4 100644
--- a/drivers/misc/cs5535-mfgpt.c
+++ b/drivers/misc/cs5535-mfgpt.c
@@ -45,7 +45,8 @@ static struct cs5535_mfgpt_chip {
int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
int event, int enable)
{
- uint32_t msr, mask, value, dummy;
+ uint32_t msr, mask;
+ struct msr val;
int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
if (!timer) {
@@ -82,14 +83,14 @@ int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
return -EIO;
}
- rdmsr(msr, value, dummy);
+ rdmsrq(msr, val.q);
if (enable)
- value |= mask;
+ val.l |= mask;
else
- value &= ~mask;
+ val.l &= ~mask;
- wrmsr(msr, value, dummy);
+ wrmsrq(msr, val.q);
return 0;
}
EXPORT_SYMBOL_GPL(cs5535_mfgpt_toggle_event);
@@ -97,7 +98,7 @@ EXPORT_SYMBOL_GPL(cs5535_mfgpt_toggle_event);
int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
int enable)
{
- uint32_t zsel, lpc, dummy;
+ struct msr zsel, lpc;
int shift;
if (!timer) {
@@ -113,30 +114,31 @@ int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
* IRQ of the 1st. This can only happen if forcing an IRQ, calling this
* with *irq==0 is safe. Currently there _are_ no 2 drivers.
*/
- rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
+ rdmsrq(MSR_PIC_ZSEL_LOW, zsel.q);
shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4;
- if (((zsel >> shift) & 0xF) == 2)
+ if (((zsel.l >> shift) & 0xF) == 2)
return -EIO;
/* Choose IRQ: if none supplied, keep IRQ already set or use default */
if (!*irq)
- *irq = (zsel >> shift) & 0xF;
+ *irq = (zsel.l >> shift) & 0xF;
if (!*irq)
*irq = CONFIG_CS5535_MFGPT_DEFAULT_IRQ;
/* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
if (*irq < 1 || *irq == 2 || *irq > 15)
return -EIO;
- rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy);
- if (lpc & (1 << *irq))
+ rdmsrq(MSR_PIC_IRQM_LPC, lpc.q);
+ if (lpc.l & (1 << *irq))
return -EIO;
/* All chosen and checked - go for it */
if (cs5535_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
return -EIO;
if (enable) {
- zsel = (zsel & ~(0xF << shift)) | (*irq << shift);
- wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
+ zsel.l = (zsel.l & ~(0xF << shift)) | (*irq << shift);
+ zsel.h = lpc.h;
+ wrmsrq(MSR_PIC_ZSEL_LOW, zsel.q);
}
return 0;
@@ -249,11 +251,8 @@ EXPORT_SYMBOL_GPL(cs5535_mfgpt_write);
*/
static void reset_all_timers(void)
{
- uint32_t val, dummy;
-
/* The following undocumented bit resets the MFGPT timers */
- val = 0xFF; dummy = 0;
- wrmsr(MSR_MFGPT_SETUP, val, dummy);
+ wrmsrq(MSR_MFGPT_SETUP, 0xff);
}
/*
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 26/32] x86/msr: Remove wrmsr()
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (24 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 25/32] drivers/misc: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 27/32] x86/hyperv: Stop using 32-bit MSR interfaces Juergen Gross
` (6 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86, virtualization
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list
wrmsr() has no users left. Delete it.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/include/asm/msr.h | 5 -----
arch/x86/include/asm/paravirt.h | 5 -----
2 files changed, 10 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 776a2daa2ba2..badab5762f3a 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -186,11 +186,6 @@ do { \
(void)((high) = (u32)(__val >> 32)); \
} while (0)
-static inline void wrmsr(u32 msr, u32 low, u32 high)
-{
- native_write_msr(msr, (u64)high << 32 | low);
-}
-
#define rdmsrq(msr, val) \
((val) = native_read_msr((msr)))
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 97b082095572..47d4e36d14cb 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -157,11 +157,6 @@ do { \
val2 = _l >> 32; \
} while (0)
-static __always_inline void wrmsr(u32 msr, u32 low, u32 high)
-{
- paravirt_write_msr(msr, (u64)high << 32 | low);
-}
-
#define rdmsrq(msr, val) \
do { \
val = paravirt_read_msr(msr); \
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 27/32] x86/hyperv: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (25 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 26/32] x86/msr: Remove wrmsr() Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 28/32] x86/olpc: " Juergen Gross
` (5 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86, linux-hyperv
Cc: Juergen Gross, K. Y. Srinivasan, Haiyang Zhang, Wei Liu,
Dexuan Cui, Long Li, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin
The 32-bit MSR interface rdmsr() is planned to be removed. Use the
related 64-bit variant instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/hyperv/hv_apic.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/x86/hyperv/hv_apic.c b/arch/x86/hyperv/hv_apic.c
index a8de503def37..95f1782d1e17 100644
--- a/arch/x86/hyperv/hv_apic.c
+++ b/arch/x86/hyperv/hv_apic.c
@@ -60,17 +60,15 @@ void hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set)
static u32 hv_apic_read(u32 reg)
{
- u32 reg_val, hi;
+ struct msr reg_val;
switch (reg) {
case APIC_EOI:
- rdmsr(HV_X64_MSR_EOI, reg_val, hi);
- (void)hi;
- return reg_val;
+ rdmsrq(HV_X64_MSR_EOI, reg_val.q);
+ return reg_val.l;
case APIC_TASKPRI:
- rdmsr(HV_X64_MSR_TPR, reg_val, hi);
- (void)hi;
- return reg_val;
+ rdmsrq(HV_X64_MSR_TPR, reg_val.q);
+ return reg_val.l;
default:
return native_apic_mem_read(reg);
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 28/32] x86/olpc: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (26 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 27/32] x86/hyperv: Stop using 32-bit MSR interfaces Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 29/32] hwmon: " Juergen Gross
` (4 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin
The 32-bit MSR interface rdmsr() is planned to be removed. Use the
related 64-bit variant instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/platform/olpc/olpc-xo1-sci.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/x86/platform/olpc/olpc-xo1-sci.c b/arch/x86/platform/olpc/olpc-xo1-sci.c
index 30751b42d54e..97eb4738d602 100644
--- a/arch/x86/platform/olpc/olpc-xo1-sci.c
+++ b/arch/x86/platform/olpc/olpc-xo1-sci.c
@@ -311,12 +311,13 @@ static int xo1_sci_resume(struct platform_device *pdev)
static int setup_sci_interrupt(struct platform_device *pdev)
{
- u32 lo, hi;
+ u64 msr;
+ u32 lo;
u32 sts;
int r;
- rdmsr(0x51400020, lo, hi);
- sci_irq = (lo >> 20) & 15;
+ rdmsrq(0x51400020, msr);
+ sci_irq = (msr >> 20) & 15;
if (sci_irq) {
dev_info(&pdev->dev, "SCI is mapped to IRQ %d\n", sci_irq);
@@ -324,8 +325,8 @@ static int setup_sci_interrupt(struct platform_device *pdev)
/* Zero means masked */
dev_info(&pdev->dev, "SCI unmapped. Mapping to IRQ 3\n");
sci_irq = 3;
- lo |= 0x00300000;
- wrmsrq(0x51400020, lo);
+ msr |= 0x00300000;
+ wrmsrq(0x51400020, msr);
}
/* Select level triggered in PIC */
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 29/32] hwmon: Stop using 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (27 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 28/32] x86/olpc: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 15:05 ` Guenter Roeck
2026-06-29 6:05 ` [PATCH 30/32] x86/msr: Remove rdmsr() Juergen Gross
` (3 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, linux-hwmon; +Cc: Juergen Gross, Guenter Roeck
The 32-bit MSR interface rdmsr() is planned to be removed. Use the
related 64-bit variant instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/hwmon/hwmon-vid.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c
index 2df4956296ed..dee42c163d92 100644
--- a/drivers/hwmon/hwmon-vid.c
+++ b/drivers/hwmon/hwmon-vid.c
@@ -237,16 +237,17 @@ static struct vrm_model vrm_models[] = {
*/
static u8 get_via_model_d_vrm(void)
{
- unsigned int vid, brand, __maybe_unused dummy;
+ u64 msr;
+ unsigned int vid, brand;
static const char *brands[4] = {
"C7-M", "C7", "Eden", "C7-D"
};
- rdmsr(0x198, dummy, vid);
- vid &= 0xff;
+ rdmsrq(0x198, msr);
+ vid = (msr >> 32) & 0xff;
- rdmsr(0x1154, brand, dummy);
- brand = ((brand >> 4) ^ (brand >> 2)) & 0x03;
+ rdmsrq(0x1154, msr);
+ brand = ((msr >> 4) ^ (msr >> 2)) & 0x03;
if (vid > 0x3f) {
pr_info("Using %d-bit VID table for VIA %s CPU\n",
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 30/32] x86/msr: Remove rdmsr()
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (28 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 29/32] hwmon: " Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 31/32] treewide: convert rdmsrq() from a macro to an inline function Juergen Gross
` (2 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86, virtualization
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list
rdmsr() has no users left. Delete it.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/include/asm/msr.h | 7 -------
arch/x86/include/asm/paravirt.h | 7 -------
2 files changed, 14 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index badab5762f3a..6d7bab33af71 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -179,13 +179,6 @@ static inline u64 native_read_pmc(int counter)
* pointer indirection), this allows gcc to optimize better
*/
-#define rdmsr(msr, low, high) \
-do { \
- u64 __val = native_read_msr((msr)); \
- (void)((low) = (u32)__val); \
- (void)((high) = (u32)(__val >> 32)); \
-} while (0)
-
#define rdmsrq(msr, val) \
((val) = native_read_msr((msr)))
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 47d4e36d14cb..93754aa60d5e 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -150,13 +150,6 @@ static inline int paravirt_write_msr_safe(u32 msr, u64 val)
return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val);
}
-#define rdmsr(msr, val1, val2) \
-do { \
- u64 _l = paravirt_read_msr(msr); \
- val1 = (u32)_l; \
- val2 = _l >> 32; \
-} while (0)
-
#define rdmsrq(msr, val) \
do { \
val = paravirt_read_msr(msr); \
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 31/32] treewide: convert rdmsrq() from a macro to an inline function
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (29 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 30/32] x86/msr: Remove rdmsr() Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:05 ` [PATCH 32/32] x86/msr: Simplify some rdmsrq() use cases Juergen Gross
2026-06-29 6:52 ` [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Arnd Bergmann
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86, linux-perf-users, linux-hyperv, kvm,
virtualization, linux-edac, linux-pci, linux-pm, linux-coco,
linux-acpi, linux-ide, dri-devel, linux-crypto, linux-gpio,
linux-hwmon, linux-mtd, platform-driver-x86, linux-fbdev
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Peter Zijlstra,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui,
Long Li, Sean Christopherson, Paolo Bonzini, Ajay Kaher,
Alexey Makhalov, Broadcom internal kernel review list,
Josh Poimboeuf, Pawan Gupta, Pu Wen, Tony Luck, Reinette Chatre,
Dave Martin, James Morse, Babu Moger, Tony W Wang-oc,
Vitaly Kuznetsov, Andy Lutomirski, Bjorn Helgaas,
Rafael J. Wysocki, Pavel Machek, Kiryl Shutsemau, Rick Edgecombe,
Boris Ostrovsky, Len Brown, Damien Le Moal, Niklas Cassel,
David Airlie, Olivia Mackall, Herbert Xu, Viresh Kumar, Huang Rui,
Mario Limonciello, Perry Yuan, K Prateek Nayak,
Srinivas Pandruvada, Yazen Ghannam, Linus Walleij,
Bartosz Golaszewski, Guenter Roeck, Artem Bityutskiy,
Artem Bityutskiy, Arnd Bergmann, Greg Kroah-Hartman,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, Ashok Raj,
Hans de Goede, Ilpo Järvinen, Rajneesh Bhardwaj, David E Box,
Daniel Lezcano, Zhang Rui, Lukasz Luba, Helge Deller, xen-devel,
linux-geode
Today rdmsrq() is a macro using its second parameter as the target for
storing the read MSR value.
Convert rdmsrq() to an inline function returning the MSR value.
The users have been converted using the following semantic patch:
// Options: --include-headers
virtual patch
virtual report
@@
expression msr, val;
@@
(
- rdmsrq(msr,val)
+ val = rdmsrq(msr)
)
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/coco/sev/core.c | 2 +-
arch/x86/events/amd/brs.c | 4 +--
arch/x86/events/amd/core.c | 4 +--
arch/x86/events/amd/ibs.c | 18 +++++-----
arch/x86/events/amd/lbr.c | 8 ++---
arch/x86/events/amd/power.c | 8 ++---
arch/x86/events/amd/uncore.c | 4 +--
arch/x86/events/core.c | 20 +++++------
arch/x86/events/intel/core.c | 10 +++---
arch/x86/events/intel/cstate.c | 2 +-
arch/x86/events/intel/ds.c | 2 +-
arch/x86/events/intel/knc.c | 6 ++--
arch/x86/events/intel/lbr.c | 14 ++++----
arch/x86/events/intel/p4.c | 6 ++--
arch/x86/events/intel/p6.c | 4 +--
arch/x86/events/intel/pt.c | 12 +++----
arch/x86/events/intel/uncore.c | 2 +-
arch/x86/events/intel/uncore_nhmex.c | 4 +--
arch/x86/events/intel/uncore_snb.c | 2 +-
arch/x86/events/intel/uncore_snbep.c | 6 ++--
arch/x86/events/msr.c | 2 +-
arch/x86/events/perf_event.h | 6 ++--
arch/x86/events/rapl.c | 4 +--
arch/x86/events/zhaoxin/core.c | 6 ++--
arch/x86/hyperv/hv_apic.c | 6 ++--
arch/x86/hyperv/hv_init.c | 26 +++++++-------
arch/x86/hyperv/hv_spinlock.c | 2 +-
arch/x86/include/asm/apic.h | 4 +--
arch/x86/include/asm/debugreg.h | 2 +-
arch/x86/include/asm/fsgsbase.h | 2 +-
arch/x86/include/asm/kvm_host.h | 2 +-
arch/x86/include/asm/msr.h | 15 ++++----
arch/x86/include/asm/paravirt.h | 8 ++---
arch/x86/kernel/apic/apic.c | 14 ++++----
arch/x86/kernel/apic/apic_numachip.c | 6 ++--
arch/x86/kernel/cet.c | 2 +-
arch/x86/kernel/cpu/amd.c | 14 ++++----
arch/x86/kernel/cpu/aperfmperf.c | 8 ++---
arch/x86/kernel/cpu/bugs.c | 12 +++----
arch/x86/kernel/cpu/bus_lock.c | 8 ++---
arch/x86/kernel/cpu/centaur.c | 8 ++---
arch/x86/kernel/cpu/common.c | 12 +++----
arch/x86/kernel/cpu/feat_ctl.c | 4 +--
arch/x86/kernel/cpu/hygon.c | 4 +--
arch/x86/kernel/cpu/intel.c | 6 ++--
arch/x86/kernel/cpu/intel_epb.c | 4 +--
arch/x86/kernel/cpu/mce/amd.c | 4 +--
arch/x86/kernel/cpu/mce/core.c | 8 ++---
arch/x86/kernel/cpu/mce/inject.c | 2 +-
arch/x86/kernel/cpu/mce/intel.c | 18 +++++-----
arch/x86/kernel/cpu/mce/p5.c | 8 ++---
arch/x86/kernel/cpu/mce/winchip.c | 2 +-
arch/x86/kernel/cpu/microcode/intel.c | 2 +-
arch/x86/kernel/cpu/mshyperv.c | 6 ++--
arch/x86/kernel/cpu/mtrr/amd.c | 4 +--
arch/x86/kernel/cpu/mtrr/cleanup.c | 4 +--
arch/x86/kernel/cpu/mtrr/generic.c | 32 ++++++++---------
arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +-
arch/x86/kernel/cpu/resctrl/core.c | 2 +-
arch/x86/kernel/cpu/resctrl/monitor.c | 4 +--
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 +--
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 2 +-
arch/x86/kernel/cpu/topology.c | 2 +-
arch/x86/kernel/cpu/topology_amd.c | 4 +--
arch/x86/kernel/cpu/transmeta.c | 2 +-
arch/x86/kernel/cpu/tsx.c | 10 +++---
arch/x86/kernel/cpu/umwait.c | 2 +-
arch/x86/kernel/cpu/zhaoxin.c | 4 +--
arch/x86/kernel/fpu/core.c | 2 +-
arch/x86/kernel/hpet.c | 2 +-
arch/x86/kernel/kvm.c | 2 +-
arch/x86/kernel/mmconf-fam10h_64.c | 6 ++--
arch/x86/kernel/process.c | 4 +--
arch/x86/kernel/process_64.c | 14 ++++----
arch/x86/kernel/shstk.c | 8 ++---
arch/x86/kernel/traps.c | 4 +--
arch/x86/kernel/tsc.c | 2 +-
arch/x86/kernel/tsc_msr.c | 6 ++--
arch/x86/kernel/tsc_sync.c | 6 ++--
arch/x86/kvm/svm/pmu.c | 4 +--
arch/x86/kvm/svm/svm.c | 4 +--
arch/x86/kvm/vmx/nested.c | 4 +--
arch/x86/kvm/vmx/pmu_intel.c | 8 ++---
arch/x86/kvm/vmx/sgx.c | 6 ++--
arch/x86/kvm/vmx/vmx.c | 36 +++++++++----------
arch/x86/kvm/x86.c | 8 ++---
arch/x86/lib/insn-eval.c | 6 ++--
arch/x86/lib/msr-smp.c | 2 +-
arch/x86/mm/pat/memtype.c | 2 +-
arch/x86/pci/amd_bus.c | 8 ++---
arch/x86/platform/olpc/olpc-xo1-rtc.c | 6 ++--
arch/x86/platform/olpc/olpc-xo1-sci.c | 2 +-
arch/x86/power/cpu.c | 10 +++---
arch/x86/realmode/init.c | 2 +-
arch/x86/virt/hw.c | 8 ++---
arch/x86/virt/svm/sev.c | 18 +++++-----
arch/x86/virt/vmx/tdx/tdx.c | 2 +-
arch/x86/xen/suspend.c | 2 +-
drivers/acpi/processor_perflib.c | 2 +-
drivers/ata/pata_cs5535.c | 4 +--
drivers/ata/pata_cs5536.c | 2 +-
drivers/char/agp/nvidia-agp.c | 6 ++--
drivers/char/hw_random/via-rng.c | 4 +--
drivers/cpufreq/acpi-cpufreq.c | 8 ++---
drivers/cpufreq/amd-pstate.c | 4 +--
drivers/cpufreq/e_powersaver.c | 20 +++++------
drivers/cpufreq/intel_pstate.c | 30 ++++++++--------
drivers/cpufreq/longhaul.c | 12 +++----
drivers/cpufreq/longrun.c | 16 ++++-----
drivers/cpufreq/powernow-k7.c | 10 +++---
drivers/cpufreq/powernow-k8.c | 8 ++---
drivers/cpufreq/speedstep-centrino.c | 4 +--
drivers/cpufreq/speedstep-lib.c | 14 ++++----
drivers/edac/amd64_edac.c | 6 ++--
drivers/gpio/gpio-cs5535.c | 2 +-
drivers/hv/mshv_vtl_main.c | 2 +-
drivers/hwmon/hwmon-vid.c | 4 +--
drivers/idle/intel_idle.c | 26 +++++++-------
drivers/misc/cs5535-mfgpt.c | 6 ++--
drivers/mtd/nand/raw/cs553x_nand.c | 6 ++--
drivers/platform/x86/intel/ifs/load.c | 10 +++---
drivers/platform/x86/intel/ifs/runtest.c | 8 ++---
drivers/platform/x86/intel/pmc/cnp.c | 2 +-
.../intel/speed_select_if/isst_if_mbox_msr.c | 6 ++--
.../intel/speed_select_if/isst_tpmi_core.c | 2 +-
drivers/platform/x86/intel_ips.c | 20 +++++------
drivers/powercap/intel_rapl_msr.c | 2 +-
drivers/thermal/intel/intel_hfi.c | 8 ++---
drivers/thermal/intel/therm_throt.c | 18 +++++-----
drivers/thermal/intel/x86_pkg_temp_thermal.c | 6 ++--
drivers/video/fbdev/geode/display_gx.c | 2 +-
drivers/video/fbdev/geode/gxfb_core.c | 2 +-
drivers/video/fbdev/geode/lxfb_ops.c | 18 +++++-----
drivers/video/fbdev/geode/suspend_gx.c | 8 ++---
drivers/video/fbdev/geode/video_gx.c | 8 ++---
include/linux/cs5535.h | 2 +-
136 files changed, 482 insertions(+), 483 deletions(-)
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index ecd77d3217f3..0a67c71a6ba0 100644
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -2037,7 +2037,7 @@ void __init snp_secure_tsc_init(void)
secrets = (__force struct snp_secrets_page *)mem;
setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
- rdmsrq(MSR_AMD64_GUEST_TSC_FREQ, tsc_freq_mhz);
+ tsc_freq_mhz = rdmsrq(MSR_AMD64_GUEST_TSC_FREQ);
/* Extract the GUEST TSC MHZ from BIT[17:0], rest is reserved space */
tsc_freq_mhz &= GENMASK_ULL(17, 0);
diff --git a/arch/x86/events/amd/brs.c b/arch/x86/events/amd/brs.c
index 06f35a6b58a5..35c56bcffd92 100644
--- a/arch/x86/events/amd/brs.c
+++ b/arch/x86/events/amd/brs.c
@@ -325,7 +325,7 @@ void amd_brs_drain(void)
u32 brs_idx = tos - i;
u64 from, to;
- rdmsrq(brs_to(brs_idx), to);
+ to = rdmsrq(brs_to(brs_idx));
/* Entry does not belong to us (as marked by kernel) */
if (to == BRS_POISON)
@@ -341,7 +341,7 @@ void amd_brs_drain(void)
if (!amd_brs_match_plm(event, to))
continue;
- rdmsrq(brs_from(brs_idx), from);
+ from = rdmsrq(brs_from(brs_idx));
perf_clear_branch_entry_bitfields(br+nr);
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 6569048a8c1c..ee08ed4f41ec 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -663,7 +663,7 @@ static inline u64 amd_pmu_get_global_status(void)
u64 status;
/* PerfCntrGlobalStatus is read-only */
- rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status);
+ status = rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS);
return status;
}
@@ -683,7 +683,7 @@ static bool amd_pmu_test_overflow_topbit(int idx)
{
u64 counter;
- rdmsrq(x86_pmu_event_addr(idx), counter);
+ counter = rdmsrq(x86_pmu_event_addr(idx));
return !(counter & BIT_ULL(x86_pmu.cntval_bits - 1));
}
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 3531f9c23b8c..17eab32164df 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -505,7 +505,7 @@ perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
* prev count manually on overflow.
*/
while (!perf_event_try_update(event, count, 64)) {
- rdmsrq(event->hw.config_base, *config);
+ *config = rdmsrq(event->hw.config_base);
count = perf_ibs->get_count(*config);
}
}
@@ -610,7 +610,7 @@ static void perf_ibs_stop(struct perf_event *event, int flags)
if (!stopping && (hwc->state & PERF_HES_UPTODATE))
return;
- rdmsrq(hwc->config_base, config);
+ config = rdmsrq(hwc->config_base);
if (stopping) {
/*
@@ -1437,7 +1437,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
hwc = &event->hw;
msr = hwc->config_base;
buf = ibs_data.regs;
- rdmsrq(msr, *buf);
+ *buf = rdmsrq(msr);
if (!(*buf++ & perf_ibs->valid_mask))
goto fail;
@@ -1455,7 +1455,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
offset_max = perf_ibs_get_offset_max(perf_ibs, event, check_rip);
do {
- rdmsrq(msr + offset, *buf++);
+ *buf++ = rdmsrq(msr + offset);
size++;
offset = find_next_bit(perf_ibs->offset_mask,
perf_ibs->offset_max,
@@ -1497,17 +1497,17 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
if (event->attr.sample_type & PERF_SAMPLE_RAW) {
if (perf_ibs == &perf_ibs_op) {
if (ibs_caps & IBS_CAPS_BRNTRGT) {
- rdmsrq(MSR_AMD64_IBSBRTARGET, *buf++);
+ *buf++ = rdmsrq(MSR_AMD64_IBSBRTARGET);
br_target_idx = size;
size++;
}
if (ibs_caps & IBS_CAPS_OPDATA4) {
- rdmsrq(MSR_AMD64_IBSOPDATA4, *buf++);
+ *buf++ = rdmsrq(MSR_AMD64_IBSOPDATA4);
size++;
}
}
if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {
- rdmsrq(MSR_AMD64_ICIBSEXTDCTL, *buf++);
+ *buf++ = rdmsrq(MSR_AMD64_ICIBSEXTDCTL);
size++;
}
}
@@ -1768,7 +1768,7 @@ static inline int ibs_eilvt_valid(void)
preempt_disable();
- rdmsrq(MSR_AMD64_IBSCTL, val);
+ val = rdmsrq(MSR_AMD64_IBSCTL);
offset = val & IBSCTL_LVT_OFFSET_MASK;
if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
@@ -1883,7 +1883,7 @@ static inline int get_ibs_lvt_offset(void)
{
u64 val;
- rdmsrq(MSR_AMD64_IBSCTL, val);
+ val = rdmsrq(MSR_AMD64_IBSCTL);
if (!(val & IBSCTL_LVT_OFFSET_VALID))
return -EINVAL;
diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c
index 5b437dc8e4ce..0b6aec1e5bf1 100644
--- a/arch/x86/events/amd/lbr.c
+++ b/arch/x86/events/amd/lbr.c
@@ -76,7 +76,7 @@ static __always_inline u64 amd_pmu_lbr_get_from(unsigned int idx)
{
u64 val;
- rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2, val);
+ val = rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2);
return val;
}
@@ -85,7 +85,7 @@ static __always_inline u64 amd_pmu_lbr_get_to(unsigned int idx)
{
u64 val;
- rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val);
+ val = rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1);
return val;
}
@@ -403,11 +403,11 @@ void amd_pmu_lbr_enable_all(void)
}
if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
- rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
+ dbg_ctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
}
- rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
+ dbg_extn_cfg = rdmsrq(MSR_AMD_DBG_EXTN_CFG);
wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN);
}
diff --git a/arch/x86/events/amd/power.c b/arch/x86/events/amd/power.c
index 744dffa42dee..553a6d0c8a14 100644
--- a/arch/x86/events/amd/power.c
+++ b/arch/x86/events/amd/power.c
@@ -52,8 +52,8 @@ static void event_update(struct perf_event *event)
prev_pwr_acc = hwc->pwr_acc;
prev_ptsc = hwc->ptsc;
- rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR, new_pwr_acc);
- rdmsrq(MSR_F15H_PTSC, new_ptsc);
+ new_pwr_acc = rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR);
+ new_ptsc = rdmsrq(MSR_F15H_PTSC);
/*
* Calculate the CU power consumption over a time period, the unit of
@@ -79,8 +79,8 @@ static void __pmu_event_start(struct perf_event *event)
event->hw.state = 0;
- rdmsrq(MSR_F15H_PTSC, event->hw.ptsc);
- rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR, event->hw.pwr_acc);
+ event->hw.ptsc = rdmsrq(MSR_F15H_PTSC);
+ event->hw.pwr_acc = rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR);
}
static void pmu_event_start(struct perf_event *event, int mode)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index dbc00b6dd69e..eca29ba9a795 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -151,7 +151,7 @@ static void amd_uncore_read(struct perf_event *event)
* read counts directly from the corresponding PERF_CTR.
*/
if (hwc->event_base_rdpmc < 0)
- rdmsrq(hwc->event_base, new);
+ new = rdmsrq(hwc->event_base);
else
new = rdpmc(hwc->event_base_rdpmc);
@@ -967,7 +967,7 @@ static void amd_uncore_umc_read(struct perf_event *event)
* UMC counters do not have RDPMC assignments. Read counts directly
* from the corresponding PERF_CTR.
*/
- rdmsrq(hwc->event_base, new);
+ new = rdmsrq(hwc->event_base);
/*
* Unlike the other uncore counters, UMC counters saturate and set the
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d1af33d96d0a..b97f4cb1ca5f 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -713,7 +713,7 @@ void x86_pmu_disable_all(void)
if (!test_bit(idx, cpuc->active_mask))
continue;
- rdmsrq(x86_pmu_config_addr(idx), val);
+ val = rdmsrq(x86_pmu_config_addr(idx));
if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
continue;
val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
@@ -1578,10 +1578,10 @@ void perf_event_print_debug(void)
return;
if (x86_pmu.version >= 2) {
- rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
- rdmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
- rdmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
+ ctrl = rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL);
+ status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
+ overflow = rdmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL);
+ fixed = rdmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL);
pr_info("\n");
pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
@@ -1589,19 +1589,19 @@ void perf_event_print_debug(void)
pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
if (pebs_constraints) {
- rdmsrq(MSR_IA32_PEBS_ENABLE, pebs);
+ pebs = rdmsrq(MSR_IA32_PEBS_ENABLE);
pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
}
if (x86_pmu.lbr_nr) {
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
}
}
pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
for_each_set_bit(idx, cntr_mask, X86_PMC_IDX_MAX) {
- rdmsrq(x86_pmu_config_addr(idx), pmc_ctrl);
- rdmsrq(x86_pmu_event_addr(idx), pmc_count);
+ pmc_ctrl = rdmsrq(x86_pmu_config_addr(idx));
+ pmc_count = rdmsrq(x86_pmu_event_addr(idx));
prev_left = per_cpu(pmc_prev_left[idx], cpu);
@@ -1615,7 +1615,7 @@ void perf_event_print_debug(void)
for_each_set_bit(idx, fixed_cntr_mask, X86_PMC_IDX_MAX) {
if (fixed_counter_disabled(idx, cpuc->pmu))
continue;
- rdmsrq(x86_pmu_fixed_ctr_addr(idx), pmc_count);
+ pmc_count = rdmsrq(x86_pmu_fixed_ctr_addr(idx));
pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
cpu, idx, pmc_count);
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2b35483e2b70..c6fc2d9079d9 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2965,7 +2965,7 @@ static inline u64 intel_pmu_get_status(void)
{
u64 status;
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
+ status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
return status;
}
@@ -3494,7 +3494,7 @@ static void intel_pmu_enable_event_ext(struct perf_event *event)
else
new.thresh = ARCH_PEBS_THRESH_SINGLE;
- rdmsrq(MSR_IA32_PEBS_INDEX, old.whole);
+ old.whole = rdmsrq(MSR_IA32_PEBS_INDEX);
if (new.thresh != old.thresh || !old.en) {
if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) {
/*
@@ -6239,7 +6239,7 @@ static void update_pmu_cap(struct pmu *pmu)
if (!intel_pmu_broken_perf_cap()) {
/* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities);
+ hybrid(pmu, intel_cap).capabilities = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
}
}
@@ -6387,7 +6387,7 @@ static void intel_pmu_cpu_starting(int cpu)
if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
union perf_capabilities perf_cap;
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
+ perf_cap.capabilities = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
if (!perf_cap.perf_metrics) {
x86_pmu.intel_cap.perf_metrics = 0;
x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
@@ -7931,7 +7931,7 @@ __init int intel_pmu_init(void)
if (boot_cpu_has(X86_FEATURE_PDCM)) {
u64 capabilities;
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities);
+ capabilities = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
x86_pmu.intel_cap.capabilities = capabilities;
}
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index f3d5ee07f8f2..69eb6cf51d3b 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -324,7 +324,7 @@ static inline u64 cstate_pmu_read_counter(struct perf_event *event)
{
u64 val;
- rdmsrq(event->hw.event_base, val);
+ val = rdmsrq(event->hw.event_base);
return val;
}
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 91a093d8cf2e..0b3f2bf101f2 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -3244,7 +3244,7 @@ static void intel_pmu_drain_arch_pebs(struct pt_regs *iregs,
void *base, *at, *top;
u64 mask;
- rdmsrq(MSR_IA32_PEBS_INDEX, index.whole);
+ index.whole = rdmsrq(MSR_IA32_PEBS_INDEX);
if (unlikely(!index.wr)) {
intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX);
diff --git a/arch/x86/events/intel/knc.c b/arch/x86/events/intel/knc.c
index e887adc108ac..c4f81215f758 100644
--- a/arch/x86/events/intel/knc.c
+++ b/arch/x86/events/intel/knc.c
@@ -160,7 +160,7 @@ static void knc_pmu_disable_all(void)
{
u64 val;
- rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
+ val = rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL);
val &= ~(KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1);
wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
}
@@ -169,7 +169,7 @@ static void knc_pmu_enable_all(int added)
{
u64 val;
- rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
+ val = rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL);
val |= (KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1);
wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
}
@@ -201,7 +201,7 @@ static inline u64 knc_pmu_get_status(void)
{
u64 status;
- rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_STATUS, status);
+ status = rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_STATUS);
return status;
}
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index cae2e02fe6cc..e65a4ed121d7 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -141,7 +141,7 @@ static void __intel_pmu_lbr_enable(bool pmi)
if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && !pmi && cpuc->lbr_sel)
wrmsrq(MSR_LBR_SELECT, lbr_select);
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
orig_debugctl = debugctl;
if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
@@ -211,7 +211,7 @@ static inline u64 intel_pmu_lbr_tos(void)
{
u64 tos;
- rdmsrq(x86_pmu.lbr_tos, tos);
+ tos = rdmsrq(x86_pmu.lbr_tos);
return tos;
}
@@ -304,7 +304,7 @@ static __always_inline u64 rdlbr_from(unsigned int idx, struct lbr_entry *lbr)
if (lbr)
return lbr->from;
- rdmsrq(x86_pmu.lbr_from + idx, val);
+ val = rdmsrq(x86_pmu.lbr_from + idx);
return lbr_from_signext_quirk_rd(val);
}
@@ -316,7 +316,7 @@ static __always_inline u64 rdlbr_to(unsigned int idx, struct lbr_entry *lbr)
if (lbr)
return lbr->to;
- rdmsrq(x86_pmu.lbr_to + idx, val);
+ val = rdmsrq(x86_pmu.lbr_to + idx);
return val;
}
@@ -328,7 +328,7 @@ static __always_inline u64 rdlbr_info(unsigned int idx, struct lbr_entry *lbr)
if (lbr)
return lbr->info;
- rdmsrq(x86_pmu.lbr_info + idx, val);
+ val = rdmsrq(x86_pmu.lbr_info + idx);
return val;
}
@@ -477,7 +477,7 @@ void intel_pmu_lbr_save(void *ctx)
task_ctx->tos = tos;
if (cpuc->lbr_select)
- rdmsrq(MSR_LBR_SELECT, task_ctx->lbr_sel);
+ task_ctx->lbr_sel = rdmsrq(MSR_LBR_SELECT);
}
static void intel_pmu_arch_lbr_save(void *ctx)
@@ -754,7 +754,7 @@ void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
u64 lbr;
} msr_lastbranch;
- rdmsrq(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
+ msr_lastbranch.lbr = rdmsrq(x86_pmu.lbr_from + lbr_idx);
perf_clear_branch_entry_bitfields(br);
diff --git a/arch/x86/events/intel/p4.c b/arch/x86/events/intel/p4.c
index 5368dc31787c..e675e85682f1 100644
--- a/arch/x86/events/intel/p4.c
+++ b/arch/x86/events/intel/p4.c
@@ -860,7 +860,7 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
u64 v;
/* an official way for overflow indication */
- rdmsrq(hwc->config_base, v);
+ v = rdmsrq(hwc->config_base);
if (v & P4_CCCR_OVF) {
wrmsrq(hwc->config_base, v & ~P4_CCCR_OVF);
return 1;
@@ -873,7 +873,7 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
* the counter has reached zero value and continued counting before
* real NMI signal was received:
*/
- rdmsrq(hwc->event_base, v);
+ v = rdmsrq(hwc->event_base);
if (!(v & ARCH_P4_UNFLAGGED_BIT))
return 1;
@@ -1373,7 +1373,7 @@ __init int p4_pmu_init(void)
/* If we get stripped -- indexing fails */
BUILD_BUG_ON(ARCH_P4_MAX_CCCR > INTEL_PMC_MAX_GENERIC);
- rdmsrq(MSR_IA32_MISC_ENABLE, misc);
+ misc = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(misc & MSR_IA32_MISC_ENABLE_EMON)) {
pr_cont("unsupported Netburst CPU model %d ",
boot_cpu_data.x86_model);
diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c
index fb991e0ac614..4268b576b5d8 100644
--- a/arch/x86/events/intel/p6.c
+++ b/arch/x86/events/intel/p6.c
@@ -143,7 +143,7 @@ static void p6_pmu_disable_all(void)
u64 val;
/* p6 only has one enable register */
- rdmsrq(MSR_P6_EVNTSEL0, val);
+ val = rdmsrq(MSR_P6_EVNTSEL0);
val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
wrmsrq(MSR_P6_EVNTSEL0, val);
}
@@ -153,7 +153,7 @@ static void p6_pmu_enable_all(int added)
unsigned long val;
/* p6 only has one enable register */
- rdmsrq(MSR_P6_EVNTSEL0, val);
+ val = rdmsrq(MSR_P6_EVNTSEL0);
val |= ARCH_PERFMON_EVENTSEL_ENABLE;
wrmsrq(MSR_P6_EVNTSEL0, val);
}
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index b5726b50e77d..c8f23e68a4bb 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -196,7 +196,7 @@ static int __init pt_pmu_hw_init(void)
int ret;
long i;
- rdmsrq(MSR_PLATFORM_INFO, reg);
+ reg = rdmsrq(MSR_PLATFORM_INFO);
pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8;
/*
@@ -232,7 +232,7 @@ static int __init pt_pmu_hw_init(void)
* "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
* post-VMXON.
*/
- rdmsrq(MSR_IA32_VMX_MISC, reg);
+ reg = rdmsrq(MSR_IA32_VMX_MISC);
if (reg & BIT(14))
pt_pmu.vmx = true;
}
@@ -928,7 +928,7 @@ static void pt_handle_status(struct pt *pt)
int advance = 0;
u64 status;
- rdmsrq(MSR_IA32_RTIT_STATUS, status);
+ status = rdmsrq(MSR_IA32_RTIT_STATUS);
if (status & RTIT_STATUS_ERROR) {
pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n");
@@ -987,12 +987,12 @@ static void pt_read_offset(struct pt_buffer *buf)
struct topa_page *tp;
if (!buf->single) {
- rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE, pt->output_base);
+ pt->output_base = rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE);
tp = phys_to_virt(pt->output_base);
buf->cur = &tp->topa;
}
- rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask);
+ pt->output_mask = rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK);
/* offset within current output region */
buf->output_off = pt->output_mask >> 32;
/* index of current output region within this table */
@@ -1612,7 +1612,7 @@ static void pt_event_start(struct perf_event *event, int mode)
* PMI might have just cleared these, so resume_allowed
* must be checked again also.
*/
- rdmsrq(MSR_IA32_RTIT_STATUS, status);
+ status = rdmsrq(MSR_IA32_RTIT_STATUS);
if (!(status & (RTIT_STATUS_TRIGGEREN |
RTIT_STATUS_ERROR |
RTIT_STATUS_STOPPED)) &&
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index 7857959c6e82..0067bd35aa7f 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -171,7 +171,7 @@ u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *eve
{
u64 count;
- rdmsrq(event->hw.event_base, count);
+ count = rdmsrq(event->hw.event_base);
return count;
}
diff --git a/arch/x86/events/intel/uncore_nhmex.c b/arch/x86/events/intel/uncore_nhmex.c
index 8962e7cb21e3..c06ffcdce6e0 100644
--- a/arch/x86/events/intel/uncore_nhmex.c
+++ b/arch/x86/events/intel/uncore_nhmex.c
@@ -215,7 +215,7 @@ static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box)
u64 config;
if (msr) {
- rdmsrq(msr, config);
+ config = rdmsrq(msr);
config &= ~((1ULL << uncore_num_counters(box)) - 1);
/* WBox has a fixed counter */
if (uncore_msr_fixed_ctl(box))
@@ -230,7 +230,7 @@ static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box)
u64 config;
if (msr) {
- rdmsrq(msr, config);
+ config = rdmsrq(msr);
config |= (1ULL << uncore_num_counters(box)) - 1;
/* WBox has a fixed counter */
if (uncore_msr_fixed_ctl(box))
diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index edddd4f9ab5f..b095b0fdeb3a 100644
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -529,7 +529,7 @@ static int icl_get_cbox_num(void)
{
u64 num_boxes;
- rdmsrq(ICL_UNC_CBO_CONFIG, num_boxes);
+ num_boxes = rdmsrq(ICL_UNC_CBO_CONFIG);
return num_boxes & ICL_UNC_NUM_CBO_MASK;
}
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 334dc384b5b9..5c2c4199eb74 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -642,7 +642,7 @@ static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
msr = uncore_msr_box_ctl(box);
if (msr) {
- rdmsrq(msr, config);
+ config = rdmsrq(msr);
config |= SNBEP_PMON_BOX_CTL_FRZ;
wrmsrq(msr, config);
}
@@ -655,7 +655,7 @@ static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
msr = uncore_msr_box_ctl(box);
if (msr) {
- rdmsrq(msr, config);
+ config = rdmsrq(msr);
config &= ~SNBEP_PMON_BOX_CTL_FRZ;
wrmsrq(msr, config);
}
@@ -6357,7 +6357,7 @@ void spr_uncore_cpu_init(void)
* of UNCORE_SPR_CHA) is incorrect on some SPR variants because of a
* firmware bug. Using the value from SPR_MSR_UNC_CBO_CONFIG to replace it.
*/
- rdmsrq(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
+ num_cbo = rdmsrq(SPR_MSR_UNC_CBO_CONFIG);
/*
* The MSR doesn't work on the EMR XCC, but the firmware bug doesn't impact
* the EMR XCC. Don't let the value from the MSR replace the existing value.
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 76d6418c5055..0e59781549ca 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -158,7 +158,7 @@ static inline u64 msr_read_counter(struct perf_event *event)
u64 now;
if (event->hw.event_base)
- rdmsrq(event->hw.event_base, now);
+ now = rdmsrq(event->hw.event_base);
else
now = rdtsc_ordered();
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index eae24bb35dc1..a4b1cfccedd1 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1481,11 +1481,11 @@ static __always_inline void __amd_pmu_lbr_disable(void)
{
u64 dbg_ctl, dbg_extn_cfg;
- rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
+ dbg_extn_cfg = rdmsrq(MSR_AMD_DBG_EXTN_CFG);
wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);
if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
- rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
+ dbg_ctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
}
}
@@ -1639,7 +1639,7 @@ static __always_inline void __intel_pmu_lbr_disable(void)
{
u64 debugctl;
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
}
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 8ed03c32f560..180cc18282ca 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -193,7 +193,7 @@ static inline unsigned int get_rapl_pmu_idx(int cpu, int scope)
static inline u64 rapl_read_counter(struct perf_event *event)
{
u64 raw;
- rdmsrq(event->hw.event_base, raw);
+ raw = rdmsrq(event->hw.event_base);
return raw;
}
@@ -222,7 +222,7 @@ static u64 rapl_event_update(struct perf_event *event)
prev_raw_count = local64_read(&hwc->prev_count);
do {
- rdmsrq(event->hw.event_base, new_raw_count);
+ new_raw_count = rdmsrq(event->hw.event_base);
} while (!local64_try_cmpxchg(&hwc->prev_count,
&prev_raw_count, new_raw_count));
diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index e506f677db57..1980e5995e27 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -268,7 +268,7 @@ static inline u64 zhaoxin_pmu_get_status(void)
{
u64 status;
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
+ status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
return status;
}
@@ -295,7 +295,7 @@ static void zhaoxin_pmu_disable_fixed(struct hw_perf_event *hwc)
mask = 0xfULL << (idx * 4);
- rdmsrq(hwc->config_base, ctrl_val);
+ ctrl_val = rdmsrq(hwc->config_base);
ctrl_val &= ~mask;
wrmsrq(hwc->config_base, ctrl_val);
}
@@ -331,7 +331,7 @@ static void zhaoxin_pmu_enable_fixed(struct hw_perf_event *hwc)
bits <<= (idx * 4);
mask = 0xfULL << (idx * 4);
- rdmsrq(hwc->config_base, ctrl_val);
+ ctrl_val = rdmsrq(hwc->config_base);
ctrl_val &= ~mask;
ctrl_val |= bits;
wrmsrq(hwc->config_base, ctrl_val);
diff --git a/arch/x86/hyperv/hv_apic.c b/arch/x86/hyperv/hv_apic.c
index 95f1782d1e17..4e30f9a11bc4 100644
--- a/arch/x86/hyperv/hv_apic.c
+++ b/arch/x86/hyperv/hv_apic.c
@@ -38,7 +38,7 @@ static u64 hv_apic_icr_read(void)
{
u64 reg_val;
- rdmsrq(HV_X64_MSR_ICR, reg_val);
+ reg_val = rdmsrq(HV_X64_MSR_ICR);
return reg_val;
}
@@ -64,10 +64,10 @@ static u32 hv_apic_read(u32 reg)
switch (reg) {
case APIC_EOI:
- rdmsrq(HV_X64_MSR_EOI, reg_val.q);
+ reg_val.q = rdmsrq(HV_X64_MSR_EOI);
return reg_val.l;
case APIC_TASKPRI:
- rdmsrq(HV_X64_MSR_TPR, reg_val.q);
+ reg_val.q = rdmsrq(HV_X64_MSR_TPR);
return reg_val.l;
default:
diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
index 55a8b6de2865..bc8f91114868 100644
--- a/arch/x86/hyperv/hv_init.c
+++ b/arch/x86/hyperv/hv_init.c
@@ -101,7 +101,7 @@ static int hyperv_init_ghcb(void)
* returned by MSR_AMD64_SEV_ES_GHCB is above shared
* memory boundary and map it here.
*/
- rdmsrq(MSR_AMD64_SEV_ES_GHCB, ghcb_gpa);
+ ghcb_gpa = rdmsrq(MSR_AMD64_SEV_ES_GHCB);
/* Mask out vTOM bit and map as decrypted */
ghcb_gpa &= ~ms_hyperv.shared_gpa_boundary;
@@ -134,7 +134,7 @@ static int hv_cpu_init(unsigned int cpu)
* For root partition we get the hypervisor provided VP assist
* page, instead of allocating a new page.
*/
- rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64);
+ msr.as_uint64 = rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE);
*hvp = memremap(msr.pfn << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT,
PAGE_SIZE, MEMREMAP_WB);
} else {
@@ -183,7 +183,7 @@ static void hv_reenlightenment_notify(struct work_struct *dummy)
{
struct hv_tsc_emulation_status emu_status;
- rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status);
+ *(u64 *)&emu_status = rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS);
/* Don't issue the callback if TSC accesses are not emulated */
if (hv_reenlightenment_cb && emu_status.inprogress)
@@ -196,11 +196,11 @@ void hyperv_stop_tsc_emulation(void)
u64 freq;
struct hv_tsc_emulation_status emu_status;
- rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status);
+ *(u64 *)&emu_status = rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS);
emu_status.inprogress = 0;
wrmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status);
- rdmsrq(HV_X64_MSR_TSC_FREQUENCY, freq);
+ freq = rdmsrq(HV_X64_MSR_TSC_FREQUENCY);
tsc_khz = div64_u64(freq, 1000);
}
EXPORT_SYMBOL_GPL(hyperv_stop_tsc_emulation);
@@ -260,7 +260,7 @@ void clear_hv_tscchange_cb(void)
if (!hv_reenlightenment_available())
return;
- rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl);
+ *(u64 *)&re_ctrl = rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL);
re_ctrl.enabled = 0;
wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl);
@@ -297,7 +297,7 @@ static int hv_cpu_die(unsigned int cpu)
*/
memunmap(hv_vp_assist_page[cpu]);
hv_vp_assist_page[cpu] = NULL;
- rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64);
+ msr.as_uint64 = rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE);
msr.enable = 0;
}
wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64);
@@ -306,7 +306,7 @@ static int hv_cpu_die(unsigned int cpu)
if (hv_reenlightenment_cb == NULL)
return 0;
- rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl));
+ *((u64 *)&re_ctrl) = rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL);
if (re_ctrl.target_vp == hv_vp_index[cpu]) {
/*
* Reassign reenlightenment notifications to some other online
@@ -377,7 +377,7 @@ static int hv_suspend(void *data)
hv_set_hypercall_pg(NULL);
/* Disable the hypercall page in the hypervisor */
- rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
+ hypercall_msr.as_uint64 = rdmsrq(HV_X64_MSR_HYPERCALL);
hypercall_msr.enable = 0;
wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
@@ -394,7 +394,7 @@ static void hv_resume(void *data)
WARN_ON(ret);
/* Re-enable the hypercall page */
- rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
+ hypercall_msr.as_uint64 = rdmsrq(HV_X64_MSR_HYPERCALL);
hypercall_msr.enable = 1;
hypercall_msr.guest_physical_address =
vmalloc_to_pfn(hv_hypercall_pg_saved);
@@ -529,7 +529,7 @@ void __init hyperv_init(void)
if (hv_hypercall_pg == NULL)
goto clean_guest_os_id;
- rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
+ hypercall_msr.as_uint64 = rdmsrq(HV_X64_MSR_HYPERCALL);
hypercall_msr.enable = 1;
if (hv_root_partition()) {
@@ -671,7 +671,7 @@ void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die)
return;
panic_reported = true;
- rdmsrq(HV_X64_MSR_GUEST_OS_ID, guest_id);
+ guest_id = rdmsrq(HV_X64_MSR_GUEST_OS_ID);
wrmsrq(HV_X64_MSR_CRASH_P0, err);
wrmsrq(HV_X64_MSR_CRASH_P1, guest_id);
@@ -705,7 +705,7 @@ bool hv_is_hyperv_initialized(void)
* that the hypercall page is setup
*/
hypercall_msr.as_uint64 = 0;
- rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
+ hypercall_msr.as_uint64 = rdmsrq(HV_X64_MSR_HYPERCALL);
return hypercall_msr.enable;
}
diff --git a/arch/x86/hyperv/hv_spinlock.c b/arch/x86/hyperv/hv_spinlock.c
index 210b494e4de0..29dad837f459 100644
--- a/arch/x86/hyperv/hv_spinlock.c
+++ b/arch/x86/hyperv/hv_spinlock.c
@@ -50,7 +50,7 @@ static void hv_qlock_wait(u8 *byte, u8 val)
if (READ_ONCE(*byte) == val) {
unsigned long msr_val;
- rdmsrq(HV_X64_MSR_GUEST_IDLE, msr_val);
+ msr_val = rdmsrq(HV_X64_MSR_GUEST_IDLE);
(void)msr_val;
}
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 9cd493d467d4..e028140fac49 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -220,7 +220,7 @@ static inline u32 native_apic_msr_read(u32 reg)
if (reg == APIC_DFR)
return -1;
- rdmsrq(APIC_BASE_MSR + (reg >> 4), msr);
+ msr = rdmsrq(APIC_BASE_MSR + (reg >> 4));
return (u32)msr;
}
@@ -233,7 +233,7 @@ static inline u64 native_x2apic_icr_read(void)
{
unsigned long val;
- rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), val);
+ val = rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4));
return val;
}
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index a2c1f2d24b64..426d48beef81 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -180,7 +180,7 @@ static inline unsigned long get_debugctlmsr(void)
if (boot_cpu_data.x86 < 6)
return 0;
#endif
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
+ debugctlmsr = rdmsrq(MSR_IA32_DEBUGCTLMSR);
return debugctlmsr;
}
diff --git a/arch/x86/include/asm/fsgsbase.h b/arch/x86/include/asm/fsgsbase.h
index 70ff4ef457b1..9de49d732e9e 100644
--- a/arch/x86/include/asm/fsgsbase.h
+++ b/arch/x86/include/asm/fsgsbase.h
@@ -60,7 +60,7 @@ static inline unsigned long x86_fsbase_read_cpu(void)
if (boot_cpu_has(X86_FEATURE_FSGSBASE))
fsbase = rdfsbase();
else
- rdmsrq(MSR_FS_BASE, fsbase);
+ fsbase = rdmsrq(MSR_FS_BASE);
return fsbase;
}
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 5f6c1ce9673b..e9b4ad535643 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -2417,7 +2417,7 @@ static inline unsigned long read_msr(unsigned long msr)
{
u64 value;
- rdmsrq(msr, value);
+ value = rdmsrq(msr);
return value;
}
#endif
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 6d7bab33af71..95761803c2e6 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -173,14 +173,13 @@ static inline u64 native_read_pmc(int counter)
#include <asm/paravirt.h>
#else
#include <linux/errno.h>
-/*
- * Access to machine-specific registers (available on 586 and better only)
- * Note: the rd* operations modify the parameters directly (without using
- * pointer indirection), this allows gcc to optimize better
- */
-#define rdmsrq(msr, val) \
- ((val) = native_read_msr((msr)))
+/* Access to machine-specific registers (available on 586 and better only) */
+
+static __always_inline u64 rdmsrq(u32 msr)
+{
+ return native_read_msr(msr);
+}
static inline void wrmsrq(u32 msr, u64 val)
{
@@ -237,7 +236,7 @@ int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
#else /* CONFIG_SMP */
static inline int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
{
- rdmsrq(msr_no, *q);
+ *q = rdmsrq(msr_no);
return 0;
}
static inline int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 93754aa60d5e..19442bc3af37 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -150,10 +150,10 @@ static inline int paravirt_write_msr_safe(u32 msr, u64 val)
return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val);
}
-#define rdmsrq(msr, val) \
-do { \
- val = paravirt_read_msr(msr); \
-} while (0)
+static __always_inline u64 rdmsrq(u32 msr)
+{
+ return paravirt_read_msr(msr);
+}
static inline void wrmsrq(u32 msr, u64 val)
{
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 90025451ace2..7a6c77e6a44e 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1193,7 +1193,7 @@ void disable_local_APIC(void)
if (enabled_via_apicbase) {
struct msr val;
- rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.q = rdmsrq(MSR_IA32_APICBASE);
val.l &= ~MSR_IA32_APICBASE_ENABLE;
wrmsrq(MSR_IA32_APICBASE, val.q);
}
@@ -1710,7 +1710,7 @@ static bool x2apic_hw_locked(void)
x86_arch_cap_msr = x86_read_arch_cap_msr();
if (x86_arch_cap_msr & ARCH_CAP_XAPIC_DISABLE) {
- rdmsrq(MSR_IA32_XAPIC_DISABLE_STATUS, msr);
+ msr = rdmsrq(MSR_IA32_XAPIC_DISABLE_STATUS);
return (msr & LEGACY_XAPIC_DISABLED);
}
return false;
@@ -1723,7 +1723,7 @@ static void __x2apic_disable(void)
if (!boot_cpu_has(X86_FEATURE_APIC))
return;
- rdmsrq(MSR_IA32_APICBASE, msr);
+ msr = rdmsrq(MSR_IA32_APICBASE);
if (!(msr & X2APIC_ENABLE))
return;
/* Disable xapic and x2apic first and then reenable xapic mode */
@@ -1736,7 +1736,7 @@ static void __x2apic_enable(void)
{
u64 msr;
- rdmsrq(MSR_IA32_APICBASE, msr);
+ msr = rdmsrq(MSR_IA32_APICBASE);
if (msr & X2APIC_ENABLE)
return;
wrmsrq(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
@@ -1976,7 +1976,7 @@ static bool __init apic_verify(unsigned long addr)
/* The BIOS may have set up the APIC at some other address */
if (boot_cpu_data.x86 >= 6) {
- rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.q = rdmsrq(MSR_IA32_APICBASE);
if (val.l & MSR_IA32_APICBASE_ENABLE)
addr = val.l & MSR_IA32_APICBASE_BASE;
}
@@ -1999,7 +1999,7 @@ bool __init apic_force_enable(unsigned long addr)
* and AMD K7 (Model > 1) or later.
*/
if (boot_cpu_data.x86 >= 6) {
- rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.q = rdmsrq(MSR_IA32_APICBASE);
if (!(val.l & MSR_IA32_APICBASE_ENABLE)) {
pr_info("Local APIC disabled by BIOS -- reenabling.\n");
val.l &= ~MSR_IA32_APICBASE_BASE;
@@ -2476,7 +2476,7 @@ static void lapic_resume(void *data)
* SMP! We'll need to do this as part of the CPU restore!
*/
if (boot_cpu_data.x86 >= 6) {
- rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.q = rdmsrq(MSR_IA32_APICBASE);
val.l &= ~MSR_IA32_APICBASE_BASE;
val.l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
wrmsrq(MSR_IA32_APICBASE, val.q);
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 5c5be2d58242..e61bab997e61 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -32,7 +32,7 @@ static u32 numachip1_get_apic_id(u32 x)
unsigned int id = (x >> 24) & 0xff;
if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
- rdmsrq(MSR_FAM10H_NODE_ID, value);
+ value = rdmsrq(MSR_FAM10H_NODE_ID);
id |= (value << 2) & 0xff00;
}
@@ -43,7 +43,7 @@ static u32 numachip2_get_apic_id(u32 x)
{
u64 mcfg;
- rdmsrq(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
+ mcfg = rdmsrq(MSR_FAM10H_MMIO_CONF_BASE);
return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
}
@@ -151,7 +151,7 @@ static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
/* Account for nodes per socket in multi-core-module processors */
if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
- rdmsrq(MSR_FAM10H_NODE_ID, val);
+ val = rdmsrq(MSR_FAM10H_NODE_ID);
nodes = ((val >> 3) & 7) + 1;
}
diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c
index 99444409c026..3efceee443b7 100644
--- a/arch/x86/kernel/cet.c
+++ b/arch/x86/kernel/cet.c
@@ -56,7 +56,7 @@ static void do_user_cp_fault(struct pt_regs *regs, unsigned long error_code)
* will be whatever is live in userspace. So read the SSP before enabling
* interrupts so locking the fpregs to do it later is not required.
*/
- rdmsrq(MSR_IA32_PL3_SSP, ssp);
+ ssp = rdmsrq(MSR_IA32_PL3_SSP);
cond_local_irq_enable(regs);
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 169e373418bb..47052e8c328b 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -160,7 +160,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
if (mbytes > 508)
mbytes = 508;
- rdmsrq(MSR_K6_WHCR, val.q);
+ val.q = rdmsrq(MSR_K6_WHCR);
if ((val.l & 0x0000FFFF) == 0) {
unsigned long flags;
val.l = (1 << 0) | ((mbytes / 4) << 1);
@@ -181,7 +181,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
if (mbytes > 4092)
mbytes = 4092;
- rdmsrq(MSR_K6_WHCR, val.q);
+ val.q = rdmsrq(MSR_K6_WHCR);
if ((val.l & 0xFFFF0000) == 0) {
unsigned long flags;
val.l = ((mbytes >> 2) << 22) | (1 << 16);
@@ -228,7 +228,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
* As per AMD technical note 27212 0.2
*/
if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
- rdmsrq(MSR_K7_CLK_CTL, val.q);
+ val.q = rdmsrq(MSR_K7_CLK_CTL);
if ((val.l & 0xfff00000) != 0x20000000) {
pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
val.l, ((val.l & 0x000fffff) | 0x20000000));
@@ -429,7 +429,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
(c->x86 == 0x10 && c->x86_model >= 0x2)) {
u64 val;
- rdmsrq(MSR_K7_HWCR, val);
+ val = rdmsrq(MSR_K7_HWCR);
if (!(val & BIT(24)))
pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
}
@@ -581,7 +581,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
*/
if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
/* Check if memory encryption is enabled */
- rdmsrq(MSR_AMD64_SYSCFG, msr);
+ msr = rdmsrq(MSR_AMD64_SYSCFG);
if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
goto clear_all;
@@ -598,7 +598,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
if (!sme_me_mask)
setup_clear_cpu_cap(X86_FEATURE_SME);
- rdmsrq(MSR_K7_HWCR, msr);
+ msr = rdmsrq(MSR_K7_HWCR);
if (!(msr & MSR_K7_HWCR_SMMLOCK))
goto clear_sev;
@@ -1109,7 +1109,7 @@ static void init_amd(struct cpuinfo_x86 *c)
init_amd_cacheinfo(c);
if (cpu_has(c, X86_FEATURE_SVM)) {
- rdmsrq(MSR_VM_CR, vm_cr);
+ vm_cr = rdmsrq(MSR_VM_CR);
if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) {
pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n");
clear_cpu_cap(c, X86_FEATURE_SVM);
diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmperf.c
index 7ffc78d5ebf2..492dc9a11d6b 100644
--- a/arch/x86/kernel/cpu/aperfmperf.c
+++ b/arch/x86/kernel/cpu/aperfmperf.c
@@ -41,8 +41,8 @@ static void init_counter_refs(void *data)
{
u64 aperf, mperf;
- rdmsrq(MSR_IA32_APERF, aperf);
- rdmsrq(MSR_IA32_MPERF, mperf);
+ aperf = rdmsrq(MSR_IA32_APERF);
+ mperf = rdmsrq(MSR_IA32_MPERF);
this_cpu_write(cpu_samples.aperf, aperf);
this_cpu_write(cpu_samples.mperf, mperf);
@@ -479,8 +479,8 @@ void arch_scale_freq_tick(void)
if (!cpu_feature_enabled(X86_FEATURE_APERFMPERF))
return;
- rdmsrq(MSR_IA32_APERF, aperf);
- rdmsrq(MSR_IA32_MPERF, mperf);
+ aperf = rdmsrq(MSR_IA32_APERF);
+ mperf = rdmsrq(MSR_IA32_MPERF);
acnt = aperf - s->aperf;
mcnt = mperf - s->mperf;
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 83f51cab0b1e..bad99e491e13 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -760,7 +760,7 @@ void update_srbds_msr(void)
if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
return;
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
+ mcu_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
switch (srbds_mitigation) {
case SRBDS_MITIGATION_OFF:
@@ -896,7 +896,7 @@ void update_gds_msr(void)
switch (gds_mitigation) {
case GDS_MITIGATION_OFF:
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
+ mcu_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
mcu_ctrl |= GDS_MITG_DIS;
break;
case GDS_MITIGATION_FULL_LOCKED:
@@ -906,7 +906,7 @@ void update_gds_msr(void)
* CPUs.
*/
case GDS_MITIGATION_FULL:
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
+ mcu_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
mcu_ctrl &= ~GDS_MITG_DIS;
break;
case GDS_MITIGATION_FORCE:
@@ -923,7 +923,7 @@ void update_gds_msr(void)
* GDS_MITG_DIS will be ignored if this processor is locked but the boot
* processor was not.
*/
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after);
+ mcu_ctrl_after = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after);
}
@@ -958,7 +958,7 @@ static void __init gds_select_mitigation(void)
if (gds_mitigation == GDS_MITIGATION_FORCE)
gds_mitigation = GDS_MITIGATION_FULL;
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
+ mcu_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
if (mcu_ctrl & GDS_MITG_LOCKED) {
if (gds_mitigation == GDS_MITIGATION_OFF)
pr_warn("Mitigation locked. Disable failed.\n");
@@ -3232,7 +3232,7 @@ void __init cpu_select_mitigations(void)
* init code as it is not enumerated and depends on the family.
*/
if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
- rdmsrq(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
+ x86_spec_ctrl_base = rdmsrq(MSR_IA32_SPEC_CTRL);
/*
* Previously running kernel (kexec), may have some controls
diff --git a/arch/x86/kernel/cpu/bus_lock.c b/arch/x86/kernel/cpu/bus_lock.c
index bba28607a59a..c9074c368146 100644
--- a/arch/x86/kernel/cpu/bus_lock.c
+++ b/arch/x86/kernel/cpu/bus_lock.c
@@ -105,7 +105,7 @@ static bool split_lock_verify_msr(bool on)
ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
if (wrmsrq_safe(MSR_TEST_CTRL, ctrl))
return false;
- rdmsrq(MSR_TEST_CTRL, tmp);
+ tmp = rdmsrq(MSR_TEST_CTRL);
return ctrl == tmp;
}
@@ -145,7 +145,7 @@ static void __init __split_lock_setup(void)
return;
}
- rdmsrq(MSR_TEST_CTRL, msr_test_ctrl_cache);
+ msr_test_ctrl_cache = rdmsrq(MSR_TEST_CTRL);
if (!split_lock_verify_msr(true)) {
pr_info("MSR access failed: Disabled\n");
@@ -305,7 +305,7 @@ void bus_lock_init(void)
if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
return;
- rdmsrq(MSR_IA32_DEBUGCTLMSR, val);
+ val = rdmsrq(MSR_IA32_DEBUGCTLMSR);
if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
(sld_state == sld_warn || sld_state == sld_fatal)) ||
@@ -383,7 +383,7 @@ static void __init split_lock_setup(struct cpuinfo_x86 *c)
* MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is. All CPUs that set
* it have split lock detection.
*/
- rdmsrq(MSR_IA32_CORE_CAPS, ia32_core_caps);
+ ia32_core_caps = rdmsrq(MSR_IA32_CORE_CAPS);
if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)
goto supported;
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 513fa1f640f9..6cd89b5ac9de 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -30,7 +30,7 @@ static void init_c3(struct cpuinfo_x86 *c)
/* enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsrq(MSR_VIA_FCR, msr);
+ msr = rdmsrq(MSR_VIA_FCR);
/* enable ACE unit */
wrmsrq(MSR_VIA_FCR, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
@@ -38,7 +38,7 @@ static void init_c3(struct cpuinfo_x86 *c)
/* enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsrq(MSR_VIA_RNG, msr);
+ msr = rdmsrq(MSR_VIA_RNG);
/* enable RNG unit */
wrmsrq(MSR_VIA_RNG, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
@@ -52,7 +52,7 @@ static void init_c3(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_32
/* Cyrix III family needs CX8 & PGE explicitly enabled. */
if (c->x86_model >= 6 && c->x86_model <= 13) {
- rdmsrq(MSR_VIA_FCR, msr);
+ msr = rdmsrq(MSR_VIA_FCR);
wrmsrq(MSR_VIA_FCR, msr | (1 << 1 | 1 << 7));
set_cpu_cap(c, X86_FEATURE_CX8);
}
@@ -169,7 +169,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
name = "??";
}
- rdmsrq(MSR_IDT_FCR1, val.q);
+ val.q = rdmsrq(MSR_IDT_FCR1);
newlo = (val.l | fcr_set) & (~fcr_clr);
if (newlo != val.l) {
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index cbef2c6c8478..5a36d96595b4 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -346,7 +346,7 @@ static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
/* Disable processor serial number: */
- rdmsrq(MSR_IA32_BBL_CR_CTL, val.q);
+ val.q = rdmsrq(MSR_IA32_BBL_CR_CTL);
val.l |= 0x200000;
wrmsrq(MSR_IA32_BBL_CR_CTL, val.q);
@@ -610,7 +610,7 @@ __noendbr u64 ibt_save(bool disable)
u64 msr = 0;
if (cpu_feature_enabled(X86_FEATURE_IBT)) {
- rdmsrq(MSR_IA32_S_CET, msr);
+ msr = rdmsrq(MSR_IA32_S_CET);
if (disable)
wrmsrq(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
}
@@ -623,7 +623,7 @@ __noendbr void ibt_restore(u64 save)
u64 msr;
if (cpu_feature_enabled(X86_FEATURE_IBT)) {
- rdmsrq(MSR_IA32_S_CET, msr);
+ msr = rdmsrq(MSR_IA32_S_CET);
msr &= ~CET_ENDBR_EN;
msr |= (save & CET_ENDBR_EN);
wrmsrq(MSR_IA32_S_CET, msr);
@@ -1361,7 +1361,7 @@ u64 x86_read_arch_cap_msr(void)
u64 x86_arch_cap_msr = 0;
if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
- rdmsrq(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr);
+ x86_arch_cap_msr = rdmsrq(MSR_IA32_ARCH_CAPABILITIES);
return x86_arch_cap_msr;
}
@@ -1913,10 +1913,10 @@ static bool detect_null_seg_behavior(void)
*/
unsigned long old_base, tmp;
- rdmsrq(MSR_FS_BASE, old_base);
+ old_base = rdmsrq(MSR_FS_BASE);
wrmsrq(MSR_FS_BASE, 1);
loadsegment(fs, 0);
- rdmsrq(MSR_FS_BASE, tmp);
+ tmp = rdmsrq(MSR_FS_BASE);
wrmsrq(MSR_FS_BASE, old_base);
return tmp == 0;
}
diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c
index 1ce30a5c26ce..3adcab54c16f 100644
--- a/arch/x86/kernel/cpu/feat_ctl.c
+++ b/arch/x86/kernel/cpu/feat_ctl.c
@@ -40,7 +40,7 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c)
* as they exist on any CPU that supports VMX, i.e. we want the WARN if
* the RDMSR faults.
*/
- rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS, val.q);
+ val.q = rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS);
c->vmx_capability[PRIMARY_CTLS] = val.h;
rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &val.q);
@@ -51,7 +51,7 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c)
c->vmx_capability[TERTIARY_CTLS_LOW] = val.l;
c->vmx_capability[TERTIARY_CTLS_HIGH] = val.h;
- rdmsrq(MSR_IA32_VMX_PINBASED_CTLS, val.q);
+ val.q = rdmsrq(MSR_IA32_VMX_PINBASED_CTLS);
supported = val.h;
rdmsrq_safe(MSR_IA32_VMX_VMFUNC, &val.q);
funcs = val.h;
diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index ec51c2b9a257..44b462799cf6 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -99,7 +99,7 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c)
if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
u64 val;
- rdmsrq(MSR_K7_HWCR, val);
+ val = rdmsrq(MSR_K7_HWCR);
if (!(val & BIT(24)))
pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
}
@@ -194,7 +194,7 @@ static void init_hygon(struct cpuinfo_x86 *c)
init_hygon_cacheinfo(c);
if (cpu_has(c, X86_FEATURE_SVM)) {
- rdmsrq(MSR_VM_CR, vm_cr);
+ vm_cr = rdmsrq(MSR_VM_CR);
if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) {
pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n");
clear_cpu_cap(c, X86_FEATURE_SVM);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 076bdd0d3f85..20d48ffa27b8 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -159,7 +159,7 @@ static void detect_tme_early(struct cpuinfo_x86 *c)
u64 tme_activate;
int keyid_bits;
- rdmsrq(MSR_IA32_TME_ACTIVATE, tme_activate);
+ tme_activate = rdmsrq(MSR_IA32_TME_ACTIVATE);
if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
pr_info_once("x86/tme: not enabled by BIOS\n");
@@ -300,7 +300,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
* string flag and enhanced fast string capabilities accordingly.
*/
if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) {
- rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable);
+ misc_enable = rdmsrq(MSR_IA32_MISC_ENABLE);
if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
/* X86_FEATURE_ERMS is set based on CPUID */
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
@@ -544,7 +544,7 @@ static void init_intel(struct cpuinfo_x86 *c)
if (boot_cpu_has(X86_FEATURE_DS)) {
u64 l;
- rdmsrq(MSR_IA32_MISC_ENABLE, l);
+ l = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(l & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_BTS);
if (!(l & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c
index 2c56f8730f59..a02d562253d9 100644
--- a/arch/x86/kernel/cpu/intel_epb.c
+++ b/arch/x86/kernel/cpu/intel_epb.c
@@ -79,7 +79,7 @@ static int intel_epb_save(void *data)
{
u64 epb;
- rdmsrq(MSR_IA32_ENERGY_PERF_BIAS, epb);
+ epb = rdmsrq(MSR_IA32_ENERGY_PERF_BIAS);
/*
* Ensure that saved_epb will always be nonzero after this write even if
* the EPB value read from the MSR is 0.
@@ -94,7 +94,7 @@ static void intel_epb_restore(void *data)
u64 val = this_cpu_read(saved_epb);
u64 epb;
- rdmsrq(MSR_IA32_ENERGY_PERF_BIAS, epb);
+ epb = rdmsrq(MSR_IA32_ENERGY_PERF_BIAS);
if (val) {
val &= EPB_MASK;
} else {
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index f916fb4c5d13..febdd4fe9b3b 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -438,7 +438,7 @@ static void threshold_restart_block(void *_tr)
if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
return;
- rdmsrq(tr->b->address, val.q);
+ val.q = rdmsrq(tr->b->address);
/*
* Reset error count and overflow bit.
@@ -658,7 +658,7 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
return;
}
- rdmsrq(MSR_K7_HWCR, hwcr);
+ hwcr = rdmsrq(MSR_K7_HWCR);
/* McStatusWrEn has to be set */
need_toggle = !(hwcr & BIT(18));
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 017aaf57ba47..0d4f4c000405 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1845,7 +1845,7 @@ static void __mcheck_cpu_cap_init(void)
u64 cap;
u8 b;
- rdmsrq(MSR_IA32_MCG_CAP, cap);
+ cap = rdmsrq(MSR_IA32_MCG_CAP);
b = cap & MCG_BANKCNT_MASK;
@@ -1864,7 +1864,7 @@ static void __mcheck_cpu_init_generic(void)
{
u64 cap;
- rdmsrq(MSR_IA32_MCG_CAP, cap);
+ cap = rdmsrq(MSR_IA32_MCG_CAP);
if (cap & MCG_CTL_P)
wrmsrq(MSR_IA32_MCG_CTL, ~0ULL);
}
@@ -1896,7 +1896,7 @@ static void __mcheck_cpu_init_prepare_banks(void)
wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl);
wrmsrq(mca_msr_reg(i, MCA_STATUS), 0);
- rdmsrq(mca_msr_reg(i, MCA_CTL), msrval);
+ msrval = rdmsrq(mca_msr_reg(i, MCA_CTL));
b->init = !!msrval;
}
}
@@ -2214,7 +2214,7 @@ void mca_bsp_init(struct cpuinfo_x86 *c)
if (mce_flags.smca)
smca_bsp_init();
- rdmsrq(MSR_IA32_MCG_CAP, cap);
+ cap = rdmsrq(MSR_IA32_MCG_CAP);
/* Use accurate RIP reporting if available. */
if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 6f8a49d8baeb..aa933864f32e 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -743,7 +743,7 @@ static void check_hw_inj_possible(void)
u64 status = MCI_STATUS_VAL, ipid;
/* Check whether bank is populated */
- rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), ipid);
+ ipid = rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank));
if (!ipid)
continue;
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 4655223ba560..2edb05d5e2d7 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -94,7 +94,7 @@ static bool cmci_supported(int *banks)
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return false;
- rdmsrq(MSR_IA32_MCG_CAP, cap);
+ cap = rdmsrq(MSR_IA32_MCG_CAP);
*banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK);
return !!(cap & MCG_CMCI_P);
}
@@ -106,7 +106,7 @@ static bool lmce_supported(void)
if (mca_cfg.lmce_disabled)
return false;
- rdmsrq(MSR_IA32_MCG_CAP, tmp);
+ tmp = rdmsrq(MSR_IA32_MCG_CAP);
/*
* LMCE depends on recovery support in the processor. Hence both
@@ -123,7 +123,7 @@ static bool lmce_supported(void)
* WARN if the MSR isn't locked as init_ia32_feat_ctl() unconditionally
* locks the MSR in the event that it wasn't already locked by BIOS.
*/
- rdmsrq(MSR_IA32_FEAT_CTL, tmp);
+ tmp = rdmsrq(MSR_IA32_FEAT_CTL);
if (WARN_ON_ONCE(!(tmp & FEAT_CTL_LOCKED)))
return false;
@@ -141,7 +141,7 @@ static void cmci_set_threshold(int bank, int thresh)
u64 val;
raw_spin_lock_irqsave(&cmci_discover_lock, flags);
- rdmsrq(MSR_IA32_MCx_CTL2(bank), val);
+ val = rdmsrq(MSR_IA32_MCx_CTL2(bank));
val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh);
raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
@@ -184,7 +184,7 @@ static bool cmci_skip_bank(int bank, u64 *val)
if (test_bit(bank, mce_banks_ce_disabled))
return true;
- rdmsrq(MSR_IA32_MCx_CTL2(bank), *val);
+ *val = rdmsrq(MSR_IA32_MCx_CTL2(bank));
/* Already owned by someone else? */
if (*val & MCI_CTL2_CMCI_EN) {
@@ -233,7 +233,7 @@ static void cmci_claim_bank(int bank, u64 val, int bios_zero_thresh, int *bios_w
val |= MCI_CTL2_CMCI_EN;
wrmsrq(MSR_IA32_MCx_CTL2(bank), val);
- rdmsrq(MSR_IA32_MCx_CTL2(bank), val);
+ val = rdmsrq(MSR_IA32_MCx_CTL2(bank));
/* If the enable bit did not stick, this bank should be polled. */
if (!(val & MCI_CTL2_CMCI_EN)) {
@@ -324,7 +324,7 @@ static void __cmci_disable_bank(int bank)
if (!test_bit(bank, this_cpu_ptr(mce_banks_owned)))
return;
- rdmsrq(MSR_IA32_MCx_CTL2(bank), val);
+ val = rdmsrq(MSR_IA32_MCx_CTL2(bank));
val &= ~MCI_CTL2_CMCI_EN;
wrmsrq(MSR_IA32_MCx_CTL2(bank), val);
__clear_bit(bank, this_cpu_ptr(mce_banks_owned));
@@ -430,7 +430,7 @@ void intel_init_lmce(void)
if (!lmce_supported())
return;
- rdmsrq(MSR_IA32_MCG_EXT_CTL, val);
+ val = rdmsrq(MSR_IA32_MCG_EXT_CTL);
if (!(val & MCG_EXT_CTL_LMCE_EN))
wrmsrq(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
@@ -443,7 +443,7 @@ void intel_clear_lmce(void)
if (!lmce_supported())
return;
- rdmsrq(MSR_IA32_MCG_EXT_CTL, val);
+ val = rdmsrq(MSR_IA32_MCG_EXT_CTL);
val &= ~MCG_EXT_CTL_LMCE_EN;
wrmsrq(MSR_IA32_MCG_EXT_CTL, val);
}
diff --git a/arch/x86/kernel/cpu/mce/p5.c b/arch/x86/kernel/cpu/mce/p5.c
index eb99f384d747..7b363b604bad 100644
--- a/arch/x86/kernel/cpu/mce/p5.c
+++ b/arch/x86/kernel/cpu/mce/p5.c
@@ -26,8 +26,8 @@ noinstr void pentium_machine_check(struct pt_regs *regs)
u64 addr, type;
instrumentation_begin();
- rdmsrq(MSR_IA32_P5_MC_ADDR, addr);
- rdmsrq(MSR_IA32_P5_MC_TYPE, type);
+ addr = rdmsrq(MSR_IA32_P5_MC_ADDR);
+ type = rdmsrq(MSR_IA32_P5_MC_TYPE);
pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
smp_processor_id(), (u32)addr, (u32)type);
@@ -55,8 +55,8 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
return;
/* Read registers before enabling: */
- rdmsrq(MSR_IA32_P5_MC_ADDR, q);
- rdmsrq(MSR_IA32_P5_MC_TYPE, q);
+ q = rdmsrq(MSR_IA32_P5_MC_ADDR);
+ q = rdmsrq(MSR_IA32_P5_MC_TYPE);
pr_info("Intel old style machine check architecture supported.\n");
/* Enable MCE: */
diff --git a/arch/x86/kernel/cpu/mce/winchip.c b/arch/x86/kernel/cpu/mce/winchip.c
index 7040243533d9..7b967f2abd8f 100644
--- a/arch/x86/kernel/cpu/mce/winchip.c
+++ b/arch/x86/kernel/cpu/mce/winchip.c
@@ -30,7 +30,7 @@ void winchip_mcheck_init(struct cpuinfo_x86 *c)
{
struct msr val;
- rdmsrq(MSR_IDT_FCR1, val.q);
+ val.q = rdmsrq(MSR_IDT_FCR1);
val.l |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
val.l &= ~(1<<4); /* Enable MCE */
wrmsrq(MSR_IDT_FCR1, val.q);
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index f4a444e6114d..4d860fea5cc8 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -1027,7 +1027,7 @@ static __init bool staging_available(void)
if (!(val & ARCH_CAP_MCU_ENUM))
return false;
- rdmsrq(MSR_IA32_MCU_ENUMERATION, val);
+ val = rdmsrq(MSR_IA32_MCU_ENUMERATION);
return !!(val & MCU_STAGING);
}
diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index 185d4f677ec0..65ad235ef5c6 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -74,7 +74,7 @@ u64 hv_get_non_nested_msr(unsigned int reg)
if (hv_is_synic_msr(reg) && ms_hyperv.paravisor_present)
hv_ivm_msr_read(reg, &value);
else
- rdmsrq(reg, value);
+ value = rdmsrq(reg);
return value;
}
EXPORT_SYMBOL_GPL(hv_get_non_nested_msr);
@@ -399,7 +399,7 @@ static unsigned long hv_get_tsc_khz(void)
{
unsigned long freq;
- rdmsrq(HV_X64_MSR_TSC_FREQUENCY, freq);
+ freq = rdmsrq(HV_X64_MSR_TSC_FREQUENCY);
return freq / 1000;
}
@@ -645,7 +645,7 @@ static void __init ms_hyperv_init_platform(void)
*/
u64 hv_lapic_frequency;
- rdmsrq(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency);
+ hv_lapic_frequency = rdmsrq(HV_X64_MSR_APIC_FREQUENCY);
hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ);
lapic_timer_period = hv_lapic_frequency;
pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n",
diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c
index fad93cbf6869..6622eaf9445e 100644
--- a/arch/x86/kernel/cpu/mtrr/amd.c
+++ b/arch/x86/kernel/cpu/mtrr/amd.c
@@ -13,7 +13,7 @@ amd_get_mtrr(unsigned int reg, unsigned long *base,
unsigned long val;
struct msr msr;
- rdmsrq(MSR_K6_UWCCR, msr.q);
+ msr.q = rdmsrq(MSR_K6_UWCCR);
/* Upper dword is region 1, lower is region 0 */
if (reg == 1)
val = msr.h;
@@ -70,7 +70,7 @@ amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type
/*
* Low is MTRR0, High MTRR 1
*/
- rdmsrq(MSR_K6_UWCCR, msr.val);
+ msr.val = rdmsrq(MSR_K6_UWCCR);
/*
* Blank to disable
*/
diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
index cd1a6dec4064..2b72c784db9e 100644
--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
+++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
@@ -670,7 +670,7 @@ int __init mtrr_cleanup(void)
if (!cpu_feature_enabled(X86_FEATURE_MTRR) || enable_mtrr_cleanup < 1)
return 0;
- rdmsrq(MSR_MTRRdefType, def);
+ def = rdmsrq(MSR_MTRRdefType);
def &= 0xff;
if (def != MTRR_TYPE_UNCACHABLE)
return 0;
@@ -870,7 +870,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
if (!cpu_feature_enabled(X86_FEATURE_MTRR) || disable_mtrr_trim)
return 0;
- rdmsrq(MSR_MTRRdefType, def);
+ def = rdmsrq(MSR_MTRRdefType);
def &= MTRR_DEF_TYPE_TYPE;
if (def != MTRR_TYPE_UNCACHABLE)
return 0;
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 67cf69f24b00..4d8034a7fdc8 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -112,7 +112,7 @@ static inline void k8_check_syscfg_dram_mod_en(void)
if (cc_platform_has(CC_ATTR_HOST_SEV_SNP))
return;
- rdmsrq(MSR_AMD64_SYSCFG, val.q);
+ val.q = rdmsrq(MSR_AMD64_SYSCFG);
if (val.l & K8_MTRRFIXRANGE_DRAM_MODIFY) {
pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
" not cleared by BIOS, clearing this bit\n",
@@ -559,10 +559,10 @@ get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
{
struct msr val;
- rdmsrq(MTRRphysBase_MSR(index), val.q);
+ val.q = rdmsrq(MTRRphysBase_MSR(index));
vr->base_lo = val.l;
vr->base_hi = val.h;
- rdmsrq(MTRRphysMask_MSR(index), val.q);
+ val.q = rdmsrq(MTRRphysMask_MSR(index));
vr->mask_lo = val.l;
vr->mask_hi = val.h;
}
@@ -588,12 +588,12 @@ static void get_fixed_ranges(mtrr_type *frs)
k8_check_syscfg_dram_mod_en();
- rdmsrq(MSR_MTRRfix64K_00000, p[0]);
+ p[0] = rdmsrq(MSR_MTRRfix64K_00000);
for (i = 0; i < 2; i++)
- rdmsrq(MSR_MTRRfix16K_80000 + i, p[1 + i]);
+ p[1 + i] = rdmsrq(MSR_MTRRfix16K_80000 + i);
for (i = 0; i < 8; i++)
- rdmsrq(MSR_MTRRfix4K_C0000 + i, p[3 + i]);
+ p[3 + i] = rdmsrq(MSR_MTRRfix4K_C0000 + i);
}
void mtrr_save_fixed_ranges(void *info)
@@ -700,7 +700,7 @@ bool __init get_mtrr_state(void)
vrs = mtrr_state.var_ranges;
- rdmsrq(MSR_MTRRcap, q);
+ q = rdmsrq(MSR_MTRRcap);
mtrr_state.have_fixed = q & MTRR_CAP_FIX;
for (i = 0; i < num_var_ranges; i++)
@@ -708,13 +708,13 @@ bool __init get_mtrr_state(void)
if (mtrr_state.have_fixed)
get_fixed_ranges(mtrr_state.fixed_ranges);
- rdmsrq(MSR_MTRRdefType, q);
+ q = rdmsrq(MSR_MTRRdefType);
mtrr_state.def_type = q & MTRR_DEF_TYPE_TYPE;
mtrr_state.enabled = (q & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT;
if (amd_special_default_mtrr()) {
/* TOP_MEM2 */
- rdmsrq(MSR_K8_TOP_MEM2, mtrr_tom2);
+ mtrr_tom2 = rdmsrq(MSR_K8_TOP_MEM2);
mtrr_tom2 &= 0xffffff800000ULL;
}
@@ -770,7 +770,7 @@ static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
{
struct msr val;
- rdmsrq(msr, val.q);
+ val.q = rdmsrq(msr);
if (val.l != msrwords[0] || val.h != msrwords[1]) {
mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
@@ -818,7 +818,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
*/
get_cpu();
- rdmsrq(MTRRphysMask_MSR(reg), mask);
+ mask = rdmsrq(MTRRphysMask_MSR(reg));
if (!(mask & MTRR_PHYSMASK_V)) {
/* Invalid (i.e. free) range */
@@ -828,7 +828,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
goto out_put_cpu;
}
- rdmsrq(MTRRphysBase_MSR(reg), base_msr);
+ base_msr = rdmsrq(MTRRphysBase_MSR(reg));
/* Work out the shifted address mask: */
tmp = mask & PAGE_MASK;
@@ -889,7 +889,7 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
bool changed = false;
struct msr val;
- rdmsrq(MTRRphysBase_MSR(index), val.q);
+ val.q = rdmsrq(MTRRphysBase_MSR(index));
if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (val.l & ~MTRR_PHYSBASE_RSVD)
|| (vr->base_hi & ~phys_hi_rsvd) != (val.h & ~phys_hi_rsvd)) {
@@ -897,7 +897,7 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
changed = true;
}
- rdmsrq(MTRRphysMask_MSR(index), val.q);
+ val.q = rdmsrq(MTRRphysMask_MSR(index));
if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (val.l & ~MTRR_PHYSMASK_RSVD)
|| (vr->mask_hi & ~phys_hi_rsvd) != (val.h & ~phys_hi_rsvd)) {
@@ -952,7 +952,7 @@ void mtrr_disable(void)
struct msr val;
/* Save MTRR state */
- rdmsrq(MSR_MTRRdefType, val.q);
+ val.q = rdmsrq(MSR_MTRRdefType);
deftype_lo = val.l;
deftype_hi = val.h;
@@ -1065,7 +1065,7 @@ static int generic_have_wrcomb(void)
{
u64 config;
- rdmsrq(MSR_MTRRcap, config);
+ config = rdmsrq(MSR_MTRRcap);
return config & MTRR_CAP_WC;
}
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
index 468c53b20acf..9b7abd58b677 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
@@ -571,7 +571,7 @@ void __init mtrr_bp_init(void)
if (mtrr_enabled()) {
/* Get the number of variable MTRR ranges. */
if (mtrr_if == &generic_mtrr_ops)
- rdmsrq(MSR_MTRRcap, config);
+ config = rdmsrq(MSR_MTRRcap);
else
config = mtrr_if->var_regs;
num_var_ranges = config & MTRR_CAP_VCNT;
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index f452e8ce4cef..d4fc3964a4f1 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -165,7 +165,7 @@ static inline void cache_alloc_hsw_probe(void)
if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm))
return;
- rdmsrq(MSR_IA32_L3_CBM_BASE, l3_cbm_0);
+ l3_cbm_0 = rdmsrq(MSR_IA32_L3_CBM_BASE);
/* If all the bits were set in MSR, return success */
if (l3_cbm_0 != max_cbm)
diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
index 153dc5a268a4..591f4837ae1a 100644
--- a/arch/x86/kernel/cpu/resctrl/monitor.c
+++ b/arch/x86/kernel/cpu/resctrl/monitor.c
@@ -147,7 +147,7 @@ static int __rmid_read_phys(u32 prmid, enum resctrl_event_id eventid, u64 *val)
* are error bits.
*/
wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q);
- rdmsrq(MSR_IA32_QM_CTR, msr_val.q);
+ msr_val.q = rdmsrq(MSR_IA32_QM_CTR);
if (msr_val.q & RMID_VAL_ERROR)
return -EIO;
@@ -305,7 +305,7 @@ static int __cntr_id_read(u32 cntr_id, u64 *val)
* is set if the counter data is unavailable.
*/
wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q);
- rdmsrq(MSR_IA32_QM_CTR, msr_val.q);
+ msr_val.q = rdmsrq(MSR_IA32_QM_CTR);
if (msr_val.q & RMID_VAL_ERROR)
return -EIO;
diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index d7caab0409b6..0408ac7f66fd 100644
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -250,7 +250,7 @@ int resctrl_arch_measure_cycles_lat_fn(void *_plr)
/*
* Disable hardware prefetchers.
*/
- rdmsrq(MSR_MISC_FEATURE_CONTROL, saved);
+ saved = rdmsrq(MSR_MISC_FEATURE_CONTROL);
wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
mem_r = READ_ONCE(plr->kmem);
/*
@@ -346,7 +346,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
/*
* Disable hardware prefetchers.
*/
- rdmsrq(MSR_MISC_FEATURE_CONTROL, saved);
+ saved = rdmsrq(MSR_MISC_FEATURE_CONTROL);
wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
/* Initialize rest of local variables */
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 885026468440..6f7efe2a7c12 100644
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -96,7 +96,7 @@ void resctrl_arch_mon_event_config_read(void *_config_info)
pr_warn_once("Invalid event id %d\n", config_info->evtid);
return;
}
- rdmsrq(MSR_IA32_EVT_CFG_BASE + index, msrval);
+ msrval = rdmsrq(MSR_IA32_EVT_CFG_BASE + index);
/* Report only the valid event configuration bits */
config_info->mon_config = msrval & MAX_EVT_CONFIG_BITS;
diff --git a/arch/x86/kernel/cpu/topology.c b/arch/x86/kernel/cpu/topology.c
index 4913b64ec592..68337da5aa09 100644
--- a/arch/x86/kernel/cpu/topology.c
+++ b/arch/x86/kernel/cpu/topology.c
@@ -151,7 +151,7 @@ static __init bool check_for_real_bsp(u32 apic_id)
* kernel must rely on the firmware enumeration order.
*/
if (has_apic_base) {
- rdmsrq(MSR_IA32_APICBASE, msr);
+ msr = rdmsrq(MSR_IA32_APICBASE);
is_bsp = !!(msr & MSR_IA32_APICBASE_BSP);
}
diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c
index da080d732e10..2e05f21be2da 100644
--- a/arch/x86/kernel/cpu/topology_amd.c
+++ b/arch/x86/kernel/cpu/topology_amd.c
@@ -140,7 +140,7 @@ static void parse_fam10h_node_id(struct topo_scan *tscan)
if (!boot_cpu_has(X86_FEATURE_NODEID_MSR))
return;
- rdmsrq(MSR_FAM10H_NODE_ID, nid.msr);
+ nid.msr = rdmsrq(MSR_FAM10H_NODE_ID);
store_node(tscan, nid.nodes_per_pkg + 1, nid.node_id);
tscan->c->topo.llc_id = nid.node_id;
}
@@ -168,7 +168,7 @@ static void topoext_fixup(struct topo_scan *tscan)
MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT) <= 0)
return;
- rdmsrq(MSR_AMD64_CPUID_EXT_FEAT, msrval);
+ msrval = rdmsrq(MSR_AMD64_CPUID_EXT_FEAT);
if (msrval & MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT) {
set_cpu_cap(c, X86_FEATURE_TOPOEXT);
pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index c670fbb6ee50..6c2755acc7f1 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -87,7 +87,7 @@ static void init_transmeta(struct cpuinfo_x86 *c)
}
/* Unhide possibly hidden capability flags */
- rdmsrq(0x80860004, msr);
+ msr = rdmsrq(0x80860004);
wrmsrq(0x80860004, msr | ~0U);
c->x86_capability[CPUID_1_EDX] = cpuid_edx(0x00000001);
wrmsrq(0x80860004, msr);
diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
index 209b5a22d880..b500845d2049 100644
--- a/arch/x86/kernel/cpu/tsx.c
+++ b/arch/x86/kernel/cpu/tsx.c
@@ -35,7 +35,7 @@ static void tsx_disable(void)
{
u64 tsx;
- rdmsrq(MSR_IA32_TSX_CTRL, tsx);
+ tsx = rdmsrq(MSR_IA32_TSX_CTRL);
/* Force all transactions to immediately abort */
tsx |= TSX_CTRL_RTM_DISABLE;
@@ -55,7 +55,7 @@ static void tsx_enable(void)
{
u64 tsx;
- rdmsrq(MSR_IA32_TSX_CTRL, tsx);
+ tsx = rdmsrq(MSR_IA32_TSX_CTRL);
/* Enable the RTM feature in the cpu */
tsx &= ~TSX_CTRL_RTM_DISABLE;
@@ -126,11 +126,11 @@ static void tsx_clear_cpuid(void)
*/
if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&
boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
- rdmsrq(MSR_TSX_FORCE_ABORT, msr);
+ msr = rdmsrq(MSR_TSX_FORCE_ABORT);
msr |= MSR_TFA_TSX_CPUID_CLEAR;
wrmsrq(MSR_TSX_FORCE_ABORT, msr);
} else if (cpu_feature_enabled(X86_FEATURE_MSR_TSX_CTRL)) {
- rdmsrq(MSR_IA32_TSX_CTRL, msr);
+ msr = rdmsrq(MSR_IA32_TSX_CTRL);
msr |= TSX_CTRL_CPUID_CLEAR;
wrmsrq(MSR_IA32_TSX_CTRL, msr);
}
@@ -157,7 +157,7 @@ static void tsx_dev_mode_disable(void)
!cpu_feature_enabled(X86_FEATURE_SRBDS_CTRL))
return;
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl);
+ mcu_opt_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
if (mcu_opt_ctrl & RTM_ALLOW) {
mcu_opt_ctrl &= ~RTM_ALLOW;
diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c
index e4a31c536642..8c3cf0f95e9a 100644
--- a/arch/x86/kernel/cpu/umwait.c
+++ b/arch/x86/kernel/cpu/umwait.c
@@ -218,7 +218,7 @@ static int __init umwait_init(void)
* changed. This is the only place where orig_umwait_control_cached
* is modified.
*/
- rdmsrq(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached);
+ orig_umwait_control_cached = rdmsrq(MSR_IA32_UMWAIT_CONTROL);
ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "umwait:online",
umwait_cpu_online, umwait_cpu_offline);
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index fe504fd43c77..f89aec38a349 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -29,7 +29,7 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
/* Enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsrq(MSR_ZHAOXIN_FCR57, msr);
+ msr = rdmsrq(MSR_ZHAOXIN_FCR57);
/* Enable ACE unit */
wrmsrq(MSR_ZHAOXIN_FCR57, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
@@ -37,7 +37,7 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
/* Enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsrq(MSR_ZHAOXIN_FCR57, msr);
+ msr = rdmsrq(MSR_ZHAOXIN_FCR57);
/* Enable RNG unit */
wrmsrq(MSR_ZHAOXIN_FCR57, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
index 584fb9913be4..322398aa83bf 100644
--- a/arch/x86/kernel/fpu/core.c
+++ b/arch/x86/kernel/fpu/core.c
@@ -364,7 +364,7 @@ void fpu_sync_guest_vmexit_xfd_state(void)
lockdep_assert_irqs_disabled();
if (fpu_state_size_dynamic()) {
- rdmsrq(MSR_IA32_XFD, fpstate->xfd);
+ fpstate->xfd = rdmsrq(MSR_IA32_XFD);
__this_cpu_write(xfd_state, fpstate->xfd);
}
}
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 8dc7b710e125..8a27b9ae9fc7 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -971,7 +971,7 @@ static bool __init hpet_is_pc10_damaged(void)
return false;
/* Check whether PC10 is enabled in PKG C-state limit */
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, pcfg);
+ pcfg = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
if ((pcfg & 0xF) < 8)
return false;
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index dcef84da304b..e773e94c14ea 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -738,7 +738,7 @@ static int kvm_suspend(void *data)
#ifdef CONFIG_ARCH_CPUIDLE_HALTPOLL
if (kvm_para_has_feature(KVM_FEATURE_POLL_CONTROL))
- rdmsrq(MSR_KVM_POLL_CONTROL, val);
+ val = rdmsrq(MSR_KVM_POLL_CONTROL);
has_guest_poll = !(val & 1);
#endif
return 0;
diff --git a/arch/x86/kernel/mmconf-fam10h_64.c b/arch/x86/kernel/mmconf-fam10h_64.c
index ef6104e7cc72..348ac8fce3ad 100644
--- a/arch/x86/kernel/mmconf-fam10h_64.c
+++ b/arch/x86/kernel/mmconf-fam10h_64.c
@@ -97,7 +97,7 @@ static void get_fam10h_pci_mmconf_base(void)
/* SYS_CFG */
address = MSR_AMD64_SYSCFG;
- rdmsrq(address, val);
+ val = rdmsrq(address);
/* TOP_MEM2 is not enabled? */
if (!(val & (1<<21))) {
@@ -105,7 +105,7 @@ static void get_fam10h_pci_mmconf_base(void)
} else {
/* TOP_MEM2 */
address = MSR_K8_TOP_MEM2;
- rdmsrq(address, val);
+ val = rdmsrq(address);
tom2 = max(val & 0xffffff800000ULL, 1ULL << 32);
}
@@ -177,7 +177,7 @@ void fam10h_check_enable_mmcfg(void)
return;
address = MSR_FAM10H_MMIO_CONF_BASE;
- rdmsrq(address, val);
+ val = rdmsrq(address);
/* try to make sure that AP's setting is identical to BSP setting */
if (val & FAM10H_MMIO_CONF_ENABLE) {
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 85435044e33c..2fcf872f9854 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -730,7 +730,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
arch_has_block_step()) {
unsigned long debugctl, msk;
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
debugctl &= ~DEBUGCTLMSR_BTF;
msk = tifn & _TIF_BLOCKSTEP;
debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
@@ -980,7 +980,7 @@ void __init arch_post_acpi_subsys_init(void)
* the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
* MSR_K8_INT_PENDING_MSG.
*/
- rdmsrq(MSR_K8_INT_PENDING_MSG, val);
+ val = rdmsrq(MSR_K8_INT_PENDING_MSG);
if (!(val & K8_INTP_C1E_ACTIVE_MASK))
return;
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index d44afbe005bb..cec5aba41776 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -97,8 +97,8 @@ void __show_regs(struct pt_regs *regs, enum show_regs_mode mode,
return;
if (mode == SHOW_REGS_USER) {
- rdmsrq(MSR_FS_BASE, fs);
- rdmsrq(MSR_KERNEL_GS_BASE, shadowgs);
+ fs = rdmsrq(MSR_FS_BASE);
+ shadowgs = rdmsrq(MSR_KERNEL_GS_BASE);
printk("%sFS: %016lx GS: %016lx\n",
log_lvl, fs, shadowgs);
return;
@@ -109,9 +109,9 @@ void __show_regs(struct pt_regs *regs, enum show_regs_mode mode,
savesegment(fs, fsindex);
savesegment(gs, gsindex);
- rdmsrq(MSR_FS_BASE, fs);
- rdmsrq(MSR_GS_BASE, gs);
- rdmsrq(MSR_KERNEL_GS_BASE, shadowgs);
+ fs = rdmsrq(MSR_FS_BASE);
+ gs = rdmsrq(MSR_GS_BASE);
+ shadowgs = rdmsrq(MSR_KERNEL_GS_BASE);
cr0 = read_cr0();
cr2 = read_cr2();
@@ -197,7 +197,7 @@ static noinstr unsigned long __rdgsbase_inactive(void)
native_swapgs();
} else {
instrumentation_begin();
- rdmsrq(MSR_KERNEL_GS_BASE, gsbase);
+ gsbase = rdmsrq(MSR_KERNEL_GS_BASE);
instrumentation_end();
}
@@ -463,7 +463,7 @@ unsigned long x86_gsbase_read_cpu_inactive(void)
gsbase = __rdgsbase_inactive();
local_irq_restore(flags);
} else {
- rdmsrq(MSR_KERNEL_GS_BASE, gsbase);
+ gsbase = rdmsrq(MSR_KERNEL_GS_BASE);
}
return gsbase;
diff --git a/arch/x86/kernel/shstk.c b/arch/x86/kernel/shstk.c
index 0ca64900192f..f3d1f385c626 100644
--- a/arch/x86/kernel/shstk.c
+++ b/arch/x86/kernel/shstk.c
@@ -231,7 +231,7 @@ static unsigned long get_user_shstk_addr(void)
fpregs_lock_and_load();
- rdmsrq(MSR_IA32_PL3_SSP, ssp);
+ ssp = rdmsrq(MSR_IA32_PL3_SSP);
fpregs_unlock();
@@ -248,7 +248,7 @@ int shstk_pop(u64 *val)
fpregs_lock_and_load();
- rdmsrq(MSR_IA32_PL3_SSP, ssp);
+ ssp = rdmsrq(MSR_IA32_PL3_SSP);
if (val && get_user(*val, (__user u64 *)ssp))
ret = -EFAULT;
else
@@ -268,7 +268,7 @@ int shstk_push(u64 val)
fpregs_lock_and_load();
- rdmsrq(MSR_IA32_PL3_SSP, ssp);
+ ssp = rdmsrq(MSR_IA32_PL3_SSP);
ssp -= SS_FRAME_SIZE;
ret = write_user_shstk_64((__user void *)ssp, val);
if (!ret)
@@ -497,7 +497,7 @@ static int wrss_control(bool enable)
return 0;
fpregs_lock_and_load();
- rdmsrq(MSR_IA32_U_CET, msrval);
+ msrval = rdmsrq(MSR_IA32_U_CET);
if (enable) {
features_set(ARCH_SHSTK_WRSS);
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 30aa8369957e..9cd11dc7bb17 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -1250,7 +1250,7 @@ static noinstr void exc_debug_kernel(struct pt_regs *regs, unsigned long dr6)
*/
unsigned long debugctl;
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
debugctl |= DEBUGCTLMSR_BTF;
wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
}
@@ -1509,7 +1509,7 @@ static bool handle_xfd_event(struct pt_regs *regs)
if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD))
return false;
- rdmsrq(MSR_IA32_XFD_ERR, xfd_err);
+ xfd_err = rdmsrq(MSR_IA32_XFD_ERR);
if (!xfd_err)
return false;
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 723347e2cf7f..39baee2307c3 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1088,7 +1088,7 @@ static void __init detect_art(void)
if (art_base_clk.denominator < ART_MIN_DENOMINATOR)
return;
- rdmsrq(MSR_IA32_TSC_ADJUST, art_base_clk.offset);
+ art_base_clk.offset = rdmsrq(MSR_IA32_TSC_ADJUST);
/* Make this sticky over multiple CPU init calls */
setup_force_cpu_cap(X86_FEATURE_ART);
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index d74743c8d2a4..6a1d22e8b846 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -179,15 +179,15 @@ unsigned long cpu_khz_from_msr(void)
freq_desc = (struct freq_desc *)id->driver_data;
if (freq_desc->use_msr_plat) {
- rdmsrq(MSR_PLATFORM_INFO, val.q);
+ val.q = rdmsrq(MSR_PLATFORM_INFO);
ratio = (val.l >> 8) & 0xff;
} else {
- rdmsrq(MSR_IA32_PERF_STATUS, val.q);
+ val.q = rdmsrq(MSR_IA32_PERF_STATUS);
ratio = (val.h >> 8) & 0x1f;
}
/* Get FSB FREQ ID */
- rdmsrq(MSR_FSB_FREQ, val.q);
+ val.q = rdmsrq(MSR_FSB_FREQ);
index = val.l & freq_desc->mask;
md = &freq_desc->muldiv[index];
diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index ec3aa340d351..a21ea3c85f6f 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -66,7 +66,7 @@ void tsc_verify_tsc_adjust(bool resume)
adj->nextcheck = jiffies + HZ;
- rdmsrq(MSR_IA32_TSC_ADJUST, curval);
+ curval = rdmsrq(MSR_IA32_TSC_ADJUST);
if (adj->adjusted == curval)
return;
@@ -166,7 +166,7 @@ bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
if (check_tsc_unstable())
return false;
- rdmsrq(MSR_IA32_TSC_ADJUST, bootval);
+ bootval = rdmsrq(MSR_IA32_TSC_ADJUST);
cur->bootval = bootval;
cur->nextcheck = jiffies + HZ;
tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu);
@@ -188,7 +188,7 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)
if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
return false;
- rdmsrq(MSR_IA32_TSC_ADJUST, bootval);
+ bootval = rdmsrq(MSR_IA32_TSC_ADJUST);
cur->bootval = bootval;
cur->nextcheck = jiffies + HZ;
cur->warned = false;
diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
index c18286545a7a..5ebee82dba84 100644
--- a/arch/x86/kvm/svm/pmu.c
+++ b/arch/x86/kvm/svm/pmu.c
@@ -249,7 +249,7 @@ static void amd_mediated_pmu_load(struct kvm_vcpu *vcpu)
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
u64 global_status;
- rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, global_status);
+ global_status = rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS);
/* Clear host global_status MSR if non-zero. */
if (global_status)
wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, global_status);
@@ -263,7 +263,7 @@ static void amd_mediated_pmu_put(struct kvm_vcpu *vcpu)
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);
- rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, pmu->global_status);
+ pmu->global_status = rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS);
/* Clear global status bits if non-zero */
if (pmu->global_status)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 9658ce4e0294..977112d8713c 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -4619,7 +4619,7 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu, u64 run_flags)
kvm_clear_available_registers(vcpu, SVM_REGS_LAZY_LOAD_SET);
if (!msr_write_intercepted(svm, MSR_AMD64_PERF_CNTR_GLOBAL_CTL))
- rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, vcpu_to_pmu(vcpu)->global_ctrl);
+ vcpu_to_pmu(vcpu)->global_ctrl = rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL);
trace_kvm_exit(vcpu, KVM_ISA_SVM);
@@ -5482,7 +5482,7 @@ static __init void svm_adjust_mmio_mask(void)
return;
/* If memory encryption is not enabled, use existing mask */
- rdmsrq(MSR_AMD64_SYSCFG, msr);
+ msr = rdmsrq(MSR_AMD64_SYSCFG);
if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
return;
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 6957bb6f5cf7..920521796743 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -7352,8 +7352,8 @@ static void nested_vmx_setup_cr_fixed(struct nested_vmx_msrs *msrs)
msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
/* These MSRs specify bits which the guest must keep fixed off. */
- rdmsrq(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
- rdmsrq(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
+ msrs->cr0_fixed1 = rdmsrq(MSR_IA32_VMX_CR0_FIXED1);
+ msrs->cr4_fixed1 = rdmsrq(MSR_IA32_VMX_CR4_FIXED1);
if (vmx_umip_emulated())
msrs->cr4_fixed1 |= X86_CR4_UMIP;
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 1944939c4139..5eb5636704bc 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -320,7 +320,7 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
int err = 0;
if (read)
- rdmsrq(index, msr_info->data);
+ msr_info->data = rdmsrq(index);
else
err = wrmsrq_safe(index, msr_info->data);
__set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
@@ -772,7 +772,7 @@ static bool intel_pmu_is_mediated_pmu_supported(struct x86_pmu_capability *host_
u64 host_perf_cap = 0;
if (boot_cpu_has(X86_FEATURE_PDCM))
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, host_perf_cap);
+ host_perf_cap = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
/*
* Require v4+ for MSR_CORE_PERF_GLOBAL_STATUS_SET, and full-width
@@ -802,7 +802,7 @@ static void intel_mediated_pmu_load(struct kvm_vcpu *vcpu)
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
u64 global_status, toggle;
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, global_status);
+ global_status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
toggle = pmu->global_status ^ global_status;
if (global_status & toggle)
wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, global_status & toggle);
@@ -817,7 +817,7 @@ static void intel_mediated_pmu_put(struct kvm_vcpu *vcpu)
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
/* MSR_CORE_PERF_GLOBAL_CTRL is already saved at VM-exit. */
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, pmu->global_status);
+ pmu->global_status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
/* Clear hardware MSR_CORE_PERF_GLOBAL_STATUS MSR, if non-zero. */
if (pmu->global_status)
diff --git a/arch/x86/kvm/vmx/sgx.c b/arch/x86/kvm/vmx/sgx.c
index 771c75a58343..765cac151023 100644
--- a/arch/x86/kvm/vmx/sgx.c
+++ b/arch/x86/kvm/vmx/sgx.c
@@ -420,9 +420,9 @@ void setup_default_sgx_lepubkeyhash(void)
sgx_pubkey_hash[3] = 0xd4f8c05909f9bb3bULL;
} else {
/* MSR_IA32_SGXLEPUBKEYHASH0 is read above */
- rdmsrq(MSR_IA32_SGXLEPUBKEYHASH1, sgx_pubkey_hash[1]);
- rdmsrq(MSR_IA32_SGXLEPUBKEYHASH2, sgx_pubkey_hash[2]);
- rdmsrq(MSR_IA32_SGXLEPUBKEYHASH3, sgx_pubkey_hash[3]);
+ sgx_pubkey_hash[1] = rdmsrq(MSR_IA32_SGXLEPUBKEYHASH1);
+ sgx_pubkey_hash[2] = rdmsrq(MSR_IA32_SGXLEPUBKEYHASH2);
+ sgx_pubkey_hash[3] = rdmsrq(MSR_IA32_SGXLEPUBKEYHASH3);
}
}
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 49948bbaf2de..3d53b5bb6914 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -1246,13 +1246,13 @@ static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
{
u32 i;
- rdmsrq(MSR_IA32_RTIT_STATUS, ctx->status);
- rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
- rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
- rdmsrq(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
+ ctx->status = rdmsrq(MSR_IA32_RTIT_STATUS);
+ ctx->output_base = rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE);
+ ctx->output_mask = rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK);
+ ctx->cr3_match = rdmsrq(MSR_IA32_RTIT_CR3_MATCH);
for (i = 0; i < addr_range; i++) {
- rdmsrq(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
- rdmsrq(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
+ ctx->addr_a[i] = rdmsrq(MSR_IA32_RTIT_ADDR0_A + i * 2);
+ ctx->addr_b[i] = rdmsrq(MSR_IA32_RTIT_ADDR0_B + i * 2);
}
}
@@ -1265,7 +1265,7 @@ static void pt_guest_enter(struct vcpu_vmx *vmx)
* GUEST_IA32_RTIT_CTL is already set in the VMCS.
* Save host state before VM entry.
*/
- rdmsrq(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
+ vmx->pt_desc.host.ctl = rdmsrq(MSR_IA32_RTIT_CTL);
if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
wrmsrq(MSR_IA32_RTIT_CTL, 0);
pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
@@ -1403,7 +1403,7 @@ static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
++vmx->vcpu.stat.host_state_reload;
#ifdef CONFIG_X86_64
- rdmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
+ vmx->msr_guest_kernel_gs_base = rdmsrq(MSR_KERNEL_GS_BASE);
#endif
if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
kvm_load_ldt(host_state->ldt_sel);
@@ -2679,7 +2679,7 @@ static int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, u32 msr, u32 *result)
struct msr vmx_msr;
u32 ctl = ctl_min | ctl_opt;
- rdmsrq(msr, vmx_msr.q);
+ vmx_msr.q = rdmsrq(msr);
ctl &= vmx_msr.h; /* bit == 0 in high word ==> must be zero */
ctl |= vmx_msr.l; /* bit == 1 in low word ==> must be one */
@@ -2696,7 +2696,7 @@ static u64 adjust_vmx_controls64(u64 ctl_opt, u32 msr)
{
u64 allowed;
- rdmsrq(msr, allowed);
+ allowed = rdmsrq(msr);
return ctl_opt & allowed;
}
@@ -2882,7 +2882,7 @@ static int setup_vmcs_config(struct vmcs_config *vmcs_conf,
break;
}
- rdmsrq(MSR_IA32_VMX_BASIC, basic_msr);
+ basic_msr = rdmsrq(MSR_IA32_VMX_BASIC);
/* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
if (vmx_basic_vmcs_size(basic_msr) > PAGE_SIZE)
@@ -2902,7 +2902,7 @@ static int setup_vmcs_config(struct vmcs_config *vmcs_conf,
if (vmx_basic_vmcs_mem_type(basic_msr) != X86_MEMTYPE_WB)
return -EIO;
- rdmsrq(MSR_IA32_VMX_MISC, misc_msr);
+ misc_msr = rdmsrq(MSR_IA32_VMX_MISC);
vmcs_conf->basic = basic_msr;
vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
@@ -4478,7 +4478,7 @@ void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
- rdmsrq(MSR_IA32_SYSENTER_CS, val.q);
+ val.q = rdmsrq(MSR_IA32_SYSENTER_CS);
vmcs_write32(HOST_IA32_SYSENTER_CS, val.l);
/*
@@ -4490,11 +4490,11 @@ void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
if (!IS_ENABLED(CONFIG_IA32_EMULATION) && !IS_ENABLED(CONFIG_X86_32))
vmcs_writel(HOST_IA32_SYSENTER_ESP, 0);
- rdmsrq(MSR_IA32_SYSENTER_EIP, tmpl);
+ tmpl = rdmsrq(MSR_IA32_SYSENTER_EIP);
vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
- rdmsrq(MSR_IA32_CR_PAT, val.q);
+ val.q = rdmsrq(MSR_IA32_CR_PAT);
vmcs_write64(HOST_IA32_PAT, val.q);
}
@@ -7152,7 +7152,7 @@ static void handle_nm_fault_irqoff(struct kvm_vcpu *vcpu)
* the #NM exception.
*/
if (is_xfd_nm_fault(vcpu))
- rdmsrq(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
+ vcpu->arch.guest_fpu.xfd_err = rdmsrq(MSR_IA32_XFD_ERR);
}
static void handle_exception_irqoff(struct kvm_vcpu *vcpu, u32 intr_info)
@@ -8043,7 +8043,7 @@ static __init u64 vmx_get_perf_capabilities(void)
return 0;
if (boot_cpu_has(X86_FEATURE_PDCM))
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, host_perf_cap);
+ host_perf_cap = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) &&
!enable_mediated_pmu) {
@@ -8600,7 +8600,7 @@ __init int vmx_hardware_setup(void)
vmx_setup_user_return_msrs();
if (boot_cpu_has(X86_FEATURE_MPX)) {
- rdmsrq(MSR_IA32_BNDCFGS, host_bndcfgs);
+ host_bndcfgs = rdmsrq(MSR_IA32_BNDCFGS);
WARN_ONCE(host_bndcfgs, "BNDCFGS in host will be lost");
}
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 9b645563ece9..7abe482efe46 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -3859,7 +3859,7 @@ static __always_inline void kvm_access_xstate_msr(struct kvm_vcpu *vcpu,
kvm_fpu_get();
if (access == MSR_TYPE_R)
- rdmsrq(msr_info->index, msr_info->data);
+ msr_info->data = rdmsrq(msr_info->index);
else
wrmsrq(msr_info->index, msr_info->data);
kvm_fpu_put();
@@ -10098,7 +10098,7 @@ int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
}
if (boot_cpu_has(X86_FEATURE_SHSTK) || boot_cpu_has(X86_FEATURE_IBT)) {
- rdmsrq(MSR_IA32_S_CET, kvm_host.s_cet);
+ kvm_host.s_cet = rdmsrq(MSR_IA32_S_CET);
/*
* Linux doesn't yet support supervisor shadow stacks (SSS), so
* KVM doesn't save/restore the associated MSRs, i.e. KVM may
@@ -10130,7 +10130,7 @@ int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
}
if (boot_cpu_has(X86_FEATURE_XSAVES)) {
- rdmsrq(MSR_IA32_XSS, kvm_host.xss);
+ kvm_host.xss = rdmsrq(MSR_IA32_XSS);
kvm_caps.supported_xss = kvm_host.xss & KVM_SUPPORTED_XSS;
}
@@ -10142,7 +10142,7 @@ int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
kvm_init_pmu_capability(ops->pmu_ops);
if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
- rdmsrq(MSR_IA32_ARCH_CAPABILITIES, kvm_host.arch_capabilities);
+ kvm_host.arch_capabilities = rdmsrq(MSR_IA32_ARCH_CAPABILITIES);
WARN_ON_ONCE(kvm_nr_uret_msrs);
diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
index e03eeec55cfe..b9db2012a75e 100644
--- a/arch/x86/lib/insn-eval.c
+++ b/arch/x86/lib/insn-eval.c
@@ -709,16 +709,16 @@ unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx)
unsigned long base;
if (seg_reg_idx == INAT_SEG_REG_FS) {
- rdmsrq(MSR_FS_BASE, base);
+ base = rdmsrq(MSR_FS_BASE);
} else if (seg_reg_idx == INAT_SEG_REG_GS) {
/*
* swapgs was called at the kernel entry point. Thus,
* MSR_KERNEL_GS_BASE will have the user-space GS base.
*/
if (user_mode(regs))
- rdmsrq(MSR_KERNEL_GS_BASE, base);
+ base = rdmsrq(MSR_KERNEL_GS_BASE);
else
- rdmsrq(MSR_GS_BASE, base);
+ base = rdmsrq(MSR_GS_BASE);
} else {
base = 0;
}
diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c
index 7b6cfc2c0970..ddff68050322 100644
--- a/arch/x86/lib/msr-smp.c
+++ b/arch/x86/lib/msr-smp.c
@@ -15,7 +15,7 @@ static void __rdmsr_on_cpu(void *info)
else
reg = &rv->reg;
- rdmsrq(rv->msr_no, reg->q);
+ reg->q = rdmsrq(rv->msr_no);
}
static void __wrmsr_on_cpu(void *info)
diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
index cf94fb561310..114853c212ed 100644
--- a/arch/x86/mm/pat/memtype.c
+++ b/arch/x86/mm/pat/memtype.c
@@ -257,7 +257,7 @@ void __init pat_bp_init(void)
if (!cpu_feature_enabled(X86_FEATURE_PAT))
pat_disable("PAT not supported by the CPU.");
else
- rdmsrq(MSR_IA32_CR_PAT, pat_msr_val);
+ pat_msr_val = rdmsrq(MSR_IA32_CR_PAT);
if (!pat_msr_val) {
pat_disable("PAT support disabled by the firmware.");
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 99b1727136c1..342371081f60 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -202,7 +202,7 @@ static int __init early_root_info_init(void)
/* need to take out [0, TOM) for RAM*/
address = MSR_K8_TOP_MEM1;
- rdmsrq(address, val);
+ val = rdmsrq(address);
end = (val & 0xffffff800000ULL);
printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
if (end < (1ULL<<32))
@@ -293,12 +293,12 @@ static int __init early_root_info_init(void)
/* need to take out [4G, TOM2) for RAM*/
/* SYS_CFG */
address = MSR_AMD64_SYSCFG;
- rdmsrq(address, val);
+ val = rdmsrq(address);
/* TOP_MEM2 is enabled? */
if (val & (1<<21)) {
/* TOP_MEM2 */
address = MSR_K8_TOP_MEM2;
- rdmsrq(address, val);
+ val = rdmsrq(address);
end = (val & 0xffffff800000ULL);
printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
subtract_range(range, RANGE_NUM, 1ULL<<32, end);
@@ -341,7 +341,7 @@ static int amd_bus_cpu_online(unsigned int cpu)
{
u64 reg;
- rdmsrq(MSR_AMD64_NB_CFG, reg);
+ reg = rdmsrq(MSR_AMD64_NB_CFG);
if (!(reg & ENABLE_CF8_EXT_CFG)) {
reg |= ENABLE_CF8_EXT_CFG;
wrmsrq(MSR_AMD64_NB_CFG, reg);
diff --git a/arch/x86/platform/olpc/olpc-xo1-rtc.c b/arch/x86/platform/olpc/olpc-xo1-rtc.c
index ee77d57bcab7..95dfd90b1f05 100644
--- a/arch/x86/platform/olpc/olpc-xo1-rtc.c
+++ b/arch/x86/platform/olpc/olpc-xo1-rtc.c
@@ -64,9 +64,9 @@ static int __init xo1_rtc_init(void)
of_node_put(node);
pr_info("olpc-xo1-rtc: Initializing OLPC XO-1 RTC\n");
- rdmsrq(MSR_RTC_DOMA_OFFSET, rtc_info.rtc_day_alarm);
- rdmsrq(MSR_RTC_MONA_OFFSET, rtc_info.rtc_mon_alarm);
- rdmsrq(MSR_RTC_CEN_OFFSET, rtc_info.rtc_century);
+ rtc_info.rtc_day_alarm = rdmsrq(MSR_RTC_DOMA_OFFSET);
+ rtc_info.rtc_mon_alarm = rdmsrq(MSR_RTC_MONA_OFFSET);
+ rtc_info.rtc_century = rdmsrq(MSR_RTC_CEN_OFFSET);
r = platform_device_register(&xo1_rtc_device);
if (r)
diff --git a/arch/x86/platform/olpc/olpc-xo1-sci.c b/arch/x86/platform/olpc/olpc-xo1-sci.c
index 97eb4738d602..b2e12d780e58 100644
--- a/arch/x86/platform/olpc/olpc-xo1-sci.c
+++ b/arch/x86/platform/olpc/olpc-xo1-sci.c
@@ -316,7 +316,7 @@ static int setup_sci_interrupt(struct platform_device *pdev)
u32 sts;
int r;
- rdmsrq(0x51400020, msr);
+ msr = rdmsrq(0x51400020);
sci_irq = (msr >> 20) & 15;
if (sci_irq) {
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index 702f30eaf9c4..f44ebe2fe099 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -45,7 +45,7 @@ static void msr_save_context(struct saved_context *ctxt)
while (msr < end) {
if (msr->valid)
- rdmsrq(msr->info.msr_no, msr->info.reg.q);
+ msr->info.reg.q = rdmsrq(msr->info.msr_no);
msr++;
}
}
@@ -111,12 +111,12 @@ static void __save_processor_state(struct saved_context *ctxt)
savesegment(ds, ctxt->ds);
savesegment(es, ctxt->es);
- rdmsrq(MSR_FS_BASE, ctxt->fs_base);
- rdmsrq(MSR_GS_BASE, ctxt->kernelmode_gs_base);
- rdmsrq(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
+ ctxt->fs_base = rdmsrq(MSR_FS_BASE);
+ ctxt->kernelmode_gs_base = rdmsrq(MSR_GS_BASE);
+ ctxt->usermode_gs_base = rdmsrq(MSR_KERNEL_GS_BASE);
mtrr_save_fixed_ranges(NULL);
- rdmsrq(MSR_EFER, ctxt->efer);
+ ctxt->efer = rdmsrq(MSR_EFER);
#endif
/*
diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c
index 694d80a5c68e..469f2aa8e105 100644
--- a/arch/x86/realmode/init.c
+++ b/arch/x86/realmode/init.c
@@ -147,7 +147,7 @@ static void __init setup_real_mode(void)
* Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR
* so we need to mask it out.
*/
- rdmsrq(MSR_EFER, efer);
+ efer = rdmsrq(MSR_EFER);
trampoline_header->efer = efer & ~EFER_LMA;
trampoline_header->start = (u64) secondary_startup_64;
diff --git a/arch/x86/virt/hw.c b/arch/x86/virt/hw.c
index 7e9091c640be..a2e4b99d7276 100644
--- a/arch/x86/virt/hw.c
+++ b/arch/x86/virt/hw.c
@@ -178,7 +178,7 @@ static __init int __x86_vmx_init(void)
if (!cpu_feature_enabled(X86_FEATURE_VMX))
return -EOPNOTSUPP;
- rdmsrq(MSR_IA32_VMX_BASIC, basic_msr);
+ basic_msr = rdmsrq(MSR_IA32_VMX_BASIC);
/* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
if (WARN_ON_ONCE(vmx_basic_vmcs_size(basic_msr) > PAGE_SIZE))
@@ -230,7 +230,7 @@ static int x86_svm_enable_virtualization_cpu(void)
{
u64 efer;
- rdmsrq(MSR_EFER, efer);
+ efer = rdmsrq(MSR_EFER);
if (efer & EFER_SVME)
return -EBUSY;
@@ -253,7 +253,7 @@ static int x86_svm_disable_virtualization_cpu(void)
r = 0;
fault:
- rdmsrq(MSR_EFER, efer);
+ efer = rdmsrq(MSR_EFER);
wrmsrq(MSR_EFER, efer & ~EFER_SVME);
return r;
}
@@ -264,7 +264,7 @@ static void x86_svm_emergency_disable_virtualization_cpu(void)
virt_rebooting = true;
- rdmsrq(MSR_EFER, efer);
+ efer = rdmsrq(MSR_EFER);
if (!(efer & EFER_SVME))
return;
diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c
index 8bcdce98f6dc..124566c56e59 100644
--- a/arch/x86/virt/svm/sev.c
+++ b/arch/x86/virt/svm/sev.c
@@ -150,7 +150,7 @@ static void snp_enable(void *arg)
if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP))
return;
- rdmsrq(MSR_AMD64_SYSCFG, val);
+ val = rdmsrq(MSR_AMD64_SYSCFG);
val |= MSR_AMD64_SYSCFG_SNP_EN;
val |= MSR_AMD64_SYSCFG_SNP_VMPL_EN;
@@ -254,7 +254,7 @@ static void clear_rmp(void)
return;
/* Clearing the RMP while SNP is enabled will cause an exception */
- rdmsrq(MSR_AMD64_SYSCFG, val);
+ val = rdmsrq(MSR_AMD64_SYSCFG);
if (WARN_ON_ONCE(val & MSR_AMD64_SYSCFG_SNP_EN))
return;
@@ -520,7 +520,7 @@ int snp_prepare(void)
* Check if SEV-SNP is already enabled, this can happen in case of
* kexec boot.
*/
- rdmsrq(MSR_AMD64_SYSCFG, val);
+ val = rdmsrq(MSR_AMD64_SYSCFG);
if (val & MSR_AMD64_SYSCFG_SNP_EN)
return 0;
@@ -559,7 +559,7 @@ void snp_shutdown(void)
{
u64 syscfg;
- rdmsrq(MSR_AMD64_SYSCFG, syscfg);
+ syscfg = rdmsrq(MSR_AMD64_SYSCFG);
if (syscfg & MSR_AMD64_SYSCFG_SNP_EN)
return;
@@ -606,8 +606,8 @@ static bool probe_contiguous_rmptable_info(void)
{
u64 rmp_sz, rmp_base, rmp_end;
- rdmsrq(MSR_AMD64_RMP_BASE, rmp_base);
- rdmsrq(MSR_AMD64_RMP_END, rmp_end);
+ rmp_base = rdmsrq(MSR_AMD64_RMP_BASE);
+ rmp_end = rdmsrq(MSR_AMD64_RMP_END);
if (!(rmp_base & RMP_ADDR_MASK) || !(rmp_end & RMP_ADDR_MASK)) {
pr_err("Memory for the RMP table has not been reserved by BIOS\n");
@@ -640,13 +640,13 @@ static bool probe_segmented_rmptable_info(void)
unsigned int eax, ebx, segment_shift, segment_shift_min, segment_shift_max;
u64 rmp_base, rmp_end;
- rdmsrq(MSR_AMD64_RMP_BASE, rmp_base);
+ rmp_base = rdmsrq(MSR_AMD64_RMP_BASE);
if (!(rmp_base & RMP_ADDR_MASK)) {
pr_err("Memory for the RMP table has not been reserved by BIOS\n");
return false;
}
- rdmsrq(MSR_AMD64_RMP_END, rmp_end);
+ rmp_end = rdmsrq(MSR_AMD64_RMP_END);
WARN_ONCE(rmp_end & RMP_ADDR_MASK,
"Segmented RMP enabled but RMP_END MSR is non-zero\n");
@@ -682,7 +682,7 @@ static bool probe_segmented_rmptable_info(void)
bool snp_probe_rmptable_info(void)
{
if (cpu_feature_enabled(X86_FEATURE_SEGMENTED_RMP))
- rdmsrq(MSR_AMD64_RMP_CFG, rmp_cfg);
+ rmp_cfg = rdmsrq(MSR_AMD64_RMP_CFG);
if (rmp_cfg & MSR_AMD64_SEG_RMP_ENABLED)
return probe_segmented_rmptable_info();
diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c
index 1b9ff749dd8e..9839f5b8dcc3 100644
--- a/arch/x86/virt/vmx/tdx/tdx.c
+++ b/arch/x86/virt/vmx/tdx/tdx.c
@@ -1523,7 +1523,7 @@ static void __init check_tdx_erratum(void)
* Some TDX-capable CPUs have an erratum where the current VMCS is
* cleared after calling into P-SEAMLDR.
*/
- rdmsrq(MSR_IA32_VMX_BASIC, basic_msr);
+ basic_msr = rdmsrq(MSR_IA32_VMX_BASIC);
if (!(basic_msr & VMX_BASIC_NO_SEAMRET_INVD_VMCS))
setup_force_cpu_bug(X86_BUG_SEAMRET_INVD_VMCS);
}
diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c
index ba2f17e64321..b0e1152aa80e 100644
--- a/arch/x86/xen/suspend.c
+++ b/arch/x86/xen/suspend.c
@@ -56,7 +56,7 @@ static void xen_vcpu_notify_suspend(void *data)
tick_suspend_local();
if (xen_pv_domain() && boot_cpu_has(X86_FEATURE_SPEC_CTRL)) {
- rdmsrq(MSR_IA32_SPEC_CTRL, tmp);
+ tmp = rdmsrq(MSR_IA32_SPEC_CTRL);
this_cpu_write(spec_ctrl, tmp);
wrmsrq(MSR_IA32_SPEC_CTRL, 0);
}
diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c
index 9e25d6124efd..535a0f9dd2cf 100644
--- a/drivers/acpi/processor_perflib.c
+++ b/drivers/acpi/processor_perflib.c
@@ -296,7 +296,7 @@ static void amd_fixup_frequency(struct acpi_processor_px *px, int i)
if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10) ||
boot_cpu_data.x86 == 0x11) {
- rdmsrq(MSR_AMD_PSTATE_DEF_BASE + index, val.q);
+ val.q = rdmsrq(MSR_AMD_PSTATE_DEF_BASE + index);
/*
* MSR C001_0064+:
* Bit 63: PstateEn. Read-write. If set, the P-state is valid.
diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c
index da98390cc49e..e38eecaea1b0 100644
--- a/drivers/ata/pata_cs5535.c
+++ b/drivers/ata/pata_cs5535.c
@@ -110,7 +110,7 @@ static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
pio_cmd_timings[cmdmode] << 16 | pio_timings[mode]);
/* Set the PIO "format 1" bit in the DMA timing register */
- rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg);
+ reg = rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno);
wrmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL);
}
@@ -132,7 +132,7 @@ static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
u32 reg;
int mode = adev->dma_mode;
- rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg);
+ reg = rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno);
reg &= 0x80000000UL;
if (mode >= XFER_UDMA_0)
reg |= udma_timings[mode - XFER_UDMA_0];
diff --git a/drivers/ata/pata_cs5536.c b/drivers/ata/pata_cs5536.c
index 61d232a82b5e..eca97dce1e85 100644
--- a/drivers/ata/pata_cs5536.c
+++ b/drivers/ata/pata_cs5536.c
@@ -84,7 +84,7 @@ static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
{
#ifdef MAYBE_USE_MSR
if (unlikely(use_msr)) {
- rdmsrq(MSR_IDE_CFG + reg, *val);
+ *val = rdmsrq(MSR_IDE_CFG + reg);
return 0;
}
#endif
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index 3e760bc00afa..f646f1854981 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -72,8 +72,8 @@ static int nvidia_init_iorr(u32 base, u32 size)
/* If not found, determine the uppermost available iorr */
free_iorr_addr = AMD_K7_NUM_IORR;
for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
- rdmsrq(IORR_BASE0 + 2 * iorr_addr, base_msr.q);
- rdmsrq(IORR_MASK0 + 2 * iorr_addr, mask_msr.q);
+ base_msr.q = rdmsrq(IORR_BASE0 + 2 * iorr_addr);
+ mask_msr.q = rdmsrq(IORR_MASK0 + 2 * iorr_addr);
if ((base_msr.l & 0xfffff000) == (base & 0xfffff000))
break;
@@ -94,7 +94,7 @@ static int nvidia_init_iorr(u32 base, u32 size)
wrmsrq(IORR_BASE0 + 2 * iorr_addr, base_msr.q);
wrmsrq(IORR_MASK0 + 2 * iorr_addr, mask_msr.q);
- rdmsrq(SYSCFG, sys_msr.q);
+ sys_msr.q = rdmsrq(SYSCFG);
sys_msr.l |= 0x00100000;
wrmsrq(SYSCFG, sys_msr.q);
diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
index b718e78d3c1c..a0a3488a6947 100644
--- a/drivers/char/hw_random/via-rng.c
+++ b/drivers/char/hw_random/via-rng.c
@@ -151,7 +151,7 @@ static int via_rng_init(struct hwrng *rng)
* does not say to write them as zero, so I make a guess that
* we restore the values we find in the register.
*/
- rdmsrq(MSR_VIA_RNG, val.q);
+ val.q = rdmsrq(MSR_VIA_RNG);
old_lo = val.l;
val.l &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
@@ -175,7 +175,7 @@ static int via_rng_init(struct hwrng *rng)
/* perhaps-unnecessary sanity check; remove after testing if
unneeded */
- rdmsrq(MSR_VIA_RNG, val.q);
+ val.q = rdmsrq(MSR_VIA_RNG);
if ((val.l & VIA_RNG_ENABLE) == 0) {
pr_err(PFX "cannot enable VIA C3 RNG, aborting\n");
return -ENODEV;
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index b40fa99b5ab2..cb59ed6926f2 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -110,7 +110,7 @@ static int boost_set_msr(bool enable)
return -EINVAL;
}
- rdmsrq(msr_addr, val);
+ val = rdmsrq(msr_addr);
if (enable)
val &= ~msr_mask;
@@ -248,7 +248,7 @@ static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used)
{
u64 val;
- rdmsrq(MSR_IA32_PERF_CTL, val);
+ val = rdmsrq(MSR_IA32_PERF_CTL);
return (u32)val;
}
@@ -256,7 +256,7 @@ static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val)
{
struct msr msrval;
- rdmsrq(MSR_IA32_PERF_CTL, msrval.q);
+ msrval.q = rdmsrq(MSR_IA32_PERF_CTL);
msrval.h = (msrval.h & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
wrmsrq(MSR_IA32_PERF_CTL, msrval.q);
}
@@ -265,7 +265,7 @@ static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used)
{
u64 val;
- rdmsrq(MSR_AMD_PERF_CTL, val);
+ val = rdmsrq(MSR_AMD_PERF_CTL);
return (u32)val;
}
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index a74a4cf99d22..acccceb5abf5 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -607,8 +607,8 @@ static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)
unsigned long flags;
local_irq_save(flags);
- rdmsrq(MSR_IA32_APERF, aperf);
- rdmsrq(MSR_IA32_MPERF, mperf);
+ aperf = rdmsrq(MSR_IA32_APERF);
+ mperf = rdmsrq(MSR_IA32_MPERF);
tsc = rdtsc();
if (cpudata->prev.mperf == mperf || cpudata->prev.tsc == tsc) {
diff --git a/drivers/cpufreq/e_powersaver.c b/drivers/cpufreq/e_powersaver.c
index 13709f9667ea..5cd68b51bc7a 100644
--- a/drivers/cpufreq/e_powersaver.c
+++ b/drivers/cpufreq/e_powersaver.c
@@ -99,7 +99,7 @@ static unsigned int eps_get(unsigned int cpu)
return 0;
/* Return current frequency */
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
return centaur->fsb * ((val >> 8) & 0xff);
}
@@ -111,11 +111,11 @@ static int eps_set_state(struct eps_cpu_data *centaur,
int i;
/* Wait while CPU is busy */
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
i = 0;
while (val & ((1 << 16) | (1 << 17))) {
udelay(16);
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
i++;
if (unlikely(i > 64)) {
return -ENODEV;
@@ -127,7 +127,7 @@ static int eps_set_state(struct eps_cpu_data *centaur,
i = 0;
do {
udelay(16);
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
i++;
if (unlikely(i > 64)) {
return -ENODEV;
@@ -139,7 +139,7 @@ static int eps_set_state(struct eps_cpu_data *centaur,
u8 current_multiplier, current_voltage;
/* Print voltage and multiplier */
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
current_voltage = val & 0xff;
pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
current_multiplier = (val >> 8) & 0xff;
@@ -195,12 +195,12 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
switch (c->x86_model) {
case 10:
- rdmsrq(0x1153, val);
+ val = rdmsrq(0x1153);
brand = (((val >> 2) ^ val) >> 18) & 3;
pr_cont("Model A ");
break;
case 13:
- rdmsrq(0x1154, val);
+ val = rdmsrq(0x1154);
brand = (((val >> 4) ^ (val >> 2))) & 0x000000ff;
pr_cont("Model D ");
break;
@@ -224,12 +224,12 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
return -ENODEV;
}
/* Enable Enhanced PowerSaver */
- rdmsrq(MSR_IA32_MISC_ENABLE, val);
+ val = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
val |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
wrmsrq(MSR_IA32_MISC_ENABLE, val);
/* Can be locked at 0 */
- rdmsrq(MSR_IA32_MISC_ENABLE, val);
+ val = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
pr_info("Can't enable Enhanced PowerSaver\n");
return -ENODEV;
@@ -237,7 +237,7 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
}
/* Print voltage and multiplier */
- rdmsrq(MSR_IA32_PERF_STATUS, status.q);
+ status.q = rdmsrq(MSR_IA32_PERF_STATUS);
current_voltage = status.l & 0xff;
pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
current_multiplier = (status.l >> 8) & 0xff;
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 5a0eeb84d382..7328ba57df50 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -608,7 +608,7 @@ static bool turbo_is_disabled(void)
{
u64 misc_en;
- rdmsrq(MSR_IA32_MISC_ENABLE, misc_en);
+ misc_en = rdmsrq(MSR_IA32_MISC_ENABLE);
return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
}
@@ -1395,7 +1395,7 @@ static void set_power_ctl_ee_state(bool input)
guard(mutex)(&intel_pstate_driver_lock);
- rdmsrq(MSR_IA32_POWER_CTL, power_ctl);
+ power_ctl = rdmsrq(MSR_IA32_POWER_CTL);
if (input) {
power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
power_ctl_ee_state = POWER_CTL_EE_ENABLE;
@@ -1772,7 +1772,7 @@ static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribut
u64 power_ctl;
int enable;
- rdmsrq(MSR_IA32_POWER_CTL, power_ctl);
+ power_ctl = rdmsrq(MSR_IA32_POWER_CTL);
enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
return sprintf(buf, "%d\n", !enable);
}
@@ -2066,7 +2066,7 @@ static int atom_get_min_pstate(int not_used)
{
u64 value;
- rdmsrq(MSR_ATOM_CORE_RATIOS, value);
+ value = rdmsrq(MSR_ATOM_CORE_RATIOS);
return (value >> 8) & 0x7F;
}
@@ -2074,7 +2074,7 @@ static int atom_get_max_pstate(int not_used)
{
u64 value;
- rdmsrq(MSR_ATOM_CORE_RATIOS, value);
+ value = rdmsrq(MSR_ATOM_CORE_RATIOS);
return (value >> 16) & 0x7F;
}
@@ -2082,7 +2082,7 @@ static int atom_get_turbo_pstate(int not_used)
{
u64 value;
- rdmsrq(MSR_ATOM_CORE_TURBO_RATIOS, value);
+ value = rdmsrq(MSR_ATOM_CORE_TURBO_RATIOS);
return value & 0x7F;
}
@@ -2113,7 +2113,7 @@ static int silvermont_get_scaling(void)
static int silvermont_freq_table[] = {
83300, 100000, 133300, 116700, 80000};
- rdmsrq(MSR_FSB_FREQ, value);
+ value = rdmsrq(MSR_FSB_FREQ);
i = value & 0x7;
WARN_ON(i > 4);
@@ -2129,7 +2129,7 @@ static int airmont_get_scaling(void)
83300, 100000, 133300, 116700, 80000,
93300, 90000, 88900, 87500};
- rdmsrq(MSR_FSB_FREQ, value);
+ value = rdmsrq(MSR_FSB_FREQ);
i = value & 0xF;
WARN_ON(i > 8);
@@ -2140,7 +2140,7 @@ static void atom_get_vid(struct cpudata *cpudata)
{
u64 value;
- rdmsrq(MSR_ATOM_CORE_VIDS, value);
+ value = rdmsrq(MSR_ATOM_CORE_VIDS);
cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
cpudata->vid.ratio = div_fp(
@@ -2148,7 +2148,7 @@ static void atom_get_vid(struct cpudata *cpudata)
int_tofp(cpudata->pstate.max_pstate -
cpudata->pstate.min_pstate));
- rdmsrq(MSR_ATOM_CORE_TURBO_VIDS, value);
+ value = rdmsrq(MSR_ATOM_CORE_TURBO_VIDS);
cpudata->vid.turbo = value & 0x7f;
}
@@ -2483,8 +2483,8 @@ static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
u64 tsc;
local_irq_save(flags);
- rdmsrq(MSR_IA32_APERF, aperf);
- rdmsrq(MSR_IA32_MPERF, mperf);
+ aperf = rdmsrq(MSR_IA32_APERF);
+ mperf = rdmsrq(MSR_IA32_MPERF);
tsc = rdtsc();
if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
local_irq_restore(flags);
@@ -3634,7 +3634,7 @@ static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
id = x86_match_cpu(intel_pstate_cpu_oob_ids);
if (id) {
- rdmsrq(MSR_MISC_PWR_MGMT, misc_pwr);
+ misc_pwr = rdmsrq(MSR_MISC_PWR_MGMT);
if (misc_pwr & BITMASK_OOB) {
pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
@@ -3690,7 +3690,7 @@ static bool intel_pstate_hwp_is_enabled(void)
{
u64 value;
- rdmsrq(MSR_PM_ENABLE, value);
+ value = rdmsrq(MSR_PM_ENABLE);
return !!(value & 0x1);
}
@@ -3755,7 +3755,7 @@ static bool hwp_check_dec(void)
{
u64 power_ctl;
- rdmsrq(MSR_IA32_POWER_CTL, power_ctl);
+ power_ctl = rdmsrq(MSR_IA32_POWER_CTL);
return !!(power_ctl & BIT(POWER_CTL_DEC_ENABLE));
}
diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
index 4c2599264333..9bc0acc0ea69 100644
--- a/drivers/cpufreq/longhaul.c
+++ b/drivers/cpufreq/longhaul.c
@@ -121,7 +121,7 @@ static int longhaul_get_cpu_mult(void)
unsigned long invalue = 0;
u64 val;
- rdmsrq(MSR_IA32_EBL_CR_POWERON, val);
+ val = rdmsrq(MSR_IA32_EBL_CR_POWERON);
invalue = (val & (1<<22|1<<23|1<<24|1<<25))>>22;
if (longhaul_version == TYPE_LONGHAUL_V2 ||
longhaul_version == TYPE_POWERSAVER) {
@@ -137,7 +137,7 @@ static void do_longhaul1(unsigned int mults_index)
{
union msr_bcr2 bcr2;
- rdmsrq(MSR_VIA_BCR2, bcr2.val);
+ bcr2.val = rdmsrq(MSR_VIA_BCR2);
/* Enable software clock multiplier */
bcr2.bits.ESOFTBF = 1;
bcr2.bits.CLOCKMUL = mults_index & 0xff;
@@ -152,7 +152,7 @@ static void do_longhaul1(unsigned int mults_index)
/* Disable software clock multiplier */
local_irq_disable();
- rdmsrq(MSR_VIA_BCR2, bcr2.val);
+ bcr2.val = rdmsrq(MSR_VIA_BCR2);
bcr2.bits.ESOFTBF = 0;
wrmsrq(MSR_VIA_BCR2, bcr2.val);
}
@@ -165,7 +165,7 @@ static void do_powersaver(int cx_address, unsigned int mults_index,
union msr_longhaul longhaul;
u32 t;
- rdmsrq(MSR_VIA_LONGHAUL, longhaul.val);
+ longhaul.val = rdmsrq(MSR_VIA_LONGHAUL);
/* Setup new frequency */
if (!revid_errata)
longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
@@ -534,7 +534,7 @@ static void longhaul_setup_voltagescaling(void)
unsigned int j, speed, pos, kHz_step, numvscales;
int min_vid_speed;
- rdmsrq(MSR_VIA_LONGHAUL, longhaul.val);
+ longhaul.val = rdmsrq(MSR_VIA_LONGHAUL);
if (!(longhaul.bits.RevisionID & 1)) {
pr_info("Voltage scaling not supported by CPU\n");
return;
@@ -836,7 +836,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
}
/* Check Longhaul ver. 2 */
if (longhaul_version == TYPE_LONGHAUL_V2) {
- rdmsrq(MSR_VIA_LONGHAUL, val);
+ val = rdmsrq(MSR_VIA_LONGHAUL);
if (val == 0)
/* Looks like MSR isn't present */
longhaul_version = TYPE_LONGHAUL_V1;
diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c
index 99abef32e7e5..f63cbb679575 100644
--- a/drivers/cpufreq/longrun.c
+++ b/drivers/cpufreq/longrun.c
@@ -37,14 +37,14 @@ static void longrun_get_policy(struct cpufreq_policy *policy)
{
struct msr msr;
- rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_FLAGS);
pr_debug("longrun flags are %x - %x\n", msr.l, msr.h);
if (msr.l & 0x01)
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
else
policy->policy = CPUFREQ_POLICY_POWERSAVE;
- rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_CTRL);
pr_debug("longrun ctrl is %x - %x\n", msr.l, msr.h);
msr.l &= 0x0000007F;
msr.h &= 0x0000007F;
@@ -93,7 +93,7 @@ static int longrun_set_policy(struct cpufreq_policy *policy)
pctg_lo = pctg_hi;
/* performance or economy mode */
- rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_FLAGS);
msr.l &= 0xFFFFFFFE;
switch (policy->policy) {
case CPUFREQ_POLICY_PERFORMANCE:
@@ -105,7 +105,7 @@ static int longrun_set_policy(struct cpufreq_policy *policy)
wrmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
/* lower and upper boundary */
- rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_CTRL);
msr.l &= 0xFFFFFF80;
msr.h &= 0xFFFFFF80;
msr.l |= pctg_lo;
@@ -178,16 +178,16 @@ static int longrun_determine_freqs(unsigned int *low_freq,
* For maximum frequency, read out level zero.
*/
/* minimum */
- rdmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LRTI_READOUT);
msr.l = msr.h;
wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
- rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ);
*low_freq = msr.l * 1000; /* to kHz */
/* maximum */
msr.l = 0;
wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
- rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ);
*high_freq = msr.l * 1000; /* to kHz */
pr_debug("longrun table interface told %u - %u kHz\n",
@@ -204,7 +204,7 @@ static int longrun_determine_freqs(unsigned int *low_freq,
pr_debug("high frequency is %u kHz\n", *high_freq);
/* get current borders */
- rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_CTRL);
save_lo = msr.l & 0x0000007F;
save_hi = msr.h & 0x0000007F;
diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c
index 6a930d7e6a5c..1df2a8f365a3 100644
--- a/drivers/cpufreq/powernow-k7.c
+++ b/drivers/cpufreq/powernow-k7.c
@@ -220,7 +220,7 @@ static void change_FID(int fid)
{
union msr_fidvidctl fidvidctl;
- rdmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val);
+ fidvidctl.val = rdmsrq(MSR_K7_FID_VID_CTL);
if (fidvidctl.bits.FID != fid) {
fidvidctl.bits.SGTC = latency;
fidvidctl.bits.FID = fid;
@@ -235,7 +235,7 @@ static void change_VID(int vid)
{
union msr_fidvidctl fidvidctl;
- rdmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val);
+ fidvidctl.val = rdmsrq(MSR_K7_FID_VID_CTL);
if (fidvidctl.bits.VID != vid) {
fidvidctl.bits.SGTC = latency;
fidvidctl.bits.VID = vid;
@@ -261,7 +261,7 @@ static int powernow_target(struct cpufreq_policy *policy, unsigned int index)
fid = powernow_table[index].driver_data & 0xFF;
vid = (powernow_table[index].driver_data & 0xFF00) >> 8;
- rdmsrq(MSR_K7_FID_VID_STATUS, fidvidstatus.val);
+ fidvidstatus.val = rdmsrq(MSR_K7_FID_VID_STATUS);
cfid = fidvidstatus.bits.CFID;
freqs.old = fsb * fid_codes[cfid] / 10;
@@ -558,7 +558,7 @@ static unsigned int powernow_get(unsigned int cpu)
if (cpu)
return 0;
- rdmsrq(MSR_K7_FID_VID_STATUS, fidvidstatus.val);
+ fidvidstatus.val = rdmsrq(MSR_K7_FID_VID_STATUS);
cfid = fidvidstatus.bits.CFID;
return fsb * fid_codes[cfid] / 10;
@@ -599,7 +599,7 @@ static int powernow_cpu_init(struct cpufreq_policy *policy)
if (policy->cpu != 0)
return -ENODEV;
- rdmsrq(MSR_K7_FID_VID_STATUS, fidvidstatus.val);
+ fidvidstatus.val = rdmsrq(MSR_K7_FID_VID_STATUS);
recalibrate_cpu_khz();
diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c
index fe1f499b4fc0..a5a986ce8f3e 100644
--- a/drivers/cpufreq/powernow-k8.c
+++ b/drivers/cpufreq/powernow-k8.c
@@ -89,7 +89,7 @@ static int pending_bit_stuck(void)
{
u64 msr;
- rdmsrq(MSR_FIDVID_STATUS, msr);
+ msr = rdmsrq(MSR_FIDVID_STATUS);
return msr & MSR_S_LO_CHANGE_PENDING ? 1 : 0;
}
@@ -107,7 +107,7 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
pr_debug("detected change pending stuck\n");
return 1;
}
- rdmsrq(MSR_FIDVID_STATUS, msr.q);
+ msr.q = rdmsrq(MSR_FIDVID_STATUS);
} while (msr.l & MSR_S_LO_CHANGE_PENDING);
data->currvid = msr.h & MSR_S_HI_CURRENT_VID;
@@ -134,7 +134,7 @@ static void fidvid_msr_init(void)
struct msr msr;
u8 fid, vid;
- rdmsrq(MSR_FIDVID_STATUS, msr.q);
+ msr.q = rdmsrq(MSR_FIDVID_STATUS);
vid = msr.h & MSR_S_HI_CURRENT_VID;
fid = msr.l & MSR_S_LO_CURRENT_FID;
msr.l = fid | (vid << MSR_C_LO_VID_SHIFT);
@@ -293,7 +293,7 @@ static int core_voltage_pre_transition(struct powernow_k8_data *data,
if ((savefid < LO_FID_TABLE_TOP) && (reqfid < LO_FID_TABLE_TOP))
rvomult = 2;
rvosteps *= rvomult;
- rdmsrq(MSR_FIDVID_STATUS, msr.q);
+ msr.q = rdmsrq(MSR_FIDVID_STATUS);
maxvid = 0x1f & (msr.h >> 16);
pr_debug("ph1 maxvid=0x%x\n", maxvid);
if (reqvid < maxvid) /* lower numbers are higher voltages */
diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
index de50fb367c6b..2e90b658bfc2 100644
--- a/drivers/cpufreq/speedstep-centrino.c
+++ b/drivers/cpufreq/speedstep-centrino.c
@@ -378,7 +378,7 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
/* Check to see if Enhanced SpeedStep is enabled, and try to
enable it if not. */
- rdmsrq(MSR_IA32_MISC_ENABLE, q);
+ q = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(q & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
q |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
@@ -386,7 +386,7 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
wrmsrq(MSR_IA32_MISC_ENABLE, q);
/* check to see if it stuck */
- rdmsrq(MSR_IA32_MISC_ENABLE, q);
+ q = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(q & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
pr_info("couldn't enable Enhanced SpeedStep\n");
return -ENODEV;
diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
index 2afc3f177a29..188d459c7e2a 100644
--- a/drivers/cpufreq/speedstep-lib.c
+++ b/drivers/cpufreq/speedstep-lib.c
@@ -74,7 +74,7 @@ static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
int i = 0, j = 0;
/* read MSR 0x2a - we only need the low 32 bits */
- rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ msr.q = rdmsrq(MSR_IA32_EBL_CR_POWERON);
pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h);
msr_tmp = msr_lo = msr.l;
@@ -112,7 +112,7 @@ static unsigned int pentiumM_get_frequency(void)
struct msr msr;
u32 msr_tmp;
- rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ msr.q = rdmsrq(MSR_IA32_EBL_CR_POWERON);
pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h);
/* see table B-2 of 24547212.pdf */
@@ -136,7 +136,7 @@ static unsigned int pentium_core_get_frequency(void)
u32 msr_tmp;
int ret;
- rdmsrq(MSR_FSB_FREQ, msr.q);
+ msr.q = rdmsrq(MSR_FSB_FREQ);
/* see table B-2 of 25366920.pdf */
switch (msr.l & 0x07) {
case 5:
@@ -161,7 +161,7 @@ static unsigned int pentium_core_get_frequency(void)
pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
}
- rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ msr.q = rdmsrq(MSR_IA32_EBL_CR_POWERON);
pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
msr.l, msr.h);
@@ -191,7 +191,7 @@ static unsigned int pentium4_get_frequency(void)
if (c->x86_model < 2)
return cpu_khz;
- rdmsrq(0x2c, msr.q);
+ msr.q = rdmsrq(0x2c);
pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr.l, msr.h);
@@ -348,7 +348,7 @@ enum speedstep_processor speedstep_detect_processor(void)
/* all mobile PIII Coppermines have FSB 100 MHz
* ==> sort out a few desktop PIIIs. */
- rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ msr.q = rdmsrq(MSR_IA32_EBL_CR_POWERON);
pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
msr.l, msr.h);
msr.l &= 0x00c0000;
@@ -361,7 +361,7 @@ enum speedstep_processor speedstep_detect_processor(void)
* it has SpeedStep technology if either
* bit 56 or 57 is set
*/
- rdmsrq(MSR_IA32_PLATFORM_ID, msr.q);
+ msr.q = rdmsrq(MSR_IA32_PLATFORM_ID);
pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
msr.l, msr.h);
if ((msr.h & (1<<18)) &&
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c6aa69dbd9fb..ef2fc2be954a 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2956,13 +2956,13 @@ static void dct_read_mc_regs(struct amd64_pvt *pvt)
* Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
* those are Read-As-Zero.
*/
- rdmsrq(MSR_K8_TOP_MEM1, pvt->top_mem);
+ pvt->top_mem = rdmsrq(MSR_K8_TOP_MEM1);
edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
/* Check first whether TOP_MEM2 is enabled: */
- rdmsrq(MSR_AMD64_SYSCFG, msr_val);
+ msr_val = rdmsrq(MSR_AMD64_SYSCFG);
if (msr_val & BIT(21)) {
- rdmsrq(MSR_K8_TOP_MEM2, pvt->top_mem2);
+ pvt->top_mem2 = rdmsrq(MSR_K8_TOP_MEM2);
edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
} else {
edac_dbg(0, " TOP_MEM2 disabled\n");
diff --git a/drivers/gpio/gpio-cs5535.c b/drivers/gpio/gpio-cs5535.c
index a97ec7561889..e9cc577e94b7 100644
--- a/drivers/gpio/gpio-cs5535.c
+++ b/drivers/gpio/gpio-cs5535.c
@@ -148,7 +148,7 @@ int cs5535_gpio_set_irq(unsigned group, unsigned irq)
if (group > 7 || irq > 15)
return -EINVAL;
- rdmsrq(MSR_PIC_ZSEL_HIGH, val.q);
+ val.q = rdmsrq(MSR_PIC_ZSEL_HIGH);
val.l &= ~(0xF << (group * 4));
val.l |= (irq & 0xF) << (group * 4);
diff --git a/drivers/hv/mshv_vtl_main.c b/drivers/hv/mshv_vtl_main.c
index 0d3d4161974f..e1e4bce49113 100644
--- a/drivers/hv/mshv_vtl_main.c
+++ b/drivers/hv/mshv_vtl_main.c
@@ -598,7 +598,7 @@ static int mshv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set)
if (set)
wrmsrq(reg_table[i].msr_addr, *reg64);
else
- rdmsrq(reg_table[i].msr_addr, *reg64);
+ *reg64 = rdmsrq(reg_table[i].msr_addr);
}
return 0;
}
diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c
index dee42c163d92..cfb3a2975de4 100644
--- a/drivers/hwmon/hwmon-vid.c
+++ b/drivers/hwmon/hwmon-vid.c
@@ -243,10 +243,10 @@ static u8 get_via_model_d_vrm(void)
"C7-M", "C7", "Eden", "C7-D"
};
- rdmsrq(0x198, msr);
+ msr = rdmsrq(0x198);
vid = (msr >> 32) & 0xff;
- rdmsrq(0x1154, msr);
+ msr = rdmsrq(0x1154);
brand = ((msr >> 4) ^ (msr >> 2)) & 0x03;
if (vid > 0x3f) {
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index d74b478db280..94668cad683b 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -1999,35 +1999,35 @@ static void __init bxt_idle_state_table_update(void)
unsigned long long msr;
unsigned int usec;
- rdmsrq(MSR_PKGC6_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC6_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[2].exit_latency = usec;
bxt_cstates[2].target_residency = usec;
}
- rdmsrq(MSR_PKGC7_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC7_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[3].exit_latency = usec;
bxt_cstates[3].target_residency = usec;
}
- rdmsrq(MSR_PKGC8_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC8_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[4].exit_latency = usec;
bxt_cstates[4].target_residency = usec;
}
- rdmsrq(MSR_PKGC9_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC9_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[5].exit_latency = usec;
bxt_cstates[5].target_residency = usec;
}
- rdmsrq(MSR_PKGC10_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC10_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[6].exit_latency = usec;
@@ -2055,7 +2055,7 @@ static void __init sklh_idle_state_table_update(void)
if ((mwait_substates & (0xF << 28)) == 0)
return;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr);
+ msr = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
/* PC10 is not enabled in PKG C-state limit */
if ((msr & 0xF) != 8)
@@ -2067,7 +2067,7 @@ static void __init sklh_idle_state_table_update(void)
/* if SGX is present */
if (ebx & (1 << 2)) {
- rdmsrq(MSR_IA32_FEAT_CTL, msr);
+ msr = rdmsrq(MSR_IA32_FEAT_CTL);
/* if SGX is enabled */
if (msr & (1 << 18))
@@ -2087,7 +2087,7 @@ static bool __init skx_is_pc6_disabled(void)
{
u64 msr;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr);
+ msr = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
/*
* 000b: C0/C1 (no package C-state support)
@@ -2341,7 +2341,7 @@ static void auto_demotion_disable(void)
{
unsigned long long msr_bits;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
+ msr_bits = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
msr_bits &= ~auto_demotion_disable_flags;
wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
}
@@ -2350,7 +2350,7 @@ static void c1e_promotion_enable(void)
{
unsigned long long msr_bits;
- rdmsrq(MSR_IA32_POWER_CTL, msr_bits);
+ msr_bits = rdmsrq(MSR_IA32_POWER_CTL);
msr_bits |= 0x2;
wrmsrq(MSR_IA32_POWER_CTL, msr_bits);
}
@@ -2359,7 +2359,7 @@ static void c1e_promotion_disable(void)
{
unsigned long long msr_bits;
- rdmsrq(MSR_IA32_POWER_CTL, msr_bits);
+ msr_bits = rdmsrq(MSR_IA32_POWER_CTL);
msr_bits &= ~0x2;
wrmsrq(MSR_IA32_POWER_CTL, msr_bits);
}
@@ -2428,7 +2428,7 @@ static void intel_c1_demotion_toggle(void *enable)
{
unsigned long long msr_val;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
+ msr_val = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
/*
* Enable/disable C1 undemotion along with C1 demotion, as this is the
* most sensible configuration in general.
@@ -2468,7 +2468,7 @@ static ssize_t intel_c1_demotion_show(struct device *dev,
* Read the MSR value for a CPU and assume it is the same for all CPUs. Any other
* configuration would be a BIOS bug.
*/
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
+ msr_val = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
return sysfs_emit(buf, "%d\n", !!(msr_val & NHM_C1_AUTO_DEMOTE));
}
static DEVICE_ATTR_RW(intel_c1_demotion);
diff --git a/drivers/misc/cs5535-mfgpt.c b/drivers/misc/cs5535-mfgpt.c
index 9abfc44f70f4..9006b59858ff 100644
--- a/drivers/misc/cs5535-mfgpt.c
+++ b/drivers/misc/cs5535-mfgpt.c
@@ -83,7 +83,7 @@ int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
return -EIO;
}
- rdmsrq(msr, val.q);
+ val.q = rdmsrq(msr);
if (enable)
val.l |= mask;
@@ -114,7 +114,7 @@ int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
* IRQ of the 1st. This can only happen if forcing an IRQ, calling this
* with *irq==0 is safe. Currently there _are_ no 2 drivers.
*/
- rdmsrq(MSR_PIC_ZSEL_LOW, zsel.q);
+ zsel.q = rdmsrq(MSR_PIC_ZSEL_LOW);
shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4;
if (((zsel.l >> shift) & 0xF) == 2)
return -EIO;
@@ -128,7 +128,7 @@ int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
/* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
if (*irq < 1 || *irq == 2 || *irq > 15)
return -EIO;
- rdmsrq(MSR_PIC_IRQM_LPC, lpc.q);
+ lpc.q = rdmsrq(MSR_PIC_IRQM_LPC);
if (lpc.l & (1 << *irq))
return -EIO;
diff --git a/drivers/mtd/nand/raw/cs553x_nand.c b/drivers/mtd/nand/raw/cs553x_nand.c
index 0b872b1e3b04..2ed13666b48f 100644
--- a/drivers/mtd/nand/raw/cs553x_nand.c
+++ b/drivers/mtd/nand/raw/cs553x_nand.c
@@ -351,20 +351,20 @@ static int __init cs553x_init(void)
return -ENXIO;
/* If it doesn't have the CS553[56], abort */
- rdmsrq(MSR_DIVIL_GLD_CAP, val);
+ val = rdmsrq(MSR_DIVIL_GLD_CAP);
val &= ~0xFFULL;
if (val != CAP_CS5535 && val != CAP_CS5536)
return -ENXIO;
/* If it doesn't have the NAND controller enabled, abort */
- rdmsrq(MSR_DIVIL_BALL_OPTS, val);
+ val = rdmsrq(MSR_DIVIL_BALL_OPTS);
if (val & PIN_OPT_IDE) {
pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
return -ENXIO;
}
for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
- rdmsrq(MSR_DIVIL_LBAR_FLSH0 + i, val);
+ val = rdmsrq(MSR_DIVIL_LBAR_FLSH0 + i);
if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
diff --git a/drivers/platform/x86/intel/ifs/load.c b/drivers/platform/x86/intel/ifs/load.c
index 50f1fdf7dfed..6320a0e45d38 100644
--- a/drivers/platform/x86/intel/ifs/load.c
+++ b/drivers/platform/x86/intel/ifs/load.c
@@ -129,7 +129,7 @@ static void copy_hashes_authenticate_chunks(struct work_struct *work)
msrs = ifs_get_test_msrs(dev);
/* run scan hash copy */
wrmsrq(msrs->copy_hashes, ifs_hash_ptr);
- rdmsrq(msrs->copy_hashes_status, hashes_status.data);
+ hashes_status.data = rdmsrq(msrs->copy_hashes_status);
/* enumerate the scan image information */
num_chunks = hashes_status.num_chunks;
@@ -151,7 +151,7 @@ static void copy_hashes_authenticate_chunks(struct work_struct *work)
linear_addr |= i;
wrmsrq(msrs->copy_chunks, linear_addr);
- rdmsrq(msrs->copy_chunks_status, chunk_status.data);
+ chunk_status.data = rdmsrq(msrs->copy_chunks_status);
ifsd->valid_chunks = chunk_status.valid_chunks;
err_code = chunk_status.error_code;
@@ -197,7 +197,7 @@ static int copy_hashes_authenticate_chunks_gen2(struct device *dev)
if (need_copy_scan_hashes(ifsd)) {
wrmsrq(msrs->copy_hashes, ifs_hash_ptr);
- rdmsrq(msrs->copy_hashes_status, hashes_status.data);
+ hashes_status.data = rdmsrq(msrs->copy_hashes_status);
/* enumerate the scan image information */
chunk_size = hashes_status.chunk_size * SZ_1K;
@@ -218,7 +218,7 @@ static int copy_hashes_authenticate_chunks_gen2(struct device *dev)
if (ifsd->generation >= IFS_GEN_STRIDE_AWARE) {
wrmsrq(msrs->test_ctrl, INVALIDATE_STRIDE);
- rdmsrq(msrs->copy_chunks_status, chunk_status.data);
+ chunk_status.data = rdmsrq(msrs->copy_chunks_status);
if (chunk_status.valid_chunks != 0) {
dev_err(dev, "Couldn't invalidate installed stride - %d\n",
chunk_status.valid_chunks);
@@ -241,7 +241,7 @@ static int copy_hashes_authenticate_chunks_gen2(struct device *dev)
local_irq_disable();
wrmsrq(msrs->copy_chunks, (u64)chunk_table);
local_irq_enable();
- rdmsrq(msrs->copy_chunks_status, chunk_status.data);
+ chunk_status.data = rdmsrq(msrs->copy_chunks_status);
err_code = chunk_status.error_code;
} while (err_code == AUTH_INTERRUPTED_ERROR && --retry_count);
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index dfc119d7354d..46e1ea944ce7 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -211,7 +211,7 @@ static int doscan(void *data)
* are processed in a single pass) before it retires.
*/
wrmsrq(MSR_ACTIVATE_SCAN, params->activate->data);
- rdmsrq(MSR_SCAN_STATUS, status.data);
+ status.data = rdmsrq(MSR_SCAN_STATUS);
trace_ifs_status(ifsd->cur_batch, start, stop, status.data);
@@ -324,7 +324,7 @@ static int do_array_test(void *data)
if (cpu == first) {
wrmsrq(MSR_ARRAY_BIST, command->data);
/* Pass back the result of the test */
- rdmsrq(MSR_ARRAY_BIST, command->data);
+ command->data = rdmsrq(MSR_ARRAY_BIST);
}
return 0;
@@ -376,7 +376,7 @@ static int do_array_test_gen1(void *status)
if (cpu == first) {
wrmsrq(MSR_ARRAY_TRIGGER, ARRAY_GEN1_TEST_ALL_ARRAYS);
- rdmsrq(MSR_ARRAY_STATUS, *((u64 *)status));
+ *((u64 *)status) = rdmsrq(MSR_ARRAY_STATUS);
}
return 0;
@@ -528,7 +528,7 @@ static int dosbaf(void *data)
* during the "execution" of the WRMSR.
*/
wrmsrq(MSR_ACTIVATE_SBAF, run_params->activate->data);
- rdmsrq(MSR_SBAF_STATUS, status.data);
+ status.data = rdmsrq(MSR_SBAF_STATUS);
trace_ifs_sbaf(ifsd->cur_batch, *run_params->activate, status);
/* Pass back the result of the test */
diff --git a/drivers/platform/x86/intel/pmc/cnp.c b/drivers/platform/x86/intel/pmc/cnp.c
index efea4e1ba52b..44979e680361 100644
--- a/drivers/platform/x86/intel/pmc/cnp.c
+++ b/drivers/platform/x86/intel/pmc/cnp.c
@@ -228,7 +228,7 @@ static void disable_c1_auto_demote(void *unused)
int cpunum = smp_processor_id();
u64 val;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, val);
+ val = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
per_cpu(pkg_cst_config, cpunum) = val;
val &= ~NHM_C1_AUTO_DEMOTE;
wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, val);
diff --git a/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c b/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c
index 22745b217c6f..909c9e25112d 100644
--- a/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c
+++ b/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c
@@ -40,7 +40,7 @@ static int isst_if_send_mbox_cmd(u8 command, u8 sub_command, u32 parameter,
/* Poll for rb bit == 0 */
retries = OS_MAILBOX_RETRY_COUNT;
do {
- rdmsrq(MSR_OS_MAILBOX_INTERFACE, data);
+ data = rdmsrq(MSR_OS_MAILBOX_INTERFACE);
if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) {
ret = -EBUSY;
continue;
@@ -65,7 +65,7 @@ static int isst_if_send_mbox_cmd(u8 command, u8 sub_command, u32 parameter,
/* Poll for rb bit == 0 */
retries = OS_MAILBOX_RETRY_COUNT;
do {
- rdmsrq(MSR_OS_MAILBOX_INTERFACE, data);
+ data = rdmsrq(MSR_OS_MAILBOX_INTERFACE);
if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) {
ret = -EBUSY;
continue;
@@ -75,7 +75,7 @@ static int isst_if_send_mbox_cmd(u8 command, u8 sub_command, u32 parameter,
return -ENXIO;
if (response_data) {
- rdmsrq(MSR_OS_MAILBOX_DATA, data);
+ data = rdmsrq(MSR_OS_MAILBOX_DATA);
*response_data = data;
}
ret = 0;
diff --git a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
index 24334ae70d82..6f8648cc0445 100644
--- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
+++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
@@ -561,7 +561,7 @@ static bool disable_dynamic_sst_features(void)
if (!static_cpu_has(X86_FEATURE_HWP))
return true;
- rdmsrq(MSR_PM_ENABLE, value);
+ value = rdmsrq(MSR_PM_ENABLE);
return !(value & 0x1);
}
diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_ips.c
index b1b2d9caba7b..79c07f23ba0b 100644
--- a/drivers/platform/x86/intel_ips.c
+++ b/drivers/platform/x86/intel_ips.c
@@ -370,7 +370,7 @@ static void ips_cpu_raise(struct ips_driver *ips)
if (!ips->cpu_turbo_enabled)
return;
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
+ turbo_override = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
cur_tdp_limit = turbo_override & TURBO_TDP_MASK;
new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */
@@ -405,7 +405,7 @@ static void ips_cpu_lower(struct ips_driver *ips)
u64 turbo_override;
u16 cur_limit, new_limit;
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
+ turbo_override = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
cur_limit = turbo_override & TURBO_TDP_MASK;
new_limit = cur_limit - 8; /* 1W decrease */
@@ -437,7 +437,7 @@ static void do_enable_cpu_turbo(void *data)
{
u64 perf_ctl;
- rdmsrq(IA32_PERF_CTL, perf_ctl);
+ perf_ctl = rdmsrq(IA32_PERF_CTL);
if (perf_ctl & IA32_PERF_TURBO_DIS) {
perf_ctl &= ~IA32_PERF_TURBO_DIS;
wrmsrq(IA32_PERF_CTL, perf_ctl);
@@ -475,7 +475,7 @@ static void do_disable_cpu_turbo(void *data)
{
u64 perf_ctl;
- rdmsrq(IA32_PERF_CTL, perf_ctl);
+ perf_ctl = rdmsrq(IA32_PERF_CTL);
if (!(perf_ctl & IA32_PERF_TURBO_DIS)) {
perf_ctl |= IA32_PERF_TURBO_DIS;
wrmsrq(IA32_PERF_CTL, perf_ctl);
@@ -1215,7 +1215,7 @@ static int cpu_clamp_show(struct seq_file *m, void *data)
u64 turbo_override;
int tdp, tdc;
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
+ turbo_override = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
tdp = (int)(turbo_override & TURBO_TDP_MASK);
tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT);
@@ -1290,7 +1290,7 @@ static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips)
return NULL;
}
- rdmsrq(IA32_MISC_ENABLE, misc_en);
+ misc_en = rdmsrq(IA32_MISC_ENABLE);
/*
* If the turbo enable bit isn't set, we shouldn't try to enable/disable
* turbo manually or we'll get an illegal MSR access, even though
@@ -1312,7 +1312,7 @@ static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips)
return NULL;
}
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_power);
+ turbo_power = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
tdp = turbo_power & TURBO_TDP_MASK;
/* Sanity check TDP against CPU */
@@ -1496,7 +1496,7 @@ static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
* Check PLATFORM_INFO MSR to make sure this chip is
* turbo capable.
*/
- rdmsrq(PLATFORM_INFO, platform_info);
+ platform_info = rdmsrq(PLATFORM_INFO);
if (!(platform_info & PLATFORM_TDP)) {
dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n");
return -ENODEV;
@@ -1529,7 +1529,7 @@ static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
ips->mgta_val = thm_readw(THM_MGTA);
/* Save turbo limits & ratios */
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
+ ips->orig_turbo_limit = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
ips_disable_cpu_turbo(ips);
ips->cpu_turbo_enabled = false;
@@ -1596,7 +1596,7 @@ static void ips_remove(struct pci_dev *dev)
if (ips->gpu_turbo_disable)
symbol_put(i915_gpu_turbo_disable);
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
+ turbo_override = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN);
wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
wrmsrq(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rapl_msr.c
index a34543e66446..5d840de67c2b 100644
--- a/drivers/powercap/intel_rapl_msr.c
+++ b/drivers/powercap/intel_rapl_msr.c
@@ -176,7 +176,7 @@ static int rapl_msr_read_raw(int cpu, struct reg_action *ra, bool pmu_ctx)
* from any CPU in the package.
*/
if (pmu_ctx) {
- rdmsrq(ra->reg.msr, ra->value);
+ ra->value = rdmsrq(ra->reg.msr);
goto out;
}
diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c
index 3273b8fe3d4d..6b2801aaa745 100644
--- a/drivers/thermal/intel/intel_hfi.c
+++ b/drivers/thermal/intel/intel_hfi.c
@@ -285,7 +285,7 @@ void intel_hfi_process_event(__u64 pkg_therm_status_msr_val)
if (!raw_spin_trylock(&hfi_instance->event_lock))
return;
- rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS, msr);
+ msr = rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS);
hfi = msr & PACKAGE_THERM_STATUS_HFI_UPDATED;
if (!hfi) {
raw_spin_unlock(&hfi_instance->event_lock);
@@ -357,7 +357,7 @@ static void hfi_enable(void)
{
u64 msr_val;
- rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);
+ msr_val = rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG);
msr_val |= HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT;
wrmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);
}
@@ -378,7 +378,7 @@ static void hfi_disable(void)
u64 msr_val;
int i;
- rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);
+ msr_val = rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG);
msr_val &= ~HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT;
wrmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);
@@ -389,7 +389,7 @@ static void hfi_disable(void)
* memory.
*/
for (i = 0; i < 2000; i++) {
- rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
+ msr_val = rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS);
if (msr_val & PACKAGE_THERM_STATUS_HFI_UPDATED)
break;
diff --git a/drivers/thermal/intel/therm_throt.c b/drivers/thermal/intel/therm_throt.c
index 0b46a727ca7a..d12f124ef8d9 100644
--- a/drivers/thermal/intel/therm_throt.c
+++ b/drivers/thermal/intel/therm_throt.c
@@ -288,7 +288,7 @@ static void get_therm_status(int level, bool *proc_hot, u8 *temp)
else
msr = MSR_IA32_PACKAGE_THERM_STATUS;
- rdmsrq(msr, msr_val);
+ msr_val = rdmsrq(msr);
if (msr_val & THERM_STATUS_PROCHOT_LOG)
*proc_hot = true;
else
@@ -660,7 +660,7 @@ void intel_thermal_interrupt(void)
if (static_cpu_has(X86_FEATURE_HWP))
notify_hwp_interrupt();
- rdmsrq(MSR_IA32_THERM_STATUS, msr_val);
+ msr_val = rdmsrq(MSR_IA32_THERM_STATUS);
/* Check for violation of core thermal thresholds*/
notify_thresholds(msr_val);
@@ -675,7 +675,7 @@ void intel_thermal_interrupt(void)
CORE_LEVEL);
if (this_cpu_has(X86_FEATURE_PTS)) {
- rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
+ msr_val = rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS);
/* check violations of package thermal thresholds */
notify_package_thresholds(msr_val);
therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
@@ -733,7 +733,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
* be some SMM goo which handles it, so we can't even put a handler
* since it might be delivered via SMI already:
*/
- rdmsrq(MSR_IA32_MISC_ENABLE, val.q);
+ val.q = rdmsrq(MSR_IA32_MISC_ENABLE);
val.h = lvtthmr_init;
/*
@@ -759,7 +759,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
/* early Pentium M models use different method for enabling TM2 */
if (cpu_has(c, X86_FEATURE_TM2)) {
if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
- rdmsrq(MSR_THERM2_CTL, val.q);
+ val.q = rdmsrq(MSR_THERM2_CTL);
if (val.l & MSR_THERM2_CTL_TM_SELECT)
tm2 = 1;
} else if (val.l & MSR_IA32_MISC_ENABLE_TM2)
@@ -773,7 +773,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
thermal_intr_init_core_clear_mask();
thermal_intr_init_pkg_clear_mask();
- rdmsrq(MSR_IA32_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_THERM_INTERRUPT);
if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
val.l = (val.l | THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE) &
~THERM_INT_PLN_ENABLE;
@@ -785,7 +785,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
wrmsrq(MSR_IA32_THERM_INTERRUPT, val.q);
if (cpu_has(c, X86_FEATURE_PTS)) {
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
val.l = (val.l | PACKAGE_THERM_INT_LOW_ENABLE |
PACKAGE_THERM_INT_HIGH_ENABLE) &
@@ -800,13 +800,13 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
if (cpu_has(c, X86_FEATURE_HFI)) {
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT,
val.q | PACKAGE_THERM_INT_HFI_ENABLE);
}
}
- rdmsrq(MSR_IA32_MISC_ENABLE, val.q);
+ val.q = rdmsrq(MSR_IA32_MISC_ENABLE);
wrmsrq(MSR_IA32_MISC_ENABLE, val.q | MSR_IA32_MISC_ENABLE_TM1);
pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c
index 43fd5bdf1d8d..11ca647802dc 100644
--- a/drivers/thermal/intel/x86_pkg_temp_thermal.c
+++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c
@@ -187,7 +187,7 @@ static inline void enable_pkg_thres_interrupt(void)
u8 thres_0, thres_1;
struct msr val;
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
/* only enable/disable if it had valid threshold value */
thres_0 = (val.l & THERM_MASK_THRESHOLD0) >> THERM_SHIFT_THRESHOLD0;
thres_1 = (val.l & THERM_MASK_THRESHOLD1) >> THERM_SHIFT_THRESHOLD1;
@@ -203,7 +203,7 @@ static inline void disable_pkg_thres_interrupt(void)
{
struct msr val;
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
val.l &= ~(THERM_INT_THRESHOLD0_ENABLE | THERM_INT_THRESHOLD1_ENABLE);
wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
@@ -356,7 +356,7 @@ static int pkg_temp_thermal_device_add(unsigned int cpu)
goto out_unregister_tz;
/* Store MSR value for package thermal interrupt, to restore at exit */
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, zonedev->msr_pkg_therm);
+ zonedev->msr_pkg_therm = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
cpumask_set_cpu(cpu, &zonedev->cpumask);
raw_spin_lock_irq(&pkg_temp_lock);
diff --git a/drivers/video/fbdev/geode/display_gx.c b/drivers/video/fbdev/geode/display_gx.c
index b93aa21a1d2b..511cb7bf98e9 100644
--- a/drivers/video/fbdev/geode/display_gx.c
+++ b/drivers/video/fbdev/geode/display_gx.c
@@ -26,7 +26,7 @@ unsigned int gx_frame_buffer_size(void)
struct msr msr;
/* The number of pages is (PMAX - PMIN)+1 */
- rdmsrq(MSR_GLIU_P2D_RO0, msr.q);
+ msr.q = rdmsrq(MSR_GLIU_P2D_RO0);
/* PMAX */
val = ((msr.h & 0xff) << 12) | ((msr.l & 0xfff00000) >> 20);
diff --git a/drivers/video/fbdev/geode/gxfb_core.c b/drivers/video/fbdev/geode/gxfb_core.c
index 8d69be7c9d31..e0a3447f2b1b 100644
--- a/drivers/video/fbdev/geode/gxfb_core.c
+++ b/drivers/video/fbdev/geode/gxfb_core.c
@@ -378,7 +378,7 @@ static int gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
/* Figure out if this is a TFT or CRT part */
- rdmsrq(MSR_GX_GLD_MSR_CONFIG, val);
+ val = rdmsrq(MSR_GX_GLD_MSR_CONFIG);
if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP)
par->enable_crt = 0;
diff --git a/drivers/video/fbdev/geode/lxfb_ops.c b/drivers/video/fbdev/geode/lxfb_ops.c
index f5f1134cae9a..980a782214a2 100644
--- a/drivers/video/fbdev/geode/lxfb_ops.c
+++ b/drivers/video/fbdev/geode/lxfb_ops.c
@@ -127,7 +127,7 @@ static void lx_set_dotpll(u32 pllval)
struct msr dotpll;
int i;
- rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ dotpll.q = rdmsrq(MSR_GLCP_DOTPLL);
if ((dotpll.l & MSR_GLCP_DOTPLL_LOCK) && (dotpll.h == pllval))
return;
@@ -145,7 +145,7 @@ static void lx_set_dotpll(u32 pllval)
/* Now, loop for the lock bit */
for (i = 0; i < 1000; i++) {
- rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ dotpll.q = rdmsrq(MSR_GLCP_DOTPLL);
if (dotpll.l & MSR_GLCP_DOTPLL_LOCK)
break;
}
@@ -316,7 +316,7 @@ unsigned int lx_framebuffer_size(void)
struct msr msr;
/* The number of pages is (PMAX - PMIN)+1 */
- rdmsrq(MSR_GLIU_P2D_RO0, msr.q);
+ msr.q = rdmsrq(MSR_GLIU_P2D_RO0);
/* PMAX */
val = ((msr.h & 0xff) << 12) | ((msr.l & 0xfff00000) >> 20);
@@ -359,7 +359,7 @@ void lx_set_mode(struct fb_info *info)
/* Set output mode */
- rdmsrq(MSR_LX_GLD_MSR_CONFIG, msrval);
+ msrval = rdmsrq(MSR_LX_GLD_MSR_CONFIG);
msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
if (par->output & OUTPUT_PANEL) {
@@ -420,7 +420,7 @@ void lx_set_mode(struct fb_info *info)
/* Set default watermark values */
- rdmsrq(MSR_LX_SPARE_MSR, msrval);
+ msrval = rdmsrq(MSR_LX_SPARE_MSR);
msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
| MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
@@ -592,10 +592,10 @@ static void lx_save_regs(struct lxfb_par *par)
} while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE));
/* save MSRs */
- rdmsrq(MSR_LX_MSR_PADSEL, par->msr.padsel);
- rdmsrq(MSR_GLCP_DOTPLL, par->msr.dotpll);
- rdmsrq(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
- rdmsrq(MSR_LX_SPARE_MSR, par->msr.dcspare);
+ par->msr.padsel = rdmsrq(MSR_LX_MSR_PADSEL);
+ par->msr.dotpll = rdmsrq(MSR_GLCP_DOTPLL);
+ par->msr.dfglcfg = rdmsrq(MSR_LX_GLD_MSR_CONFIG);
+ par->msr.dcspare = rdmsrq(MSR_LX_SPARE_MSR);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
diff --git a/drivers/video/fbdev/geode/suspend_gx.c b/drivers/video/fbdev/geode/suspend_gx.c
index 6c0a526ee8a2..2fa20acba62e 100644
--- a/drivers/video/fbdev/geode/suspend_gx.c
+++ b/drivers/video/fbdev/geode/suspend_gx.c
@@ -21,8 +21,8 @@ static void gx_save_regs(struct gxfb_par *par)
} while (i & (GP_BLT_STATUS_BLT_PENDING | GP_BLT_STATUS_BLT_BUSY));
/* save MSRs */
- rdmsrq(MSR_GX_MSR_PADSEL, par->msr.padsel);
- rdmsrq(MSR_GLCP_DOTPLL, par->msr.dotpll);
+ par->msr.padsel = rdmsrq(MSR_GX_MSR_PADSEL);
+ par->msr.dotpll = rdmsrq(MSR_GLCP_DOTPLL);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
@@ -43,7 +43,7 @@ static void gx_set_dotpll(uint32_t dotpll_hi)
struct msr dotpll;
int i;
- rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ dotpll.q = rdmsrq(MSR_GLCP_DOTPLL);
dotpll.l |= MSR_GLCP_DOTPLL_DOTRESET;
dotpll.l &= ~MSR_GLCP_DOTPLL_BYPASS;
dotpll.h = dotpll_hi;
@@ -51,7 +51,7 @@ static void gx_set_dotpll(uint32_t dotpll_hi)
/* wait for the PLL to lock */
for (i = 0; i < 200; i++) {
- rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ dotpll.q = rdmsrq(MSR_GLCP_DOTPLL);
if (dotpll.l & MSR_GLCP_DOTPLL_LOCK)
break;
udelay(1);
diff --git a/drivers/video/fbdev/geode/video_gx.c b/drivers/video/fbdev/geode/video_gx.c
index 5717c3356949..b2cfadaf3ff8 100644
--- a/drivers/video/fbdev/geode/video_gx.c
+++ b/drivers/video/fbdev/geode/video_gx.c
@@ -142,8 +142,8 @@ void gx_set_dclk_frequency(struct fb_info *info)
}
}
- rdmsrq(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
- rdmsrq(MSR_GLCP_DOTPLL, dotpll);
+ sys_rstpll = rdmsrq(MSR_GLCP_SYS_RSTPLL);
+ dotpll = rdmsrq(MSR_GLCP_DOTPLL);
/* Program new M, N and P. */
dotpll &= 0x00000000ffffffffull;
@@ -167,7 +167,7 @@ void gx_set_dclk_frequency(struct fb_info *info)
/* Wait for LOCK bit. */
do {
- rdmsrq(MSR_GLCP_DOTPLL, dotpll);
+ dotpll = rdmsrq(MSR_GLCP_DOTPLL);
} while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
}
@@ -180,7 +180,7 @@ gx_configure_tft(struct fb_info *info)
/* Set up the DF pad select MSR */
- rdmsrq(MSR_GX_MSR_PADSEL, val);
+ val = rdmsrq(MSR_GX_MSR_PADSEL);
val &= ~MSR_GX_MSR_PADSEL_MASK;
val |= MSR_GX_MSR_PADSEL_TFT;
wrmsrq(MSR_GX_MSR_PADSEL, val);
diff --git a/include/linux/cs5535.h b/include/linux/cs5535.h
index 5ec2aca537bb..fef236cab7d8 100644
--- a/include/linux/cs5535.h
+++ b/include/linux/cs5535.h
@@ -51,7 +51,7 @@ static inline int cs5535_pic_unreqz_select_high(unsigned int group,
{
struct msr val;
- rdmsrq(MSR_PIC_ZSEL_HIGH, val.q);
+ val.q = rdmsrq(MSR_PIC_ZSEL_HIGH);
val.l &= ~(0xF << (group * 4));
val.l |= (irq & 0xF) << (group * 4);
wrmsrq(MSR_PIC_ZSEL_HIGH, val.q);
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* [PATCH 32/32] x86/msr: Simplify some rdmsrq() use cases
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (30 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 31/32] treewide: convert rdmsrq() from a macro to an inline function Juergen Gross
@ 2026-06-29 6:05 ` Juergen Gross
2026-06-29 6:52 ` [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Arnd Bergmann
32 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86, linux-perf-users, linux-hyperv, kvm
Cc: Juergen Gross, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, Thomas Gleixner, Borislav Petkov, Dave Hansen,
H. Peter Anvin, K. Y. Srinivasan, Haiyang Zhang, Wei Liu,
Dexuan Cui, Long Li, Sean Christopherson, Paolo Bonzini
After the conversion of rdmsrq() to an inline function some use cases
can be simplified by dropping an intermediate variable.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/events/amd/core.c | 6 +-----
arch/x86/events/amd/lbr.c | 12 ++----------
arch/x86/events/intel/core.c | 6 +-----
arch/x86/events/intel/cstate.c | 5 +----
arch/x86/events/intel/knc.c | 6 +-----
arch/x86/events/intel/lbr.c | 17 +++--------------
arch/x86/events/intel/uncore.c | 6 +-----
arch/x86/events/rapl.c | 4 +---
arch/x86/events/zhaoxin/core.c | 6 +-----
arch/x86/hyperv/hv_apic.c | 5 +----
arch/x86/include/asm/apic.h | 5 +----
arch/x86/include/asm/debugreg.h | 6 +-----
arch/x86/include/asm/kvm_host.h | 5 +----
13 files changed, 16 insertions(+), 73 deletions(-)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index ee08ed4f41ec..04f3c2e99c06 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -660,12 +660,8 @@ static __always_inline void amd_pmu_set_global_ctl(u64 ctl)
static inline u64 amd_pmu_get_global_status(void)
{
- u64 status;
-
/* PerfCntrGlobalStatus is read-only */
- status = rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS);
-
- return status;
+ return rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS);
}
static inline void amd_pmu_ack_global_status(u64 status)
diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c
index 0b6aec1e5bf1..ada5278285cd 100644
--- a/arch/x86/events/amd/lbr.c
+++ b/arch/x86/events/amd/lbr.c
@@ -74,20 +74,12 @@ static __always_inline void amd_pmu_lbr_set_to(unsigned int idx, u64 val)
static __always_inline u64 amd_pmu_lbr_get_from(unsigned int idx)
{
- u64 val;
-
- val = rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2);
-
- return val;
+ return rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2);
}
static __always_inline u64 amd_pmu_lbr_get_to(unsigned int idx)
{
- u64 val;
-
- val = rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1);
-
- return val;
+ return rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1);
}
static __always_inline u64 sign_ext_branch_ip(u64 ip)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c6fc2d9079d9..02cc471cb5bd 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2963,11 +2963,7 @@ static void intel_tfa_pmu_enable_all(int added)
static inline u64 intel_pmu_get_status(void)
{
- u64 status;
-
- status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
-
- return status;
+ return rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
}
static inline void intel_pmu_ack_status(u64 ack)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 69eb6cf51d3b..c6d9146d8ec8 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -322,10 +322,7 @@ static int cstate_pmu_event_init(struct perf_event *event)
static inline u64 cstate_pmu_read_counter(struct perf_event *event)
{
- u64 val;
-
- val = rdmsrq(event->hw.event_base);
- return val;
+ return rdmsrq(event->hw.event_base);
}
static void cstate_pmu_event_update(struct perf_event *event)
diff --git a/arch/x86/events/intel/knc.c b/arch/x86/events/intel/knc.c
index c4f81215f758..a74caa8280be 100644
--- a/arch/x86/events/intel/knc.c
+++ b/arch/x86/events/intel/knc.c
@@ -199,11 +199,7 @@ static void knc_pmu_enable_event(struct perf_event *event)
static inline u64 knc_pmu_get_status(void)
{
- u64 status;
-
- status = rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_STATUS);
-
- return status;
+ return rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_STATUS);
}
static inline void knc_pmu_ack_status(u64 ack)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index e65a4ed121d7..0364655a8771 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -209,10 +209,7 @@ void intel_pmu_lbr_reset(void)
*/
static inline u64 intel_pmu_lbr_tos(void)
{
- u64 tos;
-
- tos = rdmsrq(x86_pmu.lbr_tos);
- return tos;
+ return rdmsrq(x86_pmu.lbr_tos);
}
enum {
@@ -311,26 +308,18 @@ static __always_inline u64 rdlbr_from(unsigned int idx, struct lbr_entry *lbr)
static __always_inline u64 rdlbr_to(unsigned int idx, struct lbr_entry *lbr)
{
- u64 val;
-
if (lbr)
return lbr->to;
- val = rdmsrq(x86_pmu.lbr_to + idx);
-
- return val;
+ return rdmsrq(x86_pmu.lbr_to + idx);
}
static __always_inline u64 rdlbr_info(unsigned int idx, struct lbr_entry *lbr)
{
- u64 val;
-
if (lbr)
return lbr->info;
- val = rdmsrq(x86_pmu.lbr_info + idx);
-
- return val;
+ return rdmsrq(x86_pmu.lbr_info + idx);
}
static inline void
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index 0067bd35aa7f..7240849a6633 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -169,11 +169,7 @@ struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu
u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
{
- u64 count;
-
- count = rdmsrq(event->hw.event_base);
-
- return count;
+ return rdmsrq(event->hw.event_base);
}
void uncore_mmio_exit_box(struct intel_uncore_box *box)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 180cc18282ca..2d2376c59816 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -192,9 +192,7 @@ static inline unsigned int get_rapl_pmu_idx(int cpu, int scope)
static inline u64 rapl_read_counter(struct perf_event *event)
{
- u64 raw;
- raw = rdmsrq(event->hw.event_base);
- return raw;
+ return rdmsrq(event->hw.event_base);
}
static inline u64 rapl_scale(u64 v, struct perf_event *event)
diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index 1980e5995e27..9203321c18b4 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -266,11 +266,7 @@ static void zhaoxin_pmu_enable_all(int added)
static inline u64 zhaoxin_pmu_get_status(void)
{
- u64 status;
-
- status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
-
- return status;
+ return rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
}
static inline void zhaoxin_pmu_ack_status(u64 ack)
diff --git a/arch/x86/hyperv/hv_apic.c b/arch/x86/hyperv/hv_apic.c
index 4e30f9a11bc4..52ee8c237c2c 100644
--- a/arch/x86/hyperv/hv_apic.c
+++ b/arch/x86/hyperv/hv_apic.c
@@ -36,10 +36,7 @@ static struct apic orig_apic;
static u64 hv_apic_icr_read(void)
{
- u64 reg_val;
-
- reg_val = rdmsrq(HV_X64_MSR_ICR);
- return reg_val;
+ return rdmsrq(HV_X64_MSR_ICR);
}
static void hv_apic_icr_write(u32 low, u32 id)
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index e028140fac49..993b52b52625 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -231,10 +231,7 @@ static inline void native_x2apic_icr_write(u32 low, u32 id)
static inline u64 native_x2apic_icr_read(void)
{
- unsigned long val;
-
- val = rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4));
- return val;
+ return rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4));
}
extern int x2apic_mode;
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index 426d48beef81..0b2f42c7f8eb 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -174,15 +174,11 @@ static inline unsigned long amd_get_dr_addr_mask(unsigned int dr)
static inline unsigned long get_debugctlmsr(void)
{
- unsigned long debugctlmsr = 0;
-
#ifndef CONFIG_X86_DEBUGCTLMSR
if (boot_cpu_data.x86 < 6)
return 0;
#endif
- debugctlmsr = rdmsrq(MSR_IA32_DEBUGCTLMSR);
-
- return debugctlmsr;
+ return rdmsrq(MSR_IA32_DEBUGCTLMSR);
}
static inline void update_debugctlmsr(unsigned long debugctlmsr)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index e9b4ad535643..c87545070347 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -2415,10 +2415,7 @@ static inline void kvm_load_ldt(u16 sel)
#ifdef CONFIG_X86_64
static inline unsigned long read_msr(unsigned long msr)
{
- u64 value;
-
- value = rdmsrq(msr);
- return value;
+ return rdmsrq(msr);
}
#endif
--
2.54.0
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-29 6:04 [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Juergen Gross
` (31 preceding siblings ...)
2026-06-29 6:05 ` [PATCH 32/32] x86/msr: Simplify some rdmsrq() use cases Juergen Gross
@ 2026-06-29 6:52 ` Arnd Bergmann
2026-06-29 7:01 ` Jürgen Groß
32 siblings, 1 reply; 80+ messages in thread
From: Arnd Bergmann @ 2026-06-29 6:52 UTC (permalink / raw)
To: Juergen Gross, linux-kernel, linux-pm, linux-edac@vger.kernel.org,
x86, linux-acpi, kvm, linux-coco, linux-pci, virtualization,
linux-ide, dri-devel, linux-fbdev, linux-crypto,
open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86
Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Sean Christopherson,
Paolo Bonzini, Kirill A. Shutemov, Rick Edgecombe, Pu Wen,
Bjorn Helgaas, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list, Viresh Kumar,
Reinette Chatre, Dave Martin, James Morse, Babu Moger,
Tony W Wang-oc, Damien Le Moal, Niklas Cassel, Dave Airlie,
Helge Deller, linux-geode, Olivia Mackall, Herbert Xu,
Linus Walleij, Bartosz Golaszewski, Greg Kroah-Hartman,
K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui, Long Li,
Guenter Roeck, Peter Zijlstra, Arnaldo Carvalho de Melo,
Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa,
Ian Rogers, Adrian Hunter, James Clark, Josh Poimboeuf,
Pawan Gupta, Vitaly Kuznetsov, Andy Lutomirski, Boris Ostrovsky,
Huang Rui, Mario Limonciello, Perry Yuan, K Prateek Nayak,
srinivas.pandruvada@linux.intel.com, Artem Bityutskiy,
Artem Bityutskiy, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Ashok Raj, Hans de Goede, Ilpo Järvinen,
Rajneesh Bhardwaj, David E Box, xen-devel
On Mon, Jun 29, 2026, at 08:04, Juergen Gross wrote:
> For accessing the MSR registers on the local CPU, there are 2 types of
> interfaces: the "modern" 64-bit ones (rdmsrq() etc.) and the 32-bit
> ones (rdmsr() etc.) which are using the upper and lower 32-bit halves
> of the 64-bit wide MSR register values.
>
> The 32-bit interfaces are not optimal for 3 reasons:
>
> - They are based on primitives using 64-bit sized values anyway.
>
> - Modern x86 CPUs have added support for MSR access instructions using
> an immediate value instead of a register for addressing the MSR,
> while the value is in a 64-bit register.
>
> - rdmsr() is a macro storing the upper and lower 32-bit halves in
> variables specified as macro parameters. This is obscuring variable
> assignment through a macro. Additionally rdmsrq() is mimicking this
> pattern by being a macro, too, with the target variable specified as
> a parameter as well.
>
> For those reasons drop the 32-bit interfaces for accessing the x86 MSR
> registers completely and only use the 64-bit variants.
Hi Jürgen,
I assume this is fine, but since you don't mention it explicitly here,
please clarify what this means for 32-bit CPUs without the rdmsrq
instruction. Those will continue using the same instructions as before
and just change the calling conventions, right?
> Note that most patches of this series are independent from each other.
> Only the patches removing a specific interface (patches 7, 15, 26 and
> 30) and the last two patches of the series depend on all previous
> patches.
It looks like you are touching most files twice or more here, to
first convert from rdmsr to rdmsrq and then to change the
two-argument rdmsrq() macro to a single-argument inline. If you
introduce the inline version of rdmsrq() first, you should be
able to skip the second step (patch 31) as they could be able
to coexist.
Arnd
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-29 6:52 ` [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces Arnd Bergmann
@ 2026-06-29 7:01 ` Jürgen Groß
2026-06-29 8:06 ` Arnd Bergmann
0 siblings, 1 reply; 80+ messages in thread
From: Jürgen Groß @ 2026-06-29 7:01 UTC (permalink / raw)
To: Arnd Bergmann, linux-kernel, linux-pm, linux-edac@vger.kernel.org,
x86, linux-acpi, kvm, linux-coco, linux-pci, virtualization,
linux-ide, dri-devel, linux-fbdev, linux-crypto,
open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86
Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Sean Christopherson,
Paolo Bonzini, Kirill A. Shutemov, Rick Edgecombe, Pu Wen,
Bjorn Helgaas, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list, Viresh Kumar,
Reinette Chatre, Dave Martin, James Morse, Babu Moger,
Tony W Wang-oc, Damien Le Moal, Niklas Cassel, Dave Airlie,
Helge Deller, linux-geode, Olivia Mackall, Herbert Xu,
Linus Walleij, Bartosz Golaszewski, Greg Kroah-Hartman,
K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui, Long Li,
Guenter Roeck, Peter Zijlstra, Arnaldo Carvalho de Melo,
Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa,
Ian Rogers, Adrian Hunter, James Clark, Josh Poimboeuf,
Pawan Gupta, Vitaly Kuznetsov, Andy Lutomirski, Boris Ostrovsky,
Huang Rui, Mario Limonciello, Perry Yuan, K Prateek Nayak,
srinivas.pandruvada@linux.intel.com, Artem Bityutskiy,
Artem Bityutskiy, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Ashok Raj, Hans de Goede, Ilpo Järvinen,
Rajneesh Bhardwaj, David E Box, xen-devel
[-- Attachment #1.1.1: Type: text/plain, Size: 2378 bytes --]
On 29.06.26 08:52, Arnd Bergmann wrote:
> On Mon, Jun 29, 2026, at 08:04, Juergen Gross wrote:
>> For accessing the MSR registers on the local CPU, there are 2 types of
>> interfaces: the "modern" 64-bit ones (rdmsrq() etc.) and the 32-bit
>> ones (rdmsr() etc.) which are using the upper and lower 32-bit halves
>> of the 64-bit wide MSR register values.
>>
>> The 32-bit interfaces are not optimal for 3 reasons:
>>
>> - They are based on primitives using 64-bit sized values anyway.
>>
>> - Modern x86 CPUs have added support for MSR access instructions using
>> an immediate value instead of a register for addressing the MSR,
>> while the value is in a 64-bit register.
>>
>> - rdmsr() is a macro storing the upper and lower 32-bit halves in
>> variables specified as macro parameters. This is obscuring variable
>> assignment through a macro. Additionally rdmsrq() is mimicking this
>> pattern by being a macro, too, with the target variable specified as
>> a parameter as well.
>>
>> For those reasons drop the 32-bit interfaces for accessing the x86 MSR
>> registers completely and only use the 64-bit variants.
>
> Hi Jürgen,
>
> I assume this is fine, but since you don't mention it explicitly here,
> please clarify what this means for 32-bit CPUs without the rdmsrq
> instruction. Those will continue using the same instructions as before
> and just change the calling conventions, right?
Yes. I thought this would be clear from the following:
- They are based on primitives using 64-bit sized values anyway.
>
>> Note that most patches of this series are independent from each other.
>> Only the patches removing a specific interface (patches 7, 15, 26 and
>> 30) and the last two patches of the series depend on all previous
>> patches.
>
> It looks like you are touching most files twice or more here, to
> first convert from rdmsr to rdmsrq and then to change the
> two-argument rdmsrq() macro to a single-argument inline. If you
> introduce the inline version of rdmsrq() first, you should be
> able to skip the second step (patch 31) as they could be able
> to coexist.
I've discussed how to structure the series with Ingo Molnar before [1]. The
current approach was his preference.
Juergen
[1]: https://lore.kernel.org/lkml/f8d02c78-4681-4043-a5fa-921fa790b1b4@suse.com/
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^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-29 7:01 ` Jürgen Groß
@ 2026-06-29 8:06 ` Arnd Bergmann
2026-06-29 8:15 ` Jürgen Groß
2026-06-29 11:19 ` Ingo Molnar
0 siblings, 2 replies; 80+ messages in thread
From: Arnd Bergmann @ 2026-06-29 8:06 UTC (permalink / raw)
To: Juergen Gross, linux-kernel, linux-pm, linux-edac@vger.kernel.org,
x86, linux-acpi, kvm, linux-coco, linux-pci, virtualization,
linux-ide, dri-devel, linux-fbdev, linux-crypto,
open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86
Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Sean Christopherson,
Paolo Bonzini, Kirill A. Shutemov, Rick Edgecombe, Pu Wen,
Bjorn Helgaas, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list, Viresh Kumar,
Reinette Chatre, Dave Martin, James Morse, Babu Moger,
Tony W Wang-oc, Damien Le Moal, Niklas Cassel, Dave Airlie,
Helge Deller, linux-geode, Olivia Mackall, Herbert Xu,
Linus Walleij, Bartosz Golaszewski, Greg Kroah-Hartman,
K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui, Long Li,
Guenter Roeck, Peter Zijlstra, Arnaldo Carvalho de Melo,
Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa,
Ian Rogers, Adrian Hunter, James Clark, Josh Poimboeuf,
Pawan Gupta, Vitaly Kuznetsov, Andy Lutomirski, Boris Ostrovsky,
Huang Rui, Mario Limonciello, Perry Yuan, K Prateek Nayak,
srinivas.pandruvada@linux.intel.com, Artem Bityutskiy,
Artem Bityutskiy, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Ashok Raj, Hans de Goede, Ilpo Järvinen,
Rajneesh Bhardwaj, David E Box, xen-devel
On Mon, Jun 29, 2026, at 09:01, Jürgen Groß wrote:
> On 29.06.26 08:52, Arnd Bergmann wrote:
>> On Mon, Jun 29, 2026, at 08:04, Juergen Gross wrote:
>>
>> I assume this is fine, but since you don't mention it explicitly here,
>> please clarify what this means for 32-bit CPUs without the rdmsrq
>> instruction. Those will continue using the same instructions as before
>> and just change the calling conventions, right?
>
> Yes. I thought this would be clear from the following:
>
> - They are based on primitives using 64-bit sized values anyway.
Right, that was my reading of it as well, but it's not entirely
clear when the function name is the same as the mnemonic of an
instruction that only exists on newer CPUs and the later patch
descriptions (e.g. 25/32 that I was Cc's on) have a much shorter
explanation.
>>> Note that most patches of this series are independent from each other.
>>> Only the patches removing a specific interface (patches 7, 15, 26 and
>>> 30) and the last two patches of the series depend on all previous
>>> patches.
>>
>> It looks like you are touching most files twice or more here, to
>> first convert from rdmsr to rdmsrq and then to change the
>> two-argument rdmsrq() macro to a single-argument inline. If you
>> introduce the inline version of rdmsrq() first, you should be
>> able to skip the second step (patch 31) as they could be able
>> to coexist.
>
> I've discussed how to structure the series with Ingo Molnar before [1]. The
> current approach was his preference.
Ok.
Arnd
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-29 8:06 ` Arnd Bergmann
@ 2026-06-29 8:15 ` Jürgen Groß
2026-06-29 8:30 ` Jan Beulich
2026-06-29 8:38 ` Arnd Bergmann
2026-06-29 11:19 ` Ingo Molnar
1 sibling, 2 replies; 80+ messages in thread
From: Jürgen Groß @ 2026-06-29 8:15 UTC (permalink / raw)
To: Arnd Bergmann, linux-kernel, linux-pm, linux-edac@vger.kernel.org,
x86, linux-acpi, kvm, linux-coco, linux-pci, virtualization,
linux-ide, dri-devel, linux-fbdev, linux-crypto,
open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86
Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Sean Christopherson,
Paolo Bonzini, Kirill A. Shutemov, Rick Edgecombe, Pu Wen,
Bjorn Helgaas, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list, Viresh Kumar,
Reinette Chatre, Dave Martin, James Morse, Babu Moger,
Tony W Wang-oc, Damien Le Moal, Niklas Cassel, Dave Airlie,
Helge Deller, linux-geode, Olivia Mackall, Herbert Xu,
Linus Walleij, Bartosz Golaszewski, Greg Kroah-Hartman,
K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui, Long Li,
Guenter Roeck, Peter Zijlstra, Arnaldo Carvalho de Melo,
Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa,
Ian Rogers, Adrian Hunter, James Clark, Josh Poimboeuf,
Pawan Gupta, Vitaly Kuznetsov, Andy Lutomirski, Boris Ostrovsky,
Huang Rui, Mario Limonciello, Perry Yuan, K Prateek Nayak,
srinivas.pandruvada@linux.intel.com, Artem Bityutskiy,
Artem Bityutskiy, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Ashok Raj, Hans de Goede, Ilpo Järvinen,
Rajneesh Bhardwaj, David E Box, xen-devel
[-- Attachment #1.1.1: Type: text/plain, Size: 972 bytes --]
On 29.06.26 10:06, Arnd Bergmann wrote:
> On Mon, Jun 29, 2026, at 09:01, Jürgen Groß wrote:
>> On 29.06.26 08:52, Arnd Bergmann wrote:
>>> On Mon, Jun 29, 2026, at 08:04, Juergen Gross wrote:
>>>
>>> I assume this is fine, but since you don't mention it explicitly here,
>>> please clarify what this means for 32-bit CPUs without the rdmsrq
>>> instruction. Those will continue using the same instructions as before
>>> and just change the calling conventions, right?
>>
>> Yes. I thought this would be clear from the following:
>>
>> - They are based on primitives using 64-bit sized values anyway.
>
> Right, that was my reading of it as well, but it's not entirely
> clear when the function name is the same as the mnemonic of an
> instruction that only exists on newer CPUs and the later patch
There is no RDMSRQ instruction on any x86 CPU. Are you mixing this up with
WRMSRNS/RDMSR using an immediate for addressing the MSR?
Juergen
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^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-29 8:15 ` Jürgen Groß
@ 2026-06-29 8:30 ` Jan Beulich
2026-06-29 8:38 ` Arnd Bergmann
1 sibling, 0 replies; 80+ messages in thread
From: Jan Beulich @ 2026-06-29 8:30 UTC (permalink / raw)
To: Jürgen Groß
Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Sean Christopherson,
Paolo Bonzini, Kirill A. Shutemov, Rick Edgecombe, Pu Wen,
Bjorn Helgaas, Ajay Kaher, Alexey Makhalov, Viresh Kumar,
Reinette Chatre, Dave Martin, James Morse, Babu Moger,
Tony W Wang-oc, Damien Le Moal, Niklas Cassel, Dave Airlie,
Helge Deller, linux-geode, Olivia Mackall, Herbert Xu,
Linus Walleij, Bartosz Golaszewski, Greg Kroah-Hartman,
K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui, Long Li,
Guenter Roeck, Peter Zijlstra, Arnaldo Carvalho de Melo,
Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa,
Ian Rogers, Adrian Hunter, James Clark, Josh Poimboeuf,
Pawan Gupta, Vitaly Kuznetsov, Andy Lutomirski, Boris Ostrovsky,
Huang Rui, Mario Limonciello, Perry Yuan, K Prateek Nayak,
srinivas.pandruvada@linux.intel.com, Artem Bityutskiy,
Artem Bityutskiy, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Ashok Raj, Hans de Goede, Ilpo Järvinen,
Rajneesh Bhardwaj, David E Box, xen-devel, linux-kernel,
Arnd Bergmann, x86
On 29.06.2026 10:15, Jürgen Groß wrote:
> On 29.06.26 10:06, Arnd Bergmann wrote:
>> On Mon, Jun 29, 2026, at 09:01, Jürgen Groß wrote:
>>> On 29.06.26 08:52, Arnd Bergmann wrote:
>>>> On Mon, Jun 29, 2026, at 08:04, Juergen Gross wrote:
>>>>
>>>> I assume this is fine, but since you don't mention it explicitly here,
>>>> please clarify what this means for 32-bit CPUs without the rdmsrq
>>>> instruction. Those will continue using the same instructions as before
>>>> and just change the calling conventions, right?
>>>
>>> Yes. I thought this would be clear from the following:
>>>
>>> - They are based on primitives using 64-bit sized values anyway.
>>
>> Right, that was my reading of it as well, but it's not entirely
>> clear when the function name is the same as the mnemonic of an
>> instruction that only exists on newer CPUs and the later patch
>
> There is no RDMSRQ instruction on any x86 CPU.
And perhaps wrongly so. On the binutils side I did argue previously that it
is in the spirit of the original AT&T assembler language to permit, but not
require, suffixes matching the size of (uniform) register operands. Even for
insns not allowing for memory operands, simply for overall consistency.
(I took the liberty to at least limit the number of Cc-ed lists some.)
Jan
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-29 8:15 ` Jürgen Groß
2026-06-29 8:30 ` Jan Beulich
@ 2026-06-29 8:38 ` Arnd Bergmann
2026-06-30 20:06 ` H. Peter Anvin
1 sibling, 1 reply; 80+ messages in thread
From: Arnd Bergmann @ 2026-06-29 8:38 UTC (permalink / raw)
To: Juergen Gross, linux-kernel, linux-pm, linux-edac@vger.kernel.org,
x86, linux-acpi, kvm, linux-coco, linux-pci, virtualization,
linux-ide, dri-devel, linux-fbdev, linux-crypto,
open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86
Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Sean Christopherson,
Paolo Bonzini, Kirill A. Shutemov, Rick Edgecombe, Pu Wen,
Bjorn Helgaas, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list, Viresh Kumar,
Reinette Chatre, Dave Martin, James Morse, Babu Moger,
Tony W Wang-oc, Damien Le Moal, Niklas Cassel, Dave Airlie,
Helge Deller, linux-geode, Olivia Mackall, Herbert Xu,
Linus Walleij, Bartosz Golaszewski, Greg Kroah-Hartman,
K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui, Long Li,
Guenter Roeck, Peter Zijlstra, Arnaldo Carvalho de Melo,
Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa,
Ian Rogers, Adrian Hunter, James Clark, Josh Poimboeuf,
Pawan Gupta, Vitaly Kuznetsov, Andy Lutomirski, Boris Ostrovsky,
Huang Rui, Mario Limonciello, Perry Yuan, K Prateek Nayak,
srinivas.pandruvada@linux.intel.com, Artem Bityutskiy,
Artem Bityutskiy, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Ashok Raj, Hans de Goede, Ilpo Järvinen,
Rajneesh Bhardwaj, David E Box, xen-devel
On Mon, Jun 29, 2026, at 10:15, Jürgen Groß wrote:
> On 29.06.26 10:06, Arnd Bergmann wrote:
>> On Mon, Jun 29, 2026, at 09:01, Jürgen Groß wrote:
>>> On 29.06.26 08:52, Arnd Bergmann wrote:
>>>> On Mon, Jun 29, 2026, at 08:04, Juergen Gross wrote:
>>>>
>>>> I assume this is fine, but since you don't mention it explicitly here,
>>>> please clarify what this means for 32-bit CPUs without the rdmsrq
>>>> instruction. Those will continue using the same instructions as before
>>>> and just change the calling conventions, right?
>>>
>>> Yes. I thought this would be clear from the following:
>>>
>>> - They are based on primitives using 64-bit sized values anyway.
>>
>> Right, that was my reading of it as well, but it's not entirely
>> clear when the function name is the same as the mnemonic of an
>> instruction that only exists on newer CPUs and the later patch
>
> There is no RDMSRQ instruction on any x86 CPU. Are you mixing this up with
> WRMSRNS/RDMSR using an immediate for addressing the MSR?
Yes, I was just confused about the exact definition here and assumed
the single-register output version was actually called rdmsrq.
Arnd
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-29 8:38 ` Arnd Bergmann
@ 2026-06-30 20:06 ` H. Peter Anvin
0 siblings, 0 replies; 80+ messages in thread
From: H. Peter Anvin @ 2026-06-30 20:06 UTC (permalink / raw)
To: Arnd Bergmann, Juergen Gross, linux-kernel, linux-pm,
linux-edac@vger.kernel.org, x86, linux-acpi, kvm, linux-coco,
linux-pci, virtualization, linux-ide, dri-devel, linux-fbdev,
linux-crypto, open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86
Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, Sean Christopherson, Paolo Bonzini,
Kirill A. Shutemov, Rick Edgecombe, Pu Wen, Bjorn Helgaas,
Ajay Kaher, Alexey Makhalov, Broadcom internal kernel review list,
Viresh Kumar, Reinette Chatre, Dave Martin, James Morse,
Babu Moger, Tony W Wang-oc, Damien Le Moal, Niklas Cassel,
Dave Airlie, Helge Deller, linux-geode, Olivia Mackall,
Herbert Xu, Linus Walleij, Bartosz Golaszewski,
Greg Kroah-Hartman, K. Y. Srinivasan, Haiyang Zhang, Wei Liu,
Dexuan Cui, Long Li, Guenter Roeck, Peter Zijlstra,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, Josh Poimboeuf, Pawan Gupta, Vitaly Kuznetsov,
Andy Lutomirski, Boris Ostrovsky, Huang Rui, Mario Limonciello,
Perry Yuan, K Prateek Nayak, srinivas.pandruvada@linux.intel.com,
Artem Bityutskiy, Artem Bityutskiy, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, Ashok Raj, Hans de Goede,
Ilpo Järvinen, Rajneesh Bhardwaj, David E Box, xen-devel
On 2026-06-29 01:38, Arnd Bergmann wrote:
>>
>> There is no RDMSRQ instruction on any x86 CPU. Are you mixing this up with
>> WRMSRNS/RDMSR using an immediate for addressing the MSR?
>
> Yes, I was just confused about the exact definition here and assumed
> the single-register output version was actually called rdmsrq.
>
So just to be clear:
There are three instructions(*):
wrmsr - implicit form only
wrmsrns - implicit or immediate
rdmsr - implicit or immediate
The implicit form are the same on 32 and 64 bits (and, in fact, 16 bits): they
take a MSR register address in %ecx and the data as two 32-bit words in
%edx:%eax. This interface predates x86-64 by about a decade, and the Linux MSR
interfaces were designed when Linux was 32-bit only, so it made sense at the
time to treat them as two halves, especially since MSRs often are various
kinds of bitfields. It didn't help that gcc at the time was extremely
inefficient in its handling of multiword arithmetic (it is much better now),
so using a u64 would have made for much worse code.
The immediate forms are 64-bit only and use a single arbitrary 64-bit
register; the MSR address is kept in an immediate in the instruction, just
like they are for most other register types. The only thing that is "special"
there is that the possible register address space is very large (2^32)
although in practice a very small fraction of that is (currently) used.
The immediate forms are expected to be faster, and provide for further
performance improvements in future microarchitectures. This is important,
because it provides a fine-grain uniform architecture for supervisor-only
state, instead of having to give a bulk ISA (XSAVES/XRSTORS) that is different
from the fine-grained architecture, and still get good performance. This gives
the kernel very fine level control over the context switch flows, for one thing.
WRMSRNS is a non-serializing form of WRMSR, which is defined as an
architecturally hard-serializing instruction, although some MSRs have been
retconned as non-serializing (and the set is different between vendors.) We
want to switch that over to the model where the kernel explicitly opts in to
nonserialization, but that means using alternatives since not all CPUs have
the WRMSRNS instruction.
Furthermore, we want to use alternatives so we can make use of the
immediate-format instructions when the MSR address is known at compile time,
which it is in *nearly* all cases. If we are smart about it we can also use
this to let the tracing framework be specific about what MSRs to trace, since
some MSRs are frequently accessed, but many are set at startup and then
rarely, if ever, touched.
(*) There are actually two more instructions:
RDMSRLIST
WRMSRLIST
... which are bulk versions of RDMSR and WRMSRNS respectively. They can be
useful to save and restore entire groups of MSRs in one shot, such as
performance counter configurations. By architecturally allowing the memory
operations and MSR operations to operate asynchronously, they give some of the
pipeline benefits of the immediate MSR operations without requiring the MSR
set to have been set at compile time or code to be dynamically generated.
However, they expose an entirely different programming model, whereas the
immediate- and -NS instruction choices can be entirely hidden at the C level.
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-29 8:06 ` Arnd Bergmann
2026-06-29 8:15 ` Jürgen Groß
@ 2026-06-29 11:19 ` Ingo Molnar
2026-06-30 18:59 ` Sean Christopherson
1 sibling, 1 reply; 80+ messages in thread
From: Ingo Molnar @ 2026-06-29 11:19 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Juergen Gross, linux-kernel, linux-pm, linux-edac@vger.kernel.org,
x86, linux-acpi, kvm, linux-coco, linux-pci, virtualization,
linux-ide, dri-devel, linux-fbdev, linux-crypto,
open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86,
Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Sean Christopherson,
Paolo Bonzini, Kirill A. Shutemov, Rick Edgecombe, Pu Wen,
Bjorn Helgaas, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list, Viresh Kumar,
Reinette Chatre, Dave Martin, James Morse, Babu Moger,
Tony W Wang-oc, Damien Le Moal, Niklas Cassel, Dave Airlie,
Helge Deller, linux-geode, Olivia Mackall, Herbert Xu,
Linus Walleij, Bartosz Golaszewski, Greg Kroah-Hartman,
K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui, Long Li,
Guenter Roeck, Peter Zijlstra, Arnaldo Carvalho de Melo,
Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa,
Ian Rogers, Adrian Hunter, James Clark, Josh Poimboeuf,
Pawan Gupta, Vitaly Kuznetsov, Andy Lutomirski, Boris Ostrovsky,
Huang Rui, Mario Limonciello, Perry Yuan, K Prateek Nayak,
srinivas.pandruvada@linux.intel.com, Artem Bityutskiy,
Artem Bityutskiy, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Ashok Raj, Hans de Goede, Ilpo Järvinen,
Rajneesh Bhardwaj, David E Box, xen-devel
* Arnd Bergmann <arnd@arndb.de> wrote:
> >>> Note that most patches of this series are independent from each other.
> >>> Only the patches removing a specific interface (patches 7, 15, 26 and
> >>> 30) and the last two patches of the series depend on all previous
> >>> patches.
> >>
> >> It looks like you are touching most files twice or more here, to
> >> first convert from rdmsr to rdmsrq and then to change the
> >> two-argument rdmsrq() macro to a single-argument inline. If you
> >> introduce the inline version of rdmsrq() first, you should be
> >> able to skip the second step (patch 31) as they could be able
> >> to coexist.
> >
> > I've discussed how to structure the series with Ingo Molnar before [1]. The
> > current approach was his preference.
>
> Ok.
Note that the individual patches are IMO significantly easier to review
through the actual 32-bit => 64-bit variable assignment changes done
in isolation (which sometimes include minor cleanups), while
the Coccinelle semantic patch:
{ a(b,c) => c = a(b) }
which changes both the function signature and the order of terms as
well, is just a single add-on treewide patch.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-29 11:19 ` Ingo Molnar
@ 2026-06-30 18:59 ` Sean Christopherson
2026-07-01 8:33 ` Jürgen Groß
2026-07-02 10:07 ` Ingo Molnar
0 siblings, 2 replies; 80+ messages in thread
From: Sean Christopherson @ 2026-06-30 18:59 UTC (permalink / raw)
To: Ingo Molnar
Cc: Arnd Bergmann, Juergen Gross, linux-kernel, linux-pm,
linux-edac@vger.kernel.org, x86, linux-acpi, kvm, linux-coco,
linux-pci, virtualization, linux-ide, dri-devel, linux-fbdev,
linux-crypto, open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86,
Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Paolo Bonzini,
Kirill A. Shutemov, Rick Edgecombe, Pu Wen, Bjorn Helgaas,
Ajay Kaher, Alexey Makhalov, Broadcom internal kernel review list,
Viresh Kumar, Reinette Chatre, Dave Martin, James Morse,
Babu Moger, Tony W Wang-oc, Damien Le Moal, Niklas Cassel,
Dave Airlie, Helge Deller, linux-geode, Olivia Mackall,
Herbert Xu, Linus Walleij, Bartosz Golaszewski,
Greg Kroah-Hartman, K. Y. Srinivasan, Haiyang Zhang, Wei Liu,
Dexuan Cui, Long Li, Guenter Roeck, Peter Zijlstra,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, Josh Poimboeuf, Pawan Gupta, Vitaly Kuznetsov,
Andy Lutomirski, Boris Ostrovsky, Huang Rui, Mario Limonciello,
Perry Yuan, K Prateek Nayak, srinivas.pandruvada@linux.intel.com,
Artem Bityutskiy, Artem Bityutskiy, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, Ashok Raj, Hans de Goede,
Ilpo Järvinen, Rajneesh Bhardwaj, David E Box, xen-devel
On Mon, Jun 29, 2026, Ingo Molnar wrote:
> * Arnd Bergmann <arnd@arndb.de> wrote:
>
> > >>> Note that most patches of this series are independent from each other.
> > >>> Only the patches removing a specific interface (patches 7, 15, 26 and
> > >>> 30) and the last two patches of the series depend on all previous
> > >>> patches.
> > >>
> > >> It looks like you are touching most files twice or more here, to
> > >> first convert from rdmsr to rdmsrq and then to change the
> > >> two-argument rdmsrq() macro to a single-argument inline. If you
> > >> introduce the inline version of rdmsrq() first, you should be
> > >> able to skip the second step (patch 31) as they could be able
> > >> to coexist.
> > >
> > > I've discussed how to structure the series with Ingo Molnar before [1]. The
> > > current approach was his preference.
> >
> > Ok.
>
> Note that the individual patches are IMO significantly easier to review
> through the actual 32-bit => 64-bit variable assignment changes done
> in isolation (which sometimes include minor cleanups), while
> the Coccinelle semantic patch:
>
> { a(b,c) => c = a(b) }
>
> which changes both the function signature and the order of terms as
> well, is just a single add-on treewide patch.
Is the plan for subsystem maintainers to pick up the relevant patches, and then
do the treewide change one release cycle later?
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-30 18:59 ` Sean Christopherson
@ 2026-07-01 8:33 ` Jürgen Groß
2026-07-02 10:07 ` Ingo Molnar
1 sibling, 0 replies; 80+ messages in thread
From: Jürgen Groß @ 2026-07-01 8:33 UTC (permalink / raw)
To: Sean Christopherson, Ingo Molnar
Cc: Arnd Bergmann, linux-kernel, linux-pm, linux-edac@vger.kernel.org,
x86, linux-acpi, kvm, linux-coco, linux-pci, virtualization,
linux-ide, dri-devel, linux-fbdev, linux-crypto,
open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86,
Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Paolo Bonzini,
Kirill A. Shutemov, Rick Edgecombe, Pu Wen, Bjorn Helgaas,
Ajay Kaher, Alexey Makhalov, Broadcom internal kernel review list,
Viresh Kumar, Reinette Chatre, Dave Martin, James Morse,
Babu Moger, Tony W Wang-oc, Damien Le Moal, Niklas Cassel,
Dave Airlie, Helge Deller, linux-geode, Olivia Mackall,
Herbert Xu, Linus Walleij, Bartosz Golaszewski,
Greg Kroah-Hartman, K. Y. Srinivasan, Haiyang Zhang, Wei Liu,
Dexuan Cui, Long Li, Guenter Roeck, Peter Zijlstra,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, Josh Poimboeuf, Pawan Gupta, Vitaly Kuznetsov,
Andy Lutomirski, Boris Ostrovsky, Huang Rui, Mario Limonciello,
Perry Yuan, K Prateek Nayak, srinivas.pandruvada@linux.intel.com,
Artem Bityutskiy, Artem Bityutskiy, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, Ashok Raj, Hans de Goede,
Ilpo Järvinen, Rajneesh Bhardwaj, David E Box, xen-devel
[-- Attachment #1.1.1: Type: text/plain, Size: 1484 bytes --]
On 30.06.26 20:59, Sean Christopherson wrote:
> On Mon, Jun 29, 2026, Ingo Molnar wrote:
>> * Arnd Bergmann <arnd@arndb.de> wrote:
>>
>>>>>> Note that most patches of this series are independent from each other.
>>>>>> Only the patches removing a specific interface (patches 7, 15, 26 and
>>>>>> 30) and the last two patches of the series depend on all previous
>>>>>> patches.
>>>>>
>>>>> It looks like you are touching most files twice or more here, to
>>>>> first convert from rdmsr to rdmsrq and then to change the
>>>>> two-argument rdmsrq() macro to a single-argument inline. If you
>>>>> introduce the inline version of rdmsrq() first, you should be
>>>>> able to skip the second step (patch 31) as they could be able
>>>>> to coexist.
>>>>
>>>> I've discussed how to structure the series with Ingo Molnar before [1]. The
>>>> current approach was his preference.
>>>
>>> Ok.
>>
>> Note that the individual patches are IMO significantly easier to review
>> through the actual 32-bit => 64-bit variable assignment changes done
>> in isolation (which sometimes include minor cleanups), while
>> the Coccinelle semantic patch:
>>
>> { a(b,c) => c = a(b) }
>>
>> which changes both the function signature and the order of terms as
>> well, is just a single add-on treewide patch.
>
> Is the plan for subsystem maintainers to pick up the relevant patches, and then
> do the treewide change one release cycle later?
Yes, please.
Juergen
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^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-06-30 18:59 ` Sean Christopherson
2026-07-01 8:33 ` Jürgen Groß
@ 2026-07-02 10:07 ` Ingo Molnar
2026-07-02 11:03 ` Juergen Gross
1 sibling, 1 reply; 80+ messages in thread
From: Ingo Molnar @ 2026-07-02 10:07 UTC (permalink / raw)
To: Sean Christopherson
Cc: Arnd Bergmann, Juergen Gross, linux-kernel, linux-pm,
linux-edac@vger.kernel.org, x86, linux-acpi, kvm, linux-coco,
linux-pci, virtualization, linux-ide, dri-devel, linux-fbdev,
linux-crypto, open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86,
Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Paolo Bonzini,
Kirill A. Shutemov, Rick Edgecombe, Pu Wen, Bjorn Helgaas,
Ajay Kaher, Alexey Makhalov, Broadcom internal kernel review list,
Viresh Kumar, Reinette Chatre, Dave Martin, James Morse,
Babu Moger, Tony W Wang-oc, Damien Le Moal, Niklas Cassel,
Dave Airlie, Helge Deller, linux-geode, Olivia Mackall,
Herbert Xu, Linus Walleij, Bartosz Golaszewski,
Greg Kroah-Hartman, K. Y. Srinivasan, Haiyang Zhang, Wei Liu,
Dexuan Cui, Long Li, Guenter Roeck, Peter Zijlstra,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, Josh Poimboeuf, Pawan Gupta, Vitaly Kuznetsov,
Andy Lutomirski, Boris Ostrovsky, Huang Rui, Mario Limonciello,
Perry Yuan, K Prateek Nayak, srinivas.pandruvada@linux.intel.com,
Artem Bityutskiy, Artem Bityutskiy, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, Ashok Raj, Hans de Goede,
Ilpo Järvinen, Rajneesh Bhardwaj, David E Box, xen-devel
* Sean Christopherson <seanjc@google.com> wrote:
> > Note that the individual patches are IMO significantly easier to review
> > through the actual 32-bit => 64-bit variable assignment changes done
> > in isolation (which sometimes include minor cleanups), while
> > the Coccinelle semantic patch:
> >
> > { a(b,c) => c = a(b) }
> >
> > which changes both the function signature and the order of terms as
> > well, is just a single add-on treewide patch.
>
> Is the plan for subsystem maintainers to pick up the relevant patches,
> and then do the treewide change one release cycle later?
I'll try to keep the patches in a single tree (tip:x86/msr)
in the hope of not prolonging the pain two cycles - but it's
of course fine for maintainers to pick up the patches too
(most of them are standalone), we'll sort it all out in the end.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
2026-07-02 10:07 ` Ingo Molnar
@ 2026-07-02 11:03 ` Juergen Gross
0 siblings, 0 replies; 80+ messages in thread
From: Juergen Gross @ 2026-07-02 11:03 UTC (permalink / raw)
To: Ingo Molnar, Sean Christopherson
Cc: Arnd Bergmann, linux-kernel, linux-pm, linux-edac@vger.kernel.org,
x86, linux-acpi, kvm, linux-coco, linux-pci, virtualization,
linux-ide, dri-devel, linux-fbdev, linux-crypto,
open list:GPIO SUBSYSTEM, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86,
Rafael J . Wysocki, Daniel Lezcano, Zhang Rui,
lukasz.luba@arm.com, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Paolo Bonzini,
Kirill A. Shutemov, Rick Edgecombe, Pu Wen, Bjorn Helgaas,
Ajay Kaher, Alexey Makhalov, Broadcom internal kernel review list,
Viresh Kumar, Reinette Chatre, Dave Martin, James Morse,
Babu Moger, Tony W Wang-oc, Damien Le Moal, Niklas Cassel,
Dave Airlie, Helge Deller, linux-geode, Olivia Mackall,
Herbert Xu, Linus Walleij, Bartosz Golaszewski,
Greg Kroah-Hartman, K. Y. Srinivasan, Haiyang Zhang, Wei Liu,
Dexuan Cui, Long Li, Guenter Roeck, Peter Zijlstra,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, Josh Poimboeuf, Pawan Gupta, Vitaly Kuznetsov,
Andy Lutomirski, Boris Ostrovsky, Huang Rui, Mario Limonciello,
Perry Yuan, K Prateek Nayak, srinivas.pandruvada@linux.intel.com,
Artem Bityutskiy, Artem Bityutskiy, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, Ashok Raj, Hans de Goede,
Ilpo Järvinen, Rajneesh Bhardwaj, David E Box, xen-devel
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On 02.07.26 12:07, Ingo Molnar wrote:
>
> * Sean Christopherson <seanjc@google.com> wrote:
>
>>> Note that the individual patches are IMO significantly easier to review
>>> through the actual 32-bit => 64-bit variable assignment changes done
>>> in isolation (which sometimes include minor cleanups), while
>>> the Coccinelle semantic patch:
>>>
>>> { a(b,c) => c = a(b) }
>>>
>>> which changes both the function signature and the order of terms as
>>> well, is just a single add-on treewide patch.
>>
>> Is the plan for subsystem maintainers to pick up the relevant patches,
>> and then do the treewide change one release cycle later?
>
> I'll try to keep the patches in a single tree (tip:x86/msr)
> in the hope of not prolonging the pain two cycles - but it's
> of course fine for maintainers to pick up the patches too
> (most of them are standalone), we'll sort it all out in the end.
Ingo, would you be fine with me posting patch updates just as replies to the
original patch emails? This would speed things up, as I wouldn't need to wait
for more review input of all the patches before sending out new versions.
As the patches are (mostly) standalone, this should not cause any weird
problems.
The last two patches might need updates, but those can be applied only after
the rest has been accepted anyway.
Juergen
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^ permalink raw reply [flat|nested] 80+ messages in thread