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From: Andrea Righi <arighi@nvidia.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Christian Loehle <christian.loehle@arm.com>,
	K Prateek Nayak <kprateek.nayak@amd.com>,
	Ingo Molnar <mingo@redhat.com>,
	Juri Lelli <juri.lelli@redhat.com>,
	Vincent Guittot <vincent.guittot@linaro.org>,
	Dietmar Eggemann <dietmar.eggemann@arm.com>,
	Steven Rostedt <rostedt@goodmis.org>,
	Ben Segall <bsegall@google.com>, Mel Gorman <mgorman@suse.de>,
	Valentin Schneider <vschneid@redhat.com>,
	Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
	Shrikanth Hegde <sshegde@linux.ibm.com>,
	Felix Abecassis <fabecassis@nvidia.com>,
	Joel Fernandes <joelagnelf@nvidia.com>,
	Phil Auld <pauld@redhat.com>,
	linux-kernel@vger.kernel.org,
	Julia Lawall <julia.lawall@inria.fr>
Subject: Re: [PATCH] sched/fair: Stabilize idle SMT core selection with asym-capacity
Date: Fri, 3 Jul 2026 19:07:13 +0200	[thread overview]
Message-ID: <akfsQexV19pybIbB@gpd4> (raw)
In-Reply-To: <20260703165414.GR751831@noisy.programming.kicks-ass.net>

On Fri, Jul 03, 2026 at 06:54:14PM +0200, Peter Zijlstra wrote:
> On Fri, Jul 03, 2026 at 04:52:17PM +0200, Andrea Righi wrote:
> 
> > As mentioned in my other email, I found a surprising asymmetry on this machine:
> > pinning one worker per core to the first SMT siblings gives substantially better
> > performance than pinning them to the second siblings, despite firmware
> > advertising identical capacity and frequency for both.
> 
> Cute, that's something that Power7 also had. That's where
> SD_ASYM_PACKING originated from.

Yep, I'm actually experimenting with a patch that mimics the Power7 and it
seems to work. :) But I'm using a quirk to detect the particular CPU
implementation to set SD_ASYM_PACKING on the SMT domain and assign a higher
arch_asym_cpu_priority() to the first sibling, which is not the best...

So I'm checking with the firmware folks whether they can expose the relative SMT
thread priority explicitly, so that the kernel can discover the asymmetry and
the preferred sibling, instead of relying on CPU type and enumeration order
(considering that there are also multiple SMT configurations that can alter this
asymmetry... it's not just SMT on/off).

That said, we can ignore this patch for now. I'll come up with a better
solution, hopefully.

Thanks,
-Andrea

  reply	other threads:[~2026-07-03 17:07 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-30 15:27 [PATCH] sched/fair: Stabilize idle SMT core selection with asym-capacity Andrea Righi
2026-07-03  5:51 ` K Prateek Nayak
2026-07-03  9:40   ` Andrea Righi
2026-07-03 10:00     ` Christian Loehle
2026-07-03 14:52       ` Andrea Righi
2026-07-03 16:54         ` Peter Zijlstra
2026-07-03 17:07           ` Andrea Righi [this message]
2026-07-03 11:20     ` Julia Lawall
2026-07-03 14:38       ` Andrea Righi
2026-07-03 12:33     ` Andrea Righi
2026-07-03 12:51       ` Julia Lawall

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