[PATCH v2 0/4] clk: ti: fapll/dm816x: clock tree and calculation fixes

[PATCH v2 0/4] clk: ti: fapll/dm816x: clock tree and calculation fixes

[Ettore Chimenti]

During TI DM8168-EVM board testing we found that the clock hierarchy and
clock calculation was broken already on 6.12:

    main_pll_clk1       <--- main PLL should be parent of other PLLs.
       sysclk1_ck                   
       main_pll_clk7            
		...
       main_pll_clk6            
		...
       main_pll_clk5            
		...
       main_pll_clk4            
		...

This series brings fixes and additions for TI DM816x / FAPLL clock tree
and frequency calculation.

Summary:
- Fix clock tree hierarchy by not using ti_dt_clk_name() helper, that
  causes the first PLL as the parent of all clocks in DM816x.
- Correct rate calculation logic in fapll driver (1/2^24, was 1/10^7).
- Add sys_ck alias required for DM816x clock lookup, fixing a boot
  error.
- Add error logging for clocks failing registration to ease debugging.

Fixing clock tree hierarchy is critical as it fixes DM8168-EVM boot
failure in 7.3-rc7. These fixes are affecting DM816x SoCs only.

Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
---
Changes in v2:
- Fixed off-by-one error in clock calculation (Sashiko).
- Fixed clock calculation also in the set rate path.
- Added Fixes tag to clock calculation fix patch.
- Link to v1: https://patch.msgid.link/20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org

---
Andrew Goodbody (1):
      clk: ti: fapll: Fix clock speed calculation

Ettore Chimenti (1):
      clk-816x: add sys_ck clock as sys_clkin_ck alias

Rouven Czerwinski (2):
      clk: ti: fapll: remove ti_dt_clk_name helper
      clk: ti: fapll: print clock name that fails to register

 drivers/clk/ti/clk-816x.c |  1 +
 drivers/clk/ti/fapll.c    | 22 +++++++++-------------
 2 files changed, 10 insertions(+), 13 deletions(-)
---
base-commit: d135ab453a7400a34930bdda1ef4bdc8acfac80e
change-id: 20261014-patch-ektor5-dm8168-clk-e426101415b0

Best regards,
--  
Ettore Chimenti <ettore.chimenti@linaro.org>

[PATCH v2 1/4] clk: ti: fapll: remove ti_dt_clk_name helper

[Ettore Chimenti]

From: Rouven Czerwinski <rouven.czerwinski@linaro.org>

The fapll driver uses multiple `clock-output-names`, so we cannot use the
DT helper in this driver because that would assign the first clock
output name as the parent name. This change do not affect other SoCs as
the only consumer is DM816x.

Fixes: 9e56a7d4263c ("clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name()")
Signed-off-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Tested-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
---
 drivers/clk/ti/fapll.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index e54b1df3436e..ae2f6fed10f6 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -10,8 +10,6 @@
 #include <linux/of_address.h>
 #include <linux/clk/ti.h>
 
-#include "clock.h"
-
 /* FAPLL Control Register PLL_CTRL */
 #define FAPLL_MAIN_MULT_N_SHIFT	16
 #define FAPLL_MAIN_DIV_P_SHIFT	8
@@ -541,7 +539,6 @@ static void __init ti_fapll_setup(struct device_node *node)
 	struct clk_init_data *init = NULL;
 	const char *parent_name[2];
 	struct clk *pll_clk;
-	const char *name;
 	int i;
 
 	fd = kzalloc_obj(*fd);
@@ -559,8 +556,7 @@ static void __init ti_fapll_setup(struct device_node *node)
 		goto free;
 
 	init->ops = &ti_fapll_ops;
-	name = ti_dt_clk_name(node);
-	init->name = name;
+	init->name = node->name;
 
 	init->num_parents = of_clk_get_parent_count(node);
 	if (init->num_parents != 2) {
@@ -592,7 +588,7 @@ static void __init ti_fapll_setup(struct device_node *node)
 	if (fapll_is_ddr_pll(fd->base))
 		fd->bypass_bit_inverted = true;
 
-	fd->name = name;
+	fd->name = node->name;
 	fd->hw.init = init;
 
 	/* Register the parent PLL */
@@ -639,7 +635,7 @@ static void __init ti_fapll_setup(struct device_node *node)
 				freq = NULL;
 		}
 		synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
-						 output_name, name, pll_clk);
+						 output_name, node->name, pll_clk);
 		if (IS_ERR(synth_clk))
 			continue;
 

-- 
2.56.0

[PATCH v2 2/4] clk: ti: fapll: Fix clock speed calculation

[Ettore Chimenti]

From: Andrew Goodbody <andrew.goodbody@linaro.org>

The fractional part of the divider was being treated as 1/10000000
whereas it is in fact 1/2^24 (1/16777216). This led to incorrect clock
speeds being reported when a fractional divider was in use. Correct it.
As well as fixing the clock speed calculation when read, also update the
calculation on set in a similar manner.

Fixes: 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x")
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
---
 drivers/clk/ti/fapll.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index ae2f6fed10f6..8ab9acd57b60 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -336,8 +336,8 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
 		v = readl_relaxed(synth->freq);
 		synth_int_div = (v >> 24) & 0xf;
 		synth_frac_div = v & 0xffffff;
-		synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
-		rate *= 10000000;
+		synth_div_freq = (synth_int_div * 16777216) + synth_frac_div;
+		rate *= 16777216;
 		do_div(rate, synth_div_freq);
 		rate *= SYNTH_PHASE_K;
 	}
@@ -378,10 +378,10 @@ static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
 	for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
 		synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
 						 SYNTH_PHASE_K *
-						 10000000,
+						 16777216,
 						 rate * post_div_m);
-		synth_frac_div = synth_int_div % 10000000;
-		synth_int_div /= 10000000;
+		synth_frac_div = synth_int_div % 16777216;
+		synth_int_div /= 16777216;
 
 		if (synth_int_div <= SYNTH_MAX_INT_DIV)
 			break;

-- 
2.56.0

[PATCH v2 3/4] clk: ti: fapll: print clock name that fails to register

[Ettore Chimenti]

From: Rouven Czerwinski <rouven.czerwinski@linaro.org>

Improve the error message when a clock fails to register by including
the clock's name and its parent's name for better debugging.

Signed-off-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
---
 drivers/clk/ti/fapll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 8ab9acd57b60..d360e9d986c3 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -520,7 +520,7 @@ static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
 
 	clk = clk_register(NULL, &synth->hw);
 	if (IS_ERR(clk)) {
-		pr_err("failed to register clock\n");
+		pr_err("failed to register clock '%s' for parent '%s'\n", name, parent);
 		goto free;
 	}
 

-- 
2.56.0

[PATCH v2 4/4] clk-816x: add sys_ck clock as sys_clkin_ck alias

[Ettore Chimenti]

This patch adds a new clock alias for the DM816x system, mapping
'sys_ck' to 'sys_clkin_ck'. This change is necessary because the voltage
management driver searches for 'sys_ck' in these systems and fails
without this alias. By including 'sys_ck' as an alias for
'sys_clkin_ck', we ensure compatibility with existing drivers that may
reference 'sys_ck'.

Tested-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
---
 drivers/clk/ti/clk-816x.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c
index 3b8e483aec92..fe6f66fc5a05 100644
--- a/drivers/clk/ti/clk-816x.c
+++ b/drivers/clk/ti/clk-816x.c
@@ -57,6 +57,7 @@ static struct ti_dt_clk dm816x_clks[] = {
 	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
 	DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
 	DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
+	DT_CLK(NULL, "sys_ck", "sys_clkin_ck"),
 	{ .node_name = NULL },
 };
 

-- 
2.56.0

Re: [PATCH v2 4/4] clk-816x: add sys_ck clock as sys_clkin_ck alias

[Ettore Chimenti]

Hi,

On Wed Oct 28, 2026 at 4:53 PM CET, Ettore Chimenti wrote:
> This patch adds a new clock alias for the DM816x system, mapping
> 'sys_ck' to 'sys_clkin_ck'. This change is necessary because the voltage
> management driver searches for 'sys_ck' in these systems and fails
> without this alias. By including 'sys_ck' as an alias for
> 'sys_clkin_ck', we ensure compatibility with existing drivers that may
> reference 'sys_ck'.
>
> Tested-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
> ---
>  drivers/clk/ti/clk-816x.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c
> index 3b8e483aec92..fe6f66fc5a05 100644
> --- a/drivers/clk/ti/clk-816x.c
> +++ b/drivers/clk/ti/clk-816x.c
> @@ -57,6 +57,7 @@ static struct ti_dt_clk dm816x_clks[] = {
>  	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
>  	DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
>  	DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
> +	DT_CLK(NULL, "sys_ck", "sys_clkin_ck"),
>  	{ .node_name = NULL },
>  };
>  

I'll drop this patch from the series. The proposed approach from Sashiko
seems sound and I just sent a separate patch that implements that.

Best regards,
Ettore

Re: [PATCH v2 4/4] clk-816x: add sys_ck clock as sys_clkin_ck alias

[Brian Masney]

Hi Ettore,

On 2026-10-30 11:48:58+01:00, Ettore Chimenti wrote:
> On Wed Oct 28, 2026 at 4:53 PM CET, Ettore Chimenti wrote:
> 
> > This patch adds a new clock alias for the DM816x system, mapping
> > 'sys_ck' to 'sys_clkin_ck'. This change is necessary because the voltage
> > management driver searches for 'sys_ck' in these systems and fails
> > without this alias. By including 'sys_ck' as an alias for
> > 'sys_clkin_ck', we ensure compatibility with existing drivers that may
> > reference 'sys_ck'.
> >
> > Tested-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> > Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
> > ---
> >  drivers/clk/ti/clk-816x.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c
> > index 3b8e483aec92..fe6f66fc5a05 100644
> > --- a/drivers/clk/ti/clk-816x.c
> > +++ b/drivers/clk/ti/clk-816x.c
> > @@ -57,6 +57,7 @@ static struct ti_dt_clk dm816x_clks[] = {
> >  	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
> >  	DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
> >  	DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
> > +	DT_CLK(NULL, "sys_ck", "sys_clkin_ck"),
> >  	{ .node_name = NULL },
> >  };
> 
> I'll drop this patch from the series. The proposed approach from Sashiko
> seems sound and I just sent a separate patch that implements that.

Will there be a follow up to this series for the clk subsystem? I don't
see any. I haven't gone through the other patches in this series. Or are
just the first 3 patches here what needs to be reviewed / possibly
merged?

Brian

-- 
Brian Masney <masneyb@kernel.org>

Re: [PATCH v2 4/4] clk-816x: add sys_ck clock as sys_clkin_ck alias

[Ettore Chimenti]

Hi Brian,

On Wed Nov 11, 2026 at 7:53 PM CET, Brian Masney wrote:
> Hi Ettore,
>
> On 2026-10-30 11:48:58+01:00, Ettore Chimenti wrote:
>> On Wed Oct 28, 2026 at 4:53 PM CET, Ettore Chimenti wrote:
>> 
>> > This patch adds a new clock alias for the DM816x system, mapping
>> > 'sys_ck' to 'sys_clkin_ck'. This change is necessary because the voltage
>> > management driver searches for 'sys_ck' in these systems and fails
>> > without this alias. By including 'sys_ck' as an alias for
>> > 'sys_clkin_ck', we ensure compatibility with existing drivers that may
>> > reference 'sys_ck'.
>> >
>> > Tested-by: Andrew Goodbody <andrew.goodbody@linaro.org>
>> > Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
>> > ---
>> >  drivers/clk/ti/clk-816x.c | 1 +
>> >  1 file changed, 1 insertion(+)
>> >
>> > diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c
>> > index 3b8e483aec92..fe6f66fc5a05 100644
>> > --- a/drivers/clk/ti/clk-816x.c
>> > +++ b/drivers/clk/ti/clk-816x.c
>> > @@ -57,6 +57,7 @@ static struct ti_dt_clk dm816x_clks[] = {
>> >  	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
>> >  	DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
>> >  	DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
>> > +	DT_CLK(NULL, "sys_ck", "sys_clkin_ck"),
>> >  	{ .node_name = NULL },
>> >  };
>> 
>> I'll drop this patch from the series. The proposed approach from Sashiko
>> seems sound and I just sent a separate patch that implements that.
>
> Will there be a follow up to this series for the clk subsystem? I don't
> see any. I haven't gone through the other patches in this series. Or are
> just the first 3 patches here what needs to be reviewed / possibly
> merged?

Actually, I was waiting for reviews on the other patches before sending
a v3 to collect R-b's. 

However, this patch (4/4) can be skipped reviewing. It will be dropped
as I've already sent [1] (it belongs to another subsystem, so you might
have missed it).

[1]: https://lore.kernel.org/all/20261030-patch-ektor5-dm81xx-vd-v1-1-8ba90608c25b@linaro.org/

>
> Brian

Thanks,
Ettore

Re: [PATCH v2 2/4] clk: ti: fapll: Fix clock speed calculation

[Brian Masney]

Hi Ettore,

> The fractional part of the divider was being treated as 1/10000000
> whereas it is in fact 1/2^24 (1/16777216). This led to incorrect clock
> speeds being reported when a fractional divider was in use. Correct it.
> As well as fixing the clock speed calculation when read, also update the
> calculation on set in a similar manner.
> 
> Fixes: 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x")
> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>

Should there be a Co-Developed-By here and on the other patches?

> Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
> ---
>  drivers/clk/ti/fapll.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
> index ae2f6fed10f6..8ab9acd57b60 100644
> --- a/drivers/clk/ti/fapll.c
> +++ b/drivers/clk/ti/fapll.c
> @@ -336,8 +336,8 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
>  		v = readl_relaxed(synth->freq);
>  		synth_int_div = (v >> 24) & 0xf;
>  		synth_frac_div = v & 0xffffff;
> -		synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
> -		rate *= 10000000;
> +		synth_div_freq = (synth_int_div * 16777216) + synth_frac_div;
> +		rate *= 16777216;

The 16777216 magic number appears multiple times. Plugging this into my
calculator, I see it's 1 << 24. How about adding some defines:

#define SYNTH_FRAC_DIV_BITS	24
#define SYNTH_FRAC_DIV_SCALE	BIT(SYNTH_FRAC_DIV_BITS)

Brian

-- 
Brian Masney <masneyb@kernel.org>

Re: [PATCH v2 1/4] clk: ti: fapll: remove ti_dt_clk_name helper

[Brian Masney]

> The fapll driver uses multiple `clock-output-names`, so we cannot use the
> DT helper in this driver because that would assign the first clock
> output name as the parent name. This change do not affect other SoCs as
> the only consumer is DM816x.
> 
> Fixes: 9e56a7d4263c ("clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name()")
> Signed-off-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
> Tested-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>

I see what you are doing here but can you give a more detailed commit
message / argument here in favor of the change to make it easier on
others that will evaluate this about whether or not it should be
backported to a different kernel.

Brian

-- 
Brian Masney <masneyb@kernel.org>

Re: [PATCH v2 2/4] clk: ti: fapll: Fix clock speed calculation

[Andrew Goodbody]

On 12/11/2026 01:12, Brian Masney wrote:
> Hi Ettore,
> 
>> The fractional part of the divider was being treated as 1/10000000
>> whereas it is in fact 1/2^24 (1/16777216). This led to incorrect clock
>> speeds being reported when a fractional divider was in use. Correct it.
>> As well as fixing the clock speed calculation when read, also update the
>> calculation on set in a similar manner.
>>
>> Fixes: 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x")
>> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> 
> Should there be a Co-Developed-By here and on the other patches?

Not sure about that. This is my patch but is being submitted by Ettore 
in a series of patches that affect the clk system. We were working 
together on a project and at times each produced patches. Ettore has 
collected together this series for submission.

>> Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
>> ---
>>   drivers/clk/ti/fapll.c | 10 +++++-----
>>   1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
>> index ae2f6fed10f6..8ab9acd57b60 100644
>> --- a/drivers/clk/ti/fapll.c
>> +++ b/drivers/clk/ti/fapll.c
>> @@ -336,8 +336,8 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
>>   		v = readl_relaxed(synth->freq);
>>   		synth_int_div = (v >> 24) & 0xf;
>>   		synth_frac_div = v & 0xffffff;
>> -		synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
>> -		rate *= 10000000;
>> +		synth_div_freq = (synth_int_div * 16777216) + synth_frac_div;
>> +		rate *= 16777216;
> 
> The 16777216 magic number appears multiple times. Plugging this into my
> calculator, I see it's 1 << 24. How about adding some defines:
> 
> #define SYNTH_FRAC_DIV_BITS	24
> #define SYNTH_FRAC_DIV_SCALE	BIT(SYNTH_FRAC_DIV_BITS)

Sure, can do.

Andrew

> Brian
> 

Re: [PATCH v2 1/4] clk: ti: fapll: remove ti_dt_clk_name helper

[Andrew Goodbody]

On 12/11/2026 01:12, Brian Masney wrote:
>> The fapll driver uses multiple `clock-output-names`, so we cannot use the
>> DT helper in this driver because that would assign the first clock
>> output name as the parent name. This change do not affect other SoCs as
>> the only consumer is DM816x.
>>
>> Fixes: 9e56a7d4263c ("clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name()")
>> Signed-off-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
>> Tested-by: Andrew Goodbody <andrew.goodbody@linaro.org>
>> Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
> 
> I see what you are doing here but can you give a more detailed commit
> message / argument here in favor of the change to make it easier on
> others that will evaluate this about whether or not it should be
> backported to a different kernel.
> 
> Brian
Maybe Rouven will step in here but the main thing is that fapll.c should 
never have been converted to use ti_dt_clk_name() as it does not work 
with the binding [1] and usage.

eg with the node

	main_fapll: main_fapll {
		#clock-cells = <1>;
		compatible = "ti,dm816-fapll-clock";
		reg = <0x400 0x40>;
		clocks = <&sys_clkin_ck &sys_clkin_ck>;
		clock-indices = <1>, <2>, <3>, <4>, <5>,
				<6>, <7>;
		clock-output-names = "main_pll_clk1",
				     "main_pll_clk2",
				     "main_pll_clk3",
				     "main_pll_clk4",
				     "main_pll_clk5",
				     "main_pll_clk6",
				     "main_pll_clk7";
	};

The use of ti_dt_clk_name() results in no attempt to register the clk 
main_fapll and duplicate attempts to register main_pll_clk1 of which the 
second fails leading to an early exit, the clk system is left not fully 
initialised and other problems follow with eg USB failing to init due to 
lack of clock.

Andrew

1. Documentation/devicetree/bindings/clock/ti/fapll.txt

Re: [PATCH v2 2/4] clk: ti: fapll: Fix clock speed calculation

[Brian Masney]

On Thu, Nov 12, 2026 at 05:24:41PM +0000, Andrew Goodbody wrote:
> On 12/11/2026 01:12, Brian Masney wrote:
> > Hi Ettore,
> > 
> > > The fractional part of the divider was being treated as 1/10000000
> > > whereas it is in fact 1/2^24 (1/16777216). This led to incorrect clock
> > > speeds being reported when a fractional divider was in use. Correct it.
> > > As well as fixing the clock speed calculation when read, also update the
> > > calculation on set in a similar manner.
> > > 
> > > Fixes: 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x")
> > > Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> > 
> > Should there be a Co-Developed-By here and on the other patches?
> 
> Not sure about that. This is my patch but is being submitted by Ettore in a
> series of patches that affect the clk system. We were working together on a
> project and at times each produced patches. Ettore has collected together
> this series for submission.

OK, I see. That makes sense. Thanks for confirming.

Brian