[PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Prashanth K]

Enabling U1 and U2 power-saving states can lead to stability and
performance issues, particularly for latency-sensitive or high-
throughput applications. These low-power link states are intended
to reduce power consumption by allowing the device to enter partial
low-power modes during idle periods. However, they can sometimes
result in unexpected behavior. Over the years, some of the issues
seen are as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent low power states. These packet drops are often reflected
as Missed Isochronous transfers as the controller was not able to
send the packet in that microframe interval and hence glitches are
seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

4. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

5. On targets like SDX75, intermittent disconnects were observed
with certain cables due to impedence variations.

To avoid such issues, the USB team at Qualcomm added these quirks
to all targets in the past 4-5 years and extensive testing was done.
Although these are intermittent power states, disabling them didn't
cause any major increase in power numbers.

This series was earlier started by Krishna Kurapati where he disabled
U1/U2 on some SM targets. I'm extending this to more devices including
Auto, Compute and IOT platforms. On a side note, this quirk has been
already included on some mobile targets like SM8550/8650.

Changes in v2:
- Removed the wrongly added quirks from tcsr_mutex node.
- Link to v2: https://lore.kernel.org/all/20241213095237.1409174-1-quic_prashk@quicinc.com/

Link to RFC:
https://lore.kernel.org/all/20241107073650.13473-1-quic_kriskura@quicinc.com/#Z31arch:arm64:boot:dts:qcom:sm8250.dtsi

Krishna Kurapati (8):
  arm64: dts: qcom: Disable USB U1/U2 entry for SM8350
  arm64: dts: qcom: Disable USB U1/U2 entry for SM8450
  arm64: dts: qcom: Disable USB U1/U2 entry for SM8150
  arm64: dts: qcom: Disable USB U1/U2 entry for SM6125
  arm64: dts: qcom: Disable USB U1/U2 entry for SM8250
  arm64: dts: qcom: Disable USB U1/U2 entry for SM6350
  arm64: dts: qcom: Disable USB U1/U2 entry for SC7280
  arm64: dts: qcom: Disable USB U1/U2 entry for SA8775P

Prashanth K (11):
  arm64: dts: qcom: Disable USB U1/U2 entry for SDM630
  arm64: dts: qcom: Disable USB U1/U2 entry for SDM845
  arm64: dts: qcom: Disable USB U1/U2 entry for SDX75
  ARM: dts: qcom: Disable USB U1/U2 entry for SDX65
  ARM: dts: qcom: Disable USB U1/U2 entry for SDX55
  arm64: dts: qcom: Disable USB U1/U2 entry for QCS404
  arm64: dts: qcom: Disable USB U1/U2 entry for SC7180
  arm64: dts: qcom: Disable USB U1/U2 entry for X1E80100
  arm64: dts: qcom: Disable USB U1/U2 entry for QDU1000
  arm64: dts: qcom: Disable USB U1/U2 entry for SC8280XP
  arm64: dts: qcom: Disable USB U1/U2 entry for SC8180X

 arch/arm/boot/dts/qcom/qcom-sdx55.dtsi |  2 ++
 arch/arm/boot/dts/qcom/qcom-sdx65.dtsi |  2 ++
 arch/arm64/boot/dts/qcom/qcs404.dtsi   |  4 ++++
 arch/arm64/boot/dts/qcom/qdu1000.dtsi  |  2 ++
 arch/arm64/boot/dts/qcom/sa8775p.dtsi  |  6 ++++++
 arch/arm64/boot/dts/qcom/sc7180.dtsi   |  2 ++
 arch/arm64/boot/dts/qcom/sc7280.dtsi   |  4 ++++
 arch/arm64/boot/dts/qcom/sc8180x.dtsi  |  6 ++++++
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi |  6 ++++++
 arch/arm64/boot/dts/qcom/sdm630.dtsi   |  4 ++++
 arch/arm64/boot/dts/qcom/sdm845.dtsi   |  4 ++++
 arch/arm64/boot/dts/qcom/sdx75.dtsi    |  2 ++
 arch/arm64/boot/dts/qcom/sm6125.dtsi   |  2 ++
 arch/arm64/boot/dts/qcom/sm6350.dtsi   |  2 ++
 arch/arm64/boot/dts/qcom/sm8150.dtsi   |  4 ++++
 arch/arm64/boot/dts/qcom/sm8250.dtsi   |  4 ++++
 arch/arm64/boot/dts/qcom/sm8350.dtsi   |  4 ++++
 arch/arm64/boot/dts/qcom/sm8450.dtsi   |  2 ++
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++
 19 files changed, 72 insertions(+)

-- 
2.25.1

[PATCH v3 01/19] arm64: dts: qcom: Disable USB U1/U2 entry for SM8350

[Prashanth K]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 877905dfd861..e8f9d8bab309 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2409,6 +2409,8 @@ usb_1_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -2485,6 +2487,8 @@ usb_2_dwc3: usb@a800000 {
 				iommus = <&apps_smmu 0x20 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
-- 
2.25.1

[PATCH v3 02/19] arm64: dts: qcom: Disable USB U1/U2 entry for SM8450

[Prashanth K]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 53147aa6f7e4..331f223f47c3 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -4672,6 +4672,8 @@ usb_1_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
-- 
2.25.1

[PATCH v3 03/19] arm64: dts: qcom: Disable USB U1/U2 entry for SM8150

[Prashanth K]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index cedae8d03a51..4dbda54b47a5 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3658,6 +3658,8 @@ usb_1_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x140 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -3735,6 +3737,8 @@ usb_2_dwc3: usb@a800000 {
 				iommus = <&apps_smmu 0x160 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
-- 
2.25.1

[PATCH v3 04/19] arm64: dts: qcom: Disable USB U1/U2 entry for SM6125

[Prashanth K]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 17d528d63934..2da6466b2029 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -1209,6 +1209,8 @@ usb3_dwc3: usb@4e00000 {
 				phy-names = "usb2-phy";
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				maximum-speed = "high-speed";
 				dr_mode = "peripheral";
 			};
-- 
2.25.1

[PATCH v3 05/19] arm64: dts: qcom: Disable USB U1/U2 entry for SM8250

[Prashanth K]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 48318ed1ce98..e40f3b21e37a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4207,6 +4207,8 @@ usb_1_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -4294,6 +4296,8 @@ usb_2_dwc3: usb@a800000 {
 				iommus = <&apps_smmu 0x20 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
-- 
2.25.1

[PATCH v3 06/19] arm64: dts: qcom: Disable USB U1/U2 entry for SM6350

[Prashanth K]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 8d697280249f..e64447b765a2 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1924,6 +1924,8 @@ usb_1_dwc3: usb@a600000 {
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				usb-role-switch;
-- 
2.25.1

[PATCH v3 07/19] arm64: dts: qcom: Disable USB U1/U2 entry for SC7280

[Prashanth K]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 55db1c83ef55..e0fda894724b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3715,6 +3715,8 @@ usb_2_dwc3: usb@8c00000 {
 				iommus = <&apps_smmu 0xa0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>;
 				phy-names = "usb2-phy";
 				maximum-speed = "high-speed";
@@ -4244,6 +4246,8 @@ usb_1_dwc3: usb@a600000 {
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				maximum-speed = "super-speed";
-- 
2.25.1

[PATCH v3 08/19] arm64: dts: qcom: Disable USB U1/U2 entry for SA8775P

[Prashanth K]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 9f315a51a7c1..530fea25af55 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3411,6 +3411,8 @@ usb_0_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x080 0x0>;
 				phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3500,6 +3502,8 @@ usb_1_dwc3: usb@a800000 {
 				iommus = <&apps_smmu 0x0a0 0x0>;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3563,6 +3567,8 @@ usb_2_dwc3: usb@a400000 {
 				iommus = <&apps_smmu 0x020 0x0>;
 				phys = <&usb_2_hsphy>;
 				phy-names = "usb2-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
-- 
2.25.1

[PATCH v3 09/19] arm64: dts: qcom: Disable USB U1/U2 entry for SDM630

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 19420cfdadf1..a2c079bac1a7 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1300,6 +1300,8 @@ usb3_dwc3: usb@a800000 {
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				phys = <&qusb2phy0>, <&usb3_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
@@ -1505,6 +1507,8 @@ usb2_dwc3: usb@c200000 {
 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				/* This is the HS-only host */
 				maximum-speed = "high-speed";
-- 
2.25.1

[PATCH v3 10/19] arm64: dts: qcom: Disable USB U1/U2 entry for SDM845

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 1ed794638a7c..373a591bfb4d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4139,6 +4139,8 @@ usb_1_dwc3: usb@a600000 {
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -4215,6 +4217,8 @@ usb_2_dwc3: usb@a800000 {
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
-- 
2.25.1

[PATCH v3 11/19] arm64: dts: qcom: Disable USB U1/U2 entry for SDX75

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

3. On targets like SDX75, intermittent disconnects were observed
with certain cables due to impedence variations.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index 5f7e59ecf1ca..8e444a9d00ed 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -1037,6 +1037,8 @@ usb_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x80 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_hsphy>,
 				       <&usb_qmpphy>;
 				phy-names = "usb2-phy",
-- 
2.25.1

[PATCH v3 12/19] ARM: dts: qcom: Disable USB U1/U2 entry for SDX65

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

3. On targets like SDX75, intermittent disconnects were observed
with certain cables due to impedence variations.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 3bc67bb8c1eb..3941d1f1af72 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -526,6 +526,8 @@ usb_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x1a0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_hsphy>, <&usb_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
-- 
2.25.1

[PATCH v3 13/19] ARM: dts: qcom: Disable USB U1/U2 entry for SDX55

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

3. On targets like SDX75, intermittent disconnects were observed
with certain cables due to impedence variations.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
index d0f6120b665d..f431cdfbbc3d 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
@@ -613,6 +613,8 @@ usb_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x1a0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_hsphy>, <&usb_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
-- 
2.25.1

[PATCH v3 14/19] arm64: dts: qcom: Disable USB U1/U2 entry for QCS404

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 215ba146207a..a77a22e3f234 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -694,6 +694,8 @@ usb3_dwc3: usb@7580000 {
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				dr_mode = "otg";
 			};
 		};
@@ -731,6 +733,8 @@ usb@78c0000 {
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				dr_mode = "peripheral";
 			};
 		};
-- 
2.25.1

[PATCH v3 15/19] arm64: dts: qcom: Disable USB U1/U2 entry for SC7180

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 76fe314d2ad5..3daff0ca152f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3064,6 +3064,8 @@ usb_1_dwc3: usb@a600000 {
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				maximum-speed = "super-speed";
-- 
2.25.1

[PATCH v3 16/19] arm64: dts: qcom: Disable USB U1/U2 entry for X1E80100

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 88805629ed2b..d522255bb249 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -4063,6 +4063,8 @@ usb_1_ss2_dwc3: usb@a000000 {
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 
@@ -4151,6 +4153,8 @@ usb_2_dwc3: usb@a200000 {
 				phys = <&usb_2_hsphy>;
 				phy-names = "usb2-phy";
 				maximum-speed = "high-speed";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				ports {
 					#address-cells = <1>;
@@ -4247,6 +4251,8 @@ usb_mp_dwc3: usb@a400000 {
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 			};
@@ -4318,6 +4324,8 @@ usb_1_ss0_dwc3: usb@a600000 {
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 
@@ -4418,6 +4426,8 @@ usb_1_ss1_dwc3: usb@a800000 {
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 
-- 
2.25.1

[PATCH v3 17/19] arm64: dts: qcom: Disable USB U1/U2 entry for QDU1000

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 47c0dd31aaf2..85e9ccfc9655 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1009,6 +1009,8 @@ usb_1_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0xc0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>,
 				       <&usb_1_qmpphy>;
 				phy-names = "usb2-phy",
-- 
2.25.1

[PATCH v3 18/19] arm64: dts: qcom: Disable USB U1/U2 entry for SC8280XP

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index ef06d1ac084d..db1d7f158866 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3536,6 +3536,8 @@ usb_2_dwc3: usb@a400000 {
 					    "usb2-2",
 					    "usb2-3";
 				dr_mode = "host";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3593,6 +3595,8 @@ usb_0_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x820 0x0>;
 				phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				ports {
 					#address-cells = <1>;
@@ -3670,6 +3674,8 @@ usb_1_dwc3: usb@a800000 {
 				iommus = <&apps_smmu 0x860 0x0>;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				ports {
 					#address-cells = <1>;
-- 
2.25.1

[PATCH v3 19/19] arm64: dts: qcom: Disable USB U1/U2 entry for SC8180X

[Prashanth K]

Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

Disabling these intermittent power states enhances device stability
without affecting power usage.

Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 745a7d0b8381..28693a3bfc7f 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2762,6 +2762,8 @@ usb_mp_dwc3: usb@a400000 {
 				iommus = <&apps_smmu 0x60 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_mp_hsphy0>,
 				       <&usb_mp_qmpphy0>,
 				       <&usb_mp_hsphy1>,
@@ -2825,6 +2827,8 @@ usb_prim_dwc3: usb@a600000 {
 				iommus = <&apps_smmu 0x140 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -2902,6 +2906,8 @@ usb_sec_dwc3: usb@a800000 {
 				iommus = <&apps_smmu 0x160 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
-- 
2.25.1

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Dmitry Baryshkov]

On Wed, Dec 18, 2024 at 03:56:48PM +0530, Prashanth K wrote:
> Enabling U1 and U2 power-saving states can lead to stability and
> performance issues, particularly for latency-sensitive or high-
> throughput applications. These low-power link states are intended
> to reduce power consumption by allowing the device to enter partial
> low-power modes during idle periods. However, they can sometimes
> result in unexpected behavior. Over the years, some of the issues
> seen are as follows:
> 

[..]

> 
> This series was earlier started by Krishna Kurapati where he disabled
> U1/U2 on some SM targets. I'm extending this to more devices including
> Auto, Compute and IOT platforms. On a side note, this quirk has been
> already included on some mobile targets like SM8550/8650.

Why are you resending previous patches rather than adding another series
on top of it?

> 
> Changes in v2:
> - Removed the wrongly added quirks from tcsr_mutex node.
> - Link to v2: https://lore.kernel.org/all/20241213095237.1409174-1-quic_prashk@quicinc.com/

What was changed in v3?

> 
> Link to RFC:
> https://lore.kernel.org/all/20241107073650.13473-1-quic_kriskura@quicinc.com/#Z31arch:arm64:boot:dts:qcom:sm8250.dtsi
> 

-- 
With best wishes
Dmitry

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Prashanth K]

On 18-12-24 04:57 pm, Dmitry Baryshkov wrote:
> On Wed, Dec 18, 2024 at 03:56:48PM +0530, Prashanth K wrote:
>> Enabling U1 and U2 power-saving states can lead to stability and
>> performance issues, particularly for latency-sensitive or high-
>> throughput applications. These low-power link states are intended
>> to reduce power consumption by allowing the device to enter partial
>> low-power modes during idle periods. However, they can sometimes
>> result in unexpected behavior. Over the years, some of the issues
>> seen are as follows:
>>
> 
> [..]
> 
>>
>> This series was earlier started by Krishna Kurapati where he disabled
>> U1/U2 on some SM targets. I'm extending this to more devices including
>> Auto, Compute and IOT platforms. On a side note, this quirk has been
>> already included on some mobile targets like SM8550/8650.
> 
> Why are you resending previous patches rather than adding another series
> on top of it?
> 
Hi Dmitry,

RFC had only one patch with quirks (to disable u1/u2) only for few
targets (SM8150, 8250, 8350, 8450). It was later decided to split it
into per-file commits as per the review comments. Hence I clubbed
Krishna's changes along with few more targets. Let me know if this needs
to be changed.

>>
>> Changes in v2:
>> - Removed the wrongly added quirks from tcsr_mutex node.
>> - Link to v2: https://lore.kernel.org/all/20241213095237.1409174-1-quic_prashk@quicinc.com/
> 
> What was changed in v3?
It was supposed to be "Changes in v3" instead of v2.
> 
>>
>> Link to RFC:
>> https://lore.kernel.org/all/20241107073650.13473-1-quic_kriskura@quicinc.com/#Z31arch:arm64:boot:dts:qcom:sm8250.dtsi
>>
> 
Regards,
Prashanth K

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Dmitry Baryshkov]

On Wed, Dec 18, 2024 at 05:18:50PM +0530, Prashanth K wrote:
> 
> 
> On 18-12-24 04:57 pm, Dmitry Baryshkov wrote:
> > On Wed, Dec 18, 2024 at 03:56:48PM +0530, Prashanth K wrote:
> >> Enabling U1 and U2 power-saving states can lead to stability and
> >> performance issues, particularly for latency-sensitive or high-
> >> throughput applications. These low-power link states are intended
> >> to reduce power consumption by allowing the device to enter partial
> >> low-power modes during idle periods. However, they can sometimes
> >> result in unexpected behavior. Over the years, some of the issues
> >> seen are as follows:
> >>
> > 
> > [..]
> > 
> >>
> >> This series was earlier started by Krishna Kurapati where he disabled
> >> U1/U2 on some SM targets. I'm extending this to more devices including
> >> Auto, Compute and IOT platforms. On a side note, this quirk has been
> >> already included on some mobile targets like SM8550/8650.
> > 
> > Why are you resending previous patches rather than adding another series
> > on top of it?
> > 
> Hi Dmitry,
> 
> RFC had only one patch with quirks (to disable u1/u2) only for few
> targets (SM8150, 8250, 8350, 8450). It was later decided to split it
> into per-file commits as per the review comments. Hence I clubbed
> Krishna's changes along with few more targets. Let me know if this needs
> to be changed.

No, it's fine. The text in the commit message lead me to a wrong
conclusion.

> 
> >>
> >> Changes in v2:
> >> - Removed the wrongly added quirks from tcsr_mutex node.
> >> - Link to v2: https://lore.kernel.org/all/20241213095237.1409174-1-quic_prashk@quicinc.com/
> > 
> > What was changed in v3?
> It was supposed to be "Changes in v3" instead of v2.

Then where is a changelog between RFC and v2?

Please consider switching to the b4 tool, it handles such issues for
you.

> > 
> >>
> >> Link to RFC:
> >> https://lore.kernel.org/all/20241107073650.13473-1-quic_kriskura@quicinc.com/#Z31arch:arm64:boot:dts:qcom:sm8250.dtsi
> >>
> > 
> Regards,
> Prashanth K
> 

-- 
With best wishes
Dmitry

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Prashanth K]

On 19-12-24 08:37 am, Dmitry Baryshkov wrote:
> On Wed, Dec 18, 2024 at 05:18:50PM +0530, Prashanth K wrote:
>>
>>
>> On 18-12-24 04:57 pm, Dmitry Baryshkov wrote:
>>> On Wed, Dec 18, 2024 at 03:56:48PM +0530, Prashanth K wrote:
>>>> Enabling U1 and U2 power-saving states can lead to stability and
>>>> performance issues, particularly for latency-sensitive or high-
>>>> throughput applications. These low-power link states are intended
>>>> to reduce power consumption by allowing the device to enter partial
>>>> low-power modes during idle periods. However, they can sometimes
>>>> result in unexpected behavior. Over the years, some of the issues
>>>> seen are as follows:
>>>>
>>>
>>> [..]
>>>
>>>>
>>>> This series was earlier started by Krishna Kurapati where he disabled
>>>> U1/U2 on some SM targets. I'm extending this to more devices including
>>>> Auto, Compute and IOT platforms. On a side note, this quirk has been
>>>> already included on some mobile targets like SM8550/8650.
>>>
>>> Why are you resending previous patches rather than adding another series
>>> on top of it?
>>>
>> Hi Dmitry,
>>
>> RFC had only one patch with quirks (to disable u1/u2) only for few
>> targets (SM8150, 8250, 8350, 8450). It was later decided to split it
>> into per-file commits as per the review comments. Hence I clubbed
>> Krishna's changes along with few more targets. Let me know if this needs
>> to be changed.
> 
> No, it's fine. The text in the commit message lead me to a wrong
> conclusion.
> 
Ok sure.
>>
>>>>
>>>> Changes in v2:
>>>> - Removed the wrongly added quirks from tcsr_mutex node.
>>>> - Link to v2: https://lore.kernel.org/all/20241213095237.1409174-1-quic_prashk@quicinc.com/
>>>
>>> What was changed in v3?
>> It was supposed to be "Changes in v3" instead of v2.
> 
> Then where is a changelog between RFC and v2?
> 
> Please consider switching to the b4 tool, it handles such issues for
> you.
> 
Ok, Should I send a new version updating the cover letter?
>>>
>>>>
>>>> Link to RFC:
>>>> https://lore.kernel.org/all/20241107073650.13473-1-quic_kriskura@quicinc.com/#Z31arch:arm64:boot:dts:qcom:sm8250.dtsi
>>>>
>>>
>> Regards,
>> Prashanth K
>>
> 

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Dmitry Baryshkov]

On Thu, Dec 19, 2024 at 09:47:12AM +0530, Prashanth K wrote:
> 
> 
> On 19-12-24 08:37 am, Dmitry Baryshkov wrote:
> > On Wed, Dec 18, 2024 at 05:18:50PM +0530, Prashanth K wrote:
> >>
> >>
> >> On 18-12-24 04:57 pm, Dmitry Baryshkov wrote:
> >>> On Wed, Dec 18, 2024 at 03:56:48PM +0530, Prashanth K wrote:
> >>>> Enabling U1 and U2 power-saving states can lead to stability and
> >>>> performance issues, particularly for latency-sensitive or high-
> >>>> throughput applications. These low-power link states are intended
> >>>> to reduce power consumption by allowing the device to enter partial
> >>>> low-power modes during idle periods. However, they can sometimes
> >>>> result in unexpected behavior. Over the years, some of the issues
> >>>> seen are as follows:
> >>>>
> >>>
> >>> [..]
> >>>
> >>>>
> >>>> This series was earlier started by Krishna Kurapati where he disabled
> >>>> U1/U2 on some SM targets. I'm extending this to more devices including
> >>>> Auto, Compute and IOT platforms. On a side note, this quirk has been
> >>>> already included on some mobile targets like SM8550/8650.
> >>>
> >>> Why are you resending previous patches rather than adding another series
> >>> on top of it?
> >>>
> >> Hi Dmitry,
> >>
> >> RFC had only one patch with quirks (to disable u1/u2) only for few
> >> targets (SM8150, 8250, 8350, 8450). It was later decided to split it
> >> into per-file commits as per the review comments. Hence I clubbed
> >> Krishna's changes along with few more targets. Let me know if this needs
> >> to be changed.
> > 
> > No, it's fine. The text in the commit message lead me to a wrong
> > conclusion.
> > 
> Ok sure.
> >>
> >>>>
> >>>> Changes in v2:
> >>>> - Removed the wrongly added quirks from tcsr_mutex node.
> >>>> - Link to v2: https://lore.kernel.org/all/20241213095237.1409174-1-quic_prashk@quicinc.com/
> >>>
> >>> What was changed in v3?
> >> It was supposed to be "Changes in v3" instead of v2.
> > 
> > Then where is a changelog between RFC and v2?
> > 
> > Please consider switching to the b4 tool, it handles such issues for
> > you.
> > 
> Ok, Should I send a new version updating the cover letter?


For now you can provide data in the reply. Just make sure to include it
in the cover letter if the patchset gets reposted.

> >>>
> >>>>
> >>>> Link to RFC:
> >>>> https://lore.kernel.org/all/20241107073650.13473-1-quic_kriskura@quicinc.com/#Z31arch:arm64:boot:dts:qcom:sm8250.dtsi
> >>>>
> >>>
> >> Regards,
> >> Prashanth K
> >>
> > 
> 

-- 
With best wishes
Dmitry

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Prashanth K]

On 19-12-24 06:44 pm, Dmitry Baryshkov wrote:
> On Thu, Dec 19, 2024 at 09:47:12AM +0530, Prashanth K wrote:
>>
>>

[...]

>>>>>> Changes in v2:
>>>>>> - Removed the wrongly added quirks from tcsr_mutex node.
>>>>>> - Link to v2: https://lore.kernel.org/all/20241213095237.1409174-1-quic_prashk@quicinc.com/
>>>>>
>>>>> What was changed in v3?
>>>> It was supposed to be "Changes in v3" instead of v2.
>>>
>>> Then where is a changelog between RFC and v2?
>>>
>>> Please consider switching to the b4 tool, it handles such issues for
>>> you.
>>>
>> Ok, Should I send a new version updating the cover letter?
> 
> 
> For now you can provide data in the reply. Just make sure to include it
> in the cover letter if the patchset gets reposted.
> 

Sure, will update it if I post next version, here's the delta

Changes in v3:
- Removed wrongly added quirks from tcsr_mutex node.
- Link to v2:
https://lore.kernel.org/all/20241213095237.1409174-1-quic_prashk@quicinc.com/

Changes in v2:
- RFC patch was split into series of per-file commits.
- Added the quirks to more targets (Auto, IoT, Mobile, Compute).
- Link to RFC:
https://lore.kernel.org/all/20241107073650.13473-1-quic_kriskura@quicinc.com/#Z31arch:arm64:boot:dts:qcom:sm8250.dtsi

Thanks in advance,
Prashanth K

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Konrad Dybcio]

On 18.12.2024 11:26 AM, Prashanth K wrote:
> Enabling U1 and U2 power-saving states can lead to stability and
> performance issues, particularly for latency-sensitive or high-
> throughput applications. These low-power link states are intended
> to reduce power consumption by allowing the device to enter partial
> low-power modes during idle periods. However, they can sometimes
> result in unexpected behavior. Over the years, some of the issues
> seen are as follows:

For the series:

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Bjorn Andersson]

On Wed, Dec 18, 2024 at 03:56:48PM +0530, Prashanth K wrote:
> Enabling U1 and U2 power-saving states can lead to stability and
> performance issues, particularly for latency-sensitive or high-
> throughput applications. These low-power link states are intended
> to reduce power consumption by allowing the device to enter partial
> low-power modes during idle periods. However, they can sometimes
> result in unexpected behavior. Over the years, some of the issues
> seen are as follows:
> 
> 1. In device mode of operation, when UVC is active, enabling U1/U2
> is sometimes causing packets drops due to delay in entry/exit of
> intermittent low power states. These packet drops are often reflected
> as Missed Isochronous transfers as the controller was not able to
> send the packet in that microframe interval and hence glitches are
> seen on the final transmitted video output.
> 
> 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
> when U1/U2 is enabled. Often when link enters U2, there is a re-
> enumeration seen and device is unusable for many use cases.
> 
> 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
> the cable is disconnected and reconnected to host PC in HS, there
> is no link status change interrupt seen and the plug-in in HS doesn't
> show up a bus reset and enumeration failure happens.
> 
> 4. On older targets like SM8150/SM8250/SM8350, there have been
> throughput issues seen during tethering use cases.
> 
> 5. On targets like SDX75, intermittent disconnects were observed
> with certain cables due to impedence variations.
> 
> To avoid such issues, the USB team at Qualcomm added these quirks
> to all targets in the past 4-5 years and extensive testing was done.
> Although these are intermittent power states, disabling them didn't
> cause any major increase in power numbers.
> 
> This series was earlier started by Krishna Kurapati where he disabled
> U1/U2 on some SM targets. I'm extending this to more devices including
> Auto, Compute and IOT platforms. On a side note, this quirk has been
> already included on some mobile targets like SM8550/8650.
> 
> Changes in v2:
> - Removed the wrongly added quirks from tcsr_mutex node.
> - Link to v2: https://lore.kernel.org/all/20241213095237.1409174-1-quic_prashk@quicinc.com/
> 
> Link to RFC:
> https://lore.kernel.org/all/20241107073650.13473-1-quic_kriskura@quicinc.com/#Z31arch:arm64:boot:dts:qcom:sm8250.dtsi
> 
> Krishna Kurapati (8):
>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8350
>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8450
>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8150
>   arm64: dts: qcom: Disable USB U1/U2 entry for SM6125
>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8250
>   arm64: dts: qcom: Disable USB U1/U2 entry for SM6350
>   arm64: dts: qcom: Disable USB U1/U2 entry for SC7280
>   arm64: dts: qcom: Disable USB U1/U2 entry for SA8775P

Thank you for submitting this, changes looks good and this is very
welcome corrections!

But patch subject is not okay. The prefix should match other changes in
these files, and no "for XYZ" suffix.

As such, these should all look like:

"arm64: dts: qcom: <soc>: Disable USB U1/U2 entry"

> 
> Prashanth K (11):
>   arm64: dts: qcom: Disable USB U1/U2 entry for SDM630
>   arm64: dts: qcom: Disable USB U1/U2 entry for SDM845
>   arm64: dts: qcom: Disable USB U1/U2 entry for SDX75
>   ARM: dts: qcom: Disable USB U1/U2 entry for SDX65
>   ARM: dts: qcom: Disable USB U1/U2 entry for SDX55

I merge Arm and Arm64 patches through different trees, so I would
appreciate if you send these two as a separate series (also v4).

Thanks,
Bjorn

>   arm64: dts: qcom: Disable USB U1/U2 entry for QCS404
>   arm64: dts: qcom: Disable USB U1/U2 entry for SC7180
>   arm64: dts: qcom: Disable USB U1/U2 entry for X1E80100
>   arm64: dts: qcom: Disable USB U1/U2 entry for QDU1000
>   arm64: dts: qcom: Disable USB U1/U2 entry for SC8280XP
>   arm64: dts: qcom: Disable USB U1/U2 entry for SC8180X
> 
>  arch/arm/boot/dts/qcom/qcom-sdx55.dtsi |  2 ++
>  arch/arm/boot/dts/qcom/qcom-sdx65.dtsi |  2 ++
>  arch/arm64/boot/dts/qcom/qcs404.dtsi   |  4 ++++
>  arch/arm64/boot/dts/qcom/qdu1000.dtsi  |  2 ++
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi  |  6 ++++++
>  arch/arm64/boot/dts/qcom/sc7180.dtsi   |  2 ++
>  arch/arm64/boot/dts/qcom/sc7280.dtsi   |  4 ++++
>  arch/arm64/boot/dts/qcom/sc8180x.dtsi  |  6 ++++++
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi |  6 ++++++
>  arch/arm64/boot/dts/qcom/sdm630.dtsi   |  4 ++++
>  arch/arm64/boot/dts/qcom/sdm845.dtsi   |  4 ++++
>  arch/arm64/boot/dts/qcom/sdx75.dtsi    |  2 ++
>  arch/arm64/boot/dts/qcom/sm6125.dtsi   |  2 ++
>  arch/arm64/boot/dts/qcom/sm6350.dtsi   |  2 ++
>  arch/arm64/boot/dts/qcom/sm8150.dtsi   |  4 ++++
>  arch/arm64/boot/dts/qcom/sm8250.dtsi   |  4 ++++
>  arch/arm64/boot/dts/qcom/sm8350.dtsi   |  4 ++++
>  arch/arm64/boot/dts/qcom/sm8450.dtsi   |  2 ++
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++
>  19 files changed, 72 insertions(+)
> 
> -- 
> 2.25.1
> 

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Prashanth K]

On 26-12-24 10:13 am, Bjorn Andersson wrote:
> On Wed, Dec 18, 2024 at 03:56:48PM +0530, Prashanth K wrote:
>> Enabling U1 and U2 power-saving states can lead to stability and
>> performance issues, particularly for latency-sensitive or high-
>> throughput applications. These low-power link states are intended
>> to reduce power consumption by allowing the device to enter partial
>> low-power modes during idle periods. However, they can sometimes
>> result in unexpected behavior. Over the years, some of the issues
>> seen are as follows:

[...]

>> Krishna Kurapati (8):
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8350
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8450
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8150
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM6125
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8250
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM6350
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SC7280
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SA8775P
> 
> Thank you for submitting this, changes looks good and this is very
> welcome corrections!
> 
> But patch subject is not okay. The prefix should match other changes in
> these files, and no "for XYZ" suffix.
> 
> As such, these should all look like:
> 
> "arm64: dts: qcom: <soc>: Disable USB U1/U2 entry"
> 
>>
>> Prashanth K (11):
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SDM630
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SDM845
>>   arm64: dts: qcom: Disable USB U1/U2 entry for SDX75
>>   ARM: dts: qcom: Disable USB U1/U2 entry for SDX65
>>   ARM: dts: qcom: Disable USB U1/U2 entry for SDX55
> 
> I merge Arm and Arm64 patches through different trees, so I would
> appreciate if you send these two as a separate series (also v4).
> 

Sure, will update the subject for all patches, and split it into 2
series (v4 for for both arm and arm64). I hope its fine to keep the
Reviewed-by tag from Konrad on next version.

Thanks for the review,
Prashanth K

Re: [PATCH v3 00/19] Disable USB U1/U2 entry for QC targets

[Konrad Dybcio]

On 26.12.2024 5:55 AM, Prashanth K wrote:
> 
> 
> On 26-12-24 10:13 am, Bjorn Andersson wrote:
>> On Wed, Dec 18, 2024 at 03:56:48PM +0530, Prashanth K wrote:
>>> Enabling U1 and U2 power-saving states can lead to stability and
>>> performance issues, particularly for latency-sensitive or high-
>>> throughput applications. These low-power link states are intended
>>> to reduce power consumption by allowing the device to enter partial
>>> low-power modes during idle periods. However, they can sometimes
>>> result in unexpected behavior. Over the years, some of the issues
>>> seen are as follows:
> 
> [...]
> 
>>> Krishna Kurapati (8):
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8350
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8450
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8150
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM6125
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM8250
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SM6350
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SC7280
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SA8775P
>>
>> Thank you for submitting this, changes looks good and this is very
>> welcome corrections!
>>
>> But patch subject is not okay. The prefix should match other changes in
>> these files, and no "for XYZ" suffix.
>>
>> As such, these should all look like:
>>
>> "arm64: dts: qcom: <soc>: Disable USB U1/U2 entry"
>>
>>>
>>> Prashanth K (11):
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SDM630
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SDM845
>>>   arm64: dts: qcom: Disable USB U1/U2 entry for SDX75
>>>   ARM: dts: qcom: Disable USB U1/U2 entry for SDX65
>>>   ARM: dts: qcom: Disable USB U1/U2 entry for SDX55
>>
>> I merge Arm and Arm64 patches through different trees, so I would
>> appreciate if you send these two as a separate series (also v4).
>>
> 
> Sure, will update the subject for all patches, and split it into 2
> series (v4 for for both arm and arm64). I hope its fine to keep the
> Reviewed-by tag from Konrad on next version.

Yes, you can usually feel free to keep tags, unless there's major
changes

Konrad