[PATCH 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC

[PATCH 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

This series enables the SMMU and adds DMA coherency support for the
XGMAC nodes across the affected board device trees.

Patch 1 enables the SMMU for the SoCFPGA board device trees where it
was missing. The SoC uses a different memory-mapped base address for
its peripherals, which requires the SMMU to be active so that the
Secure Device Manager (SDM) can correctly access those regions through
address translation.

Patch 2 adds the dma-coherent property to the XGMAC nodes. The SMMU
is enabled and transactions going through it are cache coherent.
Adding dma-coherent prevents redundant cache flush/invalidate
operations and potential stale data issues.

Nazim Amirul (2):
  arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees
  arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts         | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts         | 5 +++++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts    | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts    | 5 +++++
 5 files changed, 13 insertions(+)

-- 
2.43.7

[PATCH 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

Enable the SMMU on the SoCFPGA board device trees where it was
missing. The SoC uses a different memory-mapped base address for
its peripherals, which requires the System Memory Management Unit
(SMMU) to be active so that the Secure Device Manager (SDM) can
correctly access those regions through address translation.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts      | 4 ++++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index dae0db9f8819..66fc3c546b66 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -109,6 +109,10 @@ &usb0 {
 	disable-over-current;
 };
 
+&smmu {
+	status = "okay";
+};
+
 &watchdog0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
index 21faa47681fa..33e6455ead0f 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
@@ -104,6 +104,10 @@ &uart0 {
 	status = "okay";
 };
 
+&smmu {
+	status = "okay";
+};
+
 &watchdog0 {
 	status = "okay";
 };
-- 
2.43.7

Re: [PATCH 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[Dinh Nguyen]

On 5/14/26 06:41, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> 
> Enable the SMMU on the SoCFPGA board device trees where it was
> missing. The SoC uses a different memory-mapped base address for
> its peripherals, which requires the System Memory Management Unit
> (SMMU) to be active so that the Secure Device Manager (SDM) can
> correctly access those regions through address translation.
> 
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> ---
>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts      | 4 ++++
>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts | 4 ++++
>   2 files changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> index dae0db9f8819..66fc3c546b66 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> @@ -109,6 +109,10 @@ &usb0 {
>   	disable-over-current;
>   };
>   
> +&smmu {
> +	status = "okay";
> +};
> +

The SMMU is an SOC specific device, so it should be enabled in the base 
DTSI file.

Dinh

[PATCH 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

The SMMU is enabled and transactions going through it are cache
coherent. Add the dma-coherent property to the XGMAC nodes to prevent
redundant cache flush/invalidate operations and potential stale data
issues.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts         | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts         | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts    | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts    | 1 +
 5 files changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
index 25e17df0cbdb..2061d301126e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
@@ -52,6 +52,7 @@ &gmac2 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac2_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		compatible = "snps,dwmac-mdio";
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 66fc3c546b66..0af0b2e7d867 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -47,6 +47,7 @@ &gmac2 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac2_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
index 86137380df04..9bff6b57f19d 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
@@ -46,6 +46,7 @@ &gmac2 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac2_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
index e728cedb4cbd..6c61add0ef09 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
@@ -49,6 +49,7 @@ &gmac2 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac2_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		compatible = "snps,dwmac-mdio";
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
index 33e6455ead0f..1a9d44e2bcb3 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
@@ -44,6 +44,7 @@ &gmac0 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac0_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		#address-cells = <1>;
-- 
2.43.7

Re: [PATCH 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[Dinh Nguyen]

On 5/14/26 06:41, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> 
> The SMMU is enabled and transactions going through it are cache
> coherent. Add the dma-coherent property to the XGMAC nodes to prevent
> redundant cache flush/invalidate operations and potential stale data
> issues.
> 
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> ---
>   arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts         | 1 +
>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts         | 1 +
>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts    | 1 +
>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 1 +
>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts    | 1 +
>   5 files changed, 5 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
> index 25e17df0cbdb..2061d301126e 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
> @@ -52,6 +52,7 @@ &gmac2 {
>   	phy-mode = "rgmii-id";
>   	phy-handle = <&emac2_phy0>;
>   	max-frame-size = <9000>;
> +	dma-coherent;
>   
This property should be in placed in the Agilex5 dtsi file.

Thanks,
Dinh

Re: [PATCH 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[Nazle Asmade, Muhammad Nazim Amirul]

On 15/5/2026 7:43 am, Dinh Nguyen wrote:
> 
> 
> On 5/14/26 06:41, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>
>> The SMMU is enabled and transactions going through it are cache
>> coherent. Add the dma-coherent property to the XGMAC nodes to prevent
>> redundant cache flush/invalidate operations and potential stale data
>> issues.
>>
>> Signed-off-by: Nazim Amirul 
>> <muhammad.nazim.amirul.nazle.asmade@altera.com>
>> ---
>>   arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts         | 1 +
>>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts         | 1 +
>>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts    | 1 +
>>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 1 +
>>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts    | 1 +
>>   5 files changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/ 
>> arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
>> index 25e17df0cbdb..2061d301126e 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
>> @@ -52,6 +52,7 @@ &gmac2 {
>>       phy-mode = "rgmii-id";
>>       phy-handle = <&emac2_phy0>;
>>       max-frame-size = <9000>;
>> +    dma-coherent;
> This property should be in placed in the Agilex5 dtsi file.
> 
> Thanks,
> Dinh
All the changes had been reflected in v2. Thanks Dinh!

https://lore.kernel.org/all/20260515080014.6260-1-muhammad.nazim.amirul.nazle.asmade@altera.com/

https://lore.kernel.org/all/20260515080014.6260-2-muhammad.nazim.amirul.nazle.asmade@altera.com/

https://lore.kernel.org/all/20260515080014.6260-3-muhammad.nazim.amirul.nazle.asmade@altera.com/

BR,
Nazim