[PATCH v3 0/2] iio: adc: ad9467: fixes for ad9434

[PATCH v3 0/2] iio: adc: ad9467: fixes for ad9434

[Tomas Melin]

Add support for setting offset range (calibration) for the ad9434
and fixup vref mask handling.

Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
---
Changes in v3:
- Removed comment about transfer as it is generally known to a familiar reader
  that the operation is required for specific registers 
- Aligned indendation with recommendations
- Link to v2: https://lore.kernel.org/r/20251202-ad9434-fixes-v2-0-fa73d4eabbea@vaisala.com

Changes in v2:
Updates according to received feedback:
- embed ad9434 channel description instead of resorting to macro
- change INFO_OFFSET to INFO_CALIBBIAS
- keep offset value untouched in case of error
- drop length from avail_range
- Link to v1: https://lore.kernel.org/r/20251201-ad9434-fixes-v1-0-54a9ca2ac514@vaisala.com

---
Tomas Melin (2):
      iio: adc: ad9467: fix ad9434 vref mask
      iio: adc: ad9467: support write/read offset

 drivers/iio/adc/ad9467.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 60 insertions(+), 2 deletions(-)
---
base-commit: 9b9e43704d2b05514aeeaea36311addba2c72408
change-id: 20251201-ad9434-fixes-6dfdc86fb881

Best regards,
-- 
Tomas Melin <tomas.melin@vaisala.com>

[PATCH v3 1/2] iio: adc: ad9467: fix ad9434 vref mask

[Tomas Melin]

The mask setting is 5 bits wide for the ad9434
(ref. data sheet register 0x18 FLEX_VREF). Apparently the settings
from ad9265 were copied by mistake when support for the device was added
to the driver.

Fixes: 4606d0f4b05f ("iio: adc: ad9467: add support for AD9434 high-speed ADC")
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
---
 drivers/iio/adc/ad9467.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c
index f7a9f46ea0dc405e25f312197df4b2131871b4bc..2d8f8da3671dac61994a1864a82cdbef7f54c1af 100644
--- a/drivers/iio/adc/ad9467.c
+++ b/drivers/iio/adc/ad9467.c
@@ -95,7 +95,7 @@
 
 #define CHIPID_AD9434			0x6A
 #define AD9434_DEF_OUTPUT_MODE		0x00
-#define AD9434_REG_VREF_MASK		0xC0
+#define AD9434_REG_VREF_MASK		GENMASK(4, 0)
 
 /*
  * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC

-- 
2.47.3

[PATCH v3 2/2] iio: adc: ad9467: support write/read offset

[Tomas Melin]

Support configuring output calibration value. Among the devices
currently supported by this driver, this setting is specific to
ad9434. The offset can be used to calibrate the output against
a known input. The register is called offset, but the procedure
is best mapped internally with calibbias operation.

Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
---
 drivers/iio/adc/ad9467.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c
index 2d8f8da3671dac61994a1864a82cdbef7f54c1af..48c10acb1566ba471be0804e7c39b0b553d76188 100644
--- a/drivers/iio/adc/ad9467.c
+++ b/drivers/iio/adc/ad9467.c
@@ -145,6 +145,7 @@ struct ad9467_chip_info {
 	unsigned int num_lanes;
 	unsigned int dco_en;
 	unsigned int test_points;
+	const int *offset_range;
 	/* data clock output */
 	bool has_dco;
 	bool has_dco_invert;
@@ -234,6 +235,10 @@ static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg,
 	return 0;
 }
 
+static const int ad9434_offset_range[] = {
+	-128, 1, 127,
+};
+
 static const unsigned int ad9265_scale_table[][2] = {
 	{1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
 };
@@ -298,7 +303,24 @@ static void __ad9467_get_scale(struct ad9467_state *st, int index,
 }
 
 static const struct iio_chan_spec ad9434_channels[] = {
-	AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 12, 's'),
+	{
+		.type = IIO_VOLTAGE,
+		.indexed = 1,
+		.channel = 0,
+		.info_mask_shared_by_type =
+			BIT(IIO_CHAN_INFO_SCALE) |
+			BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+			BIT(IIO_CHAN_INFO_CALIBBIAS),
+		.info_mask_shared_by_type_available =
+			BIT(IIO_CHAN_INFO_SCALE) |
+			BIT(IIO_CHAN_INFO_CALIBBIAS),
+		.scan_index = 0,
+		.scan_type = {
+			.sign = 's',
+			.realbits = 12,
+			.storagebits = 16,
+		},
+	},
 };
 
 static const struct iio_chan_spec ad9467_channels[] = {
@@ -367,6 +389,7 @@ static const struct ad9467_chip_info ad9434_chip_tbl = {
 	.default_output_mode = AD9434_DEF_OUTPUT_MODE,
 	.vref_mask = AD9434_REG_VREF_MASK,
 	.num_lanes = 6,
+	.offset_range = ad9434_offset_range,
 };
 
 static const struct ad9467_chip_info ad9265_chip_tbl = {
@@ -499,6 +522,33 @@ static int ad9467_set_scale(struct ad9467_state *st, int val, int val2)
 	return -EINVAL;
 }
 
+static int ad9467_get_offset(struct ad9467_state *st, int *val)
+{
+	int ret;
+
+	ret = ad9467_spi_read(st, AN877_ADC_REG_OFFSET);
+	if (ret < 0)
+		return ret;
+	*val = ret;
+
+	return IIO_VAL_INT;
+}
+
+static int ad9467_set_offset(struct ad9467_state *st, int val)
+{
+	int ret;
+
+	if (val < st->info->offset_range[0] || val > st->info->offset_range[2])
+		return -EINVAL;
+
+	ret = ad9467_spi_write(st, AN877_ADC_REG_OFFSET, val);
+	if (ret < 0)
+		return ret;
+
+	return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
+				AN877_ADC_TRANSFER_SYNC);
+}
+
 static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode)
 {
 	int ret;
@@ -802,6 +852,8 @@ static int ad9467_read_raw(struct iio_dev *indio_dev,
 	struct ad9467_state *st = iio_priv(indio_dev);
 
 	switch (m) {
+	case IIO_CHAN_INFO_CALIBBIAS:
+		return ad9467_get_offset(st, val);
 	case IIO_CHAN_INFO_SCALE:
 		return ad9467_get_scale(st, val, val2);
 	case IIO_CHAN_INFO_SAMP_FREQ:
@@ -836,6 +888,8 @@ static int ad9467_write_raw(struct iio_dev *indio_dev,
 	int ret;
 
 	switch (mask) {
+	case IIO_CHAN_INFO_CALIBBIAS:
+		return ad9467_set_offset(st, val);
 	case IIO_CHAN_INFO_SCALE:
 		return ad9467_set_scale(st, val, val2);
 	case IIO_CHAN_INFO_SAMP_FREQ:
@@ -874,6 +928,10 @@ static int ad9467_read_avail(struct iio_dev *indio_dev,
 	const struct ad9467_chip_info *info = st->info;
 
 	switch (mask) {
+	case IIO_CHAN_INFO_CALIBBIAS:
+		*type = IIO_VAL_INT;
+		*vals = info->offset_range;
+		return IIO_AVAIL_RANGE;
 	case IIO_CHAN_INFO_SCALE:
 		*vals = (const int *)st->scales;
 		*type = IIO_VAL_INT_PLUS_MICRO;

-- 
2.47.3

Re: [PATCH v3 2/2] iio: adc: ad9467: support write/read offset

[Andy Shevchenko]

On Wed, Dec 3, 2025 at 11:28 AM Tomas Melin <tomas.melin@vaisala.com> wrote:
>
> Support configuring output calibration value. Among the devices
> currently supported by this driver, this setting is specific to
> ad9434. The offset can be used to calibrate the output against
> a known input. The register is called offset, but the procedure
> is best mapped internally with calibbias operation.

This version LGTM,

Reviewed-by: Andy Shevchenko <andy@kernel.org>

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v3 2/2] iio: adc: ad9467: support write/read offset

[Nuno Sá]

On Wed, 2025-12-03 at 09:28 +0000, Tomas Melin wrote:
> Support configuring output calibration value. Among the devices
> currently supported by this driver, this setting is specific to
> ad9434. The offset can be used to calibrate the output against
> a known input. The register is called offset, but the procedure
> is best mapped internally with calibbias operation.
> 
> Reviewed-by: David Lechner <dlechner@baylibre.com>
> Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
> ---

Still don't really like the style in .info_mask_shared_by_type and 
.info_mask_shared_by_type_available. But ok, it seems I'm the only one. So:

Reviewed-by: Nuno Sá <nuno.sa@analog.com>

>  drivers/iio/adc/ad9467.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 59 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c
> index 2d8f8da3671dac61994a1864a82cdbef7f54c1af..48c10acb1566ba471be0804e7c39b0b553d76188 100644
> --- a/drivers/iio/adc/ad9467.c
> +++ b/drivers/iio/adc/ad9467.c
> @@ -145,6 +145,7 @@ struct ad9467_chip_info {
>  	unsigned int num_lanes;
>  	unsigned int dco_en;
>  	unsigned int test_points;
> +	const int *offset_range;
>  	/* data clock output */
>  	bool has_dco;
>  	bool has_dco_invert;
> @@ -234,6 +235,10 @@ static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg,
>  	return 0;
>  }
>  
> +static const int ad9434_offset_range[] = {
> +	-128, 1, 127,
> +};
> +
>  static const unsigned int ad9265_scale_table[][2] = {
>  	{1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
>  };
> @@ -298,7 +303,24 @@ static void __ad9467_get_scale(struct ad9467_state *st, int index,
>  }
>  
>  static const struct iio_chan_spec ad9434_channels[] = {
> -	AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 12, 's'),
> +	{
> +		.type = IIO_VOLTAGE,
> +		.indexed = 1,
> +		.channel = 0,
> +		.info_mask_shared_by_type =
> +			BIT(IIO_CHAN_INFO_SCALE) |
> +			BIT(IIO_CHAN_INFO_SAMP_FREQ) |
> +			BIT(IIO_CHAN_INFO_CALIBBIAS),
> +		.info_mask_shared_by_type_available =
> +			BIT(IIO_CHAN_INFO_SCALE) |
> +			BIT(IIO_CHAN_INFO_CALIBBIAS),
> +		.scan_index = 0,
> +		.scan_type = {
> +			.sign = 's',
> +			.realbits = 12,
> +			.storagebits = 16,
> +		},
> +	},
>  };
>  
>  static const struct iio_chan_spec ad9467_channels[] = {
> @@ -367,6 +389,7 @@ static const struct ad9467_chip_info ad9434_chip_tbl = {
>  	.default_output_mode = AD9434_DEF_OUTPUT_MODE,
>  	.vref_mask = AD9434_REG_VREF_MASK,
>  	.num_lanes = 6,
> +	.offset_range = ad9434_offset_range,
>  };
>  
>  static const struct ad9467_chip_info ad9265_chip_tbl = {
> @@ -499,6 +522,33 @@ static int ad9467_set_scale(struct ad9467_state *st, int val, int val2)
>  	return -EINVAL;
>  }
>  
> +static int ad9467_get_offset(struct ad9467_state *st, int *val)
> +{
> +	int ret;
> +
> +	ret = ad9467_spi_read(st, AN877_ADC_REG_OFFSET);
> +	if (ret < 0)
> +		return ret;
> +	*val = ret;
> +
> +	return IIO_VAL_INT;
> +}
> +
> +static int ad9467_set_offset(struct ad9467_state *st, int val)
> +{
> +	int ret;
> +
> +	if (val < st->info->offset_range[0] || val > st->info->offset_range[2])
> +		return -EINVAL;
> +
> +	ret = ad9467_spi_write(st, AN877_ADC_REG_OFFSET, val);
> +	if (ret < 0)
> +		return ret;
> +
> +	return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
> +				AN877_ADC_TRANSFER_SYNC);
> +}
> +
>  static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode)
>  {
>  	int ret;
> @@ -802,6 +852,8 @@ static int ad9467_read_raw(struct iio_dev *indio_dev,
>  	struct ad9467_state *st = iio_priv(indio_dev);
>  
>  	switch (m) {
> +	case IIO_CHAN_INFO_CALIBBIAS:
> +		return ad9467_get_offset(st, val);
>  	case IIO_CHAN_INFO_SCALE:
>  		return ad9467_get_scale(st, val, val2);
>  	case IIO_CHAN_INFO_SAMP_FREQ:
> @@ -836,6 +888,8 @@ static int ad9467_write_raw(struct iio_dev *indio_dev,
>  	int ret;
>  
>  	switch (mask) {
> +	case IIO_CHAN_INFO_CALIBBIAS:
> +		return ad9467_set_offset(st, val);
>  	case IIO_CHAN_INFO_SCALE:
>  		return ad9467_set_scale(st, val, val2);
>  	case IIO_CHAN_INFO_SAMP_FREQ:
> @@ -874,6 +928,10 @@ static int ad9467_read_avail(struct iio_dev *indio_dev,
>  	const struct ad9467_chip_info *info = st->info;
>  
>  	switch (mask) {
> +	case IIO_CHAN_INFO_CALIBBIAS:
> +		*type = IIO_VAL_INT;
> +		*vals = info->offset_range;
> +		return IIO_AVAIL_RANGE;
>  	case IIO_CHAN_INFO_SCALE:
>  		*vals = (const int *)st->scales;
>  		*type = IIO_VAL_INT_PLUS_MICRO;

Re: [PATCH v3 1/2] iio: adc: ad9467: fix ad9434 vref mask

[Jonathan Cameron]

On Wed, 03 Dec 2025 09:28:11 +0000
Tomas Melin <tomas.melin@vaisala.com> wrote:

> The mask setting is 5 bits wide for the ad9434
> (ref. data sheet register 0x18 FLEX_VREF). Apparently the settings
> from ad9265 were copied by mistake when support for the device was added
> to the driver.
> 
> Fixes: 4606d0f4b05f ("iio: adc: ad9467: add support for AD9434 high-speed ADC")
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
> Reviewed-by: Nuno Sá <nuno.sa@analog.com>
> Reviewed-by: David Lechner <dlechner@baylibre.com>
> Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
Applied to the fixes-togreg branch of iio.git and marked for stable.

Thanks,

Jonathan

> ---
>  drivers/iio/adc/ad9467.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c
> index f7a9f46ea0dc405e25f312197df4b2131871b4bc..2d8f8da3671dac61994a1864a82cdbef7f54c1af 100644
> --- a/drivers/iio/adc/ad9467.c
> +++ b/drivers/iio/adc/ad9467.c
> @@ -95,7 +95,7 @@
>  
>  #define CHIPID_AD9434			0x6A
>  #define AD9434_DEF_OUTPUT_MODE		0x00
> -#define AD9434_REG_VREF_MASK		0xC0
> +#define AD9434_REG_VREF_MASK		GENMASK(4, 0)
>  
>  /*
>   * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
> 

Re: [PATCH v3 2/2] iio: adc: ad9467: support write/read offset

[Jonathan Cameron]

On Wed, 03 Dec 2025 11:05:50 +0000
Nuno Sá <noname.nuno@gmail.com> wrote:

> On Wed, 2025-12-03 at 09:28 +0000, Tomas Melin wrote:
> > Support configuring output calibration value. Among the devices
> > currently supported by this driver, this setting is specific to
> > ad9434. The offset can be used to calibrate the output against
> > a known input. The register is called offset, but the procedure
> > is best mapped internally with calibbias operation.
> > 
> > Reviewed-by: David Lechner <dlechner@baylibre.com>
> > Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
> > ---  
> 
> Still don't really like the style in .info_mask_shared_by_type and 
> .info_mask_shared_by_type_available. But ok, it seems I'm the only one. So:
> 
> Reviewed-by: Nuno Sá <nuno.sa@analog.com>

Applied but with via _calibbias added to the patch title to make
it clear this isn't via _offset which might make people waste time
wondering what is going on.

Note this is on my local tree that I might push out as testing
but will only become togreg after I rebase on rc1 in a week or so.

Thanks,

Jonathan

> 
> >  drivers/iio/adc/ad9467.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 59 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c
> > index 2d8f8da3671dac61994a1864a82cdbef7f54c1af..48c10acb1566ba471be0804e7c39b0b553d76188 100644
> > --- a/drivers/iio/adc/ad9467.c
> > +++ b/drivers/iio/adc/ad9467.c
> > @@ -145,6 +145,7 @@ struct ad9467_chip_info {
> >  	unsigned int num_lanes;
> >  	unsigned int dco_en;
> >  	unsigned int test_points;
> > +	const int *offset_range;
> >  	/* data clock output */
> >  	bool has_dco;
> >  	bool has_dco_invert;
> > @@ -234,6 +235,10 @@ static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg,
> >  	return 0;
> >  }
> >  
> > +static const int ad9434_offset_range[] = {
> > +	-128, 1, 127,
> > +};
> > +
> >  static const unsigned int ad9265_scale_table[][2] = {
> >  	{1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
> >  };
> > @@ -298,7 +303,24 @@ static void __ad9467_get_scale(struct ad9467_state *st, int index,
> >  }
> >  
> >  static const struct iio_chan_spec ad9434_channels[] = {
> > -	AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 12, 's'),
> > +	{
> > +		.type = IIO_VOLTAGE,
> > +		.indexed = 1,
> > +		.channel = 0,
> > +		.info_mask_shared_by_type =
> > +			BIT(IIO_CHAN_INFO_SCALE) |
> > +			BIT(IIO_CHAN_INFO_SAMP_FREQ) |
> > +			BIT(IIO_CHAN_INFO_CALIBBIAS),
> > +		.info_mask_shared_by_type_available =
> > +			BIT(IIO_CHAN_INFO_SCALE) |
> > +			BIT(IIO_CHAN_INFO_CALIBBIAS),
> > +		.scan_index = 0,
> > +		.scan_type = {
> > +			.sign = 's',
> > +			.realbits = 12,
> > +			.storagebits = 16,
> > +		},
> > +	},
> >  };
> >  
> >  static const struct iio_chan_spec ad9467_channels[] = {
> > @@ -367,6 +389,7 @@ static const struct ad9467_chip_info ad9434_chip_tbl = {
> >  	.default_output_mode = AD9434_DEF_OUTPUT_MODE,
> >  	.vref_mask = AD9434_REG_VREF_MASK,
> >  	.num_lanes = 6,
> > +	.offset_range = ad9434_offset_range,
> >  };
> >  
> >  static const struct ad9467_chip_info ad9265_chip_tbl = {
> > @@ -499,6 +522,33 @@ static int ad9467_set_scale(struct ad9467_state *st, int val, int val2)
> >  	return -EINVAL;
> >  }
> >  
> > +static int ad9467_get_offset(struct ad9467_state *st, int *val)
> > +{
> > +	int ret;
> > +
> > +	ret = ad9467_spi_read(st, AN877_ADC_REG_OFFSET);
> > +	if (ret < 0)
> > +		return ret;
> > +	*val = ret;
> > +
> > +	return IIO_VAL_INT;
> > +}
> > +
> > +static int ad9467_set_offset(struct ad9467_state *st, int val)
> > +{
> > +	int ret;
> > +
> > +	if (val < st->info->offset_range[0] || val > st->info->offset_range[2])
> > +		return -EINVAL;
> > +
> > +	ret = ad9467_spi_write(st, AN877_ADC_REG_OFFSET, val);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
> > +				AN877_ADC_TRANSFER_SYNC);
> > +}
> > +
> >  static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode)
> >  {
> >  	int ret;
> > @@ -802,6 +852,8 @@ static int ad9467_read_raw(struct iio_dev *indio_dev,
> >  	struct ad9467_state *st = iio_priv(indio_dev);
> >  
> >  	switch (m) {
> > +	case IIO_CHAN_INFO_CALIBBIAS:
> > +		return ad9467_get_offset(st, val);
> >  	case IIO_CHAN_INFO_SCALE:
> >  		return ad9467_get_scale(st, val, val2);
> >  	case IIO_CHAN_INFO_SAMP_FREQ:
> > @@ -836,6 +888,8 @@ static int ad9467_write_raw(struct iio_dev *indio_dev,
> >  	int ret;
> >  
> >  	switch (mask) {
> > +	case IIO_CHAN_INFO_CALIBBIAS:
> > +		return ad9467_set_offset(st, val);
> >  	case IIO_CHAN_INFO_SCALE:
> >  		return ad9467_set_scale(st, val, val2);
> >  	case IIO_CHAN_INFO_SAMP_FREQ:
> > @@ -874,6 +928,10 @@ static int ad9467_read_avail(struct iio_dev *indio_dev,
> >  	const struct ad9467_chip_info *info = st->info;
> >  
> >  	switch (mask) {
> > +	case IIO_CHAN_INFO_CALIBBIAS:
> > +		*type = IIO_VAL_INT;
> > +		*vals = info->offset_range;
> > +		return IIO_AVAIL_RANGE;
> >  	case IIO_CHAN_INFO_SCALE:
> >  		*vals = (const int *)st->scales;
> >  		*type = IIO_VAL_INT_PLUS_MICRO;