* [PATCH v2] riscv: misaligned: Restore epc in error path
@ 2026-05-09 7:40 Zishun Yi
2026-05-11 7:53 ` Andreas Schwab
0 siblings, 1 reply; 3+ messages in thread
From: Zishun Yi @ 2026-05-09 7:40 UTC (permalink / raw)
To: pjw, palmer, aou, linux-riscv, linux-kernel
Cc: alex, ajones, cleger, charlie, schwab, namcao, Zishun Yi
In handle_scalar_misaligned_store/load, regs->epc is temporarily set to
0. And be restored in the first error path. But it not restore for the
rest of the error path. This cause the epc corrupted.
Fix this by restore epc in fp error and copy_from_user error.
Fixes: 7c586a555a48 ("riscv: add floating point insn support to misaligned access emulation")
Fixes: 441381506ba7 ("riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code")
Assisted-by: Gemini:gemini-3.1-pro
Signed-off-by: Zishun Yi <vulab@iscas.ac.cn>
---
Changes in v2:
- Added 'Assisted-by' tag.
arch/riscv/kernel/traps_misaligned.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 2a27d3ff4ac6..24f898853bba 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -307,13 +307,17 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
return -1;
}
- if (!IS_ENABLED(CONFIG_FPU) && fp)
+ if (!IS_ENABLED(CONFIG_FPU) && fp) {
+ regs->epc = epc;
return -EOPNOTSUPP;
+ }
val.data_u64 = 0;
if (user_mode(regs)) {
- if (copy_from_user(&val, (u8 __user *)addr, len))
+ if (copy_from_user(&val, (u8 __user *)addr, len)) {
+ regs->epc = epc;
return -1;
+ }
} else {
memcpy(&val, (u8 *)addr, len);
}
@@ -409,12 +413,16 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs)
return -1;
}
- if (!IS_ENABLED(CONFIG_FPU) && fp)
+ if (!IS_ENABLED(CONFIG_FPU) && fp) {
+ regs->epc = epc;
return -EOPNOTSUPP;
+ }
if (user_mode(regs)) {
- if (copy_to_user((u8 __user *)addr, &val, len))
+ if (copy_to_user((u8 __user *)addr, &val, len)) {
+ regs->epc = epc;
return -1;
+ }
} else {
memcpy((u8 *)addr, &val, len);
}
--
2.51.2
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] riscv: misaligned: Restore epc in error path 2026-05-09 7:40 [PATCH v2] riscv: misaligned: Restore epc in error path Zishun Yi @ 2026-05-11 7:53 ` Andreas Schwab 2026-05-11 12:41 ` [PATCH v3] " Zishun Yi 0 siblings, 1 reply; 3+ messages in thread From: Andreas Schwab @ 2026-05-11 7:53 UTC (permalink / raw) To: Zishun Yi Cc: pjw, palmer, aou, linux-riscv, linux-kernel, alex, ajones, cleger, charlie, namcao On Mai 09 2026, Zishun Yi wrote: > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c > index 2a27d3ff4ac6..24f898853bba 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -307,13 +307,17 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) > return -1; > } > > - if (!IS_ENABLED(CONFIG_FPU) && fp) > + if (!IS_ENABLED(CONFIG_FPU) && fp) { > + regs->epc = epc; > return -EOPNOTSUPP; > + } > > val.data_u64 = 0; > if (user_mode(regs)) { > - if (copy_from_user(&val, (u8 __user *)addr, len)) > + if (copy_from_user(&val, (u8 __user *)addr, len)) { > + regs->epc = epc; > return -1; > + } > } else { > memcpy(&val, (u8 *)addr, len); > } > @@ -409,12 +413,16 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs) > return -1; > } > > - if (!IS_ENABLED(CONFIG_FPU) && fp) > + if (!IS_ENABLED(CONFIG_FPU) && fp) { > + regs->epc = epc; > return -EOPNOTSUPP; > + } > > if (user_mode(regs)) { > - if (copy_to_user((u8 __user *)addr, &val, len)) > + if (copy_to_user((u8 __user *)addr, &val, len)) { > + regs->epc = epc; > return -1; > + } I think this is better handled by a common error exit. -- Andreas Schwab, SUSE Labs, schwab@suse.de GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different." ^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v3] riscv: misaligned: Restore epc in error path 2026-05-11 7:53 ` Andreas Schwab @ 2026-05-11 12:41 ` Zishun Yi 0 siblings, 0 replies; 3+ messages in thread From: Zishun Yi @ 2026-05-11 12:41 UTC (permalink / raw) To: Andreas Schwab Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andrew Jones, Clément Léger, Charlie Jenkins, Nam Cao, linux-riscv, linux-kernel, Zishun Yi In handle_scalar_misaligned_store/load, regs->epc is temporarily set to 0. And be restored in the first error path. But it not restore for the rest of the error path. This cause the epc corrupted. Fix this by restore epc in fp error and copy_from_user error. Fixes: 7c586a555a48 ("riscv: add floating point insn support to misaligned access emulation") Fixes: 441381506ba7 ("riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code") Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Zishun Yi <vulab@iscas.ac.cn> --- Change in v3: - Refactored error handling to use a centralized common error exit (goto out_restore_epc). Change in v2: - add Assisted-by tag arch/riscv/kernel/traps_misaligned.c | 32 +++++++++++++++++++--------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 2a27d3ff4ac6..21a3ceb1fae8 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -224,6 +224,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) unsigned long insn; unsigned long addr = regs->badaddr; int fp = 0, shift = 0, len = 0; + int ret = -1; perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); @@ -303,17 +304,18 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) shift = 8 * (sizeof(ulong) - len); insn = RVC_RS2S(insn) << SH_RD; } else { - regs->epc = epc; - return -1; + goto out_restore_epc; } - if (!IS_ENABLED(CONFIG_FPU) && fp) - return -EOPNOTSUPP; + if (!IS_ENABLED(CONFIG_FPU) && fp) { + ret = -EOPNOTSUPP; + goto out_restore_epc; + } val.data_u64 = 0; if (user_mode(regs)) { if (copy_from_user(&val, (u8 __user *)addr, len)) - return -1; + goto out_restore_epc; } else { memcpy(&val, (u8 *)addr, len); } @@ -328,6 +330,10 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) regs->epc = epc + INSN_LEN(insn); return 0; + +out_restore_epc: + regs->epc = epc; + return ret; } static int handle_scalar_misaligned_store(struct pt_regs *regs) @@ -337,6 +343,7 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs) unsigned long insn; unsigned long addr = regs->badaddr; int len = 0, fp = 0; + int ret = -1; perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); @@ -405,16 +412,17 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs) len = 2; val.data_ulong = GET_RS2S(insn, regs); } else { - regs->epc = epc; - return -1; + goto out_restore_epc; } - if (!IS_ENABLED(CONFIG_FPU) && fp) - return -EOPNOTSUPP; + if (!IS_ENABLED(CONFIG_FPU) && fp) { + ret = -EOPNOTSUPP; + goto out_restore_epc; + } if (user_mode(regs)) { if (copy_to_user((u8 __user *)addr, &val, len)) - return -1; + goto out_restore_epc; } else { memcpy((u8 *)addr, &val, len); } @@ -422,6 +430,10 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs) regs->epc = epc + INSN_LEN(insn); return 0; + +out_restore_epc: + regs->epc = epc; + return ret; } int handle_misaligned_load(struct pt_regs *regs) -- 2.51.2 ^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-05-11 12:41 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-05-09 7:40 [PATCH v2] riscv: misaligned: Restore epc in error path Zishun Yi 2026-05-11 7:53 ` Andreas Schwab 2026-05-11 12:41 ` [PATCH v3] " Zishun Yi
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