* [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder
@ 2016-07-20 8:30 Adrian Hunter
2016-07-20 8:30 ` [PATCH V2 1/4] x86/insn: perf tools: Fix vcvtph2ps instruction decoding Adrian Hunter
` (4 more replies)
0 siblings, 5 replies; 18+ messages in thread
From: Adrian Hunter @ 2016-07-20 8:30 UTC (permalink / raw)
To: linux-kernel
Cc: Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams,
Masami Hiramatsu, Ingo Molnar, H. Peter Anvin, Thomas Gleixner,
Andy Lutomirski, X86 ML
Hi
Here are patches to add support for Intel's AVX-512 instructions to the
instruction decoder. Also there is a patch to fix vcvtph2ps.
AVX-512 instructions are documented in Intel Architecture Instruction Set
Extensions Programming Reference (February 2016).
These patches do not conflict with Dan's removal of pcommit.
Changes in V2:
Split patches: separate out perf tools and new instructions test.
Amend decription of 'evo' annotation in x86-opcode-map.txt
Adrian Hunter (4):
x86/insn: perf tools: Fix vcvtph2ps instruction decoding
x86/insn: Add AVX-512 support to the instruction decoder
perf tools: Add AVX-512 support to the instruction decoder used by Intel PT
perf tools: Add AVX-512 instructions to the new instructions test
arch/x86/include/asm/inat.h | 17 +-
arch/x86/include/asm/insn.h | 12 +-
arch/x86/lib/insn.c | 18 +-
arch/x86/lib/x86-opcode-map.txt | 263 ++-
arch/x86/tools/gen-insn-attr-x86.awk | 11 +-
tools/perf/arch/x86/tests/insn-x86-dat-32.c | 1018 ++++++++++-
tools/perf/arch/x86/tests/insn-x86-dat-64.c | 940 +++++++++-
tools/perf/arch/x86/tests/insn-x86-dat-src.c | 1789 ++++++++++++++++++++
.../util/intel-pt-decoder/gen-insn-attr-x86.awk | 11 +-
tools/perf/util/intel-pt-decoder/inat.h | 17 +-
tools/perf/util/intel-pt-decoder/insn.c | 18 +-
tools/perf/util/intel-pt-decoder/insn.h | 12 +-
.../perf/util/intel-pt-decoder/x86-opcode-map.txt | 263 ++-
13 files changed, 4179 insertions(+), 210 deletions(-)
Regards
Adrian
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH V2 1/4] x86/insn: perf tools: Fix vcvtph2ps instruction decoding 2016-07-20 8:30 [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Adrian Hunter @ 2016-07-20 8:30 ` Adrian Hunter 2016-07-25 18:08 ` [tip:perf/core] " tip-bot for Adrian Hunter 2016-07-20 8:30 ` [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder Adrian Hunter ` (3 subsequent siblings) 4 siblings, 1 reply; 18+ messages in thread From: Adrian Hunter @ 2016-07-20 8:30 UTC (permalink / raw) To: linux-kernel Cc: Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Masami Hiramatsu, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML vcvtph2ps does not have an immediate operand, so remove the erroneous 'Ib' from its opcode map entry. Add vcvtph2ps to the perf tools new instructions test to verify it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> --- arch/x86/lib/x86-opcode-map.txt | 2 +- tools/perf/arch/x86/tests/insn-x86-dat-32.c | 10 ++++++---- tools/perf/arch/x86/tests/insn-x86-dat-64.c | 10 ++++++---- tools/perf/arch/x86/tests/insn-x86-dat-src.c | 4 ++++ tools/perf/util/intel-pt-decoder/x86-opcode-map.txt | 2 +- 5 files changed, 18 insertions(+), 10 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index d388de72eaca..28082de46f0d 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -629,7 +629,7 @@ AVXcode: 2 10: pblendvb Vdq,Wdq (66) 11: 12: -13: vcvtph2ps Vx,Wx,Ib (66),(v) +13: vcvtph2ps Vx,Wx (66),(v) 14: blendvps Vdq,Wdq (66) 15: blendvpd Vdq,Wdq (66) 16: vpermps Vqq,Hqq,Wqq (66),(v) diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c index 3b491cfe204e..ca08e6eb988f 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-32.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c @@ -6,6 +6,8 @@ {{0x0f, 0x31, }, 2, 0, "", "", "0f 31 \trdtsc ",}, +{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "", +"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",}, {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", "f3 0f 1b 00 \tbndmk (%eax),%bnd0",}, {{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", @@ -309,19 +311,19 @@ {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax,%ecx,1)",}, {{0xf2, 0xe8, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "call", "unconditional", -"f2 e8 fc ff ff ff \tbnd call 3c3 <main+0x3c3>",}, +"f2 e8 fc ff ff ff \tbnd call 3c8 <main+0x3c8>",}, {{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect", "f2 ff 10 \tbnd call *(%eax)",}, {{0xf2, 0xc3, }, 2, 0, "ret", "indirect", "f2 c3 \tbnd ret ",}, {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", -"f2 e9 fc ff ff ff \tbnd jmp 3ce <main+0x3ce>",}, +"f2 e9 fc ff ff ff \tbnd jmp 3d3 <main+0x3d3>",}, {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", -"f2 e9 fc ff ff ff \tbnd jmp 3d4 <main+0x3d4>",}, +"f2 e9 fc ff ff ff \tbnd jmp 3d9 <main+0x3d9>",}, {{0xf2, 0xff, 0x21, }, 3, 0, "jmp", "indirect", "f2 ff 21 \tbnd jmp *(%ecx)",}, {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffffffc, "jcc", "conditional", -"f2 0f 85 fc ff ff ff \tbnd jne 3de <main+0x3de>",}, +"f2 0f 85 fc ff ff ff \tbnd jne 3e3 <main+0x3e3>",}, {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "", "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",}, {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "", diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-64.c b/tools/perf/arch/x86/tests/insn-x86-dat-64.c index 4fe7cce179c4..262d9d25a6fa 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-64.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-64.c @@ -6,6 +6,8 @@ {{0x0f, 0x31, }, 2, 0, "", "", "0f 31 \trdtsc ",}, +{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "", +"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",}, {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", "f3 0f 1b 00 \tbndmk (%rax),%bnd0",}, {{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", @@ -325,19 +327,19 @@ {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",}, {{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional", -"f2 e8 00 00 00 00 \tbnd callq 3f6 <main+0x3f6>",}, +"f2 e8 00 00 00 00 \tbnd callq 3fb <main+0x3fb>",}, {{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect", "67 f2 ff 10 \tbnd callq *(%eax)",}, {{0xf2, 0xc3, }, 2, 0, "ret", "indirect", "f2 c3 \tbnd retq ",}, {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", -"f2 e9 00 00 00 00 \tbnd jmpq 402 <main+0x402>",}, +"f2 e9 00 00 00 00 \tbnd jmpq 407 <main+0x407>",}, {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", -"f2 e9 00 00 00 00 \tbnd jmpq 408 <main+0x408>",}, +"f2 e9 00 00 00 00 \tbnd jmpq 40d <main+0x40d>",}, {{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect", "67 f2 ff 21 \tbnd jmpq *(%ecx)",}, {{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional", -"f2 0f 85 00 00 00 00 \tbnd jne 413 <main+0x413>",}, +"f2 0f 85 00 00 00 00 \tbnd jne 418 <main+0x418>",}, {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "", "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",}, {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "", diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c index 41b1b1c62660..3cd677513e9e 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-src.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c @@ -19,6 +19,10 @@ int main(void) /* Following line is a marker for the awk script - do not change */ asm volatile("rdtsc"); /* Start here */ + /* Test fix for vcvtph2ps in x86-opcode-map.txt */ + + asm volatile("vcvtph2ps %xmm3,%ymm5"); + #ifdef __x86_64__ /* bndmk m64, bnd */ diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt index d388de72eaca..28082de46f0d 100644 --- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt +++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt @@ -629,7 +629,7 @@ AVXcode: 2 10: pblendvb Vdq,Wdq (66) 11: 12: -13: vcvtph2ps Vx,Wx,Ib (66),(v) +13: vcvtph2ps Vx,Wx (66),(v) 14: blendvps Vdq,Wdq (66) 15: blendvpd Vdq,Wdq (66) 16: vpermps Vqq,Hqq,Wqq (66),(v) -- 1.9.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [tip:perf/core] x86/insn: perf tools: Fix vcvtph2ps instruction decoding 2016-07-20 8:30 ` [PATCH V2 1/4] x86/insn: perf tools: Fix vcvtph2ps instruction decoding Adrian Hunter @ 2016-07-25 18:08 ` tip-bot for Adrian Hunter 0 siblings, 0 replies; 18+ messages in thread From: tip-bot for Adrian Hunter @ 2016-07-25 18:08 UTC (permalink / raw) To: linux-tip-commits Cc: acme, hpa, luto, adrian.hunter, dan.j.williams, mhiramat, linux-kernel, mingo, x86, jolsa, tglx Commit-ID: 6f6ef07f412c5bfc37cde57e94b1fec789471907 Gitweb: http://git.kernel.org/tip/6f6ef07f412c5bfc37cde57e94b1fec789471907 Author: Adrian Hunter <adrian.hunter@intel.com> AuthorDate: Wed, 20 Jul 2016 11:30:34 +0300 Committer: Arnaldo Carvalho de Melo <acme@redhat.com> CommitDate: Wed, 20 Jul 2016 09:57:46 -0300 x86/insn: perf tools: Fix vcvtph2ps instruction decoding vcvtph2ps does not have an immediate operand, so remove the erroneous 'Ib' from its opcode map entry. Add vcvtph2ps to the perf tools new instructions test to verify it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ingo Molnar <mingo@kernel.org> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dan Williams <dan.j.williams@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: X86 ML <x86@kernel.org> Link: http://lkml.kernel.org/r/1469003437-32706-2-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> --- arch/x86/lib/x86-opcode-map.txt | 2 +- tools/perf/arch/x86/tests/insn-x86-dat-32.c | 10 ++++++---- tools/perf/arch/x86/tests/insn-x86-dat-64.c | 10 ++++++---- tools/perf/arch/x86/tests/insn-x86-dat-src.c | 4 ++++ tools/perf/util/intel-pt-decoder/x86-opcode-map.txt | 2 +- 5 files changed, 18 insertions(+), 10 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index d388de7..28082de 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -629,7 +629,7 @@ AVXcode: 2 10: pblendvb Vdq,Wdq (66) 11: 12: -13: vcvtph2ps Vx,Wx,Ib (66),(v) +13: vcvtph2ps Vx,Wx (66),(v) 14: blendvps Vdq,Wdq (66) 15: blendvpd Vdq,Wdq (66) 16: vpermps Vqq,Hqq,Wqq (66),(v) diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c index 3b491cf..ca08e6e 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-32.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c @@ -6,6 +6,8 @@ {{0x0f, 0x31, }, 2, 0, "", "", "0f 31 \trdtsc ",}, +{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "", +"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",}, {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", "f3 0f 1b 00 \tbndmk (%eax),%bnd0",}, {{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", @@ -309,19 +311,19 @@ {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax,%ecx,1)",}, {{0xf2, 0xe8, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "call", "unconditional", -"f2 e8 fc ff ff ff \tbnd call 3c3 <main+0x3c3>",}, +"f2 e8 fc ff ff ff \tbnd call 3c8 <main+0x3c8>",}, {{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect", "f2 ff 10 \tbnd call *(%eax)",}, {{0xf2, 0xc3, }, 2, 0, "ret", "indirect", "f2 c3 \tbnd ret ",}, {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", -"f2 e9 fc ff ff ff \tbnd jmp 3ce <main+0x3ce>",}, +"f2 e9 fc ff ff ff \tbnd jmp 3d3 <main+0x3d3>",}, {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", -"f2 e9 fc ff ff ff \tbnd jmp 3d4 <main+0x3d4>",}, +"f2 e9 fc ff ff ff \tbnd jmp 3d9 <main+0x3d9>",}, {{0xf2, 0xff, 0x21, }, 3, 0, "jmp", "indirect", "f2 ff 21 \tbnd jmp *(%ecx)",}, {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffffffc, "jcc", "conditional", -"f2 0f 85 fc ff ff ff \tbnd jne 3de <main+0x3de>",}, +"f2 0f 85 fc ff ff ff \tbnd jne 3e3 <main+0x3e3>",}, {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "", "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",}, {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "", diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-64.c b/tools/perf/arch/x86/tests/insn-x86-dat-64.c index 4fe7cce..262d9d2 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-64.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-64.c @@ -6,6 +6,8 @@ {{0x0f, 0x31, }, 2, 0, "", "", "0f 31 \trdtsc ",}, +{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "", +"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",}, {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", "f3 0f 1b 00 \tbndmk (%rax),%bnd0",}, {{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", @@ -325,19 +327,19 @@ {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",}, {{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional", -"f2 e8 00 00 00 00 \tbnd callq 3f6 <main+0x3f6>",}, +"f2 e8 00 00 00 00 \tbnd callq 3fb <main+0x3fb>",}, {{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect", "67 f2 ff 10 \tbnd callq *(%eax)",}, {{0xf2, 0xc3, }, 2, 0, "ret", "indirect", "f2 c3 \tbnd retq ",}, {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", -"f2 e9 00 00 00 00 \tbnd jmpq 402 <main+0x402>",}, +"f2 e9 00 00 00 00 \tbnd jmpq 407 <main+0x407>",}, {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", -"f2 e9 00 00 00 00 \tbnd jmpq 408 <main+0x408>",}, +"f2 e9 00 00 00 00 \tbnd jmpq 40d <main+0x40d>",}, {{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect", "67 f2 ff 21 \tbnd jmpq *(%ecx)",}, {{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional", -"f2 0f 85 00 00 00 00 \tbnd jne 413 <main+0x413>",}, +"f2 0f 85 00 00 00 00 \tbnd jne 418 <main+0x418>",}, {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "", "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",}, {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "", diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c index 41b1b1c..3cd6775 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-src.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c @@ -19,6 +19,10 @@ int main(void) /* Following line is a marker for the awk script - do not change */ asm volatile("rdtsc"); /* Start here */ + /* Test fix for vcvtph2ps in x86-opcode-map.txt */ + + asm volatile("vcvtph2ps %xmm3,%ymm5"); + #ifdef __x86_64__ /* bndmk m64, bnd */ diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt index d388de7..28082de 100644 --- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt +++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt @@ -629,7 +629,7 @@ AVXcode: 2 10: pblendvb Vdq,Wdq (66) 11: 12: -13: vcvtph2ps Vx,Wx,Ib (66),(v) +13: vcvtph2ps Vx,Wx (66),(v) 14: blendvps Vdq,Wdq (66) 15: blendvpd Vdq,Wdq (66) 16: vpermps Vqq,Hqq,Wqq (66),(v) ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder 2016-07-20 8:30 [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Adrian Hunter 2016-07-20 8:30 ` [PATCH V2 1/4] x86/insn: perf tools: Fix vcvtph2ps instruction decoding Adrian Hunter @ 2016-07-20 8:30 ` Adrian Hunter 2016-07-25 18:08 ` [tip:perf/core] " tip-bot for Adrian Hunter 2025-11-30 16:05 ` [PATCH V2 2/4] " Borislav Petkov 2016-07-20 8:30 ` [PATCH V2 3/4] perf tools: Add AVX-512 support to the instruction decoder used by Intel PT Adrian Hunter ` (2 subsequent siblings) 4 siblings, 2 replies; 18+ messages in thread From: Adrian Hunter @ 2016-07-20 8:30 UTC (permalink / raw) To: linux-kernel Cc: Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Masami Hiramatsu, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML Add support for Intel's AVX-512 instructions to the instruction decoder. AVX-512 instructions are documented in Intel Architecture Instruction Set Extensions Programming Reference (February 2016). AVX-512 instructions are identified by a EVEX prefix which, for the purpose of instruction decoding, can be treated as though it were a 4-byte VEX prefix. Existing instructions which can now accept an EVEX prefix need not be further annotated in the op code map (x86-opcode-map.txt). In the case of new instructions, the op code map is updated accordingly. Also add associated Mask Instructions that are used to manipulate mask registers used in AVX-512 instructions. 'perf tools' instruction decoder is updated in a subsequent patch. And a representative set of instructions is added to the perf tools new instructions test in a subsequent patch. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> --- arch/x86/include/asm/inat.h | 17 ++- arch/x86/include/asm/insn.h | 12 +- arch/x86/lib/insn.c | 18 ++- arch/x86/lib/x86-opcode-map.txt | 263 +++++++++++++++++++++++------------ arch/x86/tools/gen-insn-attr-x86.awk | 11 +- 5 files changed, 220 insertions(+), 101 deletions(-) diff --git a/arch/x86/include/asm/inat.h b/arch/x86/include/asm/inat.h index 74a2e312e8a2..02aff0867211 100644 --- a/arch/x86/include/asm/inat.h +++ b/arch/x86/include/asm/inat.h @@ -48,6 +48,7 @@ /* AVX VEX prefixes */ #define INAT_PFX_VEX2 13 /* 2-bytes VEX prefix */ #define INAT_PFX_VEX3 14 /* 3-bytes VEX prefix */ +#define INAT_PFX_EVEX 15 /* EVEX prefix */ #define INAT_LSTPFX_MAX 3 #define INAT_LGCPFX_MAX 11 @@ -89,6 +90,7 @@ #define INAT_VARIANT (1 << (INAT_FLAG_OFFS + 4)) #define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5)) #define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6)) +#define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7)) /* Attribute making macros for attribute tables */ #define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS) #define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS) @@ -141,7 +143,13 @@ static inline int inat_last_prefix_id(insn_attr_t attr) static inline int inat_is_vex_prefix(insn_attr_t attr) { attr &= INAT_PFX_MASK; - return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3; + return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3 || + attr == INAT_PFX_EVEX; +} + +static inline int inat_is_evex_prefix(insn_attr_t attr) +{ + return (attr & INAT_PFX_MASK) == INAT_PFX_EVEX; } static inline int inat_is_vex3_prefix(insn_attr_t attr) @@ -216,6 +224,11 @@ static inline int inat_accept_vex(insn_attr_t attr) static inline int inat_must_vex(insn_attr_t attr) { - return attr & INAT_VEXONLY; + return attr & (INAT_VEXONLY | INAT_EVEXONLY); +} + +static inline int inat_must_evex(insn_attr_t attr) +{ + return attr & INAT_EVEXONLY; } #endif diff --git a/arch/x86/include/asm/insn.h b/arch/x86/include/asm/insn.h index e7814b74caf8..b3e32b010ab1 100644 --- a/arch/x86/include/asm/insn.h +++ b/arch/x86/include/asm/insn.h @@ -91,6 +91,7 @@ struct insn { #define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */ #define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */ /* VEX bit fields */ +#define X86_EVEX_M(vex) ((vex) & 0x03) /* EVEX Byte1 */ #define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */ #define X86_VEX2_M 1 /* VEX2.M always 1 */ #define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */ @@ -133,6 +134,13 @@ static inline int insn_is_avx(struct insn *insn) return (insn->vex_prefix.value != 0); } +static inline int insn_is_evex(struct insn *insn) +{ + if (!insn->prefixes.got) + insn_get_prefixes(insn); + return (insn->vex_prefix.nbytes == 4); +} + /* Ensure this instruction is decoded completely */ static inline int insn_complete(struct insn *insn) { @@ -144,8 +152,10 @@ static inline insn_byte_t insn_vex_m_bits(struct insn *insn) { if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */ return X86_VEX2_M; - else + else if (insn->vex_prefix.nbytes == 3) /* 3 bytes VEX */ return X86_VEX3_M(insn->vex_prefix.bytes[1]); + else /* EVEX */ + return X86_EVEX_M(insn->vex_prefix.bytes[1]); } static inline insn_byte_t insn_vex_p_bits(struct insn *insn) diff --git a/arch/x86/lib/insn.c b/arch/x86/lib/insn.c index 1a416935bac9..1088eb8f3a5f 100644 --- a/arch/x86/lib/insn.c +++ b/arch/x86/lib/insn.c @@ -155,14 +155,24 @@ found: /* * In 32-bits mode, if the [7:6] bits (mod bits of * ModRM) on the second byte are not 11b, it is - * LDS or LES. + * LDS or LES or BOUND. */ if (X86_MODRM_MOD(b2) != 3) goto vex_end; } insn->vex_prefix.bytes[0] = b; insn->vex_prefix.bytes[1] = b2; - if (inat_is_vex3_prefix(attr)) { + if (inat_is_evex_prefix(attr)) { + b2 = peek_nbyte_next(insn_byte_t, insn, 2); + insn->vex_prefix.bytes[2] = b2; + b2 = peek_nbyte_next(insn_byte_t, insn, 3); + insn->vex_prefix.bytes[3] = b2; + insn->vex_prefix.nbytes = 4; + insn->next_byte += 4; + if (insn->x86_64 && X86_VEX_W(b2)) + /* VEX.W overrides opnd_size */ + insn->opnd_bytes = 8; + } else if (inat_is_vex3_prefix(attr)) { b2 = peek_nbyte_next(insn_byte_t, insn, 2); insn->vex_prefix.bytes[2] = b2; insn->vex_prefix.nbytes = 3; @@ -221,7 +231,9 @@ void insn_get_opcode(struct insn *insn) m = insn_vex_m_bits(insn); p = insn_vex_p_bits(insn); insn->attr = inat_get_avx_attribute(op, m, p); - if (!inat_accept_vex(insn->attr) && !inat_is_group(insn->attr)) + if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) || + (!inat_accept_vex(insn->attr) && + !inat_is_group(insn->attr))) insn->attr = 0; /* This instruction is bad */ goto end; /* VEX has only 1 byte for opcode */ } diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index 28082de46f0d..ec378cd7b71e 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -13,12 +13,17 @@ # opcode: escape # escaped-name # EndTable # +# mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix +# mnemonics that begin with lowercase 'k' accept a VEX prefix +# #<group maps> # GrpTable: GrpXXX # reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...] # EndTable # # AVX Superscripts +# (ev): this opcode requires EVEX prefix. +# (evo): this opcode is changed by EVEX prefix (EVEX opcode) # (v): this opcode requires VEX prefix. # (v1): this opcode only supports 128bit VEX. # @@ -137,7 +142,7 @@ AVXcode: # 0x60 - 0x6f 60: PUSHA/PUSHAD (i64) 61: POPA/POPAD (i64) -62: BOUND Gv,Ma (i64) +62: BOUND Gv,Ma (i64) | EVEX (Prefix) 63: ARPL Ew,Gw (i64) | MOVSXD Gv,Ev (o64) 64: SEG=FS (Prefix) 65: SEG=GS (Prefix) @@ -399,17 +404,17 @@ AVXcode: 1 3f: # 0x0f 0x40-0x4f 40: CMOVO Gv,Ev -41: CMOVNO Gv,Ev -42: CMOVB/C/NAE Gv,Ev +41: CMOVNO Gv,Ev | kandw/q Vk,Hk,Uk | kandb/d Vk,Hk,Uk (66) +42: CMOVB/C/NAE Gv,Ev | kandnw/q Vk,Hk,Uk | kandnb/d Vk,Hk,Uk (66) 43: CMOVAE/NB/NC Gv,Ev -44: CMOVE/Z Gv,Ev -45: CMOVNE/NZ Gv,Ev -46: CMOVBE/NA Gv,Ev -47: CMOVA/NBE Gv,Ev +44: CMOVE/Z Gv,Ev | knotw/q Vk,Uk | knotb/d Vk,Uk (66) +45: CMOVNE/NZ Gv,Ev | korw/q Vk,Hk,Uk | korb/d Vk,Hk,Uk (66) +46: CMOVBE/NA Gv,Ev | kxnorw/q Vk,Hk,Uk | kxnorb/d Vk,Hk,Uk (66) +47: CMOVA/NBE Gv,Ev | kxorw/q Vk,Hk,Uk | kxorb/d Vk,Hk,Uk (66) 48: CMOVS Gv,Ev 49: CMOVNS Gv,Ev -4a: CMOVP/PE Gv,Ev -4b: CMOVNP/PO Gv,Ev +4a: CMOVP/PE Gv,Ev | kaddw/q Vk,Hk,Uk | kaddb/d Vk,Hk,Uk (66) +4b: CMOVNP/PO Gv,Ev | kunpckbw Vk,Hk,Uk (66) | kunpckwd/dq Vk,Hk,Uk 4c: CMOVL/NGE Gv,Ev 4d: CMOVNL/GE Gv,Ev 4e: CMOVLE/NG Gv,Ev @@ -426,7 +431,7 @@ AVXcode: 1 58: vaddps Vps,Hps,Wps | vaddpd Vpd,Hpd,Wpd (66) | vaddss Vss,Hss,Wss (F3),(v1) | vaddsd Vsd,Hsd,Wsd (F2),(v1) 59: vmulps Vps,Hps,Wps | vmulpd Vpd,Hpd,Wpd (66) | vmulss Vss,Hss,Wss (F3),(v1) | vmulsd Vsd,Hsd,Wsd (F2),(v1) 5a: vcvtps2pd Vpd,Wps | vcvtpd2ps Vps,Wpd (66) | vcvtss2sd Vsd,Hx,Wss (F3),(v1) | vcvtsd2ss Vss,Hx,Wsd (F2),(v1) -5b: vcvtdq2ps Vps,Wdq | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) +5b: vcvtdq2ps Vps,Wdq | vcvtqq2ps Vps,Wqq (evo) | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) 5c: vsubps Vps,Hps,Wps | vsubpd Vpd,Hpd,Wpd (66) | vsubss Vss,Hss,Wss (F3),(v1) | vsubsd Vsd,Hsd,Wsd (F2),(v1) 5d: vminps Vps,Hps,Wps | vminpd Vpd,Hpd,Wpd (66) | vminss Vss,Hss,Wss (F3),(v1) | vminsd Vsd,Hsd,Wsd (F2),(v1) 5e: vdivps Vps,Hps,Wps | vdivpd Vpd,Hpd,Wpd (66) | vdivss Vss,Hss,Wss (F3),(v1) | vdivsd Vsd,Hsd,Wsd (F2),(v1) @@ -447,7 +452,7 @@ AVXcode: 1 6c: vpunpcklqdq Vx,Hx,Wx (66),(v1) 6d: vpunpckhqdq Vx,Hx,Wx (66),(v1) 6e: movd/q Pd,Ey | vmovd/q Vy,Ey (66),(v1) -6f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqu Vx,Wx (F3) +6f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqa32/64 Vx,Wx (66),(evo) | vmovdqu Vx,Wx (F3) | vmovdqu32/64 Vx,Wx (F3),(evo) | vmovdqu8/16 Vx,Wx (F2),(ev) # 0x0f 0x70-0x7f 70: pshufw Pq,Qq,Ib | vpshufd Vx,Wx,Ib (66),(v1) | vpshufhw Vx,Wx,Ib (F3),(v1) | vpshuflw Vx,Wx,Ib (F2),(v1) 71: Grp12 (1A) @@ -458,14 +463,14 @@ AVXcode: 1 76: pcmpeqd Pq,Qq | vpcmpeqd Vx,Hx,Wx (66),(v1) # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX. 77: emms | vzeroupper | vzeroall -78: VMREAD Ey,Gy -79: VMWRITE Gy,Ey -7a: -7b: +78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) +79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) +7a: vcvtudq2pd/uqq2pd Vpd,Wx (F3),(ev) | vcvtudq2ps/uqq2ps Vpd,Wx (F2),(ev) | vcvttps2qq/pd2qq Vx,Wx (66),(ev) +7b: vcvtusi2sd Vpd,Hpd,Ev (F2),(ev) | vcvtusi2ss Vps,Hps,Ev (F3),(ev) | vcvtps2qq/pd2qq Vx,Wx (66),(ev) 7c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2) 7d: vhsubpd Vpd,Hpd,Wpd (66) | vhsubps Vps,Hps,Wps (F2) 7e: movd/q Ey,Pd | vmovd/q Ey,Vy (66),(v1) | vmovq Vq,Wq (F3),(v1) -7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqu Wx,Vx (F3) +7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev) # 0x0f 0x80-0x8f # Note: "forced64" is Intel CPU behavior (see comment about CALL insn). 80: JO Jz (f64) @@ -485,16 +490,16 @@ AVXcode: 1 8e: JLE/JNG Jz (f64) 8f: JNLE/JG Jz (f64) # 0x0f 0x90-0x9f -90: SETO Eb -91: SETNO Eb -92: SETB/C/NAE Eb -93: SETAE/NB/NC Eb +90: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66) +91: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66) +92: SETB/C/NAE Eb | kmovw Vk,Rv | kmovb Vk,Rv (66) | kmovq/d Vk,Rv (F2) +93: SETAE/NB/NC Eb | kmovw Gv,Uk | kmovb Gv,Uk (66) | kmovq/d Gv,Uk (F2) 94: SETE/Z Eb 95: SETNE/NZ Eb 96: SETBE/NA Eb 97: SETA/NBE Eb -98: SETS Eb -99: SETNS Eb +98: SETS Eb | kortestw/q Vk,Uk | kortestb/d Vk,Uk (66) +99: SETNS Eb | ktestw/q Vk,Uk | ktestb/d Vk,Uk (66) 9a: SETP/PE Eb 9b: SETNP/PO Eb 9c: SETL/NGE Eb @@ -564,11 +569,11 @@ d7: pmovmskb Gd,Nq | vpmovmskb Gd,Ux (66),(v1) d8: psubusb Pq,Qq | vpsubusb Vx,Hx,Wx (66),(v1) d9: psubusw Pq,Qq | vpsubusw Vx,Hx,Wx (66),(v1) da: pminub Pq,Qq | vpminub Vx,Hx,Wx (66),(v1) -db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1) +db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1) | vpandd/q Vx,Hx,Wx (66),(evo) dc: paddusb Pq,Qq | vpaddusb Vx,Hx,Wx (66),(v1) dd: paddusw Pq,Qq | vpaddusw Vx,Hx,Wx (66),(v1) de: pmaxub Pq,Qq | vpmaxub Vx,Hx,Wx (66),(v1) -df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1) +df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1) | vpandnd/q Vx,Hx,Wx (66),(evo) # 0x0f 0xe0-0xef e0: pavgb Pq,Qq | vpavgb Vx,Hx,Wx (66),(v1) e1: psraw Pq,Qq | vpsraw Vx,Hx,Wx (66),(v1) @@ -576,16 +581,16 @@ e2: psrad Pq,Qq | vpsrad Vx,Hx,Wx (66),(v1) e3: pavgw Pq,Qq | vpavgw Vx,Hx,Wx (66),(v1) e4: pmulhuw Pq,Qq | vpmulhuw Vx,Hx,Wx (66),(v1) e5: pmulhw Pq,Qq | vpmulhw Vx,Hx,Wx (66),(v1) -e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtpd2dq Vx,Wpd (F2) +e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtdq2pd/qq2pd Vx,Wdq (F3),(evo) | vcvtpd2dq Vx,Wpd (F2) e7: movntq Mq,Pq | vmovntdq Mx,Vx (66) e8: psubsb Pq,Qq | vpsubsb Vx,Hx,Wx (66),(v1) e9: psubsw Pq,Qq | vpsubsw Vx,Hx,Wx (66),(v1) ea: pminsw Pq,Qq | vpminsw Vx,Hx,Wx (66),(v1) -eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1) +eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1) | vpord/q Vx,Hx,Wx (66),(evo) ec: paddsb Pq,Qq | vpaddsb Vx,Hx,Wx (66),(v1) ed: paddsw Pq,Qq | vpaddsw Vx,Hx,Wx (66),(v1) ee: pmaxsw Pq,Qq | vpmaxsw Vx,Hx,Wx (66),(v1) -ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1) +ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1) | vpxord/q Vx,Hx,Wx (66),(evo) # 0x0f 0xf0-0xff f0: vlddqu Vx,Mx (F2) f1: psllw Pq,Qq | vpsllw Vx,Hx,Wx (66),(v1) @@ -626,81 +631,105 @@ AVXcode: 2 0e: vtestps Vx,Wx (66),(v) 0f: vtestpd Vx,Wx (66),(v) # 0x0f 0x38 0x10-0x1f -10: pblendvb Vdq,Wdq (66) -11: -12: -13: vcvtph2ps Vx,Wx (66),(v) -14: blendvps Vdq,Wdq (66) -15: blendvpd Vdq,Wdq (66) -16: vpermps Vqq,Hqq,Wqq (66),(v) +10: pblendvb Vdq,Wdq (66) | vpsrlvw Vx,Hx,Wx (66),(evo) | vpmovuswb Wx,Vx (F3),(ev) +11: vpmovusdb Wx,Vd (F3),(ev) | vpsravw Vx,Hx,Wx (66),(ev) +12: vpmovusqb Wx,Vq (F3),(ev) | vpsllvw Vx,Hx,Wx (66),(ev) +13: vcvtph2ps Vx,Wx (66),(v) | vpmovusdw Wx,Vd (F3),(ev) +14: blendvps Vdq,Wdq (66) | vpmovusqw Wx,Vq (F3),(ev) | vprorvd/q Vx,Hx,Wx (66),(evo) +15: blendvpd Vdq,Wdq (66) | vpmovusqd Wx,Vq (F3),(ev) | vprolvd/q Vx,Hx,Wx (66),(evo) +16: vpermps Vqq,Hqq,Wqq (66),(v) | vpermps/d Vqq,Hqq,Wqq (66),(evo) 17: vptest Vx,Wx (66) 18: vbroadcastss Vx,Wd (66),(v) -19: vbroadcastsd Vqq,Wq (66),(v) -1a: vbroadcastf128 Vqq,Mdq (66),(v) -1b: +19: vbroadcastsd Vqq,Wq (66),(v) | vbroadcastf32x2 Vqq,Wq (66),(evo) +1a: vbroadcastf128 Vqq,Mdq (66),(v) | vbroadcastf32x4/64x2 Vqq,Wq (66),(evo) +1b: vbroadcastf32x8/64x4 Vqq,Mdq (66),(ev) 1c: pabsb Pq,Qq | vpabsb Vx,Wx (66),(v1) 1d: pabsw Pq,Qq | vpabsw Vx,Wx (66),(v1) 1e: pabsd Pq,Qq | vpabsd Vx,Wx (66),(v1) -1f: +1f: vpabsq Vx,Wx (66),(ev) # 0x0f 0x38 0x20-0x2f -20: vpmovsxbw Vx,Ux/Mq (66),(v1) -21: vpmovsxbd Vx,Ux/Md (66),(v1) -22: vpmovsxbq Vx,Ux/Mw (66),(v1) -23: vpmovsxwd Vx,Ux/Mq (66),(v1) -24: vpmovsxwq Vx,Ux/Md (66),(v1) -25: vpmovsxdq Vx,Ux/Mq (66),(v1) -26: -27: -28: vpmuldq Vx,Hx,Wx (66),(v1) -29: vpcmpeqq Vx,Hx,Wx (66),(v1) -2a: vmovntdqa Vx,Mx (66),(v1) +20: vpmovsxbw Vx,Ux/Mq (66),(v1) | vpmovswb Wx,Vx (F3),(ev) +21: vpmovsxbd Vx,Ux/Md (66),(v1) | vpmovsdb Wx,Vd (F3),(ev) +22: vpmovsxbq Vx,Ux/Mw (66),(v1) | vpmovsqb Wx,Vq (F3),(ev) +23: vpmovsxwd Vx,Ux/Mq (66),(v1) | vpmovsdw Wx,Vd (F3),(ev) +24: vpmovsxwq Vx,Ux/Md (66),(v1) | vpmovsqw Wx,Vq (F3),(ev) +25: vpmovsxdq Vx,Ux/Mq (66),(v1) | vpmovsqd Wx,Vq (F3),(ev) +26: vptestmb/w Vk,Hx,Wx (66),(ev) | vptestnmb/w Vk,Hx,Wx (F3),(ev) +27: vptestmd/q Vk,Hx,Wx (66),(ev) | vptestnmd/q Vk,Hx,Wx (F3),(ev) +28: vpmuldq Vx,Hx,Wx (66),(v1) | vpmovm2b/w Vx,Uk (F3),(ev) +29: vpcmpeqq Vx,Hx,Wx (66),(v1) | vpmovb2m/w2m Vk,Ux (F3),(ev) +2a: vmovntdqa Vx,Mx (66),(v1) | vpbroadcastmb2q Vx,Uk (F3),(ev) 2b: vpackusdw Vx,Hx,Wx (66),(v1) -2c: vmaskmovps Vx,Hx,Mx (66),(v) -2d: vmaskmovpd Vx,Hx,Mx (66),(v) +2c: vmaskmovps Vx,Hx,Mx (66),(v) | vscalefps/d Vx,Hx,Wx (66),(evo) +2d: vmaskmovpd Vx,Hx,Mx (66),(v) | vscalefss/d Vx,Hx,Wx (66),(evo) 2e: vmaskmovps Mx,Hx,Vx (66),(v) 2f: vmaskmovpd Mx,Hx,Vx (66),(v) # 0x0f 0x38 0x30-0x3f -30: vpmovzxbw Vx,Ux/Mq (66),(v1) -31: vpmovzxbd Vx,Ux/Md (66),(v1) -32: vpmovzxbq Vx,Ux/Mw (66),(v1) -33: vpmovzxwd Vx,Ux/Mq (66),(v1) -34: vpmovzxwq Vx,Ux/Md (66),(v1) -35: vpmovzxdq Vx,Ux/Mq (66),(v1) -36: vpermd Vqq,Hqq,Wqq (66),(v) +30: vpmovzxbw Vx,Ux/Mq (66),(v1) | vpmovwb Wx,Vx (F3),(ev) +31: vpmovzxbd Vx,Ux/Md (66),(v1) | vpmovdb Wx,Vd (F3),(ev) +32: vpmovzxbq Vx,Ux/Mw (66),(v1) | vpmovqb Wx,Vq (F3),(ev) +33: vpmovzxwd Vx,Ux/Mq (66),(v1) | vpmovdw Wx,Vd (F3),(ev) +34: vpmovzxwq Vx,Ux/Md (66),(v1) | vpmovqw Wx,Vq (F3),(ev) +35: vpmovzxdq Vx,Ux/Mq (66),(v1) | vpmovqd Wx,Vq (F3),(ev) +36: vpermd Vqq,Hqq,Wqq (66),(v) | vpermd/q Vqq,Hqq,Wqq (66),(evo) 37: vpcmpgtq Vx,Hx,Wx (66),(v1) -38: vpminsb Vx,Hx,Wx (66),(v1) -39: vpminsd Vx,Hx,Wx (66),(v1) -3a: vpminuw Vx,Hx,Wx (66),(v1) -3b: vpminud Vx,Hx,Wx (66),(v1) +38: vpminsb Vx,Hx,Wx (66),(v1) | vpmovm2d/q Vx,Uk (F3),(ev) +39: vpminsd Vx,Hx,Wx (66),(v1) | vpminsd/q Vx,Hx,Wx (66),(evo) | vpmovd2m/q2m Vk,Ux (F3),(ev) +3a: vpminuw Vx,Hx,Wx (66),(v1) | vpbroadcastmw2d Vx,Uk (F3),(ev) +3b: vpminud Vx,Hx,Wx (66),(v1) | vpminud/q Vx,Hx,Wx (66),(evo) 3c: vpmaxsb Vx,Hx,Wx (66),(v1) -3d: vpmaxsd Vx,Hx,Wx (66),(v1) +3d: vpmaxsd Vx,Hx,Wx (66),(v1) | vpmaxsd/q Vx,Hx,Wx (66),(evo) 3e: vpmaxuw Vx,Hx,Wx (66),(v1) -3f: vpmaxud Vx,Hx,Wx (66),(v1) +3f: vpmaxud Vx,Hx,Wx (66),(v1) | vpmaxud/q Vx,Hx,Wx (66),(evo) # 0x0f 0x38 0x40-0x8f -40: vpmulld Vx,Hx,Wx (66),(v1) +40: vpmulld Vx,Hx,Wx (66),(v1) | vpmulld/q Vx,Hx,Wx (66),(evo) 41: vphminposuw Vdq,Wdq (66),(v1) -42: -43: -44: +42: vgetexpps/d Vx,Wx (66),(ev) +43: vgetexpss/d Vx,Hx,Wx (66),(ev) +44: vplzcntd/q Vx,Wx (66),(ev) 45: vpsrlvd/q Vx,Hx,Wx (66),(v) -46: vpsravd Vx,Hx,Wx (66),(v) +46: vpsravd Vx,Hx,Wx (66),(v) | vpsravd/q Vx,Hx,Wx (66),(evo) 47: vpsllvd/q Vx,Hx,Wx (66),(v) -# Skip 0x48-0x57 +# Skip 0x48-0x4b +4c: vrcp14ps/d Vpd,Wpd (66),(ev) +4d: vrcp14ss/d Vsd,Hpd,Wsd (66),(ev) +4e: vrsqrt14ps/d Vpd,Wpd (66),(ev) +4f: vrsqrt14ss/d Vsd,Hsd,Wsd (66),(ev) +# Skip 0x50-0x57 58: vpbroadcastd Vx,Wx (66),(v) -59: vpbroadcastq Vx,Wx (66),(v) -5a: vbroadcasti128 Vqq,Mdq (66),(v) -# Skip 0x5b-0x77 +59: vpbroadcastq Vx,Wx (66),(v) | vbroadcasti32x2 Vx,Wx (66),(evo) +5a: vbroadcasti128 Vqq,Mdq (66),(v) | vbroadcasti32x4/64x2 Vx,Wx (66),(evo) +5b: vbroadcasti32x8/64x4 Vqq,Mdq (66),(ev) +# Skip 0x5c-0x63 +64: vpblendmd/q Vx,Hx,Wx (66),(ev) +65: vblendmps/d Vx,Hx,Wx (66),(ev) +66: vpblendmb/w Vx,Hx,Wx (66),(ev) +# Skip 0x67-0x74 +75: vpermi2b/w Vx,Hx,Wx (66),(ev) +76: vpermi2d/q Vx,Hx,Wx (66),(ev) +77: vpermi2ps/d Vx,Hx,Wx (66),(ev) 78: vpbroadcastb Vx,Wx (66),(v) 79: vpbroadcastw Vx,Wx (66),(v) -# Skip 0x7a-0x7f +7a: vpbroadcastb Vx,Rv (66),(ev) +7b: vpbroadcastw Vx,Rv (66),(ev) +7c: vpbroadcastd/q Vx,Rv (66),(ev) +7d: vpermt2b/w Vx,Hx,Wx (66),(ev) +7e: vpermt2d/q Vx,Hx,Wx (66),(ev) +7f: vpermt2ps/d Vx,Hx,Wx (66),(ev) 80: INVEPT Gy,Mdq (66) 81: INVPID Gy,Mdq (66) 82: INVPCID Gy,Mdq (66) +83: vpmultishiftqb Vx,Hx,Wx (66),(ev) +88: vexpandps/d Vpd,Wpd (66),(ev) +89: vpexpandd/q Vx,Wx (66),(ev) +8a: vcompressps/d Wx,Vx (66),(ev) +8b: vpcompressd/q Wx,Vx (66),(ev) 8c: vpmaskmovd/q Vx,Hx,Mx (66),(v) +8d: vpermb/w Vx,Hx,Wx (66),(ev) 8e: vpmaskmovd/q Mx,Vx,Hx (66),(v) # 0x0f 0x38 0x90-0xbf (FMA) -90: vgatherdd/q Vx,Hx,Wx (66),(v) -91: vgatherqd/q Vx,Hx,Wx (66),(v) +90: vgatherdd/q Vx,Hx,Wx (66),(v) | vpgatherdd/q Vx,Wx (66),(evo) +91: vgatherqd/q Vx,Hx,Wx (66),(v) | vpgatherqd/q Vx,Wx (66),(evo) 92: vgatherdps/d Vx,Hx,Wx (66),(v) 93: vgatherqps/d Vx,Hx,Wx (66),(v) 94: @@ -715,6 +744,10 @@ AVXcode: 2 9d: vfnmadd132ss/d Vx,Hx,Wx (66),(v),(v1) 9e: vfnmsub132ps/d Vx,Hx,Wx (66),(v) 9f: vfnmsub132ss/d Vx,Hx,Wx (66),(v),(v1) +a0: vpscatterdd/q Wx,Vx (66),(ev) +a1: vpscatterqd/q Wx,Vx (66),(ev) +a2: vscatterdps/d Wx,Vx (66),(ev) +a3: vscatterqps/d Wx,Vx (66),(ev) a6: vfmaddsub213ps/d Vx,Hx,Wx (66),(v) a7: vfmsubadd213ps/d Vx,Hx,Wx (66),(v) a8: vfmadd213ps/d Vx,Hx,Wx (66),(v) @@ -725,6 +758,8 @@ ac: vfnmadd213ps/d Vx,Hx,Wx (66),(v) ad: vfnmadd213ss/d Vx,Hx,Wx (66),(v),(v1) ae: vfnmsub213ps/d Vx,Hx,Wx (66),(v) af: vfnmsub213ss/d Vx,Hx,Wx (66),(v),(v1) +b4: vpmadd52luq Vx,Hx,Wx (66),(ev) +b5: vpmadd52huq Vx,Hx,Wx (66),(ev) b6: vfmaddsub231ps/d Vx,Hx,Wx (66),(v) b7: vfmsubadd231ps/d Vx,Hx,Wx (66),(v) b8: vfmadd231ps/d Vx,Hx,Wx (66),(v) @@ -736,12 +771,15 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1) be: vfnmsub231ps/d Vx,Hx,Wx (66),(v) bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1) # 0x0f 0x38 0xc0-0xff -c8: sha1nexte Vdq,Wdq +c4: vpconflictd/q Vx,Wx (66),(ev) +c6: Grp18 (1A) +c7: Grp19 (1A) +c8: sha1nexte Vdq,Wdq | vexp2ps/d Vx,Wx (66),(ev) c9: sha1msg1 Vdq,Wdq -ca: sha1msg2 Vdq,Wdq -cb: sha256rnds2 Vdq,Wdq -cc: sha256msg1 Vdq,Wdq -cd: sha256msg2 Vdq,Wdq +ca: sha1msg2 Vdq,Wdq | vrcp28ps/d Vx,Wx (66),(ev) +cb: sha256rnds2 Vdq,Wdq | vrcp28ss/d Vx,Hx,Wx (66),(ev) +cc: sha256msg1 Vdq,Wdq | vrsqrt28ps/d Vx,Wx (66),(ev) +cd: sha256msg2 Vdq,Wdq | vrsqrt28ss/d Vx,Hx,Wx (66),(ev) db: VAESIMC Vdq,Wdq (66),(v1) dc: VAESENC Vdq,Hdq,Wdq (66),(v1) dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1) @@ -763,15 +801,15 @@ AVXcode: 3 00: vpermq Vqq,Wqq,Ib (66),(v) 01: vpermpd Vqq,Wqq,Ib (66),(v) 02: vpblendd Vx,Hx,Wx,Ib (66),(v) -03: +03: valignd/q Vx,Hx,Wx,Ib (66),(ev) 04: vpermilps Vx,Wx,Ib (66),(v) 05: vpermilpd Vx,Wx,Ib (66),(v) 06: vperm2f128 Vqq,Hqq,Wqq,Ib (66),(v) 07: -08: vroundps Vx,Wx,Ib (66) -09: vroundpd Vx,Wx,Ib (66) -0a: vroundss Vss,Wss,Ib (66),(v1) -0b: vroundsd Vsd,Wsd,Ib (66),(v1) +08: vroundps Vx,Wx,Ib (66) | vrndscaleps Vx,Wx,Ib (66),(evo) +09: vroundpd Vx,Wx,Ib (66) | vrndscalepd Vx,Wx,Ib (66),(evo) +0a: vroundss Vss,Wss,Ib (66),(v1) | vrndscaless Vx,Hx,Wx,Ib (66),(evo) +0b: vroundsd Vsd,Wsd,Ib (66),(v1) | vrndscalesd Vx,Hx,Wx,Ib (66),(evo) 0c: vblendps Vx,Hx,Wx,Ib (66) 0d: vblendpd Vx,Hx,Wx,Ib (66) 0e: vpblendw Vx,Hx,Wx,Ib (66),(v1) @@ -780,26 +818,51 @@ AVXcode: 3 15: vpextrw Rd/Mw,Vdq,Ib (66),(v1) 16: vpextrd/q Ey,Vdq,Ib (66),(v1) 17: vextractps Ed,Vdq,Ib (66),(v1) -18: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v) -19: vextractf128 Wdq,Vqq,Ib (66),(v) +18: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v) | vinsertf32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo) +19: vextractf128 Wdq,Vqq,Ib (66),(v) | vextractf32x4/64x2 Wdq,Vqq,Ib (66),(evo) +1a: vinsertf32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev) +1b: vextractf32x8/64x4 Wdq,Vqq,Ib (66),(ev) 1d: vcvtps2ph Wx,Vx,Ib (66),(v) +1e: vpcmpud/q Vk,Hd,Wd,Ib (66),(ev) +1f: vpcmpd/q Vk,Hd,Wd,Ib (66),(ev) 20: vpinsrb Vdq,Hdq,Ry/Mb,Ib (66),(v1) 21: vinsertps Vdq,Hdq,Udq/Md,Ib (66),(v1) 22: vpinsrd/q Vdq,Hdq,Ey,Ib (66),(v1) -38: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v) -39: vextracti128 Wdq,Vqq,Ib (66),(v) +23: vshuff32x4/64x2 Vx,Hx,Wx,Ib (66),(ev) +25: vpternlogd/q Vx,Hx,Wx,Ib (66),(ev) +26: vgetmantps/d Vx,Wx,Ib (66),(ev) +27: vgetmantss/d Vx,Hx,Wx,Ib (66),(ev) +30: kshiftrb/w Vk,Uk,Ib (66),(v) +31: kshiftrd/q Vk,Uk,Ib (66),(v) +32: kshiftlb/w Vk,Uk,Ib (66),(v) +33: kshiftld/q Vk,Uk,Ib (66),(v) +38: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v) | vinserti32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo) +39: vextracti128 Wdq,Vqq,Ib (66),(v) | vextracti32x4/64x2 Wdq,Vqq,Ib (66),(evo) +3a: vinserti32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev) +3b: vextracti32x8/64x4 Wdq,Vqq,Ib (66),(ev) +3e: vpcmpub/w Vk,Hk,Wx,Ib (66),(ev) +3f: vpcmpb/w Vk,Hk,Wx,Ib (66),(ev) 40: vdpps Vx,Hx,Wx,Ib (66) 41: vdppd Vdq,Hdq,Wdq,Ib (66),(v1) -42: vmpsadbw Vx,Hx,Wx,Ib (66),(v1) +42: vmpsadbw Vx,Hx,Wx,Ib (66),(v1) | vdbpsadbw Vx,Hx,Wx,Ib (66),(evo) +43: vshufi32x4/64x2 Vx,Hx,Wx,Ib (66),(ev) 44: vpclmulqdq Vdq,Hdq,Wdq,Ib (66),(v1) 46: vperm2i128 Vqq,Hqq,Wqq,Ib (66),(v) 4a: vblendvps Vx,Hx,Wx,Lx (66),(v) 4b: vblendvpd Vx,Hx,Wx,Lx (66),(v) 4c: vpblendvb Vx,Hx,Wx,Lx (66),(v1) +50: vrangeps/d Vx,Hx,Wx,Ib (66),(ev) +51: vrangess/d Vx,Hx,Wx,Ib (66),(ev) +54: vfixupimmps/d Vx,Hx,Wx,Ib (66),(ev) +55: vfixupimmss/d Vx,Hx,Wx,Ib (66),(ev) +56: vreduceps/d Vx,Wx,Ib (66),(ev) +57: vreducess/d Vx,Hx,Wx,Ib (66),(ev) 60: vpcmpestrm Vdq,Wdq,Ib (66),(v1) 61: vpcmpestri Vdq,Wdq,Ib (66),(v1) 62: vpcmpistrm Vdq,Wdq,Ib (66),(v1) 63: vpcmpistri Vdq,Wdq,Ib (66),(v1) +66: vfpclassps/d Vk,Wx,Ib (66),(ev) +67: vfpclassss/d Vk,Wx,Ib (66),(ev) cc: sha1rnds4 Vdq,Wdq,Ib df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1) f0: RORX Gy,Ey,Ib (F2),(v) @@ -927,8 +990,10 @@ GrpTable: Grp12 EndTable GrpTable: Grp13 +0: vprord/q Hx,Wx,Ib (66),(ev) +1: vprold/q Hx,Wx,Ib (66),(ev) 2: psrld Nq,Ib (11B) | vpsrld Hx,Ux,Ib (66),(11B),(v1) -4: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1) +4: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1) | vpsrad/q Hx,Ux,Ib (66),(evo) 6: pslld Nq,Ib (11B) | vpslld Hx,Ux,Ib (66),(11B),(v1) EndTable @@ -963,6 +1028,20 @@ GrpTable: Grp17 3: BLSI By,Ey (v) EndTable +GrpTable: Grp18 +1: vgatherpf0dps/d Wx (66),(ev) +2: vgatherpf1dps/d Wx (66),(ev) +5: vscatterpf0dps/d Wx (66),(ev) +6: vscatterpf1dps/d Wx (66),(ev) +EndTable + +GrpTable: Grp19 +1: vgatherpf0qps/d Wx (66),(ev) +2: vgatherpf1qps/d Wx (66),(ev) +5: vscatterpf0qps/d Wx (66),(ev) +6: vscatterpf1qps/d Wx (66),(ev) +EndTable + # AMD's Prefetch Group GrpTable: GrpP 0: PREFETCH diff --git a/arch/x86/tools/gen-insn-attr-x86.awk b/arch/x86/tools/gen-insn-attr-x86.awk index 093a892026f9..a3d2c62fd805 100644 --- a/arch/x86/tools/gen-insn-attr-x86.awk +++ b/arch/x86/tools/gen-insn-attr-x86.awk @@ -72,12 +72,14 @@ BEGIN { lprefix_expr = "\\((66|F2|F3)\\)" max_lprefix = 4 - # All opcodes starting with lower-case 'v' or with (v1) superscript + # All opcodes starting with lower-case 'v', 'k' or with (v1) superscript # accepts VEX prefix - vexok_opcode_expr = "^v.*" + vexok_opcode_expr = "^[vk].*" vexok_expr = "\\(v1\\)" # All opcodes with (v) superscript supports *only* VEX prefix vexonly_expr = "\\(v\\)" + # All opcodes with (ev) superscript supports *only* EVEX prefix + evexonly_expr = "\\(ev\\)" prefix_expr = "\\(Prefix\\)" prefix_num["Operand-Size"] = "INAT_PFX_OPNDSZ" @@ -95,6 +97,7 @@ BEGIN { prefix_num["Address-Size"] = "INAT_PFX_ADDRSZ" prefix_num["VEX+1byte"] = "INAT_PFX_VEX2" prefix_num["VEX+2byte"] = "INAT_PFX_VEX3" + prefix_num["EVEX"] = "INAT_PFX_EVEX" clear_vars() } @@ -319,7 +322,9 @@ function convert_operands(count,opnd, i,j,imm,mod) flags = add_flags(flags, "INAT_MODRM") # check VEX codes - if (match(ext, vexonly_expr)) + if (match(ext, evexonly_expr)) + flags = add_flags(flags, "INAT_VEXOK | INAT_EVEXONLY") + else if (match(ext, vexonly_expr)) flags = add_flags(flags, "INAT_VEXOK | INAT_VEXONLY") else if (match(ext, vexok_expr) || match(opcode, vexok_opcode_expr)) flags = add_flags(flags, "INAT_VEXOK") -- 1.9.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [tip:perf/core] x86/insn: Add AVX-512 support to the instruction decoder 2016-07-20 8:30 ` [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder Adrian Hunter @ 2016-07-25 18:08 ` tip-bot for Adrian Hunter 2025-11-30 16:05 ` [PATCH V2 2/4] " Borislav Petkov 1 sibling, 0 replies; 18+ messages in thread From: tip-bot for Adrian Hunter @ 2016-07-25 18:08 UTC (permalink / raw) To: linux-tip-commits Cc: adrian.hunter, luto, acme, jolsa, dan.j.williams, mhiramat, hpa, mingo, x86, linux-kernel, tglx Commit-ID: 25af37f4e1e0a747824e3713b80d6b97dad28b7c Gitweb: http://git.kernel.org/tip/25af37f4e1e0a747824e3713b80d6b97dad28b7c Author: Adrian Hunter <adrian.hunter@intel.com> AuthorDate: Wed, 20 Jul 2016 11:30:35 +0300 Committer: Arnaldo Carvalho de Melo <acme@redhat.com> CommitDate: Thu, 21 Jul 2016 09:37:11 -0300 x86/insn: Add AVX-512 support to the instruction decoder Add support for Intel's AVX-512 instructions to the instruction decoder. AVX-512 instructions are documented in Intel Architecture Instruction Set Extensions Programming Reference (February 2016). AVX-512 instructions are identified by a EVEX prefix which, for the purpose of instruction decoding, can be treated as though it were a 4-byte VEX prefix. Existing instructions which can now accept an EVEX prefix need not be further annotated in the op code map (x86-opcode-map.txt). In the case of new instructions, the op code map is updated accordingly. Also add associated Mask Instructions that are used to manipulate mask registers used in AVX-512 instructions. The 'perf tools' instruction decoder is updated in a subsequent patch. And a representative set of instructions is added to the perf tools new instructions test in a subsequent patch. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ingo Molnar <mingo@kernel.org> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dan Williams <dan.j.williams@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: X86 ML <x86@kernel.org> Link: http://lkml.kernel.org/r/1469003437-32706-3-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> --- arch/x86/include/asm/inat.h | 17 ++- arch/x86/include/asm/insn.h | 12 +- arch/x86/lib/insn.c | 18 ++- arch/x86/lib/x86-opcode-map.txt | 263 +++++++++++++++++++++++------------ arch/x86/tools/gen-insn-attr-x86.awk | 11 +- 5 files changed, 220 insertions(+), 101 deletions(-) diff --git a/arch/x86/include/asm/inat.h b/arch/x86/include/asm/inat.h index 74a2e31..02aff08 100644 --- a/arch/x86/include/asm/inat.h +++ b/arch/x86/include/asm/inat.h @@ -48,6 +48,7 @@ /* AVX VEX prefixes */ #define INAT_PFX_VEX2 13 /* 2-bytes VEX prefix */ #define INAT_PFX_VEX3 14 /* 3-bytes VEX prefix */ +#define INAT_PFX_EVEX 15 /* EVEX prefix */ #define INAT_LSTPFX_MAX 3 #define INAT_LGCPFX_MAX 11 @@ -89,6 +90,7 @@ #define INAT_VARIANT (1 << (INAT_FLAG_OFFS + 4)) #define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5)) #define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6)) +#define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7)) /* Attribute making macros for attribute tables */ #define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS) #define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS) @@ -141,7 +143,13 @@ static inline int inat_last_prefix_id(insn_attr_t attr) static inline int inat_is_vex_prefix(insn_attr_t attr) { attr &= INAT_PFX_MASK; - return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3; + return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3 || + attr == INAT_PFX_EVEX; +} + +static inline int inat_is_evex_prefix(insn_attr_t attr) +{ + return (attr & INAT_PFX_MASK) == INAT_PFX_EVEX; } static inline int inat_is_vex3_prefix(insn_attr_t attr) @@ -216,6 +224,11 @@ static inline int inat_accept_vex(insn_attr_t attr) static inline int inat_must_vex(insn_attr_t attr) { - return attr & INAT_VEXONLY; + return attr & (INAT_VEXONLY | INAT_EVEXONLY); +} + +static inline int inat_must_evex(insn_attr_t attr) +{ + return attr & INAT_EVEXONLY; } #endif diff --git a/arch/x86/include/asm/insn.h b/arch/x86/include/asm/insn.h index e7814b7..b3e32b0 100644 --- a/arch/x86/include/asm/insn.h +++ b/arch/x86/include/asm/insn.h @@ -91,6 +91,7 @@ struct insn { #define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */ #define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */ /* VEX bit fields */ +#define X86_EVEX_M(vex) ((vex) & 0x03) /* EVEX Byte1 */ #define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */ #define X86_VEX2_M 1 /* VEX2.M always 1 */ #define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */ @@ -133,6 +134,13 @@ static inline int insn_is_avx(struct insn *insn) return (insn->vex_prefix.value != 0); } +static inline int insn_is_evex(struct insn *insn) +{ + if (!insn->prefixes.got) + insn_get_prefixes(insn); + return (insn->vex_prefix.nbytes == 4); +} + /* Ensure this instruction is decoded completely */ static inline int insn_complete(struct insn *insn) { @@ -144,8 +152,10 @@ static inline insn_byte_t insn_vex_m_bits(struct insn *insn) { if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */ return X86_VEX2_M; - else + else if (insn->vex_prefix.nbytes == 3) /* 3 bytes VEX */ return X86_VEX3_M(insn->vex_prefix.bytes[1]); + else /* EVEX */ + return X86_EVEX_M(insn->vex_prefix.bytes[1]); } static inline insn_byte_t insn_vex_p_bits(struct insn *insn) diff --git a/arch/x86/lib/insn.c b/arch/x86/lib/insn.c index 1a41693..1088eb8 100644 --- a/arch/x86/lib/insn.c +++ b/arch/x86/lib/insn.c @@ -155,14 +155,24 @@ found: /* * In 32-bits mode, if the [7:6] bits (mod bits of * ModRM) on the second byte are not 11b, it is - * LDS or LES. + * LDS or LES or BOUND. */ if (X86_MODRM_MOD(b2) != 3) goto vex_end; } insn->vex_prefix.bytes[0] = b; insn->vex_prefix.bytes[1] = b2; - if (inat_is_vex3_prefix(attr)) { + if (inat_is_evex_prefix(attr)) { + b2 = peek_nbyte_next(insn_byte_t, insn, 2); + insn->vex_prefix.bytes[2] = b2; + b2 = peek_nbyte_next(insn_byte_t, insn, 3); + insn->vex_prefix.bytes[3] = b2; + insn->vex_prefix.nbytes = 4; + insn->next_byte += 4; + if (insn->x86_64 && X86_VEX_W(b2)) + /* VEX.W overrides opnd_size */ + insn->opnd_bytes = 8; + } else if (inat_is_vex3_prefix(attr)) { b2 = peek_nbyte_next(insn_byte_t, insn, 2); insn->vex_prefix.bytes[2] = b2; insn->vex_prefix.nbytes = 3; @@ -221,7 +231,9 @@ void insn_get_opcode(struct insn *insn) m = insn_vex_m_bits(insn); p = insn_vex_p_bits(insn); insn->attr = inat_get_avx_attribute(op, m, p); - if (!inat_accept_vex(insn->attr) && !inat_is_group(insn->attr)) + if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) || + (!inat_accept_vex(insn->attr) && + !inat_is_group(insn->attr))) insn->attr = 0; /* This instruction is bad */ goto end; /* VEX has only 1 byte for opcode */ } diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index 28082de..ec378cd 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -13,12 +13,17 @@ # opcode: escape # escaped-name # EndTable # +# mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix +# mnemonics that begin with lowercase 'k' accept a VEX prefix +# #<group maps> # GrpTable: GrpXXX # reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...] # EndTable # # AVX Superscripts +# (ev): this opcode requires EVEX prefix. +# (evo): this opcode is changed by EVEX prefix (EVEX opcode) # (v): this opcode requires VEX prefix. # (v1): this opcode only supports 128bit VEX. # @@ -137,7 +142,7 @@ AVXcode: # 0x60 - 0x6f 60: PUSHA/PUSHAD (i64) 61: POPA/POPAD (i64) -62: BOUND Gv,Ma (i64) +62: BOUND Gv,Ma (i64) | EVEX (Prefix) 63: ARPL Ew,Gw (i64) | MOVSXD Gv,Ev (o64) 64: SEG=FS (Prefix) 65: SEG=GS (Prefix) @@ -399,17 +404,17 @@ AVXcode: 1 3f: # 0x0f 0x40-0x4f 40: CMOVO Gv,Ev -41: CMOVNO Gv,Ev -42: CMOVB/C/NAE Gv,Ev +41: CMOVNO Gv,Ev | kandw/q Vk,Hk,Uk | kandb/d Vk,Hk,Uk (66) +42: CMOVB/C/NAE Gv,Ev | kandnw/q Vk,Hk,Uk | kandnb/d Vk,Hk,Uk (66) 43: CMOVAE/NB/NC Gv,Ev -44: CMOVE/Z Gv,Ev -45: CMOVNE/NZ Gv,Ev -46: CMOVBE/NA Gv,Ev -47: CMOVA/NBE Gv,Ev +44: CMOVE/Z Gv,Ev | knotw/q Vk,Uk | knotb/d Vk,Uk (66) +45: CMOVNE/NZ Gv,Ev | korw/q Vk,Hk,Uk | korb/d Vk,Hk,Uk (66) +46: CMOVBE/NA Gv,Ev | kxnorw/q Vk,Hk,Uk | kxnorb/d Vk,Hk,Uk (66) +47: CMOVA/NBE Gv,Ev | kxorw/q Vk,Hk,Uk | kxorb/d Vk,Hk,Uk (66) 48: CMOVS Gv,Ev 49: CMOVNS Gv,Ev -4a: CMOVP/PE Gv,Ev -4b: CMOVNP/PO Gv,Ev +4a: CMOVP/PE Gv,Ev | kaddw/q Vk,Hk,Uk | kaddb/d Vk,Hk,Uk (66) +4b: CMOVNP/PO Gv,Ev | kunpckbw Vk,Hk,Uk (66) | kunpckwd/dq Vk,Hk,Uk 4c: CMOVL/NGE Gv,Ev 4d: CMOVNL/GE Gv,Ev 4e: CMOVLE/NG Gv,Ev @@ -426,7 +431,7 @@ AVXcode: 1 58: vaddps Vps,Hps,Wps | vaddpd Vpd,Hpd,Wpd (66) | vaddss Vss,Hss,Wss (F3),(v1) | vaddsd Vsd,Hsd,Wsd (F2),(v1) 59: vmulps Vps,Hps,Wps | vmulpd Vpd,Hpd,Wpd (66) | vmulss Vss,Hss,Wss (F3),(v1) | vmulsd Vsd,Hsd,Wsd (F2),(v1) 5a: vcvtps2pd Vpd,Wps | vcvtpd2ps Vps,Wpd (66) | vcvtss2sd Vsd,Hx,Wss (F3),(v1) | vcvtsd2ss Vss,Hx,Wsd (F2),(v1) -5b: vcvtdq2ps Vps,Wdq | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) +5b: vcvtdq2ps Vps,Wdq | vcvtqq2ps Vps,Wqq (evo) | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) 5c: vsubps Vps,Hps,Wps | vsubpd Vpd,Hpd,Wpd (66) | vsubss Vss,Hss,Wss (F3),(v1) | vsubsd Vsd,Hsd,Wsd (F2),(v1) 5d: vminps Vps,Hps,Wps | vminpd Vpd,Hpd,Wpd (66) | vminss Vss,Hss,Wss (F3),(v1) | vminsd Vsd,Hsd,Wsd (F2),(v1) 5e: vdivps Vps,Hps,Wps | vdivpd Vpd,Hpd,Wpd (66) | vdivss Vss,Hss,Wss (F3),(v1) | vdivsd Vsd,Hsd,Wsd (F2),(v1) @@ -447,7 +452,7 @@ AVXcode: 1 6c: vpunpcklqdq Vx,Hx,Wx (66),(v1) 6d: vpunpckhqdq Vx,Hx,Wx (66),(v1) 6e: movd/q Pd,Ey | vmovd/q Vy,Ey (66),(v1) -6f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqu Vx,Wx (F3) +6f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqa32/64 Vx,Wx (66),(evo) | vmovdqu Vx,Wx (F3) | vmovdqu32/64 Vx,Wx (F3),(evo) | vmovdqu8/16 Vx,Wx (F2),(ev) # 0x0f 0x70-0x7f 70: pshufw Pq,Qq,Ib | vpshufd Vx,Wx,Ib (66),(v1) | vpshufhw Vx,Wx,Ib (F3),(v1) | vpshuflw Vx,Wx,Ib (F2),(v1) 71: Grp12 (1A) @@ -458,14 +463,14 @@ AVXcode: 1 76: pcmpeqd Pq,Qq | vpcmpeqd Vx,Hx,Wx (66),(v1) # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX. 77: emms | vzeroupper | vzeroall -78: VMREAD Ey,Gy -79: VMWRITE Gy,Ey -7a: -7b: +78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) +79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) +7a: vcvtudq2pd/uqq2pd Vpd,Wx (F3),(ev) | vcvtudq2ps/uqq2ps Vpd,Wx (F2),(ev) | vcvttps2qq/pd2qq Vx,Wx (66),(ev) +7b: vcvtusi2sd Vpd,Hpd,Ev (F2),(ev) | vcvtusi2ss Vps,Hps,Ev (F3),(ev) | vcvtps2qq/pd2qq Vx,Wx (66),(ev) 7c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2) 7d: vhsubpd Vpd,Hpd,Wpd (66) | vhsubps Vps,Hps,Wps (F2) 7e: movd/q Ey,Pd | vmovd/q Ey,Vy (66),(v1) | vmovq Vq,Wq (F3),(v1) -7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqu Wx,Vx (F3) +7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev) # 0x0f 0x80-0x8f # Note: "forced64" is Intel CPU behavior (see comment about CALL insn). 80: JO Jz (f64) @@ -485,16 +490,16 @@ AVXcode: 1 8e: JLE/JNG Jz (f64) 8f: JNLE/JG Jz (f64) # 0x0f 0x90-0x9f -90: SETO Eb -91: SETNO Eb -92: SETB/C/NAE Eb -93: SETAE/NB/NC Eb +90: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66) +91: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66) +92: SETB/C/NAE Eb | kmovw Vk,Rv | kmovb Vk,Rv (66) | kmovq/d Vk,Rv (F2) +93: SETAE/NB/NC Eb | kmovw Gv,Uk | kmovb Gv,Uk (66) | kmovq/d Gv,Uk (F2) 94: SETE/Z Eb 95: SETNE/NZ Eb 96: SETBE/NA Eb 97: SETA/NBE Eb -98: SETS Eb -99: SETNS Eb +98: SETS Eb | kortestw/q Vk,Uk | kortestb/d Vk,Uk (66) +99: SETNS Eb | ktestw/q Vk,Uk | ktestb/d Vk,Uk (66) 9a: SETP/PE Eb 9b: SETNP/PO Eb 9c: SETL/NGE Eb @@ -564,11 +569,11 @@ d7: pmovmskb Gd,Nq | vpmovmskb Gd,Ux (66),(v1) d8: psubusb Pq,Qq | vpsubusb Vx,Hx,Wx (66),(v1) d9: psubusw Pq,Qq | vpsubusw Vx,Hx,Wx (66),(v1) da: pminub Pq,Qq | vpminub Vx,Hx,Wx (66),(v1) -db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1) +db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1) | vpandd/q Vx,Hx,Wx (66),(evo) dc: paddusb Pq,Qq | vpaddusb Vx,Hx,Wx (66),(v1) dd: paddusw Pq,Qq | vpaddusw Vx,Hx,Wx (66),(v1) de: pmaxub Pq,Qq | vpmaxub Vx,Hx,Wx (66),(v1) -df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1) +df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1) | vpandnd/q Vx,Hx,Wx (66),(evo) # 0x0f 0xe0-0xef e0: pavgb Pq,Qq | vpavgb Vx,Hx,Wx (66),(v1) e1: psraw Pq,Qq | vpsraw Vx,Hx,Wx (66),(v1) @@ -576,16 +581,16 @@ e2: psrad Pq,Qq | vpsrad Vx,Hx,Wx (66),(v1) e3: pavgw Pq,Qq | vpavgw Vx,Hx,Wx (66),(v1) e4: pmulhuw Pq,Qq | vpmulhuw Vx,Hx,Wx (66),(v1) e5: pmulhw Pq,Qq | vpmulhw Vx,Hx,Wx (66),(v1) -e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtpd2dq Vx,Wpd (F2) +e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtdq2pd/qq2pd Vx,Wdq (F3),(evo) | vcvtpd2dq Vx,Wpd (F2) e7: movntq Mq,Pq | vmovntdq Mx,Vx (66) e8: psubsb Pq,Qq | vpsubsb Vx,Hx,Wx (66),(v1) e9: psubsw Pq,Qq | vpsubsw Vx,Hx,Wx (66),(v1) ea: pminsw Pq,Qq | vpminsw Vx,Hx,Wx (66),(v1) -eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1) +eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1) | vpord/q Vx,Hx,Wx (66),(evo) ec: paddsb Pq,Qq | vpaddsb Vx,Hx,Wx (66),(v1) ed: paddsw Pq,Qq | vpaddsw Vx,Hx,Wx (66),(v1) ee: pmaxsw Pq,Qq | vpmaxsw Vx,Hx,Wx (66),(v1) -ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1) +ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1) | vpxord/q Vx,Hx,Wx (66),(evo) # 0x0f 0xf0-0xff f0: vlddqu Vx,Mx (F2) f1: psllw Pq,Qq | vpsllw Vx,Hx,Wx (66),(v1) @@ -626,81 +631,105 @@ AVXcode: 2 0e: vtestps Vx,Wx (66),(v) 0f: vtestpd Vx,Wx (66),(v) # 0x0f 0x38 0x10-0x1f -10: pblendvb Vdq,Wdq (66) -11: -12: -13: vcvtph2ps Vx,Wx (66),(v) -14: blendvps Vdq,Wdq (66) -15: blendvpd Vdq,Wdq (66) -16: vpermps Vqq,Hqq,Wqq (66),(v) +10: pblendvb Vdq,Wdq (66) | vpsrlvw Vx,Hx,Wx (66),(evo) | vpmovuswb Wx,Vx (F3),(ev) +11: vpmovusdb Wx,Vd (F3),(ev) | vpsravw Vx,Hx,Wx (66),(ev) +12: vpmovusqb Wx,Vq (F3),(ev) | vpsllvw Vx,Hx,Wx (66),(ev) +13: vcvtph2ps Vx,Wx (66),(v) | vpmovusdw Wx,Vd (F3),(ev) +14: blendvps Vdq,Wdq (66) | vpmovusqw Wx,Vq (F3),(ev) | vprorvd/q Vx,Hx,Wx (66),(evo) +15: blendvpd Vdq,Wdq (66) | vpmovusqd Wx,Vq (F3),(ev) | vprolvd/q Vx,Hx,Wx (66),(evo) +16: vpermps Vqq,Hqq,Wqq (66),(v) | vpermps/d Vqq,Hqq,Wqq (66),(evo) 17: vptest Vx,Wx (66) 18: vbroadcastss Vx,Wd (66),(v) -19: vbroadcastsd Vqq,Wq (66),(v) -1a: vbroadcastf128 Vqq,Mdq (66),(v) -1b: +19: vbroadcastsd Vqq,Wq (66),(v) | vbroadcastf32x2 Vqq,Wq (66),(evo) +1a: vbroadcastf128 Vqq,Mdq (66),(v) | vbroadcastf32x4/64x2 Vqq,Wq (66),(evo) +1b: vbroadcastf32x8/64x4 Vqq,Mdq (66),(ev) 1c: pabsb Pq,Qq | vpabsb Vx,Wx (66),(v1) 1d: pabsw Pq,Qq | vpabsw Vx,Wx (66),(v1) 1e: pabsd Pq,Qq | vpabsd Vx,Wx (66),(v1) -1f: +1f: vpabsq Vx,Wx (66),(ev) # 0x0f 0x38 0x20-0x2f -20: vpmovsxbw Vx,Ux/Mq (66),(v1) -21: vpmovsxbd Vx,Ux/Md (66),(v1) -22: vpmovsxbq Vx,Ux/Mw (66),(v1) -23: vpmovsxwd Vx,Ux/Mq (66),(v1) -24: vpmovsxwq Vx,Ux/Md (66),(v1) -25: vpmovsxdq Vx,Ux/Mq (66),(v1) -26: -27: -28: vpmuldq Vx,Hx,Wx (66),(v1) -29: vpcmpeqq Vx,Hx,Wx (66),(v1) -2a: vmovntdqa Vx,Mx (66),(v1) +20: vpmovsxbw Vx,Ux/Mq (66),(v1) | vpmovswb Wx,Vx (F3),(ev) +21: vpmovsxbd Vx,Ux/Md (66),(v1) | vpmovsdb Wx,Vd (F3),(ev) +22: vpmovsxbq Vx,Ux/Mw (66),(v1) | vpmovsqb Wx,Vq (F3),(ev) +23: vpmovsxwd Vx,Ux/Mq (66),(v1) | vpmovsdw Wx,Vd (F3),(ev) +24: vpmovsxwq Vx,Ux/Md (66),(v1) | vpmovsqw Wx,Vq (F3),(ev) +25: vpmovsxdq Vx,Ux/Mq (66),(v1) | vpmovsqd Wx,Vq (F3),(ev) +26: vptestmb/w Vk,Hx,Wx (66),(ev) | vptestnmb/w Vk,Hx,Wx (F3),(ev) +27: vptestmd/q Vk,Hx,Wx (66),(ev) | vptestnmd/q Vk,Hx,Wx (F3),(ev) +28: vpmuldq Vx,Hx,Wx (66),(v1) | vpmovm2b/w Vx,Uk (F3),(ev) +29: vpcmpeqq Vx,Hx,Wx (66),(v1) | vpmovb2m/w2m Vk,Ux (F3),(ev) +2a: vmovntdqa Vx,Mx (66),(v1) | vpbroadcastmb2q Vx,Uk (F3),(ev) 2b: vpackusdw Vx,Hx,Wx (66),(v1) -2c: vmaskmovps Vx,Hx,Mx (66),(v) -2d: vmaskmovpd Vx,Hx,Mx (66),(v) +2c: vmaskmovps Vx,Hx,Mx (66),(v) | vscalefps/d Vx,Hx,Wx (66),(evo) +2d: vmaskmovpd Vx,Hx,Mx (66),(v) | vscalefss/d Vx,Hx,Wx (66),(evo) 2e: vmaskmovps Mx,Hx,Vx (66),(v) 2f: vmaskmovpd Mx,Hx,Vx (66),(v) # 0x0f 0x38 0x30-0x3f -30: vpmovzxbw Vx,Ux/Mq (66),(v1) -31: vpmovzxbd Vx,Ux/Md (66),(v1) -32: vpmovzxbq Vx,Ux/Mw (66),(v1) -33: vpmovzxwd Vx,Ux/Mq (66),(v1) -34: vpmovzxwq Vx,Ux/Md (66),(v1) -35: vpmovzxdq Vx,Ux/Mq (66),(v1) -36: vpermd Vqq,Hqq,Wqq (66),(v) +30: vpmovzxbw Vx,Ux/Mq (66),(v1) | vpmovwb Wx,Vx (F3),(ev) +31: vpmovzxbd Vx,Ux/Md (66),(v1) | vpmovdb Wx,Vd (F3),(ev) +32: vpmovzxbq Vx,Ux/Mw (66),(v1) | vpmovqb Wx,Vq (F3),(ev) +33: vpmovzxwd Vx,Ux/Mq (66),(v1) | vpmovdw Wx,Vd (F3),(ev) +34: vpmovzxwq Vx,Ux/Md (66),(v1) | vpmovqw Wx,Vq (F3),(ev) +35: vpmovzxdq Vx,Ux/Mq (66),(v1) | vpmovqd Wx,Vq (F3),(ev) +36: vpermd Vqq,Hqq,Wqq (66),(v) | vpermd/q Vqq,Hqq,Wqq (66),(evo) 37: vpcmpgtq Vx,Hx,Wx (66),(v1) -38: vpminsb Vx,Hx,Wx (66),(v1) -39: vpminsd Vx,Hx,Wx (66),(v1) -3a: vpminuw Vx,Hx,Wx (66),(v1) -3b: vpminud Vx,Hx,Wx (66),(v1) +38: vpminsb Vx,Hx,Wx (66),(v1) | vpmovm2d/q Vx,Uk (F3),(ev) +39: vpminsd Vx,Hx,Wx (66),(v1) | vpminsd/q Vx,Hx,Wx (66),(evo) | vpmovd2m/q2m Vk,Ux (F3),(ev) +3a: vpminuw Vx,Hx,Wx (66),(v1) | vpbroadcastmw2d Vx,Uk (F3),(ev) +3b: vpminud Vx,Hx,Wx (66),(v1) | vpminud/q Vx,Hx,Wx (66),(evo) 3c: vpmaxsb Vx,Hx,Wx (66),(v1) -3d: vpmaxsd Vx,Hx,Wx (66),(v1) +3d: vpmaxsd Vx,Hx,Wx (66),(v1) | vpmaxsd/q Vx,Hx,Wx (66),(evo) 3e: vpmaxuw Vx,Hx,Wx (66),(v1) -3f: vpmaxud Vx,Hx,Wx (66),(v1) +3f: vpmaxud Vx,Hx,Wx (66),(v1) | vpmaxud/q Vx,Hx,Wx (66),(evo) # 0x0f 0x38 0x40-0x8f -40: vpmulld Vx,Hx,Wx (66),(v1) +40: vpmulld Vx,Hx,Wx (66),(v1) | vpmulld/q Vx,Hx,Wx (66),(evo) 41: vphminposuw Vdq,Wdq (66),(v1) -42: -43: -44: +42: vgetexpps/d Vx,Wx (66),(ev) +43: vgetexpss/d Vx,Hx,Wx (66),(ev) +44: vplzcntd/q Vx,Wx (66),(ev) 45: vpsrlvd/q Vx,Hx,Wx (66),(v) -46: vpsravd Vx,Hx,Wx (66),(v) +46: vpsravd Vx,Hx,Wx (66),(v) | vpsravd/q Vx,Hx,Wx (66),(evo) 47: vpsllvd/q Vx,Hx,Wx (66),(v) -# Skip 0x48-0x57 +# Skip 0x48-0x4b +4c: vrcp14ps/d Vpd,Wpd (66),(ev) +4d: vrcp14ss/d Vsd,Hpd,Wsd (66),(ev) +4e: vrsqrt14ps/d Vpd,Wpd (66),(ev) +4f: vrsqrt14ss/d Vsd,Hsd,Wsd (66),(ev) +# Skip 0x50-0x57 58: vpbroadcastd Vx,Wx (66),(v) -59: vpbroadcastq Vx,Wx (66),(v) -5a: vbroadcasti128 Vqq,Mdq (66),(v) -# Skip 0x5b-0x77 +59: vpbroadcastq Vx,Wx (66),(v) | vbroadcasti32x2 Vx,Wx (66),(evo) +5a: vbroadcasti128 Vqq,Mdq (66),(v) | vbroadcasti32x4/64x2 Vx,Wx (66),(evo) +5b: vbroadcasti32x8/64x4 Vqq,Mdq (66),(ev) +# Skip 0x5c-0x63 +64: vpblendmd/q Vx,Hx,Wx (66),(ev) +65: vblendmps/d Vx,Hx,Wx (66),(ev) +66: vpblendmb/w Vx,Hx,Wx (66),(ev) +# Skip 0x67-0x74 +75: vpermi2b/w Vx,Hx,Wx (66),(ev) +76: vpermi2d/q Vx,Hx,Wx (66),(ev) +77: vpermi2ps/d Vx,Hx,Wx (66),(ev) 78: vpbroadcastb Vx,Wx (66),(v) 79: vpbroadcastw Vx,Wx (66),(v) -# Skip 0x7a-0x7f +7a: vpbroadcastb Vx,Rv (66),(ev) +7b: vpbroadcastw Vx,Rv (66),(ev) +7c: vpbroadcastd/q Vx,Rv (66),(ev) +7d: vpermt2b/w Vx,Hx,Wx (66),(ev) +7e: vpermt2d/q Vx,Hx,Wx (66),(ev) +7f: vpermt2ps/d Vx,Hx,Wx (66),(ev) 80: INVEPT Gy,Mdq (66) 81: INVPID Gy,Mdq (66) 82: INVPCID Gy,Mdq (66) +83: vpmultishiftqb Vx,Hx,Wx (66),(ev) +88: vexpandps/d Vpd,Wpd (66),(ev) +89: vpexpandd/q Vx,Wx (66),(ev) +8a: vcompressps/d Wx,Vx (66),(ev) +8b: vpcompressd/q Wx,Vx (66),(ev) 8c: vpmaskmovd/q Vx,Hx,Mx (66),(v) +8d: vpermb/w Vx,Hx,Wx (66),(ev) 8e: vpmaskmovd/q Mx,Vx,Hx (66),(v) # 0x0f 0x38 0x90-0xbf (FMA) -90: vgatherdd/q Vx,Hx,Wx (66),(v) -91: vgatherqd/q Vx,Hx,Wx (66),(v) +90: vgatherdd/q Vx,Hx,Wx (66),(v) | vpgatherdd/q Vx,Wx (66),(evo) +91: vgatherqd/q Vx,Hx,Wx (66),(v) | vpgatherqd/q Vx,Wx (66),(evo) 92: vgatherdps/d Vx,Hx,Wx (66),(v) 93: vgatherqps/d Vx,Hx,Wx (66),(v) 94: @@ -715,6 +744,10 @@ AVXcode: 2 9d: vfnmadd132ss/d Vx,Hx,Wx (66),(v),(v1) 9e: vfnmsub132ps/d Vx,Hx,Wx (66),(v) 9f: vfnmsub132ss/d Vx,Hx,Wx (66),(v),(v1) +a0: vpscatterdd/q Wx,Vx (66),(ev) +a1: vpscatterqd/q Wx,Vx (66),(ev) +a2: vscatterdps/d Wx,Vx (66),(ev) +a3: vscatterqps/d Wx,Vx (66),(ev) a6: vfmaddsub213ps/d Vx,Hx,Wx (66),(v) a7: vfmsubadd213ps/d Vx,Hx,Wx (66),(v) a8: vfmadd213ps/d Vx,Hx,Wx (66),(v) @@ -725,6 +758,8 @@ ac: vfnmadd213ps/d Vx,Hx,Wx (66),(v) ad: vfnmadd213ss/d Vx,Hx,Wx (66),(v),(v1) ae: vfnmsub213ps/d Vx,Hx,Wx (66),(v) af: vfnmsub213ss/d Vx,Hx,Wx (66),(v),(v1) +b4: vpmadd52luq Vx,Hx,Wx (66),(ev) +b5: vpmadd52huq Vx,Hx,Wx (66),(ev) b6: vfmaddsub231ps/d Vx,Hx,Wx (66),(v) b7: vfmsubadd231ps/d Vx,Hx,Wx (66),(v) b8: vfmadd231ps/d Vx,Hx,Wx (66),(v) @@ -736,12 +771,15 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1) be: vfnmsub231ps/d Vx,Hx,Wx (66),(v) bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1) # 0x0f 0x38 0xc0-0xff -c8: sha1nexte Vdq,Wdq +c4: vpconflictd/q Vx,Wx (66),(ev) +c6: Grp18 (1A) +c7: Grp19 (1A) +c8: sha1nexte Vdq,Wdq | vexp2ps/d Vx,Wx (66),(ev) c9: sha1msg1 Vdq,Wdq -ca: sha1msg2 Vdq,Wdq -cb: sha256rnds2 Vdq,Wdq -cc: sha256msg1 Vdq,Wdq -cd: sha256msg2 Vdq,Wdq +ca: sha1msg2 Vdq,Wdq | vrcp28ps/d Vx,Wx (66),(ev) +cb: sha256rnds2 Vdq,Wdq | vrcp28ss/d Vx,Hx,Wx (66),(ev) +cc: sha256msg1 Vdq,Wdq | vrsqrt28ps/d Vx,Wx (66),(ev) +cd: sha256msg2 Vdq,Wdq | vrsqrt28ss/d Vx,Hx,Wx (66),(ev) db: VAESIMC Vdq,Wdq (66),(v1) dc: VAESENC Vdq,Hdq,Wdq (66),(v1) dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1) @@ -763,15 +801,15 @@ AVXcode: 3 00: vpermq Vqq,Wqq,Ib (66),(v) 01: vpermpd Vqq,Wqq,Ib (66),(v) 02: vpblendd Vx,Hx,Wx,Ib (66),(v) -03: +03: valignd/q Vx,Hx,Wx,Ib (66),(ev) 04: vpermilps Vx,Wx,Ib (66),(v) 05: vpermilpd Vx,Wx,Ib (66),(v) 06: vperm2f128 Vqq,Hqq,Wqq,Ib (66),(v) 07: -08: vroundps Vx,Wx,Ib (66) -09: vroundpd Vx,Wx,Ib (66) -0a: vroundss Vss,Wss,Ib (66),(v1) -0b: vroundsd Vsd,Wsd,Ib (66),(v1) +08: vroundps Vx,Wx,Ib (66) | vrndscaleps Vx,Wx,Ib (66),(evo) +09: vroundpd Vx,Wx,Ib (66) | vrndscalepd Vx,Wx,Ib (66),(evo) +0a: vroundss Vss,Wss,Ib (66),(v1) | vrndscaless Vx,Hx,Wx,Ib (66),(evo) +0b: vroundsd Vsd,Wsd,Ib (66),(v1) | vrndscalesd Vx,Hx,Wx,Ib (66),(evo) 0c: vblendps Vx,Hx,Wx,Ib (66) 0d: vblendpd Vx,Hx,Wx,Ib (66) 0e: vpblendw Vx,Hx,Wx,Ib (66),(v1) @@ -780,26 +818,51 @@ AVXcode: 3 15: vpextrw Rd/Mw,Vdq,Ib (66),(v1) 16: vpextrd/q Ey,Vdq,Ib (66),(v1) 17: vextractps Ed,Vdq,Ib (66),(v1) -18: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v) -19: vextractf128 Wdq,Vqq,Ib (66),(v) +18: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v) | vinsertf32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo) +19: vextractf128 Wdq,Vqq,Ib (66),(v) | vextractf32x4/64x2 Wdq,Vqq,Ib (66),(evo) +1a: vinsertf32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev) +1b: vextractf32x8/64x4 Wdq,Vqq,Ib (66),(ev) 1d: vcvtps2ph Wx,Vx,Ib (66),(v) +1e: vpcmpud/q Vk,Hd,Wd,Ib (66),(ev) +1f: vpcmpd/q Vk,Hd,Wd,Ib (66),(ev) 20: vpinsrb Vdq,Hdq,Ry/Mb,Ib (66),(v1) 21: vinsertps Vdq,Hdq,Udq/Md,Ib (66),(v1) 22: vpinsrd/q Vdq,Hdq,Ey,Ib (66),(v1) -38: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v) -39: vextracti128 Wdq,Vqq,Ib (66),(v) +23: vshuff32x4/64x2 Vx,Hx,Wx,Ib (66),(ev) +25: vpternlogd/q Vx,Hx,Wx,Ib (66),(ev) +26: vgetmantps/d Vx,Wx,Ib (66),(ev) +27: vgetmantss/d Vx,Hx,Wx,Ib (66),(ev) +30: kshiftrb/w Vk,Uk,Ib (66),(v) +31: kshiftrd/q Vk,Uk,Ib (66),(v) +32: kshiftlb/w Vk,Uk,Ib (66),(v) +33: kshiftld/q Vk,Uk,Ib (66),(v) +38: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v) | vinserti32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo) +39: vextracti128 Wdq,Vqq,Ib (66),(v) | vextracti32x4/64x2 Wdq,Vqq,Ib (66),(evo) +3a: vinserti32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev) +3b: vextracti32x8/64x4 Wdq,Vqq,Ib (66),(ev) +3e: vpcmpub/w Vk,Hk,Wx,Ib (66),(ev) +3f: vpcmpb/w Vk,Hk,Wx,Ib (66),(ev) 40: vdpps Vx,Hx,Wx,Ib (66) 41: vdppd Vdq,Hdq,Wdq,Ib (66),(v1) -42: vmpsadbw Vx,Hx,Wx,Ib (66),(v1) +42: vmpsadbw Vx,Hx,Wx,Ib (66),(v1) | vdbpsadbw Vx,Hx,Wx,Ib (66),(evo) +43: vshufi32x4/64x2 Vx,Hx,Wx,Ib (66),(ev) 44: vpclmulqdq Vdq,Hdq,Wdq,Ib (66),(v1) 46: vperm2i128 Vqq,Hqq,Wqq,Ib (66),(v) 4a: vblendvps Vx,Hx,Wx,Lx (66),(v) 4b: vblendvpd Vx,Hx,Wx,Lx (66),(v) 4c: vpblendvb Vx,Hx,Wx,Lx (66),(v1) +50: vrangeps/d Vx,Hx,Wx,Ib (66),(ev) +51: vrangess/d Vx,Hx,Wx,Ib (66),(ev) +54: vfixupimmps/d Vx,Hx,Wx,Ib (66),(ev) +55: vfixupimmss/d Vx,Hx,Wx,Ib (66),(ev) +56: vreduceps/d Vx,Wx,Ib (66),(ev) +57: vreducess/d Vx,Hx,Wx,Ib (66),(ev) 60: vpcmpestrm Vdq,Wdq,Ib (66),(v1) 61: vpcmpestri Vdq,Wdq,Ib (66),(v1) 62: vpcmpistrm Vdq,Wdq,Ib (66),(v1) 63: vpcmpistri Vdq,Wdq,Ib (66),(v1) +66: vfpclassps/d Vk,Wx,Ib (66),(ev) +67: vfpclassss/d Vk,Wx,Ib (66),(ev) cc: sha1rnds4 Vdq,Wdq,Ib df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1) f0: RORX Gy,Ey,Ib (F2),(v) @@ -927,8 +990,10 @@ GrpTable: Grp12 EndTable GrpTable: Grp13 +0: vprord/q Hx,Wx,Ib (66),(ev) +1: vprold/q Hx,Wx,Ib (66),(ev) 2: psrld Nq,Ib (11B) | vpsrld Hx,Ux,Ib (66),(11B),(v1) -4: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1) +4: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1) | vpsrad/q Hx,Ux,Ib (66),(evo) 6: pslld Nq,Ib (11B) | vpslld Hx,Ux,Ib (66),(11B),(v1) EndTable @@ -963,6 +1028,20 @@ GrpTable: Grp17 3: BLSI By,Ey (v) EndTable +GrpTable: Grp18 +1: vgatherpf0dps/d Wx (66),(ev) +2: vgatherpf1dps/d Wx (66),(ev) +5: vscatterpf0dps/d Wx (66),(ev) +6: vscatterpf1dps/d Wx (66),(ev) +EndTable + +GrpTable: Grp19 +1: vgatherpf0qps/d Wx (66),(ev) +2: vgatherpf1qps/d Wx (66),(ev) +5: vscatterpf0qps/d Wx (66),(ev) +6: vscatterpf1qps/d Wx (66),(ev) +EndTable + # AMD's Prefetch Group GrpTable: GrpP 0: PREFETCH diff --git a/arch/x86/tools/gen-insn-attr-x86.awk b/arch/x86/tools/gen-insn-attr-x86.awk index 093a892..a3d2c62 100644 --- a/arch/x86/tools/gen-insn-attr-x86.awk +++ b/arch/x86/tools/gen-insn-attr-x86.awk @@ -72,12 +72,14 @@ BEGIN { lprefix_expr = "\\((66|F2|F3)\\)" max_lprefix = 4 - # All opcodes starting with lower-case 'v' or with (v1) superscript + # All opcodes starting with lower-case 'v', 'k' or with (v1) superscript # accepts VEX prefix - vexok_opcode_expr = "^v.*" + vexok_opcode_expr = "^[vk].*" vexok_expr = "\\(v1\\)" # All opcodes with (v) superscript supports *only* VEX prefix vexonly_expr = "\\(v\\)" + # All opcodes with (ev) superscript supports *only* EVEX prefix + evexonly_expr = "\\(ev\\)" prefix_expr = "\\(Prefix\\)" prefix_num["Operand-Size"] = "INAT_PFX_OPNDSZ" @@ -95,6 +97,7 @@ BEGIN { prefix_num["Address-Size"] = "INAT_PFX_ADDRSZ" prefix_num["VEX+1byte"] = "INAT_PFX_VEX2" prefix_num["VEX+2byte"] = "INAT_PFX_VEX3" + prefix_num["EVEX"] = "INAT_PFX_EVEX" clear_vars() } @@ -319,7 +322,9 @@ function convert_operands(count,opnd, i,j,imm,mod) flags = add_flags(flags, "INAT_MODRM") # check VEX codes - if (match(ext, vexonly_expr)) + if (match(ext, evexonly_expr)) + flags = add_flags(flags, "INAT_VEXOK | INAT_EVEXONLY") + else if (match(ext, vexonly_expr)) flags = add_flags(flags, "INAT_VEXOK | INAT_VEXONLY") else if (match(ext, vexok_expr) || match(opcode, vexok_opcode_expr)) flags = add_flags(flags, "INAT_VEXOK") ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder 2016-07-20 8:30 ` [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder Adrian Hunter 2016-07-25 18:08 ` [tip:perf/core] " tip-bot for Adrian Hunter @ 2025-11-30 16:05 ` Borislav Petkov 2025-12-01 11:25 ` Borislav Petkov 1 sibling, 1 reply; 18+ messages in thread From: Borislav Petkov @ 2025-11-30 16:05 UTC (permalink / raw) To: Adrian Hunter, Masami Hiramatsu Cc: linux-kernel, Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML Resurrecting a very old thread... On Wed, Jul 20, 2016 at 11:30:35AM +0300, Adrian Hunter wrote: > Add support for Intel's AVX-512 instructions to the instruction decoder. > > AVX-512 instructions are documented in Intel Architecture Instruction Set > Extensions Programming Reference (February 2016). > > AVX-512 instructions are identified by a EVEX prefix which, for the purpose > of instruction decoding, can be treated as though it were a 4-byte VEX > prefix. > > Existing instructions which can now accept an EVEX prefix need not be > further annotated in the op code map (x86-opcode-map.txt). In the case of > new instructions, the op code map is updated accordingly. > > Also add associated Mask Instructions that are used to manipulate mask > registers used in AVX-512 instructions. > > 'perf tools' instruction decoder is updated in a subsequent patch. And a > representative set of instructions is added to the perf tools new > instructions test in a subsequent patch. > > Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> > --- > arch/x86/include/asm/inat.h | 17 ++- > arch/x86/include/asm/insn.h | 12 +- > arch/x86/lib/insn.c | 18 ++- > arch/x86/lib/x86-opcode-map.txt | 263 +++++++++++++++++++++++------------ > arch/x86/tools/gen-insn-attr-x86.awk | 11 +- > 5 files changed, 220 insertions(+), 101 deletions(-) > > +78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) > +79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) This is all fine and dandy but those (ev*) flags cause the escape table to have INAT_EVEXONLY as a flag: const insn_attr_t inat_escape_table_1_1[INAT_OPCODE_TABLE_SIZE] = { ... [0x79] = INAT_MODRM | INAT_VEXOK | INAT_EVEXONLY, }; except that that opcode is not EVEX only. Intel's VMREAD and VMWRITE are *not* EVEX insns and AMD has there EXTRQ and INSERTQ with prefixes 66 and F2 respectively which are SSE4a and both are not EVEX. The VMREAD and VMWRITE decoding happens to work out by pure chance because those are without a prefix and the check for prefix id in inat_get_escape_attribute() happens to not select that escape table. So the first thing that comes to mind is excluding opcodes like 0x79 which can be mixed type from that inat_must_vex() enforcement...? Masami, any other ideas? -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder 2025-11-30 16:05 ` [PATCH V2 2/4] " Borislav Petkov @ 2025-12-01 11:25 ` Borislav Petkov 2025-12-01 18:15 ` Adrian Hunter 0 siblings, 1 reply; 18+ messages in thread From: Borislav Petkov @ 2025-12-01 11:25 UTC (permalink / raw) To: Adrian Hunter, Masami Hiramatsu Cc: linux-kernel, Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML On Sun, Nov 30, 2025 at 05:05:28PM +0100, Borislav Petkov wrote: > Resurrecting a very old thread... > > On Wed, Jul 20, 2016 at 11:30:35AM +0300, Adrian Hunter wrote: > > Add support for Intel's AVX-512 instructions to the instruction decoder. > > > > AVX-512 instructions are documented in Intel Architecture Instruction Set > > Extensions Programming Reference (February 2016). > > > > AVX-512 instructions are identified by a EVEX prefix which, for the purpose > > of instruction decoding, can be treated as though it were a 4-byte VEX > > prefix. > > > > Existing instructions which can now accept an EVEX prefix need not be > > further annotated in the op code map (x86-opcode-map.txt). In the case of > > new instructions, the op code map is updated accordingly. > > > > Also add associated Mask Instructions that are used to manipulate mask > > registers used in AVX-512 instructions. > > > > 'perf tools' instruction decoder is updated in a subsequent patch. And a > > representative set of instructions is added to the perf tools new > > instructions test in a subsequent patch. > > > > Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> > > --- > > arch/x86/include/asm/inat.h | 17 ++- > > arch/x86/include/asm/insn.h | 12 +- > > arch/x86/lib/insn.c | 18 ++- > > arch/x86/lib/x86-opcode-map.txt | 263 +++++++++++++++++++++++------------ > > arch/x86/tools/gen-insn-attr-x86.awk | 11 +- > > 5 files changed, 220 insertions(+), 101 deletions(-) > > > > +78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) > > +79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) > > This is all fine and dandy but those (ev*) flags cause the escape table to > have INAT_EVEXONLY as a flag: > > const insn_attr_t inat_escape_table_1_1[INAT_OPCODE_TABLE_SIZE] = { > ... > > [0x79] = INAT_MODRM | INAT_VEXOK | INAT_EVEXONLY, > > }; > > except that that opcode is not EVEX only. Intel's VMREAD and VMWRITE are *not* > EVEX insns and AMD has there EXTRQ and INSERTQ with prefixes 66 and F2 > respectively which are SSE4a and both are not EVEX. > > The VMREAD and VMWRITE decoding happens to work out by pure chance because > those are without a prefix and the check for prefix id in > inat_get_escape_attribute() happens to not select that escape table. > > So the first thing that comes to mind is excluding opcodes like 0x79 which can > be mixed type from that inat_must_vex() enforcement...? > > Masami, any other ideas? This hack seems to do the trick. We probably should take a look at all the insn tables and if there are more opcodes like that, to turn the mixed bool below into a proper flag: diff --git a/tools/arch/x86/lib/insn.c b/tools/arch/x86/lib/insn.c index 1d1c57c74d1f..e3216da11a7c 100644 --- a/tools/arch/x86/lib/insn.c +++ b/tools/arch/x86/lib/insn.c @@ -276,6 +276,7 @@ int insn_get_prefixes(struct insn *insn) int insn_get_opcode(struct insn *insn) { struct insn_field *opcode = &insn->opcode; + bool mixed = false; int pfx_id, ret; insn_byte_t op; @@ -348,13 +359,25 @@ int insn_get_opcode(struct insn *insn) while (inat_is_escape(insn->attr)) { /* Get escaped opcode */ op = get_next(insn_byte_t, insn); + opcode->bytes[opcode->nbytes++] = op; pfx_id = insn_last_prefix_id(insn); + + printf("%s: escaped op: 0x%x, pfx_id (insn table: none, 66, f3, f2): 0x%x, attr: 0x%x\n", + __func__, op, pfx_id, insn->attr); + insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr); + + printf("got attr: 0x%x\n", insn->attr); } - if (inat_must_vex(insn->attr)) { + mixed = (opcode->bytes[0] == 0xf) && (opcode->bytes[1] == 0x79); + + printf("%s: must_vex, mixed: %d\n", __func__, mixed); + + if (inat_must_vex(insn->attr) && !mixed) { /* This instruction is bad */ + printf("%s: must_vex bad\n", __func__); insn->attr = 0; return -EINVAL; } diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index 0139b864ceef..d059c8e63bfe 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -474,7 +474,7 @@ AVXcode: 1 # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX. 77: emms | vzeroupper | vzeroall 78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) -79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) | EXTRQ +79: VMWRITE Gy,Ey | EXTRQ Vo,Uo (66) | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) 7a: vcvtudq2pd/uqq2pd Vpd,Wx (F3),(ev) | vcvtudq2ps/uqq2ps Vpd,Wx (F2),(ev) | vcvttps2qq/pd2qq Vx,Wx (66),(ev) 7b: vcvtusi2sd Vpd,Hpd,Ev (F2),(ev) | vcvtusi2ss Vps,Hps,Ev (F3),(ev) | vcvtps2qq/pd2qq Vx,Wx (66),(ev) 7c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2) and insn-sanity decodes properly: $ echo "66 0f 79 ca" | ./insn_sanity -vvv -i - Instruction = { .prefixes = { .value = 1711276134, bytes[] = {66, 0, 0, 66}, .got = 1, .nbytes = 1}, .rex_prefix = { .value = 0, bytes[] = {0, 0, 0, 0}, .got = 1, .nbytes = 0}, .vex_prefix = { .value = 0, bytes[] = {0, 0, 0, 0}, .got = 1, .nbytes = 0}, .opcode = { .value = 30991, bytes[] = {f, 79, 0, 0}, .got = 1, .nbytes = 2}, .modrm = { .value = 202, bytes[] = {ca, 0, 0, 0}, .got = 1, .nbytes = 1}, .sib = { .value = 0, bytes[] = {0, 0, 0, 0}, .got = 1, .nbytes = 0}, .displacement = { .value = 0, bytes[] = {0, 0, 0, 0}, .got = 1, .nbytes = 0}, .immediate1 = { .value = 0, bytes[] = {0, 0, 0, 0}, .got = 1, .nbytes = 0}, .immediate2 = { .value = 0, bytes[] = {0, 0, 0, 0}, .got = 0, .nbytes = 0}, .attr = 508000, .opnd_bytes = 2, .addr_bytes = 4, .length = 4, .x86_64 = 0, .kaddr = 0x7ffc7d62aed0} ./insn_sanity: success: Decoded and checked 1 given instructions with 0 errors (seed:0x0) -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder 2025-12-01 11:25 ` Borislav Petkov @ 2025-12-01 18:15 ` Adrian Hunter 2025-12-01 19:01 ` Borislav Petkov 0 siblings, 1 reply; 18+ messages in thread From: Adrian Hunter @ 2025-12-01 18:15 UTC (permalink / raw) To: Borislav Petkov, Masami Hiramatsu Cc: linux-kernel, Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML On 01/12/2025 13:25, Borislav Petkov wrote: > On Sun, Nov 30, 2025 at 05:05:28PM +0100, Borislav Petkov wrote: >> Resurrecting a very old thread... >> >> On Wed, Jul 20, 2016 at 11:30:35AM +0300, Adrian Hunter wrote: >>> Add support for Intel's AVX-512 instructions to the instruction decoder. >>> >>> AVX-512 instructions are documented in Intel Architecture Instruction Set >>> Extensions Programming Reference (February 2016). >>> >>> AVX-512 instructions are identified by a EVEX prefix which, for the purpose >>> of instruction decoding, can be treated as though it were a 4-byte VEX >>> prefix. >>> >>> Existing instructions which can now accept an EVEX prefix need not be >>> further annotated in the op code map (x86-opcode-map.txt). In the case of >>> new instructions, the op code map is updated accordingly. >>> >>> Also add associated Mask Instructions that are used to manipulate mask >>> registers used in AVX-512 instructions. >>> >>> 'perf tools' instruction decoder is updated in a subsequent patch. And a >>> representative set of instructions is added to the perf tools new >>> instructions test in a subsequent patch. >>> >>> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> >>> --- >>> arch/x86/include/asm/inat.h | 17 ++- >>> arch/x86/include/asm/insn.h | 12 +- >>> arch/x86/lib/insn.c | 18 ++- >>> arch/x86/lib/x86-opcode-map.txt | 263 +++++++++++++++++++++++------------ >>> arch/x86/tools/gen-insn-attr-x86.awk | 11 +- >>> 5 files changed, 220 insertions(+), 101 deletions(-) >>> >>> +78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) >>> +79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) >> >> This is all fine and dandy but those (ev*) flags cause the escape table to >> have INAT_EVEXONLY as a flag: >> >> const insn_attr_t inat_escape_table_1_1[INAT_OPCODE_TABLE_SIZE] = { >> ... >> >> [0x79] = INAT_MODRM | INAT_VEXOK | INAT_EVEXONLY, >> >> }; >> >> except that that opcode is not EVEX only. Intel's VMREAD and VMWRITE are *not* >> EVEX insns and AMD has there EXTRQ and INSERTQ with prefixes 66 and F2 >> respectively which are SSE4a and both are not EVEX. >> >> The VMREAD and VMWRITE decoding happens to work out by pure chance because >> those are without a prefix and the check for prefix id in >> inat_get_escape_attribute() happens to not select that escape table. >> >> So the first thing that comes to mind is excluding opcodes like 0x79 which can >> be mixed type from that inat_must_vex() enforcement...? >> >> Masami, any other ideas? > > This hack seems to do the trick. We probably should take a look at all the > insn tables and if there are more opcodes like that, to turn the mixed bool > below into a proper flag: > > > diff --git a/tools/arch/x86/lib/insn.c b/tools/arch/x86/lib/insn.c > index 1d1c57c74d1f..e3216da11a7c 100644 > --- a/tools/arch/x86/lib/insn.c > +++ b/tools/arch/x86/lib/insn.c > @@ -276,6 +276,7 @@ int insn_get_prefixes(struct insn *insn) > int insn_get_opcode(struct insn *insn) > { > struct insn_field *opcode = &insn->opcode; > + bool mixed = false; > int pfx_id, ret; > insn_byte_t op; > > @@ -348,13 +359,25 @@ int insn_get_opcode(struct insn *insn) > while (inat_is_escape(insn->attr)) { > /* Get escaped opcode */ > op = get_next(insn_byte_t, insn); > + > opcode->bytes[opcode->nbytes++] = op; > pfx_id = insn_last_prefix_id(insn); > + > + printf("%s: escaped op: 0x%x, pfx_id (insn table: none, 66, f3, f2): 0x%x, attr: 0x%x\n", > + __func__, op, pfx_id, insn->attr); > + > insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr); > + > + printf("got attr: 0x%x\n", insn->attr); > } > > - if (inat_must_vex(insn->attr)) { > + mixed = (opcode->bytes[0] == 0xf) && (opcode->bytes[1] == 0x79); > + > + printf("%s: must_vex, mixed: %d\n", __func__, mixed); > + > + if (inat_must_vex(insn->attr) && !mixed) { > /* This instruction is bad */ > + printf("%s: must_vex bad\n", __func__); > insn->attr = 0; > return -EINVAL; > } > diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt > index 0139b864ceef..d059c8e63bfe 100644 > --- a/tools/arch/x86/lib/x86-opcode-map.txt > +++ b/tools/arch/x86/lib/x86-opcode-map.txt > @@ -474,7 +474,7 @@ AVXcode: 1 > # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX. > 77: emms | vzeroupper | vzeroall > 78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) > -79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) | EXTRQ > +79: VMWRITE Gy,Ey | EXTRQ Vo,Uo (66) | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) EXTRQ Vo,Uo (66) has a mandatory 66 prefix like vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) so they end up on the same attribute table, but (ev) results in INAT_EVEXONLY which is unwanted. Changing that from (ev) to (evo) is probably all that is needed e.g. +79: VMWRITE Gy,Ey | EXTRQ Vo,Uo (66) | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(evo) ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder 2025-12-01 18:15 ` Adrian Hunter @ 2025-12-01 19:01 ` Borislav Petkov 2025-12-02 6:26 ` Adrian Hunter 0 siblings, 1 reply; 18+ messages in thread From: Borislav Petkov @ 2025-12-01 19:01 UTC (permalink / raw) To: Adrian Hunter Cc: Masami Hiramatsu, linux-kernel, Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML On Mon, Dec 01, 2025 at 08:15:19PM +0200, Adrian Hunter wrote: > EXTRQ Vo,Uo (66) has a mandatory 66 prefix like vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) so they end up on the same attribute table, but (ev) results in INAT_EVEXONLY which is unwanted. > > Changing that from (ev) to (evo) is probably all that is needed e.g. > > +79: VMWRITE Gy,Ey | EXTRQ Vo,Uo (66) | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(evo) > That still sounds to me like a hack: looking at the SDM, that thing: VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values *is* EVEX-only insn: EVEX.128.66.0F.W0 the "66" meaning in this case EVEX.pp which are the VEX.pp two bits with value 1b meaning there's an implied 66 legacy prefix. To make it more concrete, let's take an example from the binutils testsuite: 62 f1 7d 4f 79 f5[ ]*vcvtps2uqq zmm6\{k7\},ymm5 and that's basically: Extended VEctor prefiX: 0x62 P1: [R:1|X:1|B:1|R':1|rsv:0|mm:1] 0xf1 P2: [W:0|vvvv:0xf |rsv:1|pp:1] 0x7d P3: [z:0|L':1|L:0|b:0|V':1|aaa:7] 0x4f with the opcode 0x79 and EVEX.pp=1b, as expected. So there's no real 66 prefix there. But our opcode map says: "# Last Prefix Superscripts # - (66): the last prefix is 0x66" So we're using the marking (66) to mean both an explicit 66 legacy prefix and an implied *VEX.pp=1 66 prefix equivalence. So now the question is, why do the *VEX opcodes need that (66) marking at all? For operand sizing? Looking at our example insn VCVTPS2UQQ, I don't see any other encoding where 66 is not present. And there's nothing in the pseudo code either. So VEX.pp=1 is part of the encoding of that insn. So, that (66) there is not really the prefix ... Hmm? -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder 2025-12-01 19:01 ` Borislav Petkov @ 2025-12-02 6:26 ` Adrian Hunter 2025-12-02 10:47 ` Borislav Petkov 0 siblings, 1 reply; 18+ messages in thread From: Adrian Hunter @ 2025-12-02 6:26 UTC (permalink / raw) To: Borislav Petkov Cc: Masami Hiramatsu, linux-kernel, Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML On 01/12/2025 21:01, Borislav Petkov wrote: > On Mon, Dec 01, 2025 at 08:15:19PM +0200, Adrian Hunter wrote: >> EXTRQ Vo,Uo (66) has a mandatory 66 prefix like vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) so they end up on the same attribute table, but (ev) results in INAT_EVEXONLY which is unwanted. >> >> Changing that from (ev) to (evo) is probably all that is needed e.g. >> >> +79: VMWRITE Gy,Ey | EXTRQ Vo,Uo (66) | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(evo) >> > > That still sounds to me like a hack: looking at the SDM, that thing: > > VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed > Unsigned Quadword Integer Values > > *is* EVEX-only insn: > > EVEX.128.66.0F.W0 The instruction decoder is permissive in the sense that it cannot tell if an instruction is valid, only what its properties are assuming it is valid. There is no need to validate EVEX-only. ev->evo makes sense to allow for another instruction. > > the "66" meaning in this case EVEX.pp which are the VEX.pp two bits with value > 1b meaning there's an implied 66 legacy prefix. > > To make it more concrete, let's take an example from the binutils testsuite: > > 62 f1 7d 4f 79 f5[ ]*vcvtps2uqq zmm6\{k7\},ymm5 > > and that's basically: > > Extended VEctor prefiX: 0x62 > P1: [R:1|X:1|B:1|R':1|rsv:0|mm:1] 0xf1 > P2: [W:0|vvvv:0xf |rsv:1|pp:1] 0x7d > P3: [z:0|L':1|L:0|b:0|V':1|aaa:7] 0x4f > > with the opcode 0x79 and EVEX.pp=1b, as expected. > > So there's no real 66 prefix there. > > But our opcode map says: > > "# Last Prefix Superscripts > # - (66): the last prefix is 0x66" > > So we're using the marking (66) to mean both an explicit 66 legacy prefix and > an implied *VEX.pp=1 66 prefix equivalence. > > So now the question is, why do the *VEX opcodes need that (66) marking at all? > For operand sizing? > > Looking at our example insn VCVTPS2UQQ, I don't see any other encoding where > 66 is not present. And there's nothing in the pseudo code either. So VEX.pp=1 > is part of the encoding of that insn. > > So, that (66) there is not really the prefix ... It puts the instruction into a different opcode/addressing-mode space (different attribute table) so we probably need to keep using it like that. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder 2025-12-02 6:26 ` Adrian Hunter @ 2025-12-02 10:47 ` Borislav Petkov 0 siblings, 0 replies; 18+ messages in thread From: Borislav Petkov @ 2025-12-02 10:47 UTC (permalink / raw) To: Adrian Hunter Cc: Masami Hiramatsu, linux-kernel, Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML On Tue, Dec 02, 2025 at 08:26:00AM +0200, Adrian Hunter wrote: > The instruction decoder is permissive in the sense that it cannot > tell if an instruction is valid, only what its properties are assuming > it is valid. There is no need to validate EVEX-only. > > ev->evo makes sense to allow for another instruction. I have no clue what you mean here. > # (ev): this opcode requires EVEX prefix. > # (evo): this opcode is changed by EVEX prefix (EVEX opcode) I can certainly see the "evo" part. This opcode - 0f 79 - means different things with different prefixes. So "ev" is wrong here because this opcode does *not* require EVEX - it can exist without EVEX. So the "ev" -> "evo" change is probably the right thing to do ATM. > It puts the instruction into a different opcode/addressing-mode space > (different attribute table) so we probably need to keep using it like that. Probably? This scheme of putting an insn in a different attribute table because of randomly selected insn properties looks silly and error prone to me. If you want to mark it as part of the whole AVX512* set, then use the fact that it has an EVEX prefix. That's all. And if you want to differentiate on VEX.pp, then invent a new "superscript" or whatever this thing is called which is called VEX_pp or whatever. But do not call it 66 to mean the legacy prefix because that is wrong and it conflates two incompatible things as it can be seen here, and causes trouble. I mean, there should be a direct 1:1 match between insn encoding and flags we need and that'll give us the different attribute tables as this thing is designed and all is fine and dandy. I'd say. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH V2 3/4] perf tools: Add AVX-512 support to the instruction decoder used by Intel PT 2016-07-20 8:30 [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Adrian Hunter 2016-07-20 8:30 ` [PATCH V2 1/4] x86/insn: perf tools: Fix vcvtph2ps instruction decoding Adrian Hunter 2016-07-20 8:30 ` [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder Adrian Hunter @ 2016-07-20 8:30 ` Adrian Hunter 2016-07-25 18:09 ` [tip:perf/core] " tip-bot for Adrian Hunter 2016-07-20 8:30 ` [PATCH V2 4/4] perf tools: Add AVX-512 instructions to the new instructions test Adrian Hunter 2016-07-20 18:11 ` [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Masami Hiramatsu 4 siblings, 1 reply; 18+ messages in thread From: Adrian Hunter @ 2016-07-20 8:30 UTC (permalink / raw) To: linux-kernel Cc: Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Masami Hiramatsu, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML Add support for Intel's AVX-512 instructions to perf tools instruction decoder used by Intel PT. The kernel's instruction decoder was updated in a previous patch. AVX-512 instructions are documented in Intel Architecture Instruction Set Extensions Programming Reference (February 2016). AVX-512 instructions are identified by a EVEX prefix which, for the purpose of instruction decoding, can be treated as though it were a 4-byte VEX prefix. Existing instructions which can now accept an EVEX prefix need not be further annotated in the op code map (x86-opcode-map.txt). In the case of new instructions, the op code map is updated accordingly. Also add associated Mask Instructions that are used to manipulate mask registers used in AVX-512 instructions. A representative set of instructions is added to the perf tools new instructions test in a subsequent patch. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> --- .../util/intel-pt-decoder/gen-insn-attr-x86.awk | 11 +- tools/perf/util/intel-pt-decoder/inat.h | 17 +- tools/perf/util/intel-pt-decoder/insn.c | 18 +- tools/perf/util/intel-pt-decoder/insn.h | 12 +- .../perf/util/intel-pt-decoder/x86-opcode-map.txt | 263 ++++++++++++++------- 5 files changed, 220 insertions(+), 101 deletions(-) diff --git a/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk b/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk index 517567347aac..54e961659514 100644 --- a/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk +++ b/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk @@ -72,12 +72,14 @@ BEGIN { lprefix_expr = "\\((66|F2|F3)\\)" max_lprefix = 4 - # All opcodes starting with lower-case 'v' or with (v1) superscript + # All opcodes starting with lower-case 'v', 'k' or with (v1) superscript # accepts VEX prefix - vexok_opcode_expr = "^v.*" + vexok_opcode_expr = "^[vk].*" vexok_expr = "\\(v1\\)" # All opcodes with (v) superscript supports *only* VEX prefix vexonly_expr = "\\(v\\)" + # All opcodes with (ev) superscript supports *only* EVEX prefix + evexonly_expr = "\\(ev\\)" prefix_expr = "\\(Prefix\\)" prefix_num["Operand-Size"] = "INAT_PFX_OPNDSZ" @@ -95,6 +97,7 @@ BEGIN { prefix_num["Address-Size"] = "INAT_PFX_ADDRSZ" prefix_num["VEX+1byte"] = "INAT_PFX_VEX2" prefix_num["VEX+2byte"] = "INAT_PFX_VEX3" + prefix_num["EVEX"] = "INAT_PFX_EVEX" clear_vars() } @@ -319,7 +322,9 @@ function convert_operands(count,opnd, i,j,imm,mod) flags = add_flags(flags, "INAT_MODRM") # check VEX codes - if (match(ext, vexonly_expr)) + if (match(ext, evexonly_expr)) + flags = add_flags(flags, "INAT_VEXOK | INAT_EVEXONLY") + else if (match(ext, vexonly_expr)) flags = add_flags(flags, "INAT_VEXOK | INAT_VEXONLY") else if (match(ext, vexok_expr) || match(opcode, vexok_opcode_expr)) flags = add_flags(flags, "INAT_VEXOK") diff --git a/tools/perf/util/intel-pt-decoder/inat.h b/tools/perf/util/intel-pt-decoder/inat.h index 611645e903a8..125ecd2a300d 100644 --- a/tools/perf/util/intel-pt-decoder/inat.h +++ b/tools/perf/util/intel-pt-decoder/inat.h @@ -48,6 +48,7 @@ /* AVX VEX prefixes */ #define INAT_PFX_VEX2 13 /* 2-bytes VEX prefix */ #define INAT_PFX_VEX3 14 /* 3-bytes VEX prefix */ +#define INAT_PFX_EVEX 15 /* EVEX prefix */ #define INAT_LSTPFX_MAX 3 #define INAT_LGCPFX_MAX 11 @@ -89,6 +90,7 @@ #define INAT_VARIANT (1 << (INAT_FLAG_OFFS + 4)) #define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5)) #define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6)) +#define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7)) /* Attribute making macros for attribute tables */ #define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS) #define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS) @@ -141,7 +143,13 @@ static inline int inat_last_prefix_id(insn_attr_t attr) static inline int inat_is_vex_prefix(insn_attr_t attr) { attr &= INAT_PFX_MASK; - return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3; + return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3 || + attr == INAT_PFX_EVEX; +} + +static inline int inat_is_evex_prefix(insn_attr_t attr) +{ + return (attr & INAT_PFX_MASK) == INAT_PFX_EVEX; } static inline int inat_is_vex3_prefix(insn_attr_t attr) @@ -216,6 +224,11 @@ static inline int inat_accept_vex(insn_attr_t attr) static inline int inat_must_vex(insn_attr_t attr) { - return attr & INAT_VEXONLY; + return attr & (INAT_VEXONLY | INAT_EVEXONLY); +} + +static inline int inat_must_evex(insn_attr_t attr) +{ + return attr & INAT_EVEXONLY; } #endif diff --git a/tools/perf/util/intel-pt-decoder/insn.c b/tools/perf/util/intel-pt-decoder/insn.c index 9f26eae6c9f0..ca983e2bea8b 100644 --- a/tools/perf/util/intel-pt-decoder/insn.c +++ b/tools/perf/util/intel-pt-decoder/insn.c @@ -155,14 +155,24 @@ found: /* * In 32-bits mode, if the [7:6] bits (mod bits of * ModRM) on the second byte are not 11b, it is - * LDS or LES. + * LDS or LES or BOUND. */ if (X86_MODRM_MOD(b2) != 3) goto vex_end; } insn->vex_prefix.bytes[0] = b; insn->vex_prefix.bytes[1] = b2; - if (inat_is_vex3_prefix(attr)) { + if (inat_is_evex_prefix(attr)) { + b2 = peek_nbyte_next(insn_byte_t, insn, 2); + insn->vex_prefix.bytes[2] = b2; + b2 = peek_nbyte_next(insn_byte_t, insn, 3); + insn->vex_prefix.bytes[3] = b2; + insn->vex_prefix.nbytes = 4; + insn->next_byte += 4; + if (insn->x86_64 && X86_VEX_W(b2)) + /* VEX.W overrides opnd_size */ + insn->opnd_bytes = 8; + } else if (inat_is_vex3_prefix(attr)) { b2 = peek_nbyte_next(insn_byte_t, insn, 2); insn->vex_prefix.bytes[2] = b2; insn->vex_prefix.nbytes = 3; @@ -221,7 +231,9 @@ void insn_get_opcode(struct insn *insn) m = insn_vex_m_bits(insn); p = insn_vex_p_bits(insn); insn->attr = inat_get_avx_attribute(op, m, p); - if (!inat_accept_vex(insn->attr) && !inat_is_group(insn->attr)) + if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) || + (!inat_accept_vex(insn->attr) && + !inat_is_group(insn->attr))) insn->attr = 0; /* This instruction is bad */ goto end; /* VEX has only 1 byte for opcode */ } diff --git a/tools/perf/util/intel-pt-decoder/insn.h b/tools/perf/util/intel-pt-decoder/insn.h index dd12da0f4593..e23578c7b1be 100644 --- a/tools/perf/util/intel-pt-decoder/insn.h +++ b/tools/perf/util/intel-pt-decoder/insn.h @@ -91,6 +91,7 @@ struct insn { #define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */ #define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */ /* VEX bit fields */ +#define X86_EVEX_M(vex) ((vex) & 0x03) /* EVEX Byte1 */ #define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */ #define X86_VEX2_M 1 /* VEX2.M always 1 */ #define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */ @@ -133,6 +134,13 @@ static inline int insn_is_avx(struct insn *insn) return (insn->vex_prefix.value != 0); } +static inline int insn_is_evex(struct insn *insn) +{ + if (!insn->prefixes.got) + insn_get_prefixes(insn); + return (insn->vex_prefix.nbytes == 4); +} + /* Ensure this instruction is decoded completely */ static inline int insn_complete(struct insn *insn) { @@ -144,8 +152,10 @@ static inline insn_byte_t insn_vex_m_bits(struct insn *insn) { if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */ return X86_VEX2_M; - else + else if (insn->vex_prefix.nbytes == 3) /* 3 bytes VEX */ return X86_VEX3_M(insn->vex_prefix.bytes[1]); + else /* EVEX */ + return X86_EVEX_M(insn->vex_prefix.bytes[1]); } static inline insn_byte_t insn_vex_p_bits(struct insn *insn) diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt index 28082de46f0d..ec378cd7b71e 100644 --- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt +++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt @@ -13,12 +13,17 @@ # opcode: escape # escaped-name # EndTable # +# mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix +# mnemonics that begin with lowercase 'k' accept a VEX prefix +# #<group maps> # GrpTable: GrpXXX # reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...] # EndTable # # AVX Superscripts +# (ev): this opcode requires EVEX prefix. +# (evo): this opcode is changed by EVEX prefix (EVEX opcode) # (v): this opcode requires VEX prefix. # (v1): this opcode only supports 128bit VEX. # @@ -137,7 +142,7 @@ AVXcode: # 0x60 - 0x6f 60: PUSHA/PUSHAD (i64) 61: POPA/POPAD (i64) -62: BOUND Gv,Ma (i64) +62: BOUND Gv,Ma (i64) | EVEX (Prefix) 63: ARPL Ew,Gw (i64) | MOVSXD Gv,Ev (o64) 64: SEG=FS (Prefix) 65: SEG=GS (Prefix) @@ -399,17 +404,17 @@ AVXcode: 1 3f: # 0x0f 0x40-0x4f 40: CMOVO Gv,Ev -41: CMOVNO Gv,Ev -42: CMOVB/C/NAE Gv,Ev +41: CMOVNO Gv,Ev | kandw/q Vk,Hk,Uk | kandb/d Vk,Hk,Uk (66) +42: CMOVB/C/NAE Gv,Ev | kandnw/q Vk,Hk,Uk | kandnb/d Vk,Hk,Uk (66) 43: CMOVAE/NB/NC Gv,Ev -44: CMOVE/Z Gv,Ev -45: CMOVNE/NZ Gv,Ev -46: CMOVBE/NA Gv,Ev -47: CMOVA/NBE Gv,Ev +44: CMOVE/Z Gv,Ev | knotw/q Vk,Uk | knotb/d Vk,Uk (66) +45: CMOVNE/NZ Gv,Ev | korw/q Vk,Hk,Uk | korb/d Vk,Hk,Uk (66) +46: CMOVBE/NA Gv,Ev | kxnorw/q Vk,Hk,Uk | kxnorb/d Vk,Hk,Uk (66) +47: CMOVA/NBE Gv,Ev | kxorw/q Vk,Hk,Uk | kxorb/d Vk,Hk,Uk (66) 48: CMOVS Gv,Ev 49: CMOVNS Gv,Ev -4a: CMOVP/PE Gv,Ev -4b: CMOVNP/PO Gv,Ev +4a: CMOVP/PE Gv,Ev | kaddw/q Vk,Hk,Uk | kaddb/d Vk,Hk,Uk (66) +4b: CMOVNP/PO Gv,Ev | kunpckbw Vk,Hk,Uk (66) | kunpckwd/dq Vk,Hk,Uk 4c: CMOVL/NGE Gv,Ev 4d: CMOVNL/GE Gv,Ev 4e: CMOVLE/NG Gv,Ev @@ -426,7 +431,7 @@ AVXcode: 1 58: vaddps Vps,Hps,Wps | vaddpd Vpd,Hpd,Wpd (66) | vaddss Vss,Hss,Wss (F3),(v1) | vaddsd Vsd,Hsd,Wsd (F2),(v1) 59: vmulps Vps,Hps,Wps | vmulpd Vpd,Hpd,Wpd (66) | vmulss Vss,Hss,Wss (F3),(v1) | vmulsd Vsd,Hsd,Wsd (F2),(v1) 5a: vcvtps2pd Vpd,Wps | vcvtpd2ps Vps,Wpd (66) | vcvtss2sd Vsd,Hx,Wss (F3),(v1) | vcvtsd2ss Vss,Hx,Wsd (F2),(v1) -5b: vcvtdq2ps Vps,Wdq | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) +5b: vcvtdq2ps Vps,Wdq | vcvtqq2ps Vps,Wqq (evo) | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) 5c: vsubps Vps,Hps,Wps | vsubpd Vpd,Hpd,Wpd (66) | vsubss Vss,Hss,Wss (F3),(v1) | vsubsd Vsd,Hsd,Wsd (F2),(v1) 5d: vminps Vps,Hps,Wps | vminpd Vpd,Hpd,Wpd (66) | vminss Vss,Hss,Wss (F3),(v1) | vminsd Vsd,Hsd,Wsd (F2),(v1) 5e: vdivps Vps,Hps,Wps | vdivpd Vpd,Hpd,Wpd (66) | vdivss Vss,Hss,Wss (F3),(v1) | vdivsd Vsd,Hsd,Wsd (F2),(v1) @@ -447,7 +452,7 @@ AVXcode: 1 6c: vpunpcklqdq Vx,Hx,Wx (66),(v1) 6d: vpunpckhqdq Vx,Hx,Wx (66),(v1) 6e: movd/q Pd,Ey | vmovd/q Vy,Ey (66),(v1) -6f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqu Vx,Wx (F3) +6f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqa32/64 Vx,Wx (66),(evo) | vmovdqu Vx,Wx (F3) | vmovdqu32/64 Vx,Wx (F3),(evo) | vmovdqu8/16 Vx,Wx (F2),(ev) # 0x0f 0x70-0x7f 70: pshufw Pq,Qq,Ib | vpshufd Vx,Wx,Ib (66),(v1) | vpshufhw Vx,Wx,Ib (F3),(v1) | vpshuflw Vx,Wx,Ib (F2),(v1) 71: Grp12 (1A) @@ -458,14 +463,14 @@ AVXcode: 1 76: pcmpeqd Pq,Qq | vpcmpeqd Vx,Hx,Wx (66),(v1) # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX. 77: emms | vzeroupper | vzeroall -78: VMREAD Ey,Gy -79: VMWRITE Gy,Ey -7a: -7b: +78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) +79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) +7a: vcvtudq2pd/uqq2pd Vpd,Wx (F3),(ev) | vcvtudq2ps/uqq2ps Vpd,Wx (F2),(ev) | vcvttps2qq/pd2qq Vx,Wx (66),(ev) +7b: vcvtusi2sd Vpd,Hpd,Ev (F2),(ev) | vcvtusi2ss Vps,Hps,Ev (F3),(ev) | vcvtps2qq/pd2qq Vx,Wx (66),(ev) 7c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2) 7d: vhsubpd Vpd,Hpd,Wpd (66) | vhsubps Vps,Hps,Wps (F2) 7e: movd/q Ey,Pd | vmovd/q Ey,Vy (66),(v1) | vmovq Vq,Wq (F3),(v1) -7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqu Wx,Vx (F3) +7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev) # 0x0f 0x80-0x8f # Note: "forced64" is Intel CPU behavior (see comment about CALL insn). 80: JO Jz (f64) @@ -485,16 +490,16 @@ AVXcode: 1 8e: JLE/JNG Jz (f64) 8f: JNLE/JG Jz (f64) # 0x0f 0x90-0x9f -90: SETO Eb -91: SETNO Eb -92: SETB/C/NAE Eb -93: SETAE/NB/NC Eb +90: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66) +91: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66) +92: SETB/C/NAE Eb | kmovw Vk,Rv | kmovb Vk,Rv (66) | kmovq/d Vk,Rv (F2) +93: SETAE/NB/NC Eb | kmovw Gv,Uk | kmovb Gv,Uk (66) | kmovq/d Gv,Uk (F2) 94: SETE/Z Eb 95: SETNE/NZ Eb 96: SETBE/NA Eb 97: SETA/NBE Eb -98: SETS Eb -99: SETNS Eb +98: SETS Eb | kortestw/q Vk,Uk | kortestb/d Vk,Uk (66) +99: SETNS Eb | ktestw/q Vk,Uk | ktestb/d Vk,Uk (66) 9a: SETP/PE Eb 9b: SETNP/PO Eb 9c: SETL/NGE Eb @@ -564,11 +569,11 @@ d7: pmovmskb Gd,Nq | vpmovmskb Gd,Ux (66),(v1) d8: psubusb Pq,Qq | vpsubusb Vx,Hx,Wx (66),(v1) d9: psubusw Pq,Qq | vpsubusw Vx,Hx,Wx (66),(v1) da: pminub Pq,Qq | vpminub Vx,Hx,Wx (66),(v1) -db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1) +db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1) | vpandd/q Vx,Hx,Wx (66),(evo) dc: paddusb Pq,Qq | vpaddusb Vx,Hx,Wx (66),(v1) dd: paddusw Pq,Qq | vpaddusw Vx,Hx,Wx (66),(v1) de: pmaxub Pq,Qq | vpmaxub Vx,Hx,Wx (66),(v1) -df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1) +df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1) | vpandnd/q Vx,Hx,Wx (66),(evo) # 0x0f 0xe0-0xef e0: pavgb Pq,Qq | vpavgb Vx,Hx,Wx (66),(v1) e1: psraw Pq,Qq | vpsraw Vx,Hx,Wx (66),(v1) @@ -576,16 +581,16 @@ e2: psrad Pq,Qq | vpsrad Vx,Hx,Wx (66),(v1) e3: pavgw Pq,Qq | vpavgw Vx,Hx,Wx (66),(v1) e4: pmulhuw Pq,Qq | vpmulhuw Vx,Hx,Wx (66),(v1) e5: pmulhw Pq,Qq | vpmulhw Vx,Hx,Wx (66),(v1) -e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtpd2dq Vx,Wpd (F2) +e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtdq2pd/qq2pd Vx,Wdq (F3),(evo) | vcvtpd2dq Vx,Wpd (F2) e7: movntq Mq,Pq | vmovntdq Mx,Vx (66) e8: psubsb Pq,Qq | vpsubsb Vx,Hx,Wx (66),(v1) e9: psubsw Pq,Qq | vpsubsw Vx,Hx,Wx (66),(v1) ea: pminsw Pq,Qq | vpminsw Vx,Hx,Wx (66),(v1) -eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1) +eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1) | vpord/q Vx,Hx,Wx (66),(evo) ec: paddsb Pq,Qq | vpaddsb Vx,Hx,Wx (66),(v1) ed: paddsw Pq,Qq | vpaddsw Vx,Hx,Wx (66),(v1) ee: pmaxsw Pq,Qq | vpmaxsw Vx,Hx,Wx (66),(v1) -ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1) +ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1) | vpxord/q Vx,Hx,Wx (66),(evo) # 0x0f 0xf0-0xff f0: vlddqu Vx,Mx (F2) f1: psllw Pq,Qq | vpsllw Vx,Hx,Wx (66),(v1) @@ -626,81 +631,105 @@ AVXcode: 2 0e: vtestps Vx,Wx (66),(v) 0f: vtestpd Vx,Wx (66),(v) # 0x0f 0x38 0x10-0x1f -10: pblendvb Vdq,Wdq (66) -11: -12: -13: vcvtph2ps Vx,Wx (66),(v) -14: blendvps Vdq,Wdq (66) -15: blendvpd Vdq,Wdq (66) -16: vpermps Vqq,Hqq,Wqq (66),(v) +10: pblendvb Vdq,Wdq (66) | vpsrlvw Vx,Hx,Wx (66),(evo) | vpmovuswb Wx,Vx (F3),(ev) +11: vpmovusdb Wx,Vd (F3),(ev) | vpsravw Vx,Hx,Wx (66),(ev) +12: vpmovusqb Wx,Vq (F3),(ev) | vpsllvw Vx,Hx,Wx (66),(ev) +13: vcvtph2ps Vx,Wx (66),(v) | vpmovusdw Wx,Vd (F3),(ev) +14: blendvps Vdq,Wdq (66) | vpmovusqw Wx,Vq (F3),(ev) | vprorvd/q Vx,Hx,Wx (66),(evo) +15: blendvpd Vdq,Wdq (66) | vpmovusqd Wx,Vq (F3),(ev) | vprolvd/q Vx,Hx,Wx (66),(evo) +16: vpermps Vqq,Hqq,Wqq (66),(v) | vpermps/d Vqq,Hqq,Wqq (66),(evo) 17: vptest Vx,Wx (66) 18: vbroadcastss Vx,Wd (66),(v) -19: vbroadcastsd Vqq,Wq (66),(v) -1a: vbroadcastf128 Vqq,Mdq (66),(v) -1b: +19: vbroadcastsd Vqq,Wq (66),(v) | vbroadcastf32x2 Vqq,Wq (66),(evo) +1a: vbroadcastf128 Vqq,Mdq (66),(v) | vbroadcastf32x4/64x2 Vqq,Wq (66),(evo) +1b: vbroadcastf32x8/64x4 Vqq,Mdq (66),(ev) 1c: pabsb Pq,Qq | vpabsb Vx,Wx (66),(v1) 1d: pabsw Pq,Qq | vpabsw Vx,Wx (66),(v1) 1e: pabsd Pq,Qq | vpabsd Vx,Wx (66),(v1) -1f: +1f: vpabsq Vx,Wx (66),(ev) # 0x0f 0x38 0x20-0x2f -20: vpmovsxbw Vx,Ux/Mq (66),(v1) -21: vpmovsxbd Vx,Ux/Md (66),(v1) -22: vpmovsxbq Vx,Ux/Mw (66),(v1) -23: vpmovsxwd Vx,Ux/Mq (66),(v1) -24: vpmovsxwq Vx,Ux/Md (66),(v1) -25: vpmovsxdq Vx,Ux/Mq (66),(v1) -26: -27: -28: vpmuldq Vx,Hx,Wx (66),(v1) -29: vpcmpeqq Vx,Hx,Wx (66),(v1) -2a: vmovntdqa Vx,Mx (66),(v1) +20: vpmovsxbw Vx,Ux/Mq (66),(v1) | vpmovswb Wx,Vx (F3),(ev) +21: vpmovsxbd Vx,Ux/Md (66),(v1) | vpmovsdb Wx,Vd (F3),(ev) +22: vpmovsxbq Vx,Ux/Mw (66),(v1) | vpmovsqb Wx,Vq (F3),(ev) +23: vpmovsxwd Vx,Ux/Mq (66),(v1) | vpmovsdw Wx,Vd (F3),(ev) +24: vpmovsxwq Vx,Ux/Md (66),(v1) | vpmovsqw Wx,Vq (F3),(ev) +25: vpmovsxdq Vx,Ux/Mq (66),(v1) | vpmovsqd Wx,Vq (F3),(ev) +26: vptestmb/w Vk,Hx,Wx (66),(ev) | vptestnmb/w Vk,Hx,Wx (F3),(ev) +27: vptestmd/q Vk,Hx,Wx (66),(ev) | vptestnmd/q Vk,Hx,Wx (F3),(ev) +28: vpmuldq Vx,Hx,Wx (66),(v1) | vpmovm2b/w Vx,Uk (F3),(ev) +29: vpcmpeqq Vx,Hx,Wx (66),(v1) | vpmovb2m/w2m Vk,Ux (F3),(ev) +2a: vmovntdqa Vx,Mx (66),(v1) | vpbroadcastmb2q Vx,Uk (F3),(ev) 2b: vpackusdw Vx,Hx,Wx (66),(v1) -2c: vmaskmovps Vx,Hx,Mx (66),(v) -2d: vmaskmovpd Vx,Hx,Mx (66),(v) +2c: vmaskmovps Vx,Hx,Mx (66),(v) | vscalefps/d Vx,Hx,Wx (66),(evo) +2d: vmaskmovpd Vx,Hx,Mx (66),(v) | vscalefss/d Vx,Hx,Wx (66),(evo) 2e: vmaskmovps Mx,Hx,Vx (66),(v) 2f: vmaskmovpd Mx,Hx,Vx (66),(v) # 0x0f 0x38 0x30-0x3f -30: vpmovzxbw Vx,Ux/Mq (66),(v1) -31: vpmovzxbd Vx,Ux/Md (66),(v1) -32: vpmovzxbq Vx,Ux/Mw (66),(v1) -33: vpmovzxwd Vx,Ux/Mq (66),(v1) -34: vpmovzxwq Vx,Ux/Md (66),(v1) -35: vpmovzxdq Vx,Ux/Mq (66),(v1) -36: vpermd Vqq,Hqq,Wqq (66),(v) +30: vpmovzxbw Vx,Ux/Mq (66),(v1) | vpmovwb Wx,Vx (F3),(ev) +31: vpmovzxbd Vx,Ux/Md (66),(v1) | vpmovdb Wx,Vd (F3),(ev) +32: vpmovzxbq Vx,Ux/Mw (66),(v1) | vpmovqb Wx,Vq (F3),(ev) +33: vpmovzxwd Vx,Ux/Mq (66),(v1) | vpmovdw Wx,Vd (F3),(ev) +34: vpmovzxwq Vx,Ux/Md (66),(v1) | vpmovqw Wx,Vq (F3),(ev) +35: vpmovzxdq Vx,Ux/Mq (66),(v1) | vpmovqd Wx,Vq (F3),(ev) +36: vpermd Vqq,Hqq,Wqq (66),(v) | vpermd/q Vqq,Hqq,Wqq (66),(evo) 37: vpcmpgtq Vx,Hx,Wx (66),(v1) -38: vpminsb Vx,Hx,Wx (66),(v1) -39: vpminsd Vx,Hx,Wx (66),(v1) -3a: vpminuw Vx,Hx,Wx (66),(v1) -3b: vpminud Vx,Hx,Wx (66),(v1) +38: vpminsb Vx,Hx,Wx (66),(v1) | vpmovm2d/q Vx,Uk (F3),(ev) +39: vpminsd Vx,Hx,Wx (66),(v1) | vpminsd/q Vx,Hx,Wx (66),(evo) | vpmovd2m/q2m Vk,Ux (F3),(ev) +3a: vpminuw Vx,Hx,Wx (66),(v1) | vpbroadcastmw2d Vx,Uk (F3),(ev) +3b: vpminud Vx,Hx,Wx (66),(v1) | vpminud/q Vx,Hx,Wx (66),(evo) 3c: vpmaxsb Vx,Hx,Wx (66),(v1) -3d: vpmaxsd Vx,Hx,Wx (66),(v1) +3d: vpmaxsd Vx,Hx,Wx (66),(v1) | vpmaxsd/q Vx,Hx,Wx (66),(evo) 3e: vpmaxuw Vx,Hx,Wx (66),(v1) -3f: vpmaxud Vx,Hx,Wx (66),(v1) +3f: vpmaxud Vx,Hx,Wx (66),(v1) | vpmaxud/q Vx,Hx,Wx (66),(evo) # 0x0f 0x38 0x40-0x8f -40: vpmulld Vx,Hx,Wx (66),(v1) +40: vpmulld Vx,Hx,Wx (66),(v1) | vpmulld/q Vx,Hx,Wx (66),(evo) 41: vphminposuw Vdq,Wdq (66),(v1) -42: -43: -44: +42: vgetexpps/d Vx,Wx (66),(ev) +43: vgetexpss/d Vx,Hx,Wx (66),(ev) +44: vplzcntd/q Vx,Wx (66),(ev) 45: vpsrlvd/q Vx,Hx,Wx (66),(v) -46: vpsravd Vx,Hx,Wx (66),(v) +46: vpsravd Vx,Hx,Wx (66),(v) | vpsravd/q Vx,Hx,Wx (66),(evo) 47: vpsllvd/q Vx,Hx,Wx (66),(v) -# Skip 0x48-0x57 +# Skip 0x48-0x4b +4c: vrcp14ps/d Vpd,Wpd (66),(ev) +4d: vrcp14ss/d Vsd,Hpd,Wsd (66),(ev) +4e: vrsqrt14ps/d Vpd,Wpd (66),(ev) +4f: vrsqrt14ss/d Vsd,Hsd,Wsd (66),(ev) +# Skip 0x50-0x57 58: vpbroadcastd Vx,Wx (66),(v) -59: vpbroadcastq Vx,Wx (66),(v) -5a: vbroadcasti128 Vqq,Mdq (66),(v) -# Skip 0x5b-0x77 +59: vpbroadcastq Vx,Wx (66),(v) | vbroadcasti32x2 Vx,Wx (66),(evo) +5a: vbroadcasti128 Vqq,Mdq (66),(v) | vbroadcasti32x4/64x2 Vx,Wx (66),(evo) +5b: vbroadcasti32x8/64x4 Vqq,Mdq (66),(ev) +# Skip 0x5c-0x63 +64: vpblendmd/q Vx,Hx,Wx (66),(ev) +65: vblendmps/d Vx,Hx,Wx (66),(ev) +66: vpblendmb/w Vx,Hx,Wx (66),(ev) +# Skip 0x67-0x74 +75: vpermi2b/w Vx,Hx,Wx (66),(ev) +76: vpermi2d/q Vx,Hx,Wx (66),(ev) +77: vpermi2ps/d Vx,Hx,Wx (66),(ev) 78: vpbroadcastb Vx,Wx (66),(v) 79: vpbroadcastw Vx,Wx (66),(v) -# Skip 0x7a-0x7f +7a: vpbroadcastb Vx,Rv (66),(ev) +7b: vpbroadcastw Vx,Rv (66),(ev) +7c: vpbroadcastd/q Vx,Rv (66),(ev) +7d: vpermt2b/w Vx,Hx,Wx (66),(ev) +7e: vpermt2d/q Vx,Hx,Wx (66),(ev) +7f: vpermt2ps/d Vx,Hx,Wx (66),(ev) 80: INVEPT Gy,Mdq (66) 81: INVPID Gy,Mdq (66) 82: INVPCID Gy,Mdq (66) +83: vpmultishiftqb Vx,Hx,Wx (66),(ev) +88: vexpandps/d Vpd,Wpd (66),(ev) +89: vpexpandd/q Vx,Wx (66),(ev) +8a: vcompressps/d Wx,Vx (66),(ev) +8b: vpcompressd/q Wx,Vx (66),(ev) 8c: vpmaskmovd/q Vx,Hx,Mx (66),(v) +8d: vpermb/w Vx,Hx,Wx (66),(ev) 8e: vpmaskmovd/q Mx,Vx,Hx (66),(v) # 0x0f 0x38 0x90-0xbf (FMA) -90: vgatherdd/q Vx,Hx,Wx (66),(v) -91: vgatherqd/q Vx,Hx,Wx (66),(v) +90: vgatherdd/q Vx,Hx,Wx (66),(v) | vpgatherdd/q Vx,Wx (66),(evo) +91: vgatherqd/q Vx,Hx,Wx (66),(v) | vpgatherqd/q Vx,Wx (66),(evo) 92: vgatherdps/d Vx,Hx,Wx (66),(v) 93: vgatherqps/d Vx,Hx,Wx (66),(v) 94: @@ -715,6 +744,10 @@ AVXcode: 2 9d: vfnmadd132ss/d Vx,Hx,Wx (66),(v),(v1) 9e: vfnmsub132ps/d Vx,Hx,Wx (66),(v) 9f: vfnmsub132ss/d Vx,Hx,Wx (66),(v),(v1) +a0: vpscatterdd/q Wx,Vx (66),(ev) +a1: vpscatterqd/q Wx,Vx (66),(ev) +a2: vscatterdps/d Wx,Vx (66),(ev) +a3: vscatterqps/d Wx,Vx (66),(ev) a6: vfmaddsub213ps/d Vx,Hx,Wx (66),(v) a7: vfmsubadd213ps/d Vx,Hx,Wx (66),(v) a8: vfmadd213ps/d Vx,Hx,Wx (66),(v) @@ -725,6 +758,8 @@ ac: vfnmadd213ps/d Vx,Hx,Wx (66),(v) ad: vfnmadd213ss/d Vx,Hx,Wx (66),(v),(v1) ae: vfnmsub213ps/d Vx,Hx,Wx (66),(v) af: vfnmsub213ss/d Vx,Hx,Wx (66),(v),(v1) +b4: vpmadd52luq Vx,Hx,Wx (66),(ev) +b5: vpmadd52huq Vx,Hx,Wx (66),(ev) b6: vfmaddsub231ps/d Vx,Hx,Wx (66),(v) b7: vfmsubadd231ps/d Vx,Hx,Wx (66),(v) b8: vfmadd231ps/d Vx,Hx,Wx (66),(v) @@ -736,12 +771,15 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1) be: vfnmsub231ps/d Vx,Hx,Wx (66),(v) bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1) # 0x0f 0x38 0xc0-0xff -c8: sha1nexte Vdq,Wdq +c4: vpconflictd/q Vx,Wx (66),(ev) +c6: Grp18 (1A) +c7: Grp19 (1A) +c8: sha1nexte Vdq,Wdq | vexp2ps/d Vx,Wx (66),(ev) c9: sha1msg1 Vdq,Wdq -ca: sha1msg2 Vdq,Wdq -cb: sha256rnds2 Vdq,Wdq -cc: sha256msg1 Vdq,Wdq -cd: sha256msg2 Vdq,Wdq +ca: sha1msg2 Vdq,Wdq | vrcp28ps/d Vx,Wx (66),(ev) +cb: sha256rnds2 Vdq,Wdq | vrcp28ss/d Vx,Hx,Wx (66),(ev) +cc: sha256msg1 Vdq,Wdq | vrsqrt28ps/d Vx,Wx (66),(ev) +cd: sha256msg2 Vdq,Wdq | vrsqrt28ss/d Vx,Hx,Wx (66),(ev) db: VAESIMC Vdq,Wdq (66),(v1) dc: VAESENC Vdq,Hdq,Wdq (66),(v1) dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1) @@ -763,15 +801,15 @@ AVXcode: 3 00: vpermq Vqq,Wqq,Ib (66),(v) 01: vpermpd Vqq,Wqq,Ib (66),(v) 02: vpblendd Vx,Hx,Wx,Ib (66),(v) -03: +03: valignd/q Vx,Hx,Wx,Ib (66),(ev) 04: vpermilps Vx,Wx,Ib (66),(v) 05: vpermilpd Vx,Wx,Ib (66),(v) 06: vperm2f128 Vqq,Hqq,Wqq,Ib (66),(v) 07: -08: vroundps Vx,Wx,Ib (66) -09: vroundpd Vx,Wx,Ib (66) -0a: vroundss Vss,Wss,Ib (66),(v1) -0b: vroundsd Vsd,Wsd,Ib (66),(v1) +08: vroundps Vx,Wx,Ib (66) | vrndscaleps Vx,Wx,Ib (66),(evo) +09: vroundpd Vx,Wx,Ib (66) | vrndscalepd Vx,Wx,Ib (66),(evo) +0a: vroundss Vss,Wss,Ib (66),(v1) | vrndscaless Vx,Hx,Wx,Ib (66),(evo) +0b: vroundsd Vsd,Wsd,Ib (66),(v1) | vrndscalesd Vx,Hx,Wx,Ib (66),(evo) 0c: vblendps Vx,Hx,Wx,Ib (66) 0d: vblendpd Vx,Hx,Wx,Ib (66) 0e: vpblendw Vx,Hx,Wx,Ib (66),(v1) @@ -780,26 +818,51 @@ AVXcode: 3 15: vpextrw Rd/Mw,Vdq,Ib (66),(v1) 16: vpextrd/q Ey,Vdq,Ib (66),(v1) 17: vextractps Ed,Vdq,Ib (66),(v1) -18: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v) -19: vextractf128 Wdq,Vqq,Ib (66),(v) +18: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v) | vinsertf32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo) +19: vextractf128 Wdq,Vqq,Ib (66),(v) | vextractf32x4/64x2 Wdq,Vqq,Ib (66),(evo) +1a: vinsertf32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev) +1b: vextractf32x8/64x4 Wdq,Vqq,Ib (66),(ev) 1d: vcvtps2ph Wx,Vx,Ib (66),(v) +1e: vpcmpud/q Vk,Hd,Wd,Ib (66),(ev) +1f: vpcmpd/q Vk,Hd,Wd,Ib (66),(ev) 20: vpinsrb Vdq,Hdq,Ry/Mb,Ib (66),(v1) 21: vinsertps Vdq,Hdq,Udq/Md,Ib (66),(v1) 22: vpinsrd/q Vdq,Hdq,Ey,Ib (66),(v1) -38: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v) -39: vextracti128 Wdq,Vqq,Ib (66),(v) +23: vshuff32x4/64x2 Vx,Hx,Wx,Ib (66),(ev) +25: vpternlogd/q Vx,Hx,Wx,Ib (66),(ev) +26: vgetmantps/d Vx,Wx,Ib (66),(ev) +27: vgetmantss/d Vx,Hx,Wx,Ib (66),(ev) +30: kshiftrb/w Vk,Uk,Ib (66),(v) +31: kshiftrd/q Vk,Uk,Ib (66),(v) +32: kshiftlb/w Vk,Uk,Ib (66),(v) +33: kshiftld/q Vk,Uk,Ib (66),(v) +38: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v) | vinserti32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo) +39: vextracti128 Wdq,Vqq,Ib (66),(v) | vextracti32x4/64x2 Wdq,Vqq,Ib (66),(evo) +3a: vinserti32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev) +3b: vextracti32x8/64x4 Wdq,Vqq,Ib (66),(ev) +3e: vpcmpub/w Vk,Hk,Wx,Ib (66),(ev) +3f: vpcmpb/w Vk,Hk,Wx,Ib (66),(ev) 40: vdpps Vx,Hx,Wx,Ib (66) 41: vdppd Vdq,Hdq,Wdq,Ib (66),(v1) -42: vmpsadbw Vx,Hx,Wx,Ib (66),(v1) +42: vmpsadbw Vx,Hx,Wx,Ib (66),(v1) | vdbpsadbw Vx,Hx,Wx,Ib (66),(evo) +43: vshufi32x4/64x2 Vx,Hx,Wx,Ib (66),(ev) 44: vpclmulqdq Vdq,Hdq,Wdq,Ib (66),(v1) 46: vperm2i128 Vqq,Hqq,Wqq,Ib (66),(v) 4a: vblendvps Vx,Hx,Wx,Lx (66),(v) 4b: vblendvpd Vx,Hx,Wx,Lx (66),(v) 4c: vpblendvb Vx,Hx,Wx,Lx (66),(v1) +50: vrangeps/d Vx,Hx,Wx,Ib (66),(ev) +51: vrangess/d Vx,Hx,Wx,Ib (66),(ev) +54: vfixupimmps/d Vx,Hx,Wx,Ib (66),(ev) +55: vfixupimmss/d Vx,Hx,Wx,Ib (66),(ev) +56: vreduceps/d Vx,Wx,Ib (66),(ev) +57: vreducess/d Vx,Hx,Wx,Ib (66),(ev) 60: vpcmpestrm Vdq,Wdq,Ib (66),(v1) 61: vpcmpestri Vdq,Wdq,Ib (66),(v1) 62: vpcmpistrm Vdq,Wdq,Ib (66),(v1) 63: vpcmpistri Vdq,Wdq,Ib (66),(v1) +66: vfpclassps/d Vk,Wx,Ib (66),(ev) +67: vfpclassss/d Vk,Wx,Ib (66),(ev) cc: sha1rnds4 Vdq,Wdq,Ib df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1) f0: RORX Gy,Ey,Ib (F2),(v) @@ -927,8 +990,10 @@ GrpTable: Grp12 EndTable GrpTable: Grp13 +0: vprord/q Hx,Wx,Ib (66),(ev) +1: vprold/q Hx,Wx,Ib (66),(ev) 2: psrld Nq,Ib (11B) | vpsrld Hx,Ux,Ib (66),(11B),(v1) -4: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1) +4: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1) | vpsrad/q Hx,Ux,Ib (66),(evo) 6: pslld Nq,Ib (11B) | vpslld Hx,Ux,Ib (66),(11B),(v1) EndTable @@ -963,6 +1028,20 @@ GrpTable: Grp17 3: BLSI By,Ey (v) EndTable +GrpTable: Grp18 +1: vgatherpf0dps/d Wx (66),(ev) +2: vgatherpf1dps/d Wx (66),(ev) +5: vscatterpf0dps/d Wx (66),(ev) +6: vscatterpf1dps/d Wx (66),(ev) +EndTable + +GrpTable: Grp19 +1: vgatherpf0qps/d Wx (66),(ev) +2: vgatherpf1qps/d Wx (66),(ev) +5: vscatterpf0qps/d Wx (66),(ev) +6: vscatterpf1qps/d Wx (66),(ev) +EndTable + # AMD's Prefetch Group GrpTable: GrpP 0: PREFETCH -- 1.9.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [tip:perf/core] perf tools: Add AVX-512 support to the instruction decoder used by Intel PT 2016-07-20 8:30 ` [PATCH V2 3/4] perf tools: Add AVX-512 support to the instruction decoder used by Intel PT Adrian Hunter @ 2016-07-25 18:09 ` tip-bot for Adrian Hunter 0 siblings, 0 replies; 18+ messages in thread From: tip-bot for Adrian Hunter @ 2016-07-25 18:09 UTC (permalink / raw) To: linux-tip-commits Cc: x86, mingo, jolsa, adrian.hunter, tglx, luto, acme, dan.j.williams, mhiramat, hpa, linux-kernel Commit-ID: c61f4d5ebaf05fbd90bf43aa2096690b85e34761 Gitweb: http://git.kernel.org/tip/c61f4d5ebaf05fbd90bf43aa2096690b85e34761 Author: Adrian Hunter <adrian.hunter@intel.com> AuthorDate: Wed, 20 Jul 2016 11:30:36 +0300 Committer: Arnaldo Carvalho de Melo <acme@redhat.com> CommitDate: Thu, 21 Jul 2016 09:37:18 -0300 perf tools: Add AVX-512 support to the instruction decoder used by Intel PT Add support for Intel's AVX-512 instructions to perf tools instruction decoder used by Intel PT. The kernel's instruction decoder was updated in a previous patch. AVX-512 instructions are documented in Intel Architecture Instruction Set Extensions Programming Reference (February 2016). AVX-512 instructions are identified by a EVEX prefix which, for the purpose of instruction decoding, can be treated as though it were a 4-byte VEX prefix. Existing instructions which can now accept an EVEX prefix need not be further annotated in the op code map (x86-opcode-map.txt). In the case of new instructions, the op code map is updated accordingly. Also add associated Mask Instructions that are used to manipulate mask registers used in AVX-512 instructions. A representative set of instructions is added to the perf tools new instructions test in a subsequent patch. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ingo Molnar <mingo@kernel.org> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dan Williams <dan.j.williams@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: X86 ML <x86@kernel.org> Link: http://lkml.kernel.org/r/1469003437-32706-4-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> --- .../util/intel-pt-decoder/gen-insn-attr-x86.awk | 11 +- tools/perf/util/intel-pt-decoder/inat.h | 17 +- tools/perf/util/intel-pt-decoder/insn.c | 18 +- tools/perf/util/intel-pt-decoder/insn.h | 12 +- .../perf/util/intel-pt-decoder/x86-opcode-map.txt | 263 ++++++++++++++------- 5 files changed, 220 insertions(+), 101 deletions(-) diff --git a/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk b/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk index 51756734..54e9616 100644 --- a/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk +++ b/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk @@ -72,12 +72,14 @@ BEGIN { lprefix_expr = "\\((66|F2|F3)\\)" max_lprefix = 4 - # All opcodes starting with lower-case 'v' or with (v1) superscript + # All opcodes starting with lower-case 'v', 'k' or with (v1) superscript # accepts VEX prefix - vexok_opcode_expr = "^v.*" + vexok_opcode_expr = "^[vk].*" vexok_expr = "\\(v1\\)" # All opcodes with (v) superscript supports *only* VEX prefix vexonly_expr = "\\(v\\)" + # All opcodes with (ev) superscript supports *only* EVEX prefix + evexonly_expr = "\\(ev\\)" prefix_expr = "\\(Prefix\\)" prefix_num["Operand-Size"] = "INAT_PFX_OPNDSZ" @@ -95,6 +97,7 @@ BEGIN { prefix_num["Address-Size"] = "INAT_PFX_ADDRSZ" prefix_num["VEX+1byte"] = "INAT_PFX_VEX2" prefix_num["VEX+2byte"] = "INAT_PFX_VEX3" + prefix_num["EVEX"] = "INAT_PFX_EVEX" clear_vars() } @@ -319,7 +322,9 @@ function convert_operands(count,opnd, i,j,imm,mod) flags = add_flags(flags, "INAT_MODRM") # check VEX codes - if (match(ext, vexonly_expr)) + if (match(ext, evexonly_expr)) + flags = add_flags(flags, "INAT_VEXOK | INAT_EVEXONLY") + else if (match(ext, vexonly_expr)) flags = add_flags(flags, "INAT_VEXOK | INAT_VEXONLY") else if (match(ext, vexok_expr) || match(opcode, vexok_opcode_expr)) flags = add_flags(flags, "INAT_VEXOK") diff --git a/tools/perf/util/intel-pt-decoder/inat.h b/tools/perf/util/intel-pt-decoder/inat.h index 611645e..125ecd2 100644 --- a/tools/perf/util/intel-pt-decoder/inat.h +++ b/tools/perf/util/intel-pt-decoder/inat.h @@ -48,6 +48,7 @@ /* AVX VEX prefixes */ #define INAT_PFX_VEX2 13 /* 2-bytes VEX prefix */ #define INAT_PFX_VEX3 14 /* 3-bytes VEX prefix */ +#define INAT_PFX_EVEX 15 /* EVEX prefix */ #define INAT_LSTPFX_MAX 3 #define INAT_LGCPFX_MAX 11 @@ -89,6 +90,7 @@ #define INAT_VARIANT (1 << (INAT_FLAG_OFFS + 4)) #define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5)) #define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6)) +#define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7)) /* Attribute making macros for attribute tables */ #define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS) #define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS) @@ -141,7 +143,13 @@ static inline int inat_last_prefix_id(insn_attr_t attr) static inline int inat_is_vex_prefix(insn_attr_t attr) { attr &= INAT_PFX_MASK; - return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3; + return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3 || + attr == INAT_PFX_EVEX; +} + +static inline int inat_is_evex_prefix(insn_attr_t attr) +{ + return (attr & INAT_PFX_MASK) == INAT_PFX_EVEX; } static inline int inat_is_vex3_prefix(insn_attr_t attr) @@ -216,6 +224,11 @@ static inline int inat_accept_vex(insn_attr_t attr) static inline int inat_must_vex(insn_attr_t attr) { - return attr & INAT_VEXONLY; + return attr & (INAT_VEXONLY | INAT_EVEXONLY); +} + +static inline int inat_must_evex(insn_attr_t attr) +{ + return attr & INAT_EVEXONLY; } #endif diff --git a/tools/perf/util/intel-pt-decoder/insn.c b/tools/perf/util/intel-pt-decoder/insn.c index 9f26eae..ca983e2 100644 --- a/tools/perf/util/intel-pt-decoder/insn.c +++ b/tools/perf/util/intel-pt-decoder/insn.c @@ -155,14 +155,24 @@ found: /* * In 32-bits mode, if the [7:6] bits (mod bits of * ModRM) on the second byte are not 11b, it is - * LDS or LES. + * LDS or LES or BOUND. */ if (X86_MODRM_MOD(b2) != 3) goto vex_end; } insn->vex_prefix.bytes[0] = b; insn->vex_prefix.bytes[1] = b2; - if (inat_is_vex3_prefix(attr)) { + if (inat_is_evex_prefix(attr)) { + b2 = peek_nbyte_next(insn_byte_t, insn, 2); + insn->vex_prefix.bytes[2] = b2; + b2 = peek_nbyte_next(insn_byte_t, insn, 3); + insn->vex_prefix.bytes[3] = b2; + insn->vex_prefix.nbytes = 4; + insn->next_byte += 4; + if (insn->x86_64 && X86_VEX_W(b2)) + /* VEX.W overrides opnd_size */ + insn->opnd_bytes = 8; + } else if (inat_is_vex3_prefix(attr)) { b2 = peek_nbyte_next(insn_byte_t, insn, 2); insn->vex_prefix.bytes[2] = b2; insn->vex_prefix.nbytes = 3; @@ -221,7 +231,9 @@ void insn_get_opcode(struct insn *insn) m = insn_vex_m_bits(insn); p = insn_vex_p_bits(insn); insn->attr = inat_get_avx_attribute(op, m, p); - if (!inat_accept_vex(insn->attr) && !inat_is_group(insn->attr)) + if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) || + (!inat_accept_vex(insn->attr) && + !inat_is_group(insn->attr))) insn->attr = 0; /* This instruction is bad */ goto end; /* VEX has only 1 byte for opcode */ } diff --git a/tools/perf/util/intel-pt-decoder/insn.h b/tools/perf/util/intel-pt-decoder/insn.h index dd12da0..e23578c 100644 --- a/tools/perf/util/intel-pt-decoder/insn.h +++ b/tools/perf/util/intel-pt-decoder/insn.h @@ -91,6 +91,7 @@ struct insn { #define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */ #define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */ /* VEX bit fields */ +#define X86_EVEX_M(vex) ((vex) & 0x03) /* EVEX Byte1 */ #define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */ #define X86_VEX2_M 1 /* VEX2.M always 1 */ #define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */ @@ -133,6 +134,13 @@ static inline int insn_is_avx(struct insn *insn) return (insn->vex_prefix.value != 0); } +static inline int insn_is_evex(struct insn *insn) +{ + if (!insn->prefixes.got) + insn_get_prefixes(insn); + return (insn->vex_prefix.nbytes == 4); +} + /* Ensure this instruction is decoded completely */ static inline int insn_complete(struct insn *insn) { @@ -144,8 +152,10 @@ static inline insn_byte_t insn_vex_m_bits(struct insn *insn) { if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */ return X86_VEX2_M; - else + else if (insn->vex_prefix.nbytes == 3) /* 3 bytes VEX */ return X86_VEX3_M(insn->vex_prefix.bytes[1]); + else /* EVEX */ + return X86_EVEX_M(insn->vex_prefix.bytes[1]); } static inline insn_byte_t insn_vex_p_bits(struct insn *insn) diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt index 28082de..ec378cd 100644 --- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt +++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt @@ -13,12 +13,17 @@ # opcode: escape # escaped-name # EndTable # +# mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix +# mnemonics that begin with lowercase 'k' accept a VEX prefix +# #<group maps> # GrpTable: GrpXXX # reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...] # EndTable # # AVX Superscripts +# (ev): this opcode requires EVEX prefix. +# (evo): this opcode is changed by EVEX prefix (EVEX opcode) # (v): this opcode requires VEX prefix. # (v1): this opcode only supports 128bit VEX. # @@ -137,7 +142,7 @@ AVXcode: # 0x60 - 0x6f 60: PUSHA/PUSHAD (i64) 61: POPA/POPAD (i64) -62: BOUND Gv,Ma (i64) +62: BOUND Gv,Ma (i64) | EVEX (Prefix) 63: ARPL Ew,Gw (i64) | MOVSXD Gv,Ev (o64) 64: SEG=FS (Prefix) 65: SEG=GS (Prefix) @@ -399,17 +404,17 @@ AVXcode: 1 3f: # 0x0f 0x40-0x4f 40: CMOVO Gv,Ev -41: CMOVNO Gv,Ev -42: CMOVB/C/NAE Gv,Ev +41: CMOVNO Gv,Ev | kandw/q Vk,Hk,Uk | kandb/d Vk,Hk,Uk (66) +42: CMOVB/C/NAE Gv,Ev | kandnw/q Vk,Hk,Uk | kandnb/d Vk,Hk,Uk (66) 43: CMOVAE/NB/NC Gv,Ev -44: CMOVE/Z Gv,Ev -45: CMOVNE/NZ Gv,Ev -46: CMOVBE/NA Gv,Ev -47: CMOVA/NBE Gv,Ev +44: CMOVE/Z Gv,Ev | knotw/q Vk,Uk | knotb/d Vk,Uk (66) +45: CMOVNE/NZ Gv,Ev | korw/q Vk,Hk,Uk | korb/d Vk,Hk,Uk (66) +46: CMOVBE/NA Gv,Ev | kxnorw/q Vk,Hk,Uk | kxnorb/d Vk,Hk,Uk (66) +47: CMOVA/NBE Gv,Ev | kxorw/q Vk,Hk,Uk | kxorb/d Vk,Hk,Uk (66) 48: CMOVS Gv,Ev 49: CMOVNS Gv,Ev -4a: CMOVP/PE Gv,Ev -4b: CMOVNP/PO Gv,Ev +4a: CMOVP/PE Gv,Ev | kaddw/q Vk,Hk,Uk | kaddb/d Vk,Hk,Uk (66) +4b: CMOVNP/PO Gv,Ev | kunpckbw Vk,Hk,Uk (66) | kunpckwd/dq Vk,Hk,Uk 4c: CMOVL/NGE Gv,Ev 4d: CMOVNL/GE Gv,Ev 4e: CMOVLE/NG Gv,Ev @@ -426,7 +431,7 @@ AVXcode: 1 58: vaddps Vps,Hps,Wps | vaddpd Vpd,Hpd,Wpd (66) | vaddss Vss,Hss,Wss (F3),(v1) | vaddsd Vsd,Hsd,Wsd (F2),(v1) 59: vmulps Vps,Hps,Wps | vmulpd Vpd,Hpd,Wpd (66) | vmulss Vss,Hss,Wss (F3),(v1) | vmulsd Vsd,Hsd,Wsd (F2),(v1) 5a: vcvtps2pd Vpd,Wps | vcvtpd2ps Vps,Wpd (66) | vcvtss2sd Vsd,Hx,Wss (F3),(v1) | vcvtsd2ss Vss,Hx,Wsd (F2),(v1) -5b: vcvtdq2ps Vps,Wdq | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) +5b: vcvtdq2ps Vps,Wdq | vcvtqq2ps Vps,Wqq (evo) | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) 5c: vsubps Vps,Hps,Wps | vsubpd Vpd,Hpd,Wpd (66) | vsubss Vss,Hss,Wss (F3),(v1) | vsubsd Vsd,Hsd,Wsd (F2),(v1) 5d: vminps Vps,Hps,Wps | vminpd Vpd,Hpd,Wpd (66) | vminss Vss,Hss,Wss (F3),(v1) | vminsd Vsd,Hsd,Wsd (F2),(v1) 5e: vdivps Vps,Hps,Wps | vdivpd Vpd,Hpd,Wpd (66) | vdivss Vss,Hss,Wss (F3),(v1) | vdivsd Vsd,Hsd,Wsd (F2),(v1) @@ -447,7 +452,7 @@ AVXcode: 1 6c: vpunpcklqdq Vx,Hx,Wx (66),(v1) 6d: vpunpckhqdq Vx,Hx,Wx (66),(v1) 6e: movd/q Pd,Ey | vmovd/q Vy,Ey (66),(v1) -6f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqu Vx,Wx (F3) +6f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqa32/64 Vx,Wx (66),(evo) | vmovdqu Vx,Wx (F3) | vmovdqu32/64 Vx,Wx (F3),(evo) | vmovdqu8/16 Vx,Wx (F2),(ev) # 0x0f 0x70-0x7f 70: pshufw Pq,Qq,Ib | vpshufd Vx,Wx,Ib (66),(v1) | vpshufhw Vx,Wx,Ib (F3),(v1) | vpshuflw Vx,Wx,Ib (F2),(v1) 71: Grp12 (1A) @@ -458,14 +463,14 @@ AVXcode: 1 76: pcmpeqd Pq,Qq | vpcmpeqd Vx,Hx,Wx (66),(v1) # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX. 77: emms | vzeroupper | vzeroall -78: VMREAD Ey,Gy -79: VMWRITE Gy,Ey -7a: -7b: +78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) +79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) +7a: vcvtudq2pd/uqq2pd Vpd,Wx (F3),(ev) | vcvtudq2ps/uqq2ps Vpd,Wx (F2),(ev) | vcvttps2qq/pd2qq Vx,Wx (66),(ev) +7b: vcvtusi2sd Vpd,Hpd,Ev (F2),(ev) | vcvtusi2ss Vps,Hps,Ev (F3),(ev) | vcvtps2qq/pd2qq Vx,Wx (66),(ev) 7c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2) 7d: vhsubpd Vpd,Hpd,Wpd (66) | vhsubps Vps,Hps,Wps (F2) 7e: movd/q Ey,Pd | vmovd/q Ey,Vy (66),(v1) | vmovq Vq,Wq (F3),(v1) -7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqu Wx,Vx (F3) +7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev) # 0x0f 0x80-0x8f # Note: "forced64" is Intel CPU behavior (see comment about CALL insn). 80: JO Jz (f64) @@ -485,16 +490,16 @@ AVXcode: 1 8e: JLE/JNG Jz (f64) 8f: JNLE/JG Jz (f64) # 0x0f 0x90-0x9f -90: SETO Eb -91: SETNO Eb -92: SETB/C/NAE Eb -93: SETAE/NB/NC Eb +90: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66) +91: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66) +92: SETB/C/NAE Eb | kmovw Vk,Rv | kmovb Vk,Rv (66) | kmovq/d Vk,Rv (F2) +93: SETAE/NB/NC Eb | kmovw Gv,Uk | kmovb Gv,Uk (66) | kmovq/d Gv,Uk (F2) 94: SETE/Z Eb 95: SETNE/NZ Eb 96: SETBE/NA Eb 97: SETA/NBE Eb -98: SETS Eb -99: SETNS Eb +98: SETS Eb | kortestw/q Vk,Uk | kortestb/d Vk,Uk (66) +99: SETNS Eb | ktestw/q Vk,Uk | ktestb/d Vk,Uk (66) 9a: SETP/PE Eb 9b: SETNP/PO Eb 9c: SETL/NGE Eb @@ -564,11 +569,11 @@ d7: pmovmskb Gd,Nq | vpmovmskb Gd,Ux (66),(v1) d8: psubusb Pq,Qq | vpsubusb Vx,Hx,Wx (66),(v1) d9: psubusw Pq,Qq | vpsubusw Vx,Hx,Wx (66),(v1) da: pminub Pq,Qq | vpminub Vx,Hx,Wx (66),(v1) -db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1) +db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1) | vpandd/q Vx,Hx,Wx (66),(evo) dc: paddusb Pq,Qq | vpaddusb Vx,Hx,Wx (66),(v1) dd: paddusw Pq,Qq | vpaddusw Vx,Hx,Wx (66),(v1) de: pmaxub Pq,Qq | vpmaxub Vx,Hx,Wx (66),(v1) -df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1) +df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1) | vpandnd/q Vx,Hx,Wx (66),(evo) # 0x0f 0xe0-0xef e0: pavgb Pq,Qq | vpavgb Vx,Hx,Wx (66),(v1) e1: psraw Pq,Qq | vpsraw Vx,Hx,Wx (66),(v1) @@ -576,16 +581,16 @@ e2: psrad Pq,Qq | vpsrad Vx,Hx,Wx (66),(v1) e3: pavgw Pq,Qq | vpavgw Vx,Hx,Wx (66),(v1) e4: pmulhuw Pq,Qq | vpmulhuw Vx,Hx,Wx (66),(v1) e5: pmulhw Pq,Qq | vpmulhw Vx,Hx,Wx (66),(v1) -e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtpd2dq Vx,Wpd (F2) +e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtdq2pd/qq2pd Vx,Wdq (F3),(evo) | vcvtpd2dq Vx,Wpd (F2) e7: movntq Mq,Pq | vmovntdq Mx,Vx (66) e8: psubsb Pq,Qq | vpsubsb Vx,Hx,Wx (66),(v1) e9: psubsw Pq,Qq | vpsubsw Vx,Hx,Wx (66),(v1) ea: pminsw Pq,Qq | vpminsw Vx,Hx,Wx (66),(v1) -eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1) +eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1) | vpord/q Vx,Hx,Wx (66),(evo) ec: paddsb Pq,Qq | vpaddsb Vx,Hx,Wx (66),(v1) ed: paddsw Pq,Qq | vpaddsw Vx,Hx,Wx (66),(v1) ee: pmaxsw Pq,Qq | vpmaxsw Vx,Hx,Wx (66),(v1) -ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1) +ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1) | vpxord/q Vx,Hx,Wx (66),(evo) # 0x0f 0xf0-0xff f0: vlddqu Vx,Mx (F2) f1: psllw Pq,Qq | vpsllw Vx,Hx,Wx (66),(v1) @@ -626,81 +631,105 @@ AVXcode: 2 0e: vtestps Vx,Wx (66),(v) 0f: vtestpd Vx,Wx (66),(v) # 0x0f 0x38 0x10-0x1f -10: pblendvb Vdq,Wdq (66) -11: -12: -13: vcvtph2ps Vx,Wx (66),(v) -14: blendvps Vdq,Wdq (66) -15: blendvpd Vdq,Wdq (66) -16: vpermps Vqq,Hqq,Wqq (66),(v) +10: pblendvb Vdq,Wdq (66) | vpsrlvw Vx,Hx,Wx (66),(evo) | vpmovuswb Wx,Vx (F3),(ev) +11: vpmovusdb Wx,Vd (F3),(ev) | vpsravw Vx,Hx,Wx (66),(ev) +12: vpmovusqb Wx,Vq (F3),(ev) | vpsllvw Vx,Hx,Wx (66),(ev) +13: vcvtph2ps Vx,Wx (66),(v) | vpmovusdw Wx,Vd (F3),(ev) +14: blendvps Vdq,Wdq (66) | vpmovusqw Wx,Vq (F3),(ev) | vprorvd/q Vx,Hx,Wx (66),(evo) +15: blendvpd Vdq,Wdq (66) | vpmovusqd Wx,Vq (F3),(ev) | vprolvd/q Vx,Hx,Wx (66),(evo) +16: vpermps Vqq,Hqq,Wqq (66),(v) | vpermps/d Vqq,Hqq,Wqq (66),(evo) 17: vptest Vx,Wx (66) 18: vbroadcastss Vx,Wd (66),(v) -19: vbroadcastsd Vqq,Wq (66),(v) -1a: vbroadcastf128 Vqq,Mdq (66),(v) -1b: +19: vbroadcastsd Vqq,Wq (66),(v) | vbroadcastf32x2 Vqq,Wq (66),(evo) +1a: vbroadcastf128 Vqq,Mdq (66),(v) | vbroadcastf32x4/64x2 Vqq,Wq (66),(evo) +1b: vbroadcastf32x8/64x4 Vqq,Mdq (66),(ev) 1c: pabsb Pq,Qq | vpabsb Vx,Wx (66),(v1) 1d: pabsw Pq,Qq | vpabsw Vx,Wx (66),(v1) 1e: pabsd Pq,Qq | vpabsd Vx,Wx (66),(v1) -1f: +1f: vpabsq Vx,Wx (66),(ev) # 0x0f 0x38 0x20-0x2f -20: vpmovsxbw Vx,Ux/Mq (66),(v1) -21: vpmovsxbd Vx,Ux/Md (66),(v1) -22: vpmovsxbq Vx,Ux/Mw (66),(v1) -23: vpmovsxwd Vx,Ux/Mq (66),(v1) -24: vpmovsxwq Vx,Ux/Md (66),(v1) -25: vpmovsxdq Vx,Ux/Mq (66),(v1) -26: -27: -28: vpmuldq Vx,Hx,Wx (66),(v1) -29: vpcmpeqq Vx,Hx,Wx (66),(v1) -2a: vmovntdqa Vx,Mx (66),(v1) +20: vpmovsxbw Vx,Ux/Mq (66),(v1) | vpmovswb Wx,Vx (F3),(ev) +21: vpmovsxbd Vx,Ux/Md (66),(v1) | vpmovsdb Wx,Vd (F3),(ev) +22: vpmovsxbq Vx,Ux/Mw (66),(v1) | vpmovsqb Wx,Vq (F3),(ev) +23: vpmovsxwd Vx,Ux/Mq (66),(v1) | vpmovsdw Wx,Vd (F3),(ev) +24: vpmovsxwq Vx,Ux/Md (66),(v1) | vpmovsqw Wx,Vq (F3),(ev) +25: vpmovsxdq Vx,Ux/Mq (66),(v1) | vpmovsqd Wx,Vq (F3),(ev) +26: vptestmb/w Vk,Hx,Wx (66),(ev) | vptestnmb/w Vk,Hx,Wx (F3),(ev) +27: vptestmd/q Vk,Hx,Wx (66),(ev) | vptestnmd/q Vk,Hx,Wx (F3),(ev) +28: vpmuldq Vx,Hx,Wx (66),(v1) | vpmovm2b/w Vx,Uk (F3),(ev) +29: vpcmpeqq Vx,Hx,Wx (66),(v1) | vpmovb2m/w2m Vk,Ux (F3),(ev) +2a: vmovntdqa Vx,Mx (66),(v1) | vpbroadcastmb2q Vx,Uk (F3),(ev) 2b: vpackusdw Vx,Hx,Wx (66),(v1) -2c: vmaskmovps Vx,Hx,Mx (66),(v) -2d: vmaskmovpd Vx,Hx,Mx (66),(v) +2c: vmaskmovps Vx,Hx,Mx (66),(v) | vscalefps/d Vx,Hx,Wx (66),(evo) +2d: vmaskmovpd Vx,Hx,Mx (66),(v) | vscalefss/d Vx,Hx,Wx (66),(evo) 2e: vmaskmovps Mx,Hx,Vx (66),(v) 2f: vmaskmovpd Mx,Hx,Vx (66),(v) # 0x0f 0x38 0x30-0x3f -30: vpmovzxbw Vx,Ux/Mq (66),(v1) -31: vpmovzxbd Vx,Ux/Md (66),(v1) -32: vpmovzxbq Vx,Ux/Mw (66),(v1) -33: vpmovzxwd Vx,Ux/Mq (66),(v1) -34: vpmovzxwq Vx,Ux/Md (66),(v1) -35: vpmovzxdq Vx,Ux/Mq (66),(v1) -36: vpermd Vqq,Hqq,Wqq (66),(v) +30: vpmovzxbw Vx,Ux/Mq (66),(v1) | vpmovwb Wx,Vx (F3),(ev) +31: vpmovzxbd Vx,Ux/Md (66),(v1) | vpmovdb Wx,Vd (F3),(ev) +32: vpmovzxbq Vx,Ux/Mw (66),(v1) | vpmovqb Wx,Vq (F3),(ev) +33: vpmovzxwd Vx,Ux/Mq (66),(v1) | vpmovdw Wx,Vd (F3),(ev) +34: vpmovzxwq Vx,Ux/Md (66),(v1) | vpmovqw Wx,Vq (F3),(ev) +35: vpmovzxdq Vx,Ux/Mq (66),(v1) | vpmovqd Wx,Vq (F3),(ev) +36: vpermd Vqq,Hqq,Wqq (66),(v) | vpermd/q Vqq,Hqq,Wqq (66),(evo) 37: vpcmpgtq Vx,Hx,Wx (66),(v1) -38: vpminsb Vx,Hx,Wx (66),(v1) -39: vpminsd Vx,Hx,Wx (66),(v1) -3a: vpminuw Vx,Hx,Wx (66),(v1) -3b: vpminud Vx,Hx,Wx (66),(v1) +38: vpminsb Vx,Hx,Wx (66),(v1) | vpmovm2d/q Vx,Uk (F3),(ev) +39: vpminsd Vx,Hx,Wx (66),(v1) | vpminsd/q Vx,Hx,Wx (66),(evo) | vpmovd2m/q2m Vk,Ux (F3),(ev) +3a: vpminuw Vx,Hx,Wx (66),(v1) | vpbroadcastmw2d Vx,Uk (F3),(ev) +3b: vpminud Vx,Hx,Wx (66),(v1) | vpminud/q Vx,Hx,Wx (66),(evo) 3c: vpmaxsb Vx,Hx,Wx (66),(v1) -3d: vpmaxsd Vx,Hx,Wx (66),(v1) +3d: vpmaxsd Vx,Hx,Wx (66),(v1) | vpmaxsd/q Vx,Hx,Wx (66),(evo) 3e: vpmaxuw Vx,Hx,Wx (66),(v1) -3f: vpmaxud Vx,Hx,Wx (66),(v1) +3f: vpmaxud Vx,Hx,Wx (66),(v1) | vpmaxud/q Vx,Hx,Wx (66),(evo) # 0x0f 0x38 0x40-0x8f -40: vpmulld Vx,Hx,Wx (66),(v1) +40: vpmulld Vx,Hx,Wx (66),(v1) | vpmulld/q Vx,Hx,Wx (66),(evo) 41: vphminposuw Vdq,Wdq (66),(v1) -42: -43: -44: +42: vgetexpps/d Vx,Wx (66),(ev) +43: vgetexpss/d Vx,Hx,Wx (66),(ev) +44: vplzcntd/q Vx,Wx (66),(ev) 45: vpsrlvd/q Vx,Hx,Wx (66),(v) -46: vpsravd Vx,Hx,Wx (66),(v) +46: vpsravd Vx,Hx,Wx (66),(v) | vpsravd/q Vx,Hx,Wx (66),(evo) 47: vpsllvd/q Vx,Hx,Wx (66),(v) -# Skip 0x48-0x57 +# Skip 0x48-0x4b +4c: vrcp14ps/d Vpd,Wpd (66),(ev) +4d: vrcp14ss/d Vsd,Hpd,Wsd (66),(ev) +4e: vrsqrt14ps/d Vpd,Wpd (66),(ev) +4f: vrsqrt14ss/d Vsd,Hsd,Wsd (66),(ev) +# Skip 0x50-0x57 58: vpbroadcastd Vx,Wx (66),(v) -59: vpbroadcastq Vx,Wx (66),(v) -5a: vbroadcasti128 Vqq,Mdq (66),(v) -# Skip 0x5b-0x77 +59: vpbroadcastq Vx,Wx (66),(v) | vbroadcasti32x2 Vx,Wx (66),(evo) +5a: vbroadcasti128 Vqq,Mdq (66),(v) | vbroadcasti32x4/64x2 Vx,Wx (66),(evo) +5b: vbroadcasti32x8/64x4 Vqq,Mdq (66),(ev) +# Skip 0x5c-0x63 +64: vpblendmd/q Vx,Hx,Wx (66),(ev) +65: vblendmps/d Vx,Hx,Wx (66),(ev) +66: vpblendmb/w Vx,Hx,Wx (66),(ev) +# Skip 0x67-0x74 +75: vpermi2b/w Vx,Hx,Wx (66),(ev) +76: vpermi2d/q Vx,Hx,Wx (66),(ev) +77: vpermi2ps/d Vx,Hx,Wx (66),(ev) 78: vpbroadcastb Vx,Wx (66),(v) 79: vpbroadcastw Vx,Wx (66),(v) -# Skip 0x7a-0x7f +7a: vpbroadcastb Vx,Rv (66),(ev) +7b: vpbroadcastw Vx,Rv (66),(ev) +7c: vpbroadcastd/q Vx,Rv (66),(ev) +7d: vpermt2b/w Vx,Hx,Wx (66),(ev) +7e: vpermt2d/q Vx,Hx,Wx (66),(ev) +7f: vpermt2ps/d Vx,Hx,Wx (66),(ev) 80: INVEPT Gy,Mdq (66) 81: INVPID Gy,Mdq (66) 82: INVPCID Gy,Mdq (66) +83: vpmultishiftqb Vx,Hx,Wx (66),(ev) +88: vexpandps/d Vpd,Wpd (66),(ev) +89: vpexpandd/q Vx,Wx (66),(ev) +8a: vcompressps/d Wx,Vx (66),(ev) +8b: vpcompressd/q Wx,Vx (66),(ev) 8c: vpmaskmovd/q Vx,Hx,Mx (66),(v) +8d: vpermb/w Vx,Hx,Wx (66),(ev) 8e: vpmaskmovd/q Mx,Vx,Hx (66),(v) # 0x0f 0x38 0x90-0xbf (FMA) -90: vgatherdd/q Vx,Hx,Wx (66),(v) -91: vgatherqd/q Vx,Hx,Wx (66),(v) +90: vgatherdd/q Vx,Hx,Wx (66),(v) | vpgatherdd/q Vx,Wx (66),(evo) +91: vgatherqd/q Vx,Hx,Wx (66),(v) | vpgatherqd/q Vx,Wx (66),(evo) 92: vgatherdps/d Vx,Hx,Wx (66),(v) 93: vgatherqps/d Vx,Hx,Wx (66),(v) 94: @@ -715,6 +744,10 @@ AVXcode: 2 9d: vfnmadd132ss/d Vx,Hx,Wx (66),(v),(v1) 9e: vfnmsub132ps/d Vx,Hx,Wx (66),(v) 9f: vfnmsub132ss/d Vx,Hx,Wx (66),(v),(v1) +a0: vpscatterdd/q Wx,Vx (66),(ev) +a1: vpscatterqd/q Wx,Vx (66),(ev) +a2: vscatterdps/d Wx,Vx (66),(ev) +a3: vscatterqps/d Wx,Vx (66),(ev) a6: vfmaddsub213ps/d Vx,Hx,Wx (66),(v) a7: vfmsubadd213ps/d Vx,Hx,Wx (66),(v) a8: vfmadd213ps/d Vx,Hx,Wx (66),(v) @@ -725,6 +758,8 @@ ac: vfnmadd213ps/d Vx,Hx,Wx (66),(v) ad: vfnmadd213ss/d Vx,Hx,Wx (66),(v),(v1) ae: vfnmsub213ps/d Vx,Hx,Wx (66),(v) af: vfnmsub213ss/d Vx,Hx,Wx (66),(v),(v1) +b4: vpmadd52luq Vx,Hx,Wx (66),(ev) +b5: vpmadd52huq Vx,Hx,Wx (66),(ev) b6: vfmaddsub231ps/d Vx,Hx,Wx (66),(v) b7: vfmsubadd231ps/d Vx,Hx,Wx (66),(v) b8: vfmadd231ps/d Vx,Hx,Wx (66),(v) @@ -736,12 +771,15 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1) be: vfnmsub231ps/d Vx,Hx,Wx (66),(v) bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1) # 0x0f 0x38 0xc0-0xff -c8: sha1nexte Vdq,Wdq +c4: vpconflictd/q Vx,Wx (66),(ev) +c6: Grp18 (1A) +c7: Grp19 (1A) +c8: sha1nexte Vdq,Wdq | vexp2ps/d Vx,Wx (66),(ev) c9: sha1msg1 Vdq,Wdq -ca: sha1msg2 Vdq,Wdq -cb: sha256rnds2 Vdq,Wdq -cc: sha256msg1 Vdq,Wdq -cd: sha256msg2 Vdq,Wdq +ca: sha1msg2 Vdq,Wdq | vrcp28ps/d Vx,Wx (66),(ev) +cb: sha256rnds2 Vdq,Wdq | vrcp28ss/d Vx,Hx,Wx (66),(ev) +cc: sha256msg1 Vdq,Wdq | vrsqrt28ps/d Vx,Wx (66),(ev) +cd: sha256msg2 Vdq,Wdq | vrsqrt28ss/d Vx,Hx,Wx (66),(ev) db: VAESIMC Vdq,Wdq (66),(v1) dc: VAESENC Vdq,Hdq,Wdq (66),(v1) dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1) @@ -763,15 +801,15 @@ AVXcode: 3 00: vpermq Vqq,Wqq,Ib (66),(v) 01: vpermpd Vqq,Wqq,Ib (66),(v) 02: vpblendd Vx,Hx,Wx,Ib (66),(v) -03: +03: valignd/q Vx,Hx,Wx,Ib (66),(ev) 04: vpermilps Vx,Wx,Ib (66),(v) 05: vpermilpd Vx,Wx,Ib (66),(v) 06: vperm2f128 Vqq,Hqq,Wqq,Ib (66),(v) 07: -08: vroundps Vx,Wx,Ib (66) -09: vroundpd Vx,Wx,Ib (66) -0a: vroundss Vss,Wss,Ib (66),(v1) -0b: vroundsd Vsd,Wsd,Ib (66),(v1) +08: vroundps Vx,Wx,Ib (66) | vrndscaleps Vx,Wx,Ib (66),(evo) +09: vroundpd Vx,Wx,Ib (66) | vrndscalepd Vx,Wx,Ib (66),(evo) +0a: vroundss Vss,Wss,Ib (66),(v1) | vrndscaless Vx,Hx,Wx,Ib (66),(evo) +0b: vroundsd Vsd,Wsd,Ib (66),(v1) | vrndscalesd Vx,Hx,Wx,Ib (66),(evo) 0c: vblendps Vx,Hx,Wx,Ib (66) 0d: vblendpd Vx,Hx,Wx,Ib (66) 0e: vpblendw Vx,Hx,Wx,Ib (66),(v1) @@ -780,26 +818,51 @@ AVXcode: 3 15: vpextrw Rd/Mw,Vdq,Ib (66),(v1) 16: vpextrd/q Ey,Vdq,Ib (66),(v1) 17: vextractps Ed,Vdq,Ib (66),(v1) -18: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v) -19: vextractf128 Wdq,Vqq,Ib (66),(v) +18: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v) | vinsertf32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo) +19: vextractf128 Wdq,Vqq,Ib (66),(v) | vextractf32x4/64x2 Wdq,Vqq,Ib (66),(evo) +1a: vinsertf32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev) +1b: vextractf32x8/64x4 Wdq,Vqq,Ib (66),(ev) 1d: vcvtps2ph Wx,Vx,Ib (66),(v) +1e: vpcmpud/q Vk,Hd,Wd,Ib (66),(ev) +1f: vpcmpd/q Vk,Hd,Wd,Ib (66),(ev) 20: vpinsrb Vdq,Hdq,Ry/Mb,Ib (66),(v1) 21: vinsertps Vdq,Hdq,Udq/Md,Ib (66),(v1) 22: vpinsrd/q Vdq,Hdq,Ey,Ib (66),(v1) -38: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v) -39: vextracti128 Wdq,Vqq,Ib (66),(v) +23: vshuff32x4/64x2 Vx,Hx,Wx,Ib (66),(ev) +25: vpternlogd/q Vx,Hx,Wx,Ib (66),(ev) +26: vgetmantps/d Vx,Wx,Ib (66),(ev) +27: vgetmantss/d Vx,Hx,Wx,Ib (66),(ev) +30: kshiftrb/w Vk,Uk,Ib (66),(v) +31: kshiftrd/q Vk,Uk,Ib (66),(v) +32: kshiftlb/w Vk,Uk,Ib (66),(v) +33: kshiftld/q Vk,Uk,Ib (66),(v) +38: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v) | vinserti32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo) +39: vextracti128 Wdq,Vqq,Ib (66),(v) | vextracti32x4/64x2 Wdq,Vqq,Ib (66),(evo) +3a: vinserti32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev) +3b: vextracti32x8/64x4 Wdq,Vqq,Ib (66),(ev) +3e: vpcmpub/w Vk,Hk,Wx,Ib (66),(ev) +3f: vpcmpb/w Vk,Hk,Wx,Ib (66),(ev) 40: vdpps Vx,Hx,Wx,Ib (66) 41: vdppd Vdq,Hdq,Wdq,Ib (66),(v1) -42: vmpsadbw Vx,Hx,Wx,Ib (66),(v1) +42: vmpsadbw Vx,Hx,Wx,Ib (66),(v1) | vdbpsadbw Vx,Hx,Wx,Ib (66),(evo) +43: vshufi32x4/64x2 Vx,Hx,Wx,Ib (66),(ev) 44: vpclmulqdq Vdq,Hdq,Wdq,Ib (66),(v1) 46: vperm2i128 Vqq,Hqq,Wqq,Ib (66),(v) 4a: vblendvps Vx,Hx,Wx,Lx (66),(v) 4b: vblendvpd Vx,Hx,Wx,Lx (66),(v) 4c: vpblendvb Vx,Hx,Wx,Lx (66),(v1) +50: vrangeps/d Vx,Hx,Wx,Ib (66),(ev) +51: vrangess/d Vx,Hx,Wx,Ib (66),(ev) +54: vfixupimmps/d Vx,Hx,Wx,Ib (66),(ev) +55: vfixupimmss/d Vx,Hx,Wx,Ib (66),(ev) +56: vreduceps/d Vx,Wx,Ib (66),(ev) +57: vreducess/d Vx,Hx,Wx,Ib (66),(ev) 60: vpcmpestrm Vdq,Wdq,Ib (66),(v1) 61: vpcmpestri Vdq,Wdq,Ib (66),(v1) 62: vpcmpistrm Vdq,Wdq,Ib (66),(v1) 63: vpcmpistri Vdq,Wdq,Ib (66),(v1) +66: vfpclassps/d Vk,Wx,Ib (66),(ev) +67: vfpclassss/d Vk,Wx,Ib (66),(ev) cc: sha1rnds4 Vdq,Wdq,Ib df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1) f0: RORX Gy,Ey,Ib (F2),(v) @@ -927,8 +990,10 @@ GrpTable: Grp12 EndTable GrpTable: Grp13 +0: vprord/q Hx,Wx,Ib (66),(ev) +1: vprold/q Hx,Wx,Ib (66),(ev) 2: psrld Nq,Ib (11B) | vpsrld Hx,Ux,Ib (66),(11B),(v1) -4: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1) +4: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1) | vpsrad/q Hx,Ux,Ib (66),(evo) 6: pslld Nq,Ib (11B) | vpslld Hx,Ux,Ib (66),(11B),(v1) EndTable @@ -963,6 +1028,20 @@ GrpTable: Grp17 3: BLSI By,Ey (v) EndTable +GrpTable: Grp18 +1: vgatherpf0dps/d Wx (66),(ev) +2: vgatherpf1dps/d Wx (66),(ev) +5: vscatterpf0dps/d Wx (66),(ev) +6: vscatterpf1dps/d Wx (66),(ev) +EndTable + +GrpTable: Grp19 +1: vgatherpf0qps/d Wx (66),(ev) +2: vgatherpf1qps/d Wx (66),(ev) +5: vscatterpf0qps/d Wx (66),(ev) +6: vscatterpf1qps/d Wx (66),(ev) +EndTable + # AMD's Prefetch Group GrpTable: GrpP 0: PREFETCH ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V2 4/4] perf tools: Add AVX-512 instructions to the new instructions test 2016-07-20 8:30 [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Adrian Hunter ` (2 preceding siblings ...) 2016-07-20 8:30 ` [PATCH V2 3/4] perf tools: Add AVX-512 support to the instruction decoder used by Intel PT Adrian Hunter @ 2016-07-20 8:30 ` Adrian Hunter 2016-07-25 18:09 ` [tip:perf/core] " tip-bot for Adrian Hunter 2016-07-20 18:11 ` [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Masami Hiramatsu 4 siblings, 1 reply; 18+ messages in thread From: Adrian Hunter @ 2016-07-20 8:30 UTC (permalink / raw) To: linux-kernel Cc: Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Masami Hiramatsu, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML Previous patches added support for Intel's AVX-512 instructions to the kernel and perf tools instruction decoders. AVX-512 instructions are documented in Intel Architecture Instruction Set Extensions Programming Reference (February 2016). Add a representative set of instructions to the perf tools new instructions test. e.g. perf test "new instructions" Or to view a particular instruction: perf test -v "new instructions" 2>&1 | grep vbroadcasti64x4 Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> --- tools/perf/arch/x86/tests/insn-x86-dat-32.c | 1016 ++++++++++++++- tools/perf/arch/x86/tests/insn-x86-dat-64.c | 938 +++++++++++++- tools/perf/arch/x86/tests/insn-x86-dat-src.c | 1785 ++++++++++++++++++++++++++ 3 files changed, 3731 insertions(+), 8 deletions(-) diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c index ca08e6eb988f..3918dd52e903 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-32.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c @@ -8,6 +8,1014 @@ "0f 31 \trdtsc ",}, {{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "", "c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",}, +{{0x62, 0x81, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 81 78 56 34 12 \tbound %eax,0x12345678(%ecx)",}, +{{0x62, 0x88, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 88 78 56 34 12 \tbound %ecx,0x12345678(%eax)",}, +{{0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 90 78 56 34 12 \tbound %edx,0x12345678(%eax)",}, +{{0x62, 0x98, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 98 78 56 34 12 \tbound %ebx,0x12345678(%eax)",}, +{{0x62, 0xa0, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 a0 78 56 34 12 \tbound %esp,0x12345678(%eax)",}, +{{0x62, 0xa8, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 a8 78 56 34 12 \tbound %ebp,0x12345678(%eax)",}, +{{0x62, 0xb0, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 b0 78 56 34 12 \tbound %esi,0x12345678(%eax)",}, +{{0x62, 0xb8, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 b8 78 56 34 12 \tbound %edi,0x12345678(%eax)",}, +{{0x62, 0x08, }, 2, 0, "", "", +"62 08 \tbound %ecx,(%eax)",}, +{{0x62, 0x05, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 05 78 56 34 12 \tbound %eax,0x12345678",}, +{{0x62, 0x14, 0x01, }, 3, 0, "", "", +"62 14 01 \tbound %edx,(%ecx,%eax,1)",}, +{{0x62, 0x14, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 14 05 78 56 34 12 \tbound %edx,0x12345678(,%eax,1)",}, +{{0x62, 0x14, 0x08, }, 3, 0, "", "", +"62 14 08 \tbound %edx,(%eax,%ecx,1)",}, +{{0x62, 0x14, 0xc8, }, 3, 0, "", "", +"62 14 c8 \tbound %edx,(%eax,%ecx,8)",}, +{{0x62, 0x50, 0x12, }, 3, 0, "", "", +"62 50 12 \tbound %edx,0x12(%eax)",}, +{{0x62, 0x55, 0x12, }, 3, 0, "", "", +"62 55 12 \tbound %edx,0x12(%ebp)",}, +{{0x62, 0x54, 0x01, 0x12, }, 4, 0, "", "", +"62 54 01 12 \tbound %edx,0x12(%ecx,%eax,1)",}, +{{0x62, 0x54, 0x05, 0x12, }, 4, 0, "", "", +"62 54 05 12 \tbound %edx,0x12(%ebp,%eax,1)",}, +{{0x62, 0x54, 0x08, 0x12, }, 4, 0, "", "", +"62 54 08 12 \tbound %edx,0x12(%eax,%ecx,1)",}, +{{0x62, 0x54, 0xc8, 0x12, }, 4, 0, "", "", +"62 54 c8 12 \tbound %edx,0x12(%eax,%ecx,8)",}, +{{0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 90 78 56 34 12 \tbound %edx,0x12345678(%eax)",}, +{{0x62, 0x95, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 95 78 56 34 12 \tbound %edx,0x12345678(%ebp)",}, +{{0x62, 0x94, 0x01, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 94 01 78 56 34 12 \tbound %edx,0x12345678(%ecx,%eax,1)",}, +{{0x62, 0x94, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 94 05 78 56 34 12 \tbound %edx,0x12345678(%ebp,%eax,1)",}, +{{0x62, 0x94, 0x08, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 94 08 78 56 34 12 \tbound %edx,0x12345678(%eax,%ecx,1)",}, +{{0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 94 c8 78 56 34 12 \tbound %edx,0x12345678(%eax,%ecx,8)",}, +{{0x66, 0x62, 0x81, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"66 62 81 78 56 34 12 \tbound %ax,0x12345678(%ecx)",}, +{{0x66, 0x62, 0x88, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"66 62 88 78 56 34 12 \tbound %cx,0x12345678(%eax)",}, +{{0x66, 0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"66 62 90 78 56 34 12 \tbound %dx,0x12345678(%eax)",}, +{{0x66, 0x62, 0x98, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", 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+"62 f1 4d 48 72 cd 12 \tvprold $0x12,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xcd, 0x48, 0x72, 0xcd, 0x12, }, 7, 0, "", "", +"62 f1 cd 48 72 cd 12 \tvprolq $0x12,%zmm5,%zmm6",}, +{{0x0f, 0x72, 0xe6, 0x02, }, 4, 0, "", "", +"0f 72 e6 02 \tpsrad $0x2,%mm6",}, +{{0xc5, 0xed, 0x72, 0xe6, 0x05, }, 5, 0, "", "", +"c5 ed 72 e6 05 \tvpsrad $0x5,%ymm6,%ymm2",}, +{{0x62, 0xf1, 0x6d, 0x48, 0x72, 0xe6, 0x05, }, 7, 0, "", "", +"62 f1 6d 48 72 e6 05 \tvpsrad $0x5,%zmm6,%zmm2",}, +{{0x62, 0xf1, 0xed, 0x48, 0x72, 0xe6, 0x05, }, 7, 0, "", "", +"62 f1 ed 48 72 e6 05 \tvpsraq $0x5,%zmm6,%zmm2",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c6 8c fd 7b 00 00 00 \tvgatherpf0dps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c6 8c fd 7b 00 00 00 \tvgatherpf0dpd 0x7b(%ebp,%ymm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c6 94 fd 7b 00 00 00 \tvgatherpf1dps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c6 94 fd 7b 00 00 00 \tvgatherpf1dpd 0x7b(%ebp,%ymm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c6 ac fd 7b 00 00 00 \tvscatterpf0dps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c6 ac fd 7b 00 00 00 \tvscatterpf0dpd 0x7b(%ebp,%ymm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c6 b4 fd 7b 00 00 00 \tvscatterpf1dps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c6 b4 fd 7b 00 00 00 \tvscatterpf1dpd 0x7b(%ebp,%ymm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c7 8c fd 7b 00 00 00 \tvgatherpf0qps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c7 8c fd 7b 00 00 00 \tvgatherpf0qpd 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c7 94 fd 7b 00 00 00 \tvgatherpf1qps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c7 94 fd 7b 00 00 00 \tvgatherpf1qpd 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c7 ac fd 7b 00 00 00 \tvscatterpf0qps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c7 ac fd 7b 00 00 00 \tvscatterpf0qpd 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c7 b4 fd 7b 00 00 00 \tvscatterpf1qps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c7 b4 fd 7b 00 00 00 \tvscatterpf1qpd 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 48 58 f4 \tvaddpd %zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x4f, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 4f 58 f4 \tvaddpd %zmm4,%zmm5,%zmm6{%k7}",}, +{{0x62, 0xf1, 0xd5, 0xcf, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 cf 58 f4 \tvaddpd %zmm4,%zmm5,%zmm6{%k7}{z}",}, +{{0x62, 0xf1, 0xd5, 0x18, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 18 58 f4 \tvaddpd {rn-sae},%zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x58, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 58 58 f4 \tvaddpd {ru-sae},%zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x38, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 38 58 f4 \tvaddpd {rd-sae},%zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x78, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 78 58 f4 \tvaddpd {rz-sae},%zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0x31, }, 6, 0, "", "", +"62 f1 d5 48 58 31 \tvaddpd (%ecx),%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0xb4, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 11, 0, "", "", +"62 f1 d5 48 58 b4 c8 23 01 00 00 \tvaddpd 0x123(%eax,%ecx,8),%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x58, 0x58, 0x31, }, 6, 0, "", "", +"62 f1 d5 58 58 31 \tvaddpd (%ecx){1to8},%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0x72, 0x7f, }, 7, 0, "", "", +"62 f1 d5 48 58 72 7f \tvaddpd 0x1fc0(%edx),%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x58, 0x58, 0x72, 0x7f, }, 7, 0, "", "", +"62 f1 d5 58 58 72 7f \tvaddpd 0x3f8(%edx){1to8},%zmm5,%zmm6",}, +{{0x62, 0xf1, 0x4c, 0x58, 0xc2, 0x6a, 0x7f, 0x08, }, 8, 0, "", "", +"62 f1 4c 58 c2 6a 7f 08 \tvcmpeq_uqps 0x1fc(%edx){1to16},%zmm6,%k5",}, +{{0x62, 0xf1, 0xe7, 0x0f, 0xc2, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, 0x01, }, 12, 0, "", "", +"62 f1 e7 0f c2 ac c8 23 01 00 00 01 \tvcmpltsd 0x123(%eax,%ecx,8),%xmm3,%k5{%k7}",}, +{{0x62, 0xf1, 0xd7, 0x1f, 0xc2, 0xec, 0x02, }, 7, 0, "", "", +"62 f1 d7 1f c2 ec 02 \tvcmplesd {sae},%xmm4,%xmm5,%k5{%k7}",}, +{{0x62, 0xf3, 0x5d, 0x0f, 0x27, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, 0x5b, }, 12, 0, "", "", +"62 f3 5d 0f 27 ac c8 23 01 00 00 5b \tvgetmantss $0x5b,0x123(%eax,%ecx,8),%xmm4,%xmm5{%k7}",}, {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", "f3 0f 1b 00 \tbndmk (%eax),%bnd0",}, {{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", @@ -311,19 +1319,19 @@ {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax,%ecx,1)",}, {{0xf2, 0xe8, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "call", "unconditional", -"f2 e8 fc ff ff ff \tbnd call 3c8 <main+0x3c8>",}, +"f2 e8 fc ff ff ff \tbnd call fce <main+0xfce>",}, {{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect", "f2 ff 10 \tbnd call *(%eax)",}, {{0xf2, 0xc3, }, 2, 0, "ret", "indirect", "f2 c3 \tbnd ret ",}, {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", -"f2 e9 fc ff ff ff \tbnd jmp 3d3 <main+0x3d3>",}, +"f2 e9 fc ff ff ff \tbnd jmp fd9 <main+0xfd9>",}, {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", -"f2 e9 fc ff ff ff \tbnd jmp 3d9 <main+0x3d9>",}, +"f2 e9 fc ff ff ff \tbnd jmp fdf <main+0xfdf>",}, {{0xf2, 0xff, 0x21, }, 3, 0, "jmp", "indirect", "f2 ff 21 \tbnd jmp *(%ecx)",}, {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffffffc, "jcc", "conditional", -"f2 0f 85 fc ff ff ff \tbnd jne 3e3 <main+0x3e3>",}, +"f2 0f 85 fc ff ff ff \tbnd jne fe9 <main+0xfe9>",}, {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "", "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",}, {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "", diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-64.c b/tools/perf/arch/x86/tests/insn-x86-dat-64.c index 262d9d25a6fa..9c8c61e06d5a 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-64.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-64.c @@ -8,6 +8,936 @@ "0f 31 \trdtsc ",}, {{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "", "c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",}, +{{0x48, 0x0f, 0x41, 0xd8, }, 4, 0, "", "", +"48 0f 41 d8 \tcmovno %rax,%rbx",}, +{{0x48, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"48 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%rcx",}, +{{0x66, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"66 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%cx",}, +{{0x48, 0x0f, 0x44, 0xd8, }, 4, 0, "", "", +"48 0f 44 d8 \tcmove %rax,%rbx",}, +{{0x48, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"48 0f 44 88 78 56 34 12 \tcmove 0x12345678(%rax),%rcx",}, +{{0x66, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"66 0f 44 88 78 56 34 12 \tcmove 0x12345678(%rax),%cx",}, +{{0x0f, 0x90, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 90 80 78 56 34 12 \tseto 0x12345678(%rax)",}, +{{0x0f, 0x91, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 91 80 78 56 34 12 \tsetno 0x12345678(%rax)",}, +{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",}, +{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",}, +{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",}, +{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",}, +{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",}, +{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",}, +{{0x0f, 0x98, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 98 80 78 56 34 12 \tsets 0x12345678(%rax)",}, +{{0x0f, 0x99, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 99 80 78 56 34 12 \tsetns 0x12345678(%rax)",}, +{{0xc5, 0xcc, 0x41, 0xef, }, 4, 0, "", "", +"c5 cc 41 ef \tkandw %k7,%k6,%k5",}, +{{0xc4, 0xe1, 0xcc, 0x41, 0xef, }, 5, 0, "", "", +"c4 e1 cc 41 ef \tkandq %k7,%k6,%k5",}, +{{0xc5, 0xcd, 0x41, 0xef, }, 4, 0, "", "", +"c5 cd 41 ef \tkandb %k7,%k6,%k5",}, +{{0xc4, 0xe1, 0xcd, 0x41, 0xef, }, 5, 0, "", "", +"c4 e1 cd 41 ef \tkandd %k7,%k6,%k5",}, +{{0xc5, 0xcc, 0x42, 0xef, }, 4, 0, "", "", +"c5 cc 42 ef \tkandnw %k7,%k6,%k5",}, +{{0xc4, 0xe1, 0xcc, 0x42, 0xef, }, 5, 0, "", "", +"c4 e1 cc 42 ef \tkandnq %k7,%k6,%k5",}, +{{0xc5, 0xcd, 0x42, 0xef, }, 4, 0, "", "", +"c5 cd 42 ef \tkandnb %k7,%k6,%k5",}, +{{0xc4, 0xe1, 0xcd, 0x42, 0xef, }, 5, 0, "", "", +"c4 e1 cd 42 ef \tkandnd %k7,%k6,%k5",}, +{{0xc5, 0xf8, 0x44, 0xf7, }, 4, 0, "", "", +"c5 f8 44 f7 \tknotw %k7,%k6",}, +{{0xc4, 0xe1, 0xf8, 0x44, 0xf7, }, 5, 0, "", "", +"c4 e1 f8 44 f7 \tknotq %k7,%k6",}, +{{0xc5, 0xf9, 0x44, 0xf7, }, 4, 0, "", "", +"c5 f9 44 f7 \tknotb %k7,%k6",}, +{{0xc4, 0xe1, 0xf9, 0x44, 0xf7, }, 5, 0, "", "", +"c4 e1 f9 44 f7 \tknotd %k7,%k6",}, +{{0xc5, 0xcc, 0x45, 0xef, }, 4, 0, "", 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0, "", "", +"62 61 95 40 58 72 7f \tvaddpd 0x1fc0(%rdx),%zmm29,%zmm30",}, +{{0x62, 0x61, 0x95, 0x50, 0x58, 0x72, 0x7f, }, 7, 0, "", "", +"62 61 95 50 58 72 7f \tvaddpd 0x3f8(%rdx){1to8},%zmm29,%zmm30",}, +{{0x62, 0xf1, 0x0c, 0x50, 0xc2, 0x6a, 0x7f, 0x08, }, 8, 0, "", "", +"62 f1 0c 50 c2 6a 7f 08 \tvcmpeq_uqps 0x1fc(%rdx){1to16},%zmm30,%k5",}, +{{0x62, 0xb1, 0x97, 0x07, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x01, }, 12, 0, "", "", +"62 b1 97 07 c2 ac f0 23 01 00 00 01 \tvcmpltsd 0x123(%rax,%r14,8),%xmm29,%k5{%k7}",}, +{{0x62, 0x91, 0x97, 0x17, 0xc2, 0xec, 0x02, }, 7, 0, "", "", +"62 91 97 17 c2 ec 02 \tvcmplesd {sae},%xmm28,%xmm29,%k5{%k7}",}, +{{0x62, 0x23, 0x15, 0x07, 0x27, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x5b, }, 12, 0, "", "", +"62 23 15 07 27 b4 f0 23 01 00 00 5b \tvgetmantss $0x5b,0x123(%rax,%r14,8),%xmm29,%xmm30{%k7}",}, {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", "f3 0f 1b 00 \tbndmk (%rax),%bnd0",}, {{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", @@ -327,19 +1257,19 @@ {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",}, {{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional", -"f2 e8 00 00 00 00 \tbnd callq 3fb <main+0x3fb>",}, +"f2 e8 00 00 00 00 \tbnd callq f22 <main+0xf22>",}, {{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect", "67 f2 ff 10 \tbnd callq *(%eax)",}, {{0xf2, 0xc3, }, 2, 0, "ret", "indirect", "f2 c3 \tbnd retq ",}, {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", -"f2 e9 00 00 00 00 \tbnd jmpq 407 <main+0x407>",}, +"f2 e9 00 00 00 00 \tbnd jmpq f2e <main+0xf2e>",}, {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", -"f2 e9 00 00 00 00 \tbnd jmpq 40d <main+0x40d>",}, +"f2 e9 00 00 00 00 \tbnd jmpq f34 <main+0xf34>",}, {{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect", "67 f2 ff 21 \tbnd jmpq *(%ecx)",}, {{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional", -"f2 0f 85 00 00 00 00 \tbnd jne 418 <main+0x418>",}, +"f2 0f 85 00 00 00 00 \tbnd jne f3f <main+0xf3f>",}, {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "", "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",}, {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "", diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c index 3cd677513e9e..76e0ec379c8b 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-src.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c @@ -25,6 +25,876 @@ int main(void) #ifdef __x86_64__ + /* AVX-512: Instructions with the same op codes as Mask Instructions */ + + asm volatile("cmovno %rax,%rbx"); + asm volatile("cmovno 0x12345678(%rax),%rcx"); + asm volatile("cmovno 0x12345678(%rax),%cx"); + + asm volatile("cmove %rax,%rbx"); + asm volatile("cmove 0x12345678(%rax),%rcx"); + asm volatile("cmove 0x12345678(%rax),%cx"); + + asm volatile("seto 0x12345678(%rax)"); + asm volatile("setno 0x12345678(%rax)"); + asm volatile("setb 0x12345678(%rax)"); + asm volatile("setc 0x12345678(%rax)"); + asm volatile("setnae 0x12345678(%rax)"); + asm volatile("setae 0x12345678(%rax)"); + asm volatile("setnb 0x12345678(%rax)"); + asm volatile("setnc 0x12345678(%rax)"); + asm volatile("sets 0x12345678(%rax)"); + asm volatile("setns 0x12345678(%rax)"); + + /* AVX-512: Mask Instructions */ + + asm volatile("kandw %k7,%k6,%k5"); + asm volatile("kandq %k7,%k6,%k5"); + asm volatile("kandb %k7,%k6,%k5"); + asm volatile("kandd %k7,%k6,%k5"); + + asm volatile("kandnw %k7,%k6,%k5"); + asm volatile("kandnq %k7,%k6,%k5"); + asm volatile("kandnb %k7,%k6,%k5"); + asm volatile("kandnd %k7,%k6,%k5"); + + asm volatile("knotw %k7,%k6"); + asm volatile("knotq %k7,%k6"); + asm volatile("knotb %k7,%k6"); + asm volatile("knotd %k7,%k6"); + + asm volatile("korw %k7,%k6,%k5"); + asm volatile("korq %k7,%k6,%k5"); + asm volatile("korb %k7,%k6,%k5"); + asm volatile("kord %k7,%k6,%k5"); + + asm volatile("kxnorw %k7,%k6,%k5"); + asm volatile("kxnorq %k7,%k6,%k5"); + asm volatile("kxnorb %k7,%k6,%k5"); + asm volatile("kxnord %k7,%k6,%k5"); + + asm volatile("kxorw %k7,%k6,%k5"); + asm volatile("kxorq %k7,%k6,%k5"); + asm volatile("kxorb %k7,%k6,%k5"); + asm volatile("kxord %k7,%k6,%k5"); + + asm volatile("kaddw %k7,%k6,%k5"); + asm volatile("kaddq %k7,%k6,%k5"); + asm volatile("kaddb %k7,%k6,%k5"); + asm volatile("kaddd %k7,%k6,%k5"); + + asm volatile("kunpckbw %k7,%k6,%k5"); + asm volatile("kunpckwd %k7,%k6,%k5"); + asm volatile("kunpckdq %k7,%k6,%k5"); + + asm volatile("kmovw %k6,%k5"); + asm volatile("kmovw (%rcx),%k5"); + asm volatile("kmovw 0x123(%rax,%r14,8),%k5"); + asm volatile("kmovw %k5,(%rcx)"); + asm volatile("kmovw %k5,0x123(%rax,%r14,8)"); + asm volatile("kmovw %eax,%k5"); + asm volatile("kmovw %ebp,%k5"); + asm volatile("kmovw %r13d,%k5"); + asm volatile("kmovw %k5,%eax"); + asm volatile("kmovw %k5,%ebp"); + asm volatile("kmovw %k5,%r13d"); + + asm volatile("kmovq %k6,%k5"); + asm volatile("kmovq (%rcx),%k5"); + asm volatile("kmovq 0x123(%rax,%r14,8),%k5"); + asm volatile("kmovq %k5,(%rcx)"); + asm volatile("kmovq %k5,0x123(%rax,%r14,8)"); + asm volatile("kmovq %rax,%k5"); + asm volatile("kmovq %rbp,%k5"); + asm volatile("kmovq %r13,%k5"); + asm volatile("kmovq %k5,%rax"); + asm volatile("kmovq %k5,%rbp"); + asm volatile("kmovq %k5,%r13"); + + asm volatile("kmovb %k6,%k5"); + asm volatile("kmovb (%rcx),%k5"); + asm volatile("kmovb 0x123(%rax,%r14,8),%k5"); + asm volatile("kmovb %k5,(%rcx)"); + asm volatile("kmovb %k5,0x123(%rax,%r14,8)"); + asm volatile("kmovb %eax,%k5"); + asm volatile("kmovb %ebp,%k5"); + asm volatile("kmovb %r13d,%k5"); + asm volatile("kmovb %k5,%eax"); + asm volatile("kmovb %k5,%ebp"); + asm volatile("kmovb %k5,%r13d"); + + asm volatile("kmovd %k6,%k5"); + asm volatile("kmovd (%rcx),%k5"); + asm volatile("kmovd 0x123(%rax,%r14,8),%k5"); + asm volatile("kmovd %k5,(%rcx)"); + asm volatile("kmovd %k5,0x123(%rax,%r14,8)"); + asm volatile("kmovd %eax,%k5"); + asm volatile("kmovd %ebp,%k5"); + asm volatile("kmovd %r13d,%k5"); + asm volatile("kmovd %k5,%eax"); + asm volatile("kmovd %k5,%ebp"); + asm volatile("kmovd %k5,%r13d"); + + asm volatile("kortestw %k6,%k5"); + asm volatile("kortestq %k6,%k5"); + asm volatile("kortestb %k6,%k5"); + asm volatile("kortestd %k6,%k5"); + + asm volatile("ktestw %k6,%k5"); + asm volatile("ktestq %k6,%k5"); + asm volatile("ktestb %k6,%k5"); + asm volatile("ktestd %k6,%k5"); + + asm volatile("kshiftrw $0x12,%k6,%k5"); + asm volatile("kshiftrq $0x5b,%k6,%k5"); + asm volatile("kshiftlw $0x12,%k6,%k5"); + asm volatile("kshiftlq $0x5b,%k6,%k5"); + + /* AVX-512: Op code 0f 5b */ + asm volatile("vcvtdq2ps %xmm5,%xmm6"); + asm volatile("vcvtqq2ps %zmm29,%ymm6{%k7}"); + asm volatile("vcvtps2dq %xmm5,%xmm6"); + asm volatile("vcvttps2dq %xmm5,%xmm6"); + + /* AVX-512: Op code 0f 6f */ + + asm volatile("movq %mm0,%mm4"); + asm volatile("vmovdqa %ymm4,%ymm6"); + asm volatile("vmovdqa32 %zmm25,%zmm26"); + asm volatile("vmovdqa64 %zmm25,%zmm26"); + asm volatile("vmovdqu %ymm4,%ymm6"); + asm volatile("vmovdqu32 %zmm29,%zmm30"); + asm volatile("vmovdqu64 %zmm25,%zmm26"); + asm volatile("vmovdqu8 %zmm29,%zmm30"); + asm volatile("vmovdqu16 %zmm25,%zmm26"); + + /* AVX-512: Op code 0f 78 */ + + asm volatile("vmread %rax,%rbx"); + asm volatile("vcvttps2udq %zmm25,%zmm26"); + asm volatile("vcvttpd2udq %zmm29,%ymm6{%k7}"); + asm volatile("vcvttsd2usi %xmm6,%rax"); + asm volatile("vcvttss2usi %xmm6,%rax"); + asm volatile("vcvttps2uqq %ymm5,%zmm26{%k7}"); + asm volatile("vcvttpd2uqq %zmm29,%zmm30"); + + /* AVX-512: Op code 0f 79 */ + + asm volatile("vmwrite %rax,%rbx"); + asm volatile("vcvtps2udq %zmm25,%zmm26"); + asm volatile("vcvtpd2udq %zmm29,%ymm6{%k7}"); + asm volatile("vcvtsd2usi %xmm6,%rax"); + asm volatile("vcvtss2usi %xmm6,%rax"); + asm volatile("vcvtps2uqq %ymm5,%zmm26{%k7}"); + asm volatile("vcvtpd2uqq %zmm29,%zmm30"); + + /* AVX-512: Op code 0f 7a */ + + asm volatile("vcvtudq2pd %ymm5,%zmm29{%k7}"); + asm volatile("vcvtuqq2pd %zmm25,%zmm26"); + asm volatile("vcvtudq2ps %zmm29,%zmm30"); + asm volatile("vcvtuqq2ps %zmm25,%ymm26{%k7}"); + asm volatile("vcvttps2qq %ymm25,%zmm26{%k7}"); + asm volatile("vcvttpd2qq %zmm29,%zmm30"); + + /* AVX-512: Op code 0f 7b */ + + asm volatile("vcvtusi2sd %eax,%xmm5,%xmm6"); + asm volatile("vcvtusi2ss %eax,%xmm5,%xmm6"); + asm volatile("vcvtps2qq %ymm5,%zmm26{%k7}"); + asm volatile("vcvtpd2qq %zmm29,%zmm30"); + + /* AVX-512: Op code 0f 7f */ + + asm volatile("movq.s %mm0,%mm4"); + asm volatile("vmovdqa %ymm8,%ymm6"); + asm volatile("vmovdqa32.s %zmm25,%zmm26"); + asm volatile("vmovdqa64.s %zmm25,%zmm26"); + asm volatile("vmovdqu %ymm8,%ymm6"); + asm volatile("vmovdqu32.s %zmm25,%zmm26"); + asm volatile("vmovdqu64.s %zmm25,%zmm26"); + asm volatile("vmovdqu8.s %zmm30,(%rcx)"); + asm volatile("vmovdqu16.s %zmm25,%zmm26"); + + /* AVX-512: Op code 0f db */ + + asm volatile("pand %mm1,%mm2"); + asm volatile("pand %xmm1,%xmm2"); + asm volatile("vpand %ymm4,%ymm6,%ymm2"); + asm volatile("vpandd %zmm24,%zmm25,%zmm26"); + asm volatile("vpandq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f df */ + + asm volatile("pandn %mm1,%mm2"); + asm volatile("pandn %xmm1,%xmm2"); + asm volatile("vpandn %ymm4,%ymm6,%ymm2"); + asm volatile("vpandnd %zmm24,%zmm25,%zmm26"); + asm volatile("vpandnq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f e6 */ + + asm volatile("vcvttpd2dq %xmm1,%xmm2"); + asm volatile("vcvtdq2pd %xmm5,%xmm6"); + asm volatile("vcvtdq2pd %ymm5,%zmm26{%k7}"); + asm volatile("vcvtqq2pd %zmm25,%zmm26"); + asm volatile("vcvtpd2dq %xmm1,%xmm2"); + + /* AVX-512: Op code 0f eb */ + + asm volatile("por %mm4,%mm6"); + asm volatile("vpor %ymm4,%ymm6,%ymm2"); + asm volatile("vpord %zmm24,%zmm25,%zmm26"); + asm volatile("vporq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f ef */ + + asm volatile("pxor %mm4,%mm6"); + asm volatile("vpxor %ymm4,%ymm6,%ymm2"); + asm volatile("vpxord %zmm24,%zmm25,%zmm26"); + asm volatile("vpxorq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 10 */ + + asm volatile("pblendvb %xmm1,%xmm0"); + asm volatile("vpsrlvw %zmm27,%zmm28,%zmm29"); + asm volatile("vpmovuswb %zmm28,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 11 */ + + asm volatile("vpmovusdb %zmm28,%xmm6{%k7}"); + asm volatile("vpsravw %zmm27,%zmm28,%zmm29"); + + /* AVX-512: Op code 0f 38 12 */ + + asm volatile("vpmovusqb %zmm27,%xmm6{%k7}"); + asm volatile("vpsllvw %zmm27,%zmm28,%zmm29"); + + /* AVX-512: Op code 0f 38 13 */ + + asm volatile("vcvtph2ps %xmm3,%ymm5"); + asm volatile("vcvtph2ps %ymm5,%zmm27{%k7}"); + asm volatile("vpmovusdw %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 14 */ + + asm volatile("blendvps %xmm1,%xmm0"); + asm volatile("vpmovusqw %zmm27,%xmm6{%k7}"); + asm volatile("vprorvd %zmm27,%zmm28,%zmm29"); + asm volatile("vprorvq %zmm27,%zmm28,%zmm29"); + + /* AVX-512: Op code 0f 38 15 */ + + asm volatile("blendvpd %xmm1,%xmm0"); + asm volatile("vpmovusqd %zmm27,%ymm6{%k7}"); + asm volatile("vprolvd %zmm27,%zmm28,%zmm29"); + asm volatile("vprolvq %zmm27,%zmm28,%zmm29"); + + /* AVX-512: Op code 0f 38 16 */ + + asm volatile("vpermps %ymm4,%ymm6,%ymm2"); + asm volatile("vpermps %ymm24,%ymm26,%ymm22{%k7}"); + asm volatile("vpermpd %ymm24,%ymm26,%ymm22{%k7}"); + + /* AVX-512: Op code 0f 38 19 */ + + asm volatile("vbroadcastsd %xmm4,%ymm6"); + asm volatile("vbroadcastf32x2 %xmm27,%zmm26"); + + /* AVX-512: Op code 0f 38 1a */ + + asm volatile("vbroadcastf128 (%rcx),%ymm4"); + asm volatile("vbroadcastf32x4 (%rcx),%zmm26"); + asm volatile("vbroadcastf64x2 (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 1b */ + + asm volatile("vbroadcastf32x8 (%rcx),%zmm27"); + asm volatile("vbroadcastf64x4 (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 1f */ + + asm volatile("vpabsq %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 20 */ + + asm volatile("vpmovsxbw %xmm4,%xmm5"); + asm volatile("vpmovswb %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 21 */ + + asm volatile("vpmovsxbd %xmm4,%ymm6"); + asm volatile("vpmovsdb %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 22 */ + + asm volatile("vpmovsxbq %xmm4,%ymm4"); + asm volatile("vpmovsqb %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 23 */ + + asm volatile("vpmovsxwd %xmm4,%ymm4"); + asm volatile("vpmovsdw %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 24 */ + + asm volatile("vpmovsxwq %xmm4,%ymm6"); + asm volatile("vpmovsqw %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 25 */ + + asm volatile("vpmovsxdq %xmm4,%ymm4"); + asm volatile("vpmovsqd %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 26 */ + + asm volatile("vptestmb %zmm27,%zmm28,%k5"); + asm volatile("vptestmw %zmm27,%zmm28,%k5"); + asm volatile("vptestnmb %zmm26,%zmm27,%k5"); + asm volatile("vptestnmw %zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 38 27 */ + + asm volatile("vptestmd %zmm27,%zmm28,%k5"); + asm volatile("vptestmq %zmm27,%zmm28,%k5"); + asm volatile("vptestnmd %zmm26,%zmm27,%k5"); + asm volatile("vptestnmq %zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 38 28 */ + + asm volatile("vpmuldq %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovm2b %k5,%zmm28"); + asm volatile("vpmovm2w %k5,%zmm28"); + + /* AVX-512: Op code 0f 38 29 */ + + asm volatile("vpcmpeqq %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovb2m %zmm28,%k5"); + asm volatile("vpmovw2m %zmm28,%k5"); + + /* AVX-512: Op code 0f 38 2a */ + + asm volatile("vmovntdqa (%rcx),%ymm4"); + asm volatile("vpbroadcastmb2q %k6,%zmm30"); + + /* AVX-512: Op code 0f 38 2c */ + + asm volatile("vmaskmovps (%rcx),%ymm4,%ymm6"); + asm volatile("vscalefps %zmm24,%zmm25,%zmm26"); + asm volatile("vscalefpd %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 2d */ + + asm volatile("vmaskmovpd (%rcx),%ymm4,%ymm6"); + asm volatile("vscalefss %xmm24,%xmm25,%xmm26{%k7}"); + asm volatile("vscalefsd %xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 38 30 */ + + asm volatile("vpmovzxbw %xmm4,%ymm4"); + asm volatile("vpmovwb %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 31 */ + + asm volatile("vpmovzxbd %xmm4,%ymm6"); + asm volatile("vpmovdb %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 32 */ + + asm volatile("vpmovzxbq %xmm4,%ymm4"); + asm volatile("vpmovqb %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 33 */ + + asm volatile("vpmovzxwd %xmm4,%ymm4"); + asm volatile("vpmovdw %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 34 */ + + asm volatile("vpmovzxwq %xmm4,%ymm6"); + asm volatile("vpmovqw %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 35 */ + + asm volatile("vpmovzxdq %xmm4,%ymm4"); + asm volatile("vpmovqd %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 38 */ + + asm volatile("vpermd %ymm4,%ymm6,%ymm2"); + asm volatile("vpermd %ymm24,%ymm26,%ymm22{%k7}"); + asm volatile("vpermq %ymm24,%ymm26,%ymm22{%k7}"); + + /* AVX-512: Op code 0f 38 38 */ + + asm volatile("vpminsb %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovm2d %k5,%zmm28"); + asm volatile("vpmovm2q %k5,%zmm28"); + + /* AVX-512: Op code 0f 38 39 */ + + asm volatile("vpminsd %xmm1,%xmm2,%xmm3"); + asm volatile("vpminsd %zmm24,%zmm25,%zmm26"); + asm volatile("vpminsq %zmm24,%zmm25,%zmm26"); + asm volatile("vpmovd2m %zmm28,%k5"); + asm volatile("vpmovq2m %zmm28,%k5"); + + /* AVX-512: Op code 0f 38 3a */ + + asm volatile("vpminuw %ymm4,%ymm6,%ymm2"); + asm volatile("vpbroadcastmw2d %k6,%zmm28"); + + /* AVX-512: Op code 0f 38 3b */ + + asm volatile("vpminud %ymm4,%ymm6,%ymm2"); + asm volatile("vpminud %zmm24,%zmm25,%zmm26"); + asm volatile("vpminuq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 3d */ + + asm volatile("vpmaxsd %ymm4,%ymm6,%ymm2"); + asm volatile("vpmaxsd %zmm24,%zmm25,%zmm26"); + asm volatile("vpmaxsq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 3f */ + + asm volatile("vpmaxud %ymm4,%ymm6,%ymm2"); + asm volatile("vpmaxud %zmm24,%zmm25,%zmm26"); + asm volatile("vpmaxuq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 42 */ + + asm volatile("vpmulld %ymm4,%ymm6,%ymm2"); + asm volatile("vpmulld %zmm24,%zmm25,%zmm26"); + asm volatile("vpmullq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 42 */ + + asm volatile("vgetexpps %zmm25,%zmm26"); + asm volatile("vgetexppd %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 43 */ + + asm volatile("vgetexpss %xmm24,%xmm25,%xmm26{%k7}"); + asm volatile("vgetexpsd %xmm28,%xmm29,%xmm30{%k7}"); + + /* AVX-512: Op code 0f 38 44 */ + + asm volatile("vplzcntd %zmm27,%zmm28"); + asm volatile("vplzcntq %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 46 */ + + asm volatile("vpsravd %ymm4,%ymm6,%ymm2"); + asm volatile("vpsravd %zmm24,%zmm25,%zmm26"); + asm volatile("vpsravq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 4c */ + + asm volatile("vrcp14ps %zmm25,%zmm26"); + asm volatile("vrcp14pd %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 4d */ + + asm volatile("vrcp14ss %xmm24,%xmm25,%xmm26{%k7}"); + asm volatile("vrcp14sd %xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 38 4e */ + + asm volatile("vrsqrt14ps %zmm25,%zmm26"); + asm volatile("vrsqrt14pd %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 4f */ + + asm volatile("vrsqrt14ss %xmm24,%xmm25,%xmm26{%k7}"); + asm volatile("vrsqrt14sd %xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 38 59 */ + + asm volatile("vpbroadcastq %xmm4,%xmm6"); + asm volatile("vbroadcasti32x2 %xmm27,%zmm26"); + + /* AVX-512: Op code 0f 38 5a */ + + asm volatile("vbroadcasti128 (%rcx),%ymm4"); + asm volatile("vbroadcasti32x4 (%rcx),%zmm26"); + asm volatile("vbroadcasti64x2 (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 5b */ + + asm volatile("vbroadcasti32x8 (%rcx),%zmm28"); + asm volatile("vbroadcasti64x4 (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 64 */ + + asm volatile("vpblendmd %zmm26,%zmm27,%zmm28"); + asm volatile("vpblendmq %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 65 */ + + asm volatile("vblendmps %zmm24,%zmm25,%zmm26"); + asm volatile("vblendmpd %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 66 */ + + asm volatile("vpblendmb %zmm26,%zmm27,%zmm28"); + asm volatile("vpblendmw %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 75 */ + + asm volatile("vpermi2b %zmm24,%zmm25,%zmm26"); + asm volatile("vpermi2w %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 76 */ + + asm volatile("vpermi2d %zmm26,%zmm27,%zmm28"); + asm volatile("vpermi2q %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 77 */ + + asm volatile("vpermi2ps %zmm26,%zmm27,%zmm28"); + asm volatile("vpermi2pd %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 7a */ + + asm volatile("vpbroadcastb %eax,%xmm30"); + + /* AVX-512: Op code 0f 38 7b */ + + asm volatile("vpbroadcastw %eax,%xmm30"); + + /* AVX-512: Op code 0f 38 7c */ + + asm volatile("vpbroadcastd %eax,%xmm30"); + asm volatile("vpbroadcastq %rax,%zmm30"); + + /* AVX-512: Op code 0f 38 7d */ + + asm volatile("vpermt2b %zmm26,%zmm27,%zmm28"); + asm volatile("vpermt2w %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 7e */ + + asm volatile("vpermt2d %zmm26,%zmm27,%zmm28"); + asm volatile("vpermt2q %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 7f */ + + asm volatile("vpermt2ps %zmm26,%zmm27,%zmm28"); + asm volatile("vpermt2pd %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 83 */ + + asm volatile("vpmultishiftqb %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 88 */ + + asm volatile("vexpandps (%rcx),%zmm26"); + asm volatile("vexpandpd (%rcx),%zmm28"); + + /* AVX-512: Op code 0f 38 89 */ + + asm volatile("vpexpandd (%rcx),%zmm28"); + asm volatile("vpexpandq (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 8a */ + + asm volatile("vcompressps %zmm28,(%rcx)"); + asm volatile("vcompresspd %zmm28,(%rcx)"); + + /* AVX-512: Op code 0f 38 8b */ + + asm volatile("vpcompressd %zmm28,(%rcx)"); + asm volatile("vpcompressq %zmm26,(%rcx)"); + + /* AVX-512: Op code 0f 38 8d */ + + asm volatile("vpermb %zmm26,%zmm27,%zmm28"); + asm volatile("vpermw %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 90 */ + + asm volatile("vpgatherdd %xmm2,0x02(%rbp,%xmm7,2),%xmm1"); + asm volatile("vpgatherdq %xmm2,0x04(%rbp,%xmm7,2),%xmm1"); + asm volatile("vpgatherdd 0x7b(%rbp,%zmm27,8),%zmm26{%k1}"); + asm volatile("vpgatherdq 0x7b(%rbp,%ymm27,8),%zmm26{%k1}"); + + /* AVX-512: Op code 0f 38 91 */ + + asm volatile("vpgatherqd %xmm2,0x02(%rbp,%xmm7,2),%xmm1"); + asm volatile("vpgatherqq %xmm2,0x02(%rbp,%xmm7,2),%xmm1"); + asm volatile("vpgatherqd 0x7b(%rbp,%zmm27,8),%ymm26{%k1}"); + asm volatile("vpgatherqq 0x7b(%rbp,%zmm27,8),%zmm26{%k1}"); + + /* AVX-512: Op code 0f 38 a0 */ + + asm volatile("vpscatterdd %zmm28,0x7b(%rbp,%zmm29,8){%k1}"); + asm volatile("vpscatterdq %zmm26,0x7b(%rbp,%ymm27,8){%k1}"); + + /* AVX-512: Op code 0f 38 a1 */ + + asm volatile("vpscatterqd %ymm6,0x7b(%rbp,%zmm29,8){%k1}"); + asm volatile("vpscatterqq %ymm6,0x7b(%rbp,%ymm27,8){%k1}"); + + /* AVX-512: Op code 0f 38 a2 */ + + asm volatile("vscatterdps %zmm28,0x7b(%rbp,%zmm29,8){%k1}"); + asm volatile("vscatterdpd %zmm28,0x7b(%rbp,%ymm27,8){%k1}"); + + /* AVX-512: Op code 0f 38 a3 */ + + asm volatile("vscatterqps %ymm6,0x7b(%rbp,%zmm29,8){%k1}"); + asm volatile("vscatterqpd %zmm28,0x7b(%rbp,%zmm29,8){%k1}"); + + /* AVX-512: Op code 0f 38 b4 */ + + asm volatile("vpmadd52luq %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 b5 */ + + asm volatile("vpmadd52huq %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 c4 */ + + asm volatile("vpconflictd %zmm26,%zmm27"); + asm volatile("vpconflictq %zmm26,%zmm27"); + + /* AVX-512: Op code 0f 38 c8 */ + + asm volatile("vexp2ps %zmm29,%zmm30"); + asm volatile("vexp2pd %zmm26,%zmm27"); + + /* AVX-512: Op code 0f 38 ca */ + + asm volatile("vrcp28ps %zmm29,%zmm30"); + asm volatile("vrcp28pd %zmm26,%zmm27"); + + /* AVX-512: Op code 0f 38 cb */ + + asm volatile("vrcp28ss %xmm28,%xmm29,%xmm30{%k7}"); + asm volatile("vrcp28sd %xmm25,%xmm26,%xmm27{%k7}"); + + /* AVX-512: Op code 0f 38 cc */ + + asm volatile("vrsqrt28ps %zmm29,%zmm30"); + asm volatile("vrsqrt28pd %zmm26,%zmm27"); + + /* AVX-512: Op code 0f 38 cd */ + + asm volatile("vrsqrt28ss %xmm28,%xmm29,%xmm30{%k7}"); + asm volatile("vrsqrt28sd %xmm25,%xmm26,%xmm27{%k7}"); + + /* AVX-512: Op code 0f 3a 03 */ + + asm volatile("valignd $0x12,%zmm28,%zmm29,%zmm30"); + asm volatile("valignq $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a 08 */ + + asm volatile("vroundps $0x5,%ymm6,%ymm2"); + asm volatile("vrndscaleps $0x12,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 3a 09 */ + + asm volatile("vroundpd $0x5,%ymm6,%ymm2"); + asm volatile("vrndscalepd $0x12,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 3a 1a */ + + asm volatile("vroundss $0x5,%xmm4,%xmm6,%xmm2"); + asm volatile("vrndscaless $0x12,%xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 0b */ + + asm volatile("vroundsd $0x5,%xmm4,%xmm6,%xmm2"); + asm volatile("vrndscalesd $0x12,%xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 18 */ + + asm volatile("vinsertf128 $0x5,%xmm4,%ymm4,%ymm6"); + asm volatile("vinsertf32x4 $0x12,%xmm24,%zmm25,%zmm26{%k7}"); + asm volatile("vinsertf64x2 $0x12,%xmm24,%zmm25,%zmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 19 */ + + asm volatile("vextractf128 $0x5,%ymm4,%xmm4"); + asm volatile("vextractf32x4 $0x12,%zmm25,%xmm26{%k7}"); + asm volatile("vextractf64x2 $0x12,%zmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 1a */ + + asm volatile("vinsertf32x8 $0x12,%ymm25,%zmm26,%zmm27{%k7}"); + asm volatile("vinsertf64x4 $0x12,%ymm28,%zmm29,%zmm30{%k7}"); + + /* AVX-512: Op code 0f 3a 1b */ + + asm volatile("vextractf32x8 $0x12,%zmm29,%ymm30{%k7}"); + asm volatile("vextractf64x4 $0x12,%zmm26,%ymm27{%k7}"); + + /* AVX-512: Op code 0f 3a 1e */ + + asm volatile("vpcmpud $0x12,%zmm29,%zmm30,%k5"); + asm volatile("vpcmpuq $0x12,%zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 3a 1f */ + + asm volatile("vpcmpd $0x12,%zmm29,%zmm30,%k5"); + asm volatile("vpcmpq $0x12,%zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 3a 23 */ + + asm volatile("vshuff32x4 $0x12,%zmm28,%zmm29,%zmm30"); + asm volatile("vshuff64x2 $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a 25 */ + + asm volatile("vpternlogd $0x12,%zmm28,%zmm29,%zmm30"); + asm volatile("vpternlogq $0x12,%zmm28,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 26 */ + + asm volatile("vgetmantps $0x12,%zmm26,%zmm27"); + asm volatile("vgetmantpd $0x12,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 27 */ + + asm volatile("vgetmantss $0x12,%xmm25,%xmm26,%xmm27{%k7}"); + asm volatile("vgetmantsd $0x12,%xmm28,%xmm29,%xmm30{%k7}"); + + /* AVX-512: Op code 0f 3a 38 */ + + asm volatile("vinserti128 $0x5,%xmm4,%ymm4,%ymm6"); + asm volatile("vinserti32x4 $0x12,%xmm24,%zmm25,%zmm26{%k7}"); + asm volatile("vinserti64x2 $0x12,%xmm24,%zmm25,%zmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 39 */ + + asm volatile("vextracti128 $0x5,%ymm4,%xmm6"); + asm volatile("vextracti32x4 $0x12,%zmm25,%xmm26{%k7}"); + asm volatile("vextracti64x2 $0x12,%zmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 3a */ + + asm volatile("vinserti32x8 $0x12,%ymm28,%zmm29,%zmm30{%k7}"); + asm volatile("vinserti64x4 $0x12,%ymm25,%zmm26,%zmm27{%k7}"); + + /* AVX-512: Op code 0f 3a 3b */ + + asm volatile("vextracti32x8 $0x12,%zmm29,%ymm30{%k7}"); + asm volatile("vextracti64x4 $0x12,%zmm26,%ymm27{%k7}"); + + /* AVX-512: Op code 0f 3a 3e */ + + asm volatile("vpcmpub $0x12,%zmm29,%zmm30,%k5"); + asm volatile("vpcmpuw $0x12,%zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 3a 3f */ + + asm volatile("vpcmpb $0x12,%zmm29,%zmm30,%k5"); + asm volatile("vpcmpw $0x12,%zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 3a 43 */ + + asm volatile("vmpsadbw $0x5,%ymm4,%ymm6,%ymm2"); + asm volatile("vdbpsadbw $0x12,%zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 3a 43 */ + + asm volatile("vshufi32x4 $0x12,%zmm25,%zmm26,%zmm27"); + asm volatile("vshufi64x2 $0x12,%zmm28,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 50 */ + + asm volatile("vrangeps $0x12,%zmm25,%zmm26,%zmm27"); + asm volatile("vrangepd $0x12,%zmm28,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 51 */ + + asm volatile("vrangess $0x12,%xmm25,%xmm26,%xmm27"); + asm volatile("vrangesd $0x12,%xmm28,%xmm29,%xmm30"); + + /* AVX-512: Op code 0f 3a 54 */ + + asm volatile("vfixupimmps $0x12,%zmm28,%zmm29,%zmm30"); + asm volatile("vfixupimmpd $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a 55 */ + + asm volatile("vfixupimmss $0x12,%xmm28,%xmm29,%xmm30{%k7}"); + asm volatile("vfixupimmsd $0x12,%xmm25,%xmm26,%xmm27{%k7}"); + + /* AVX-512: Op code 0f 3a 56 */ + + asm volatile("vreduceps $0x12,%zmm26,%zmm27"); + asm volatile("vreducepd $0x12,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 57 */ + + asm volatile("vreducess $0x12,%xmm25,%xmm26,%xmm27"); + asm volatile("vreducesd $0x12,%xmm28,%xmm29,%xmm30"); + + /* AVX-512: Op code 0f 3a 66 */ + + asm volatile("vfpclassps $0x12,%zmm27,%k5"); + asm volatile("vfpclasspd $0x12,%zmm30,%k5"); + + /* AVX-512: Op code 0f 3a 67 */ + + asm volatile("vfpclassss $0x12,%xmm27,%k5"); + asm volatile("vfpclasssd $0x12,%xmm30,%k5"); + + /* AVX-512: Op code 0f 72 (Grp13) */ + + asm volatile("vprord $0x12,%zmm25,%zmm26"); + asm volatile("vprorq $0x12,%zmm25,%zmm26"); + asm volatile("vprold $0x12,%zmm29,%zmm30"); + asm volatile("vprolq $0x12,%zmm29,%zmm30"); + asm volatile("psrad $0x2,%mm6"); + asm volatile("vpsrad $0x5,%ymm6,%ymm2"); + asm volatile("vpsrad $0x5,%zmm26,%zmm22"); + asm volatile("vpsraq $0x5,%zmm26,%zmm22"); + + /* AVX-512: Op code 0f 38 c6 (Grp18) */ + + asm volatile("vgatherpf0dps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf0dpd 0x7b(%r14,%ymm31,8){%k1}"); + asm volatile("vgatherpf1dps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf1dpd 0x7b(%r14,%ymm31,8){%k1}"); + asm volatile("vscatterpf0dps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf0dpd 0x7b(%r14,%ymm31,8){%k1}"); + asm volatile("vscatterpf1dps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf1dpd 0x7b(%r14,%ymm31,8){%k1}"); + + /* AVX-512: Op code 0f 38 c7 (Grp19) */ + + asm volatile("vgatherpf0qps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf0qpd 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf1qps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf1qpd 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf0qps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf0qpd 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf1qps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf1qpd 0x7b(%r14,%zmm31,8){%k1}"); + + /* AVX-512: Examples */ + + asm volatile("vaddpd %zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd %zmm28,%zmm29,%zmm30{%k7}"); + asm volatile("vaddpd %zmm28,%zmm29,%zmm30{%k7}{z}"); + asm volatile("vaddpd {rn-sae},%zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd {ru-sae},%zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd {rd-sae},%zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd {rz-sae},%zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd (%rcx),%zmm29,%zmm30"); + asm volatile("vaddpd 0x123(%rax,%r14,8),%zmm29,%zmm30"); + asm volatile("vaddpd (%rcx){1to8},%zmm29,%zmm30"); + asm volatile("vaddpd 0x1fc0(%rdx),%zmm29,%zmm30"); + asm volatile("vaddpd 0x3f8(%rdx){1to8},%zmm29,%zmm30"); + asm volatile("vcmpeq_uqps 0x1fc(%rdx){1to16},%zmm30,%k5"); + asm volatile("vcmpltsd 0x123(%rax,%r14,8),%xmm29,%k5{%k7}"); + asm volatile("vcmplesd {sae},%xmm28,%xmm29,%k5{%k7}"); + asm volatile("vgetmantss $0x5b,0x123(%rax,%r14,8),%xmm29,%xmm30{%k7}"); + /* bndmk m64, bnd */ asm volatile("bndmk (%rax), %bnd0"); @@ -475,6 +1345,921 @@ int main(void) #else /* #ifdef __x86_64__ */ + /* bound r32, mem (same op code as EVEX prefix) */ + + asm volatile("bound %eax, 0x12345678(%ecx)"); + asm volatile("bound %ecx, 0x12345678(%eax)"); + asm volatile("bound %edx, 0x12345678(%eax)"); + asm volatile("bound %ebx, 0x12345678(%eax)"); + asm volatile("bound %esp, 0x12345678(%eax)"); + asm volatile("bound %ebp, 0x12345678(%eax)"); + asm volatile("bound %esi, 0x12345678(%eax)"); + asm volatile("bound %edi, 0x12345678(%eax)"); + asm volatile("bound %ecx, (%eax)"); + asm volatile("bound %eax, (0x12345678)"); + asm volatile("bound %edx, (%ecx,%eax,1)"); + asm volatile("bound %edx, 0x12345678(,%eax,1)"); + asm volatile("bound %edx, (%eax,%ecx,1)"); + asm volatile("bound %edx, (%eax,%ecx,8)"); + asm volatile("bound %edx, 0x12(%eax)"); + asm volatile("bound %edx, 0x12(%ebp)"); + asm volatile("bound %edx, 0x12(%ecx,%eax,1)"); + asm volatile("bound %edx, 0x12(%ebp,%eax,1)"); + asm volatile("bound %edx, 0x12(%eax,%ecx,1)"); + asm volatile("bound %edx, 0x12(%eax,%ecx,8)"); + asm volatile("bound %edx, 0x12345678(%eax)"); + asm volatile("bound %edx, 0x12345678(%ebp)"); + asm volatile("bound %edx, 0x12345678(%ecx,%eax,1)"); + asm volatile("bound %edx, 0x12345678(%ebp,%eax,1)"); + asm volatile("bound %edx, 0x12345678(%eax,%ecx,1)"); + asm volatile("bound %edx, 0x12345678(%eax,%ecx,8)"); + + /* bound r16, mem (same op code as EVEX prefix) */ + + asm volatile("bound %ax, 0x12345678(%ecx)"); + asm volatile("bound %cx, 0x12345678(%eax)"); + asm volatile("bound %dx, 0x12345678(%eax)"); + asm volatile("bound %bx, 0x12345678(%eax)"); + asm volatile("bound %sp, 0x12345678(%eax)"); + asm volatile("bound %bp, 0x12345678(%eax)"); + asm volatile("bound %si, 0x12345678(%eax)"); + asm volatile("bound %di, 0x12345678(%eax)"); + asm volatile("bound %cx, (%eax)"); + asm volatile("bound %ax, (0x12345678)"); + asm volatile("bound %dx, (%ecx,%eax,1)"); + asm volatile("bound %dx, 0x12345678(,%eax,1)"); + asm volatile("bound %dx, (%eax,%ecx,1)"); + asm volatile("bound %dx, (%eax,%ecx,8)"); + asm volatile("bound %dx, 0x12(%eax)"); + asm volatile("bound %dx, 0x12(%ebp)"); + asm volatile("bound %dx, 0x12(%ecx,%eax,1)"); + asm volatile("bound %dx, 0x12(%ebp,%eax,1)"); + asm volatile("bound %dx, 0x12(%eax,%ecx,1)"); + asm volatile("bound %dx, 0x12(%eax,%ecx,8)"); + asm volatile("bound %dx, 0x12345678(%eax)"); + asm volatile("bound %dx, 0x12345678(%ebp)"); + asm volatile("bound %dx, 0x12345678(%ecx,%eax,1)"); + asm volatile("bound %dx, 0x12345678(%ebp,%eax,1)"); + asm volatile("bound %dx, 0x12345678(%eax,%ecx,1)"); + asm volatile("bound %dx, 0x12345678(%eax,%ecx,8)"); + + /* AVX-512: Instructions with the same op codes as Mask Instructions */ + + asm volatile("cmovno %eax,%ebx"); + asm volatile("cmovno 0x12345678(%eax),%ecx"); + asm volatile("cmovno 0x12345678(%eax),%cx"); + + asm volatile("cmove %eax,%ebx"); + asm volatile("cmove 0x12345678(%eax),%ecx"); + asm volatile("cmove 0x12345678(%eax),%cx"); + + asm volatile("seto 0x12345678(%eax)"); + asm volatile("setno 0x12345678(%eax)"); + asm volatile("setb 0x12345678(%eax)"); + asm volatile("setc 0x12345678(%eax)"); + asm volatile("setnae 0x12345678(%eax)"); + asm volatile("setae 0x12345678(%eax)"); + asm volatile("setnb 0x12345678(%eax)"); + asm volatile("setnc 0x12345678(%eax)"); + asm volatile("sets 0x12345678(%eax)"); + asm volatile("setns 0x12345678(%eax)"); + + /* AVX-512: Mask Instructions */ + + asm volatile("kandw %k7,%k6,%k5"); + asm volatile("kandq %k7,%k6,%k5"); + asm volatile("kandb %k7,%k6,%k5"); + asm volatile("kandd %k7,%k6,%k5"); + + asm volatile("kandnw %k7,%k6,%k5"); + asm volatile("kandnq %k7,%k6,%k5"); + asm volatile("kandnb %k7,%k6,%k5"); + asm volatile("kandnd %k7,%k6,%k5"); + + asm volatile("knotw %k7,%k6"); + asm volatile("knotq %k7,%k6"); + asm volatile("knotb %k7,%k6"); + asm volatile("knotd %k7,%k6"); + + asm volatile("korw %k7,%k6,%k5"); + asm volatile("korq %k7,%k6,%k5"); + asm volatile("korb %k7,%k6,%k5"); + asm volatile("kord %k7,%k6,%k5"); + + asm volatile("kxnorw %k7,%k6,%k5"); + asm volatile("kxnorq %k7,%k6,%k5"); + asm volatile("kxnorb %k7,%k6,%k5"); + asm volatile("kxnord %k7,%k6,%k5"); + + asm volatile("kxorw %k7,%k6,%k5"); + asm volatile("kxorq %k7,%k6,%k5"); + asm volatile("kxorb %k7,%k6,%k5"); + asm volatile("kxord %k7,%k6,%k5"); + + asm volatile("kaddw %k7,%k6,%k5"); + asm volatile("kaddq %k7,%k6,%k5"); + asm volatile("kaddb %k7,%k6,%k5"); + asm volatile("kaddd %k7,%k6,%k5"); + + asm volatile("kunpckbw %k7,%k6,%k5"); + asm volatile("kunpckwd %k7,%k6,%k5"); + asm volatile("kunpckdq %k7,%k6,%k5"); + + asm volatile("kmovw %k6,%k5"); + asm volatile("kmovw (%ecx),%k5"); + asm volatile("kmovw 0x123(%eax,%ecx,8),%k5"); + asm volatile("kmovw %k5,(%ecx)"); + asm volatile("kmovw %k5,0x123(%eax,%ecx,8)"); + asm volatile("kmovw %eax,%k5"); + asm volatile("kmovw %ebp,%k5"); + asm volatile("kmovw %k5,%eax"); + asm volatile("kmovw %k5,%ebp"); + + asm volatile("kmovq %k6,%k5"); + asm volatile("kmovq (%ecx),%k5"); + asm volatile("kmovq 0x123(%eax,%ecx,8),%k5"); + asm volatile("kmovq %k5,(%ecx)"); + asm volatile("kmovq %k5,0x123(%eax,%ecx,8)"); + + asm volatile("kmovb %k6,%k5"); + asm volatile("kmovb (%ecx),%k5"); + asm volatile("kmovb 0x123(%eax,%ecx,8),%k5"); + asm volatile("kmovb %k5,(%ecx)"); + asm volatile("kmovb %k5,0x123(%eax,%ecx,8)"); + asm volatile("kmovb %eax,%k5"); + asm volatile("kmovb %ebp,%k5"); + asm volatile("kmovb %k5,%eax"); + asm volatile("kmovb %k5,%ebp"); + + asm volatile("kmovd %k6,%k5"); + asm volatile("kmovd (%ecx),%k5"); + asm volatile("kmovd 0x123(%eax,%ecx,8),%k5"); + asm volatile("kmovd %k5,(%ecx)"); + asm volatile("kmovd %k5,0x123(%eax,%ecx,8)"); + asm volatile("kmovd %eax,%k5"); + asm volatile("kmovd %ebp,%k5"); + asm volatile("kmovd %k5,%eax"); + asm volatile("kmovd %k5,%ebp"); + + asm volatile("kortestw %k6,%k5"); + asm volatile("kortestq %k6,%k5"); + asm volatile("kortestb %k6,%k5"); + asm volatile("kortestd %k6,%k5"); + + asm volatile("ktestw %k6,%k5"); + asm volatile("ktestq %k6,%k5"); + asm volatile("ktestb %k6,%k5"); + asm volatile("ktestd %k6,%k5"); + + asm volatile("kshiftrw $0x12,%k6,%k5"); + asm volatile("kshiftrq $0x5b,%k6,%k5"); + asm volatile("kshiftlw $0x12,%k6,%k5"); + asm volatile("kshiftlq $0x5b,%k6,%k5"); + + /* AVX-512: Op code 0f 5b */ + asm volatile("vcvtdq2ps %xmm5,%xmm6"); + asm volatile("vcvtqq2ps %zmm5,%ymm6{%k7}"); + asm volatile("vcvtps2dq %xmm5,%xmm6"); + asm volatile("vcvttps2dq %xmm5,%xmm6"); + + /* AVX-512: Op code 0f 6f */ + + asm volatile("movq %mm0,%mm4"); + asm volatile("vmovdqa %ymm4,%ymm6"); + asm volatile("vmovdqa32 %zmm5,%zmm6"); + asm volatile("vmovdqa64 %zmm5,%zmm6"); + asm volatile("vmovdqu %ymm4,%ymm6"); + asm volatile("vmovdqu32 %zmm5,%zmm6"); + asm volatile("vmovdqu64 %zmm5,%zmm6"); + asm volatile("vmovdqu8 %zmm5,%zmm6"); + asm volatile("vmovdqu16 %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 78 */ + + asm volatile("vmread %eax,%ebx"); + asm volatile("vcvttps2udq %zmm5,%zmm6"); + asm volatile("vcvttpd2udq %zmm5,%ymm6{%k7}"); + asm volatile("vcvttsd2usi %xmm6,%eax"); + asm volatile("vcvttss2usi %xmm6,%eax"); + asm volatile("vcvttps2uqq %ymm5,%zmm6{%k7}"); + asm volatile("vcvttpd2uqq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 79 */ + + asm volatile("vmwrite %eax,%ebx"); + asm volatile("vcvtps2udq %zmm5,%zmm6"); + asm volatile("vcvtpd2udq %zmm5,%ymm6{%k7}"); + asm volatile("vcvtsd2usi %xmm6,%eax"); + asm volatile("vcvtss2usi %xmm6,%eax"); + asm volatile("vcvtps2uqq %ymm5,%zmm6{%k7}"); + asm volatile("vcvtpd2uqq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 7a */ + + asm volatile("vcvtudq2pd %ymm5,%zmm6{%k7}"); + asm volatile("vcvtuqq2pd %zmm5,%zmm6"); + asm volatile("vcvtudq2ps %zmm5,%zmm6"); + asm volatile("vcvtuqq2ps %zmm5,%ymm6{%k7}"); + asm volatile("vcvttps2qq %ymm5,%zmm6{%k7}"); + asm volatile("vcvttpd2qq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 7b */ + + asm volatile("vcvtusi2sd %eax,%xmm5,%xmm6"); + asm volatile("vcvtusi2ss %eax,%xmm5,%xmm6"); + asm volatile("vcvtps2qq %ymm5,%zmm6{%k7}"); + asm volatile("vcvtpd2qq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 7f */ + + asm volatile("movq.s %mm0,%mm4"); + asm volatile("vmovdqa.s %ymm5,%ymm6"); + asm volatile("vmovdqa32.s %zmm5,%zmm6"); + asm volatile("vmovdqa64.s %zmm5,%zmm6"); + asm volatile("vmovdqu.s %ymm5,%ymm6"); + asm volatile("vmovdqu32.s %zmm5,%zmm6"); + asm volatile("vmovdqu64.s %zmm5,%zmm6"); + asm volatile("vmovdqu8.s %zmm5,%zmm6"); + asm volatile("vmovdqu16.s %zmm5,%zmm6"); + + /* AVX-512: Op code 0f db */ + + asm volatile("pand %mm1,%mm2"); + asm volatile("pand %xmm1,%xmm2"); + asm volatile("vpand %ymm4,%ymm6,%ymm2"); + asm volatile("vpandd %zmm4,%zmm5,%zmm6"); + asm volatile("vpandq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f df */ + + asm volatile("pandn %mm1,%mm2"); + asm volatile("pandn %xmm1,%xmm2"); + asm volatile("vpandn %ymm4,%ymm6,%ymm2"); + asm volatile("vpandnd %zmm4,%zmm5,%zmm6"); + asm volatile("vpandnq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f e6 */ + + asm volatile("vcvttpd2dq %xmm1,%xmm2"); + asm volatile("vcvtdq2pd %xmm5,%xmm6"); + asm volatile("vcvtdq2pd %ymm5,%zmm6{%k7}"); + asm volatile("vcvtqq2pd %zmm5,%zmm6"); + asm volatile("vcvtpd2dq %xmm1,%xmm2"); + + /* AVX-512: Op code 0f eb */ + + asm volatile("por %mm4,%mm6"); + asm volatile("vpor %ymm4,%ymm6,%ymm2"); + asm volatile("vpord %zmm4,%zmm5,%zmm6"); + asm volatile("vporq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f ef */ + + asm volatile("pxor %mm4,%mm6"); + asm volatile("vpxor %ymm4,%ymm6,%ymm2"); + asm volatile("vpxord %zmm4,%zmm5,%zmm6"); + asm volatile("vpxorq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 10 */ + + asm volatile("pblendvb %xmm1,%xmm0"); + asm volatile("vpsrlvw %zmm4,%zmm5,%zmm6"); + asm volatile("vpmovuswb %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 11 */ + + asm volatile("vpmovusdb %zmm5,%xmm6{%k7}"); + asm volatile("vpsravw %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 12 */ + + asm volatile("vpmovusqb %zmm5,%xmm6{%k7}"); + asm volatile("vpsllvw %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 13 */ + + asm volatile("vcvtph2ps %xmm3,%ymm5"); + asm volatile("vcvtph2ps %ymm5,%zmm6{%k7}"); + asm volatile("vpmovusdw %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 14 */ + + asm volatile("blendvps %xmm1,%xmm0"); + asm volatile("vpmovusqw %zmm5,%xmm6{%k7}"); + asm volatile("vprorvd %zmm4,%zmm5,%zmm6"); + asm volatile("vprorvq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 15 */ + + asm volatile("blendvpd %xmm1,%xmm0"); + asm volatile("vpmovusqd %zmm5,%ymm6{%k7}"); + asm volatile("vprolvd %zmm4,%zmm5,%zmm6"); + asm volatile("vprolvq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 16 */ + + asm volatile("vpermps %ymm4,%ymm6,%ymm2"); + asm volatile("vpermps %ymm4,%ymm6,%ymm2{%k7}"); + asm volatile("vpermpd %ymm4,%ymm6,%ymm2{%k7}"); + + /* AVX-512: Op code 0f 38 19 */ + + asm volatile("vbroadcastsd %xmm4,%ymm6"); + asm volatile("vbroadcastf32x2 %xmm7,%zmm6"); + + /* AVX-512: Op code 0f 38 1a */ + + asm volatile("vbroadcastf128 (%ecx),%ymm4"); + asm volatile("vbroadcastf32x4 (%ecx),%zmm6"); + asm volatile("vbroadcastf64x2 (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 1b */ + + asm volatile("vbroadcastf32x8 (%ecx),%zmm6"); + asm volatile("vbroadcastf64x4 (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 1f */ + + asm volatile("vpabsq %zmm4,%zmm6"); + + /* AVX-512: Op code 0f 38 20 */ + + asm volatile("vpmovsxbw %xmm4,%xmm5"); + asm volatile("vpmovswb %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 21 */ + + asm volatile("vpmovsxbd %xmm4,%ymm6"); + asm volatile("vpmovsdb %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 22 */ + + asm volatile("vpmovsxbq %xmm4,%ymm4"); + asm volatile("vpmovsqb %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 23 */ + + asm volatile("vpmovsxwd %xmm4,%ymm4"); + asm volatile("vpmovsdw %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 24 */ + + asm volatile("vpmovsxwq %xmm4,%ymm6"); + asm volatile("vpmovsqw %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 25 */ + + asm volatile("vpmovsxdq %xmm4,%ymm4"); + asm volatile("vpmovsqd %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 26 */ + + asm volatile("vptestmb %zmm5,%zmm6,%k5"); + asm volatile("vptestmw %zmm5,%zmm6,%k5"); + asm volatile("vptestnmb %zmm4,%zmm5,%k5"); + asm volatile("vptestnmw %zmm4,%zmm5,%k5"); + + /* AVX-512: Op code 0f 38 27 */ + + asm volatile("vptestmd %zmm5,%zmm6,%k5"); + asm volatile("vptestmq %zmm5,%zmm6,%k5"); + asm volatile("vptestnmd %zmm4,%zmm5,%k5"); + asm volatile("vptestnmq %zmm4,%zmm5,%k5"); + + /* AVX-512: Op code 0f 38 28 */ + + asm volatile("vpmuldq %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovm2b %k5,%zmm6"); + asm volatile("vpmovm2w %k5,%zmm6"); + + /* AVX-512: Op code 0f 38 29 */ + + asm volatile("vpcmpeqq %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovb2m %zmm6,%k5"); + asm volatile("vpmovw2m %zmm6,%k5"); + + /* AVX-512: Op code 0f 38 2a */ + + asm volatile("vmovntdqa (%ecx),%ymm4"); + asm volatile("vpbroadcastmb2q %k6,%zmm1"); + + /* AVX-512: Op code 0f 38 2c */ + + asm volatile("vmaskmovps (%ecx),%ymm4,%ymm6"); + asm volatile("vscalefps %zmm4,%zmm5,%zmm6"); + asm volatile("vscalefpd %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 2d */ + + asm volatile("vmaskmovpd (%ecx),%ymm4,%ymm6"); + asm volatile("vscalefss %xmm4,%xmm5,%xmm6{%k7}"); + asm volatile("vscalefsd %xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 30 */ + + asm volatile("vpmovzxbw %xmm4,%ymm4"); + asm volatile("vpmovwb %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 31 */ + + asm volatile("vpmovzxbd %xmm4,%ymm6"); + asm volatile("vpmovdb %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 32 */ + + asm volatile("vpmovzxbq %xmm4,%ymm4"); + asm volatile("vpmovqb %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 33 */ + + asm volatile("vpmovzxwd %xmm4,%ymm4"); + asm volatile("vpmovdw %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 34 */ + + asm volatile("vpmovzxwq %xmm4,%ymm6"); + asm volatile("vpmovqw %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 35 */ + + asm volatile("vpmovzxdq %xmm4,%ymm4"); + asm volatile("vpmovqd %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 36 */ + + asm volatile("vpermd %ymm4,%ymm6,%ymm2"); + asm volatile("vpermd %ymm4,%ymm6,%ymm2{%k7}"); + asm volatile("vpermq %ymm4,%ymm6,%ymm2{%k7}"); + + /* AVX-512: Op code 0f 38 38 */ + + asm volatile("vpminsb %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovm2d %k5,%zmm6"); + asm volatile("vpmovm2q %k5,%zmm6"); + + /* AVX-512: Op code 0f 38 39 */ + + asm volatile("vpminsd %xmm1,%xmm2,%xmm3"); + asm volatile("vpminsd %zmm4,%zmm5,%zmm6"); + asm volatile("vpminsq %zmm4,%zmm5,%zmm6"); + asm volatile("vpmovd2m %zmm6,%k5"); + asm volatile("vpmovq2m %zmm6,%k5"); + + /* AVX-512: Op code 0f 38 3a */ + + asm volatile("vpminuw %ymm4,%ymm6,%ymm2"); + asm volatile("vpbroadcastmw2d %k6,%zmm6"); + + /* AVX-512: Op code 0f 38 3b */ + + asm volatile("vpminud %ymm4,%ymm6,%ymm2"); + asm volatile("vpminud %zmm4,%zmm5,%zmm6"); + asm volatile("vpminuq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 3d */ + + asm volatile("vpmaxsd %ymm4,%ymm6,%ymm2"); + asm volatile("vpmaxsd %zmm4,%zmm5,%zmm6"); + asm volatile("vpmaxsq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 3f */ + + asm volatile("vpmaxud %ymm4,%ymm6,%ymm2"); + asm volatile("vpmaxud %zmm4,%zmm5,%zmm6"); + asm volatile("vpmaxuq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 40 */ + + asm volatile("vpmulld %ymm4,%ymm6,%ymm2"); + asm volatile("vpmulld %zmm4,%zmm5,%zmm6"); + asm volatile("vpmullq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 42 */ + + asm volatile("vgetexpps %zmm5,%zmm6"); + asm volatile("vgetexppd %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 43 */ + + asm volatile("vgetexpss %xmm4,%xmm5,%xmm6{%k7}"); + asm volatile("vgetexpsd %xmm2,%xmm3,%xmm4{%k7}"); + + /* AVX-512: Op code 0f 38 44 */ + + asm volatile("vplzcntd %zmm5,%zmm6"); + asm volatile("vplzcntq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 46 */ + + asm volatile("vpsravd %ymm4,%ymm6,%ymm2"); + asm volatile("vpsravd %zmm4,%zmm5,%zmm6"); + asm volatile("vpsravq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 4c */ + + asm volatile("vrcp14ps %zmm5,%zmm6"); + asm volatile("vrcp14pd %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 4d */ + + asm volatile("vrcp14ss %xmm4,%xmm5,%xmm6{%k7}"); + asm volatile("vrcp14sd %xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 4e */ + + asm volatile("vrsqrt14ps %zmm5,%zmm6"); + asm volatile("vrsqrt14pd %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 4f */ + + asm volatile("vrsqrt14ss %xmm4,%xmm5,%xmm6{%k7}"); + asm volatile("vrsqrt14sd %xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 59 */ + + asm volatile("vpbroadcastq %xmm4,%xmm6"); + asm volatile("vbroadcasti32x2 %xmm7,%zmm6"); + + /* AVX-512: Op code 0f 38 5a */ + + asm volatile("vbroadcasti128 (%ecx),%ymm4"); + asm volatile("vbroadcasti32x4 (%ecx),%zmm6"); + asm volatile("vbroadcasti64x2 (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 5b */ + + asm volatile("vbroadcasti32x8 (%ecx),%zmm6"); + asm volatile("vbroadcasti64x4 (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 64 */ + + asm volatile("vpblendmd %zmm4,%zmm5,%zmm6"); + asm volatile("vpblendmq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 65 */ + + asm volatile("vblendmps %zmm4,%zmm5,%zmm6"); + asm volatile("vblendmpd %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 66 */ + + asm volatile("vpblendmb %zmm4,%zmm5,%zmm6"); + asm volatile("vpblendmw %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 75 */ + + asm volatile("vpermi2b %zmm4,%zmm5,%zmm6"); + asm volatile("vpermi2w %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 76 */ + + asm volatile("vpermi2d %zmm4,%zmm5,%zmm6"); + asm volatile("vpermi2q %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 77 */ + + asm volatile("vpermi2ps %zmm4,%zmm5,%zmm6"); + asm volatile("vpermi2pd %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 7a */ + + asm volatile("vpbroadcastb %eax,%xmm3"); + + /* AVX-512: Op code 0f 38 7b */ + + asm volatile("vpbroadcastw %eax,%xmm3"); + + /* AVX-512: Op code 0f 38 7c */ + + asm volatile("vpbroadcastd %eax,%xmm3"); + + /* AVX-512: Op code 0f 38 7d */ + + asm volatile("vpermt2b %zmm4,%zmm5,%zmm6"); + asm volatile("vpermt2w %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 7e */ + + asm volatile("vpermt2d %zmm4,%zmm5,%zmm6"); + asm volatile("vpermt2q %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 7f */ + + asm volatile("vpermt2ps %zmm4,%zmm5,%zmm6"); + asm volatile("vpermt2pd %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 83 */ + + asm volatile("vpmultishiftqb %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 88 */ + + asm volatile("vexpandps (%ecx),%zmm6"); + asm volatile("vexpandpd (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 89 */ + + asm volatile("vpexpandd (%ecx),%zmm6"); + asm volatile("vpexpandq (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 8a */ + + asm volatile("vcompressps %zmm6,(%ecx)"); + asm volatile("vcompresspd %zmm6,(%ecx)"); + + /* AVX-512: Op code 0f 38 8b */ + + asm volatile("vpcompressd %zmm6,(%ecx)"); + asm volatile("vpcompressq %zmm6,(%ecx)"); + + /* AVX-512: Op code 0f 38 8d */ + + asm volatile("vpermb %zmm4,%zmm5,%zmm6"); + asm volatile("vpermw %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 90 */ + + asm volatile("vpgatherdd %xmm2,0x02(%ebp,%xmm7,2),%xmm1"); + asm volatile("vpgatherdq %xmm2,0x04(%ebp,%xmm7,2),%xmm1"); + asm volatile("vpgatherdd 0x7b(%ebp,%zmm7,8),%zmm6{%k1}"); + asm volatile("vpgatherdq 0x7b(%ebp,%ymm7,8),%zmm6{%k1}"); + + /* AVX-512: Op code 0f 38 91 */ + + asm volatile("vpgatherqd %xmm2,0x02(%ebp,%xmm7,2),%xmm1"); + asm volatile("vpgatherqq %xmm2,0x02(%ebp,%xmm7,2),%xmm1"); + asm volatile("vpgatherqd 0x7b(%ebp,%zmm7,8),%ymm6{%k1}"); + asm volatile("vpgatherqq 0x7b(%ebp,%zmm7,8),%zmm6{%k1}"); + + /* AVX-512: Op code 0f 38 a0 */ + + asm volatile("vpscatterdd %zmm6,0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vpscatterdq %zmm6,0x7b(%ebp,%ymm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 a1 */ + + asm volatile("vpscatterqd %ymm6,0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vpscatterqq %ymm6,0x7b(%ebp,%ymm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 a2 */ + + asm volatile("vscatterdps %zmm6,0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterdpd %zmm6,0x7b(%ebp,%ymm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 a3 */ + + asm volatile("vscatterqps %ymm6,0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterqpd %zmm6,0x7b(%ebp,%zmm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 b4 */ + + asm volatile("vpmadd52luq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 b5 */ + + asm volatile("vpmadd52huq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 c4 */ + + asm volatile("vpconflictd %zmm5,%zmm6"); + asm volatile("vpconflictq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 c8 */ + + asm volatile("vexp2ps %zmm6,%zmm7"); + asm volatile("vexp2pd %zmm6,%zmm7"); + + /* AVX-512: Op code 0f 38 ca */ + + asm volatile("vrcp28ps %zmm6,%zmm7"); + asm volatile("vrcp28pd %zmm6,%zmm7"); + + /* AVX-512: Op code 0f 38 cb */ + + asm volatile("vrcp28ss %xmm5,%xmm6,%xmm7{%k7}"); + asm volatile("vrcp28sd %xmm5,%xmm6,%xmm7{%k7}"); + + /* AVX-512: Op code 0f 38 cc */ + + asm volatile("vrsqrt28ps %zmm6,%zmm7"); + asm volatile("vrsqrt28pd %zmm6,%zmm7"); + + /* AVX-512: Op code 0f 38 cd */ + + asm volatile("vrsqrt28ss %xmm5,%xmm6,%xmm7{%k7}"); + asm volatile("vrsqrt28sd %xmm5,%xmm6,%xmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 03 */ + + asm volatile("valignd $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("valignq $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 08 */ + + asm volatile("vroundps $0x5,%ymm6,%ymm2"); + asm volatile("vrndscaleps $0x12,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 3a 09 */ + + asm volatile("vroundpd $0x5,%ymm6,%ymm2"); + asm volatile("vrndscalepd $0x12,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 3a 0a */ + + asm volatile("vroundss $0x5,%xmm4,%xmm6,%xmm2"); + asm volatile("vrndscaless $0x12,%xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 0b */ + + asm volatile("vroundsd $0x5,%xmm4,%xmm6,%xmm2"); + asm volatile("vrndscalesd $0x12,%xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 18 */ + + asm volatile("vinsertf128 $0x5,%xmm4,%ymm4,%ymm6"); + asm volatile("vinsertf32x4 $0x12,%xmm4,%zmm5,%zmm6{%k7}"); + asm volatile("vinsertf64x2 $0x12,%xmm4,%zmm5,%zmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 19 */ + + asm volatile("vextractf128 $0x5,%ymm4,%xmm4"); + asm volatile("vextractf32x4 $0x12,%zmm5,%xmm6{%k7}"); + asm volatile("vextractf64x2 $0x12,%zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 1a */ + + asm volatile("vinsertf32x8 $0x12,%ymm5,%zmm6,%zmm7{%k7}"); + asm volatile("vinsertf64x4 $0x12,%ymm5,%zmm6,%zmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 1b */ + + asm volatile("vextractf32x8 $0x12,%zmm6,%ymm7{%k7}"); + asm volatile("vextractf64x4 $0x12,%zmm6,%ymm7{%k7}"); + + /* AVX-512: Op code 0f 3a 1e */ + + asm volatile("vpcmpud $0x12,%zmm6,%zmm7,%k5"); + asm volatile("vpcmpuq $0x12,%zmm6,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 1f */ + + asm volatile("vpcmpd $0x12,%zmm6,%zmm7,%k5"); + asm volatile("vpcmpq $0x12,%zmm6,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 23 */ + + asm volatile("vshuff32x4 $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vshuff64x2 $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 25 */ + + asm volatile("vpternlogd $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vpternlogq $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 26 */ + + asm volatile("vgetmantps $0x12,%zmm6,%zmm7"); + asm volatile("vgetmantpd $0x12,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 27 */ + + asm volatile("vgetmantss $0x12,%xmm5,%xmm6,%xmm7{%k7}"); + asm volatile("vgetmantsd $0x12,%xmm5,%xmm6,%xmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 38 */ + + asm volatile("vinserti128 $0x5,%xmm4,%ymm4,%ymm6"); + asm volatile("vinserti32x4 $0x12,%xmm4,%zmm5,%zmm6{%k7}"); + asm volatile("vinserti64x2 $0x12,%xmm4,%zmm5,%zmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 39 */ + + asm volatile("vextracti128 $0x5,%ymm4,%xmm6"); + asm volatile("vextracti32x4 $0x12,%zmm5,%xmm6{%k7}"); + asm volatile("vextracti64x2 $0x12,%zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 3a */ + + asm volatile("vinserti32x8 $0x12,%ymm5,%zmm6,%zmm7{%k7}"); + asm volatile("vinserti64x4 $0x12,%ymm5,%zmm6,%zmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 3b */ + + asm volatile("vextracti32x8 $0x12,%zmm6,%ymm7{%k7}"); + asm volatile("vextracti64x4 $0x12,%zmm6,%ymm7{%k7}"); + + /* AVX-512: Op code 0f 3a 3e */ + + asm volatile("vpcmpub $0x12,%zmm6,%zmm7,%k5"); + asm volatile("vpcmpuw $0x12,%zmm6,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 3f */ + + asm volatile("vpcmpb $0x12,%zmm6,%zmm7,%k5"); + asm volatile("vpcmpw $0x12,%zmm6,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 42 */ + + asm volatile("vmpsadbw $0x5,%ymm4,%ymm6,%ymm2"); + asm volatile("vdbpsadbw $0x12,%zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 3a 43 */ + + asm volatile("vshufi32x4 $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vshufi64x2 $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 50 */ + + asm volatile("vrangeps $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vrangepd $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 51 */ + + asm volatile("vrangess $0x12,%xmm5,%xmm6,%xmm7"); + asm volatile("vrangesd $0x12,%xmm5,%xmm6,%xmm7"); + + /* AVX-512: Op code 0f 3a 54 */ + + asm volatile("vfixupimmps $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vfixupimmpd $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 55 */ + + asm volatile("vfixupimmss $0x12,%xmm5,%xmm6,%xmm7{%k7}"); + asm volatile("vfixupimmsd $0x12,%xmm5,%xmm6,%xmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 56 */ + + asm volatile("vreduceps $0x12,%zmm6,%zmm7"); + asm volatile("vreducepd $0x12,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 57 */ + + asm volatile("vreducess $0x12,%xmm5,%xmm6,%xmm7"); + asm volatile("vreducesd $0x12,%xmm5,%xmm6,%xmm7"); + + /* AVX-512: Op code 0f 3a 66 */ + + asm volatile("vfpclassps $0x12,%zmm7,%k5"); + asm volatile("vfpclasspd $0x12,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 67 */ + + asm volatile("vfpclassss $0x12,%xmm7,%k5"); + asm volatile("vfpclasssd $0x12,%xmm7,%k5"); + + /* AVX-512: Op code 0f 72 (Grp13) */ + + asm volatile("vprord $0x12,%zmm5,%zmm6"); + asm volatile("vprorq $0x12,%zmm5,%zmm6"); + asm volatile("vprold $0x12,%zmm5,%zmm6"); + asm volatile("vprolq $0x12,%zmm5,%zmm6"); + asm volatile("psrad $0x2,%mm6"); + asm volatile("vpsrad $0x5,%ymm6,%ymm2"); + asm volatile("vpsrad $0x5,%zmm6,%zmm2"); + asm volatile("vpsraq $0x5,%zmm6,%zmm2"); + + /* AVX-512: Op code 0f 38 c6 (Grp18) */ + + asm volatile("vgatherpf0dps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf0dpd 0x7b(%ebp,%ymm7,8){%k1}"); + asm volatile("vgatherpf1dps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf1dpd 0x7b(%ebp,%ymm7,8){%k1}"); + asm volatile("vscatterpf0dps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf0dpd 0x7b(%ebp,%ymm7,8){%k1}"); + asm volatile("vscatterpf1dps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf1dpd 0x7b(%ebp,%ymm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 c7 (Grp19) */ + + asm volatile("vgatherpf0qps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf0qpd 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf1qps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf1qpd 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf0qps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf0qpd 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf1qps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf1qpd 0x7b(%ebp,%zmm7,8){%k1}"); + + /* AVX-512: Examples */ + + asm volatile("vaddpd %zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd %zmm4,%zmm5,%zmm6{%k7}"); + asm volatile("vaddpd %zmm4,%zmm5,%zmm6{%k7}{z}"); + asm volatile("vaddpd {rn-sae},%zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd {ru-sae},%zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd {rd-sae},%zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd {rz-sae},%zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd (%ecx),%zmm5,%zmm6"); + asm volatile("vaddpd 0x123(%eax,%ecx,8),%zmm5,%zmm6"); + asm volatile("vaddpd (%ecx){1to8},%zmm5,%zmm6"); + asm volatile("vaddpd 0x1fc0(%edx),%zmm5,%zmm6"); + asm volatile("vaddpd 0x3f8(%edx){1to8},%zmm5,%zmm6"); + asm volatile("vcmpeq_uqps 0x1fc(%edx){1to16},%zmm6,%k5"); + asm volatile("vcmpltsd 0x123(%eax,%ecx,8),%xmm3,%k5{%k7}"); + asm volatile("vcmplesd {sae},%xmm4,%xmm5,%k5{%k7}"); + asm volatile("vgetmantss $0x5b,0x123(%eax,%ecx,8),%xmm4,%xmm5{%k7}"); + /* bndmk m32, bnd */ asm volatile("bndmk (%eax), %bnd0"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [tip:perf/core] perf tools: Add AVX-512 instructions to the new instructions test 2016-07-20 8:30 ` [PATCH V2 4/4] perf tools: Add AVX-512 instructions to the new instructions test Adrian Hunter @ 2016-07-25 18:09 ` tip-bot for Adrian Hunter 0 siblings, 0 replies; 18+ messages in thread From: tip-bot for Adrian Hunter @ 2016-07-25 18:09 UTC (permalink / raw) To: linux-tip-commits Cc: hpa, adrian.hunter, luto, mingo, tglx, linux-kernel, jolsa, dan.j.williams, acme, mhiramat, x86 Commit-ID: 6c4d0b41ce3e61fe87e6195582c66cd262399b82 Gitweb: http://git.kernel.org/tip/6c4d0b41ce3e61fe87e6195582c66cd262399b82 Author: Adrian Hunter <adrian.hunter@intel.com> AuthorDate: Wed, 20 Jul 2016 11:30:37 +0300 Committer: Arnaldo Carvalho de Melo <acme@redhat.com> CommitDate: Thu, 21 Jul 2016 09:37:26 -0300 perf tools: Add AVX-512 instructions to the new instructions test Previous patches added support for Intel's AVX-512 instructions to the kernel and perf tools instruction decoders. AVX-512 instructions are documented in Intel Architecture Instruction Set Extensions Programming Reference (February 2016). Add a representative set of instructions to perf's "new instructions" test. e.g. perf test "new instructions" Or to view a particular instruction: perf test -v "new instructions" 2>&1 | grep vbroadcasti64x4 Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ingo Molnar <mingo@kernel.org> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dan Williams <dan.j.williams@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: X86 ML <x86@kernel.org> Link: http://lkml.kernel.org/r/1469003437-32706-5-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> --- tools/perf/arch/x86/tests/insn-x86-dat-32.c | 1016 ++++++++++++++- tools/perf/arch/x86/tests/insn-x86-dat-64.c | 938 +++++++++++++- tools/perf/arch/x86/tests/insn-x86-dat-src.c | 1785 ++++++++++++++++++++++++++ 3 files changed, 3731 insertions(+), 8 deletions(-) diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c index ca08e6e..3918dd5 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-32.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c @@ -8,6 +8,1014 @@ "0f 31 \trdtsc ",}, {{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "", "c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",}, +{{0x62, 0x81, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 81 78 56 34 12 \tbound %eax,0x12345678(%ecx)",}, +{{0x62, 0x88, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 88 78 56 34 12 \tbound %ecx,0x12345678(%eax)",}, +{{0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 90 78 56 34 12 \tbound %edx,0x12345678(%eax)",}, +{{0x62, 0x98, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 98 78 56 34 12 \tbound %ebx,0x12345678(%eax)",}, +{{0x62, 0xa0, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 a0 78 56 34 12 \tbound %esp,0x12345678(%eax)",}, +{{0x62, 0xa8, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 a8 78 56 34 12 \tbound %ebp,0x12345678(%eax)",}, +{{0x62, 0xb0, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 b0 78 56 34 12 \tbound %esi,0x12345678(%eax)",}, +{{0x62, 0xb8, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 b8 78 56 34 12 \tbound %edi,0x12345678(%eax)",}, +{{0x62, 0x08, }, 2, 0, "", "", +"62 08 \tbound %ecx,(%eax)",}, +{{0x62, 0x05, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 05 78 56 34 12 \tbound %eax,0x12345678",}, +{{0x62, 0x14, 0x01, }, 3, 0, "", "", +"62 14 01 \tbound %edx,(%ecx,%eax,1)",}, +{{0x62, 0x14, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 14 05 78 56 34 12 \tbound %edx,0x12345678(,%eax,1)",}, +{{0x62, 0x14, 0x08, }, 3, 0, "", "", +"62 14 08 \tbound %edx,(%eax,%ecx,1)",}, +{{0x62, 0x14, 0xc8, }, 3, 0, "", "", +"62 14 c8 \tbound %edx,(%eax,%ecx,8)",}, +{{0x62, 0x50, 0x12, }, 3, 0, "", "", +"62 50 12 \tbound %edx,0x12(%eax)",}, +{{0x62, 0x55, 0x12, }, 3, 0, "", "", +"62 55 12 \tbound %edx,0x12(%ebp)",}, +{{0x62, 0x54, 0x01, 0x12, }, 4, 0, "", "", +"62 54 01 12 \tbound %edx,0x12(%ecx,%eax,1)",}, +{{0x62, 0x54, 0x05, 0x12, }, 4, 0, "", "", +"62 54 05 12 \tbound %edx,0x12(%ebp,%eax,1)",}, +{{0x62, 0x54, 0x08, 0x12, }, 4, 0, "", "", +"62 54 08 12 \tbound %edx,0x12(%eax,%ecx,1)",}, +{{0x62, 0x54, 0xc8, 0x12, }, 4, 0, "", "", +"62 54 c8 12 \tbound %edx,0x12(%eax,%ecx,8)",}, +{{0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 90 78 56 34 12 \tbound %edx,0x12345678(%eax)",}, +{{0x62, 0x95, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "", +"62 95 78 56 34 12 \tbound %edx,0x12345678(%ebp)",}, +{{0x62, 0x94, 0x01, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 94 01 78 56 34 12 \tbound %edx,0x12345678(%ecx,%eax,1)",}, +{{0x62, 0x94, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 94 05 78 56 34 12 \tbound %edx,0x12345678(%ebp,%eax,1)",}, +{{0x62, 0x94, 0x08, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 94 08 78 56 34 12 \tbound %edx,0x12345678(%eax,%ecx,1)",}, +{{0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"62 94 c8 78 56 34 12 \tbound %edx,0x12345678(%eax,%ecx,8)",}, +{{0x66, 0x62, 0x81, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"66 62 81 78 56 34 12 \tbound %ax,0x12345678(%ecx)",}, +{{0x66, 0x62, 0x88, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"66 62 88 78 56 34 12 \tbound %cx,0x12345678(%eax)",}, +{{0x66, 0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"66 62 90 78 56 34 12 \tbound %dx,0x12345678(%eax)",}, +{{0x66, 0x62, 0x98, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", 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0x4d, 0x08, 0x57, 0xfd, 0x12, }, 7, 0, "", "", +"62 f3 4d 08 57 fd 12 \tvreducess $0x12,%xmm5,%xmm6,%xmm7",}, +{{0x62, 0xf3, 0xcd, 0x08, 0x57, 0xfd, 0x12, }, 7, 0, "", "", +"62 f3 cd 08 57 fd 12 \tvreducesd $0x12,%xmm5,%xmm6,%xmm7",}, +{{0x62, 0xf3, 0x7d, 0x48, 0x66, 0xef, 0x12, }, 7, 0, "", "", +"62 f3 7d 48 66 ef 12 \tvfpclassps $0x12,%zmm7,%k5",}, +{{0x62, 0xf3, 0xfd, 0x48, 0x66, 0xef, 0x12, }, 7, 0, "", "", +"62 f3 fd 48 66 ef 12 \tvfpclasspd $0x12,%zmm7,%k5",}, +{{0x62, 0xf3, 0x7d, 0x08, 0x67, 0xef, 0x12, }, 7, 0, "", "", +"62 f3 7d 08 67 ef 12 \tvfpclassss $0x12,%xmm7,%k5",}, +{{0x62, 0xf3, 0xfd, 0x08, 0x67, 0xef, 0x12, }, 7, 0, "", "", +"62 f3 fd 08 67 ef 12 \tvfpclasssd $0x12,%xmm7,%k5",}, +{{0x62, 0xf1, 0x4d, 0x48, 0x72, 0xc5, 0x12, }, 7, 0, "", "", +"62 f1 4d 48 72 c5 12 \tvprord $0x12,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xcd, 0x48, 0x72, 0xc5, 0x12, }, 7, 0, "", "", +"62 f1 cd 48 72 c5 12 \tvprorq $0x12,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0x4d, 0x48, 0x72, 0xcd, 0x12, }, 7, 0, "", "", +"62 f1 4d 48 72 cd 12 \tvprold $0x12,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xcd, 0x48, 0x72, 0xcd, 0x12, }, 7, 0, "", "", +"62 f1 cd 48 72 cd 12 \tvprolq $0x12,%zmm5,%zmm6",}, +{{0x0f, 0x72, 0xe6, 0x02, }, 4, 0, "", "", +"0f 72 e6 02 \tpsrad $0x2,%mm6",}, +{{0xc5, 0xed, 0x72, 0xe6, 0x05, }, 5, 0, "", "", +"c5 ed 72 e6 05 \tvpsrad $0x5,%ymm6,%ymm2",}, +{{0x62, 0xf1, 0x6d, 0x48, 0x72, 0xe6, 0x05, }, 7, 0, "", "", +"62 f1 6d 48 72 e6 05 \tvpsrad $0x5,%zmm6,%zmm2",}, +{{0x62, 0xf1, 0xed, 0x48, 0x72, 0xe6, 0x05, }, 7, 0, "", "", +"62 f1 ed 48 72 e6 05 \tvpsraq $0x5,%zmm6,%zmm2",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c6 8c fd 7b 00 00 00 \tvgatherpf0dps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c6 8c fd 7b 00 00 00 \tvgatherpf0dpd 0x7b(%ebp,%ymm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c6 94 fd 7b 00 00 00 \tvgatherpf1dps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c6 94 fd 7b 00 00 00 \tvgatherpf1dpd 0x7b(%ebp,%ymm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c6 ac fd 7b 00 00 00 \tvscatterpf0dps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c6 ac fd 7b 00 00 00 \tvscatterpf0dpd 0x7b(%ebp,%ymm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c6 b4 fd 7b 00 00 00 \tvscatterpf1dps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c6 b4 fd 7b 00 00 00 \tvscatterpf1dpd 0x7b(%ebp,%ymm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c7 8c fd 7b 00 00 00 \tvgatherpf0qps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c7 8c fd 7b 00 00 00 \tvgatherpf0qpd 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c7 94 fd 7b 00 00 00 \tvgatherpf1qps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c7 94 fd 7b 00 00 00 \tvgatherpf1qpd 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c7 ac fd 7b 00 00 00 \tvscatterpf0qps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c7 ac fd 7b 00 00 00 \tvscatterpf0qpd 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 7d 49 c7 b4 fd 7b 00 00 00 \tvscatterpf1qps 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 f2 fd 49 c7 b4 fd 7b 00 00 00 \tvscatterpf1qpd 0x7b(%ebp,%zmm7,8){%k1}",}, +{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 48 58 f4 \tvaddpd %zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x4f, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 4f 58 f4 \tvaddpd %zmm4,%zmm5,%zmm6{%k7}",}, +{{0x62, 0xf1, 0xd5, 0xcf, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 cf 58 f4 \tvaddpd %zmm4,%zmm5,%zmm6{%k7}{z}",}, +{{0x62, 0xf1, 0xd5, 0x18, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 18 58 f4 \tvaddpd {rn-sae},%zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x58, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 58 58 f4 \tvaddpd {ru-sae},%zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x38, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 38 58 f4 \tvaddpd {rd-sae},%zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x78, 0x58, 0xf4, }, 6, 0, "", "", +"62 f1 d5 78 58 f4 \tvaddpd {rz-sae},%zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0x31, }, 6, 0, "", "", +"62 f1 d5 48 58 31 \tvaddpd (%ecx),%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0xb4, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 11, 0, "", "", +"62 f1 d5 48 58 b4 c8 23 01 00 00 \tvaddpd 0x123(%eax,%ecx,8),%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x58, 0x58, 0x31, }, 6, 0, "", "", +"62 f1 d5 58 58 31 \tvaddpd (%ecx){1to8},%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0x72, 0x7f, }, 7, 0, "", "", +"62 f1 d5 48 58 72 7f \tvaddpd 0x1fc0(%edx),%zmm5,%zmm6",}, +{{0x62, 0xf1, 0xd5, 0x58, 0x58, 0x72, 0x7f, }, 7, 0, "", "", +"62 f1 d5 58 58 72 7f \tvaddpd 0x3f8(%edx){1to8},%zmm5,%zmm6",}, +{{0x62, 0xf1, 0x4c, 0x58, 0xc2, 0x6a, 0x7f, 0x08, }, 8, 0, "", "", +"62 f1 4c 58 c2 6a 7f 08 \tvcmpeq_uqps 0x1fc(%edx){1to16},%zmm6,%k5",}, +{{0x62, 0xf1, 0xe7, 0x0f, 0xc2, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, 0x01, }, 12, 0, "", "", +"62 f1 e7 0f c2 ac c8 23 01 00 00 01 \tvcmpltsd 0x123(%eax,%ecx,8),%xmm3,%k5{%k7}",}, +{{0x62, 0xf1, 0xd7, 0x1f, 0xc2, 0xec, 0x02, }, 7, 0, "", "", +"62 f1 d7 1f c2 ec 02 \tvcmplesd {sae},%xmm4,%xmm5,%k5{%k7}",}, +{{0x62, 0xf3, 0x5d, 0x0f, 0x27, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, 0x5b, }, 12, 0, "", "", +"62 f3 5d 0f 27 ac c8 23 01 00 00 5b \tvgetmantss $0x5b,0x123(%eax,%ecx,8),%xmm4,%xmm5{%k7}",}, {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", "f3 0f 1b 00 \tbndmk (%eax),%bnd0",}, {{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", @@ -311,19 +1319,19 @@ {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax,%ecx,1)",}, {{0xf2, 0xe8, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "call", "unconditional", -"f2 e8 fc ff ff ff \tbnd call 3c8 <main+0x3c8>",}, +"f2 e8 fc ff ff ff \tbnd call fce <main+0xfce>",}, {{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect", "f2 ff 10 \tbnd call *(%eax)",}, {{0xf2, 0xc3, }, 2, 0, "ret", "indirect", "f2 c3 \tbnd ret ",}, {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", -"f2 e9 fc ff ff ff \tbnd jmp 3d3 <main+0x3d3>",}, +"f2 e9 fc ff ff ff \tbnd jmp fd9 <main+0xfd9>",}, {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", -"f2 e9 fc ff ff ff \tbnd jmp 3d9 <main+0x3d9>",}, +"f2 e9 fc ff ff ff \tbnd jmp fdf <main+0xfdf>",}, {{0xf2, 0xff, 0x21, }, 3, 0, "jmp", "indirect", "f2 ff 21 \tbnd jmp *(%ecx)",}, {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffffffc, "jcc", "conditional", -"f2 0f 85 fc ff ff ff \tbnd jne 3e3 <main+0x3e3>",}, +"f2 0f 85 fc ff ff ff \tbnd jne fe9 <main+0xfe9>",}, {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "", "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",}, {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "", diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-64.c b/tools/perf/arch/x86/tests/insn-x86-dat-64.c index 262d9d2..9c8c61e 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-64.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-64.c @@ -8,6 +8,936 @@ "0f 31 \trdtsc ",}, {{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "", "c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",}, +{{0x48, 0x0f, 0x41, 0xd8, }, 4, 0, "", "", +"48 0f 41 d8 \tcmovno %rax,%rbx",}, +{{0x48, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"48 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%rcx",}, +{{0x66, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"66 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%cx",}, +{{0x48, 0x0f, 0x44, 0xd8, }, 4, 0, "", "", +"48 0f 44 d8 \tcmove %rax,%rbx",}, +{{0x48, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"48 0f 44 88 78 56 34 12 \tcmove 0x12345678(%rax),%rcx",}, +{{0x66, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"66 0f 44 88 78 56 34 12 \tcmove 0x12345678(%rax),%cx",}, +{{0x0f, 0x90, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 90 80 78 56 34 12 \tseto 0x12345678(%rax)",}, +{{0x0f, 0x91, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 91 80 78 56 34 12 \tsetno 0x12345678(%rax)",}, +{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",}, +{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",}, +{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",}, +{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",}, +{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",}, +{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",}, +{{0x0f, 0x98, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 98 80 78 56 34 12 \tsets 0x12345678(%rax)",}, +{{0x0f, 0x99, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 99 80 78 56 34 12 \tsetns 0x12345678(%rax)",}, +{{0xc5, 0xcc, 0x41, 0xef, }, 4, 0, "", "", +"c5 cc 41 ef \tkandw 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94 fe 7b 00 00 00 \tvgatherpf1qpd 0x7b(%r14,%zmm31,8){%k1}",}, +{{0x62, 0x92, 0x7d, 0x41, 0xc7, 0xac, 0xfe, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 92 7d 41 c7 ac fe 7b 00 00 00 \tvscatterpf0qps 0x7b(%r14,%zmm31,8){%k1}",}, +{{0x62, 0x92, 0xfd, 0x41, 0xc7, 0xac, 0xfe, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 92 fd 41 c7 ac fe 7b 00 00 00 \tvscatterpf0qpd 0x7b(%r14,%zmm31,8){%k1}",}, +{{0x62, 0x92, 0x7d, 0x41, 0xc7, 0xb4, 0xfe, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 92 7d 41 c7 b4 fe 7b 00 00 00 \tvscatterpf1qps 0x7b(%r14,%zmm31,8){%k1}",}, +{{0x62, 0x92, 0xfd, 0x41, 0xc7, 0xb4, 0xfe, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", +"62 92 fd 41 c7 b4 fe 7b 00 00 00 \tvscatterpf1qpd 0x7b(%r14,%zmm31,8){%k1}",}, +{{0x62, 0x01, 0x95, 0x40, 0x58, 0xf4, }, 6, 0, "", "", +"62 01 95 40 58 f4 \tvaddpd %zmm28,%zmm29,%zmm30",}, +{{0x62, 0x01, 0x95, 0x47, 0x58, 0xf4, }, 6, 0, "", "", +"62 01 95 47 58 f4 \tvaddpd %zmm28,%zmm29,%zmm30{%k7}",}, +{{0x62, 0x01, 0x95, 0xc7, 0x58, 0xf4, }, 6, 0, "", "", +"62 01 95 c7 58 f4 \tvaddpd %zmm28,%zmm29,%zmm30{%k7}{z}",}, +{{0x62, 0x01, 0x95, 0x10, 0x58, 0xf4, }, 6, 0, "", "", +"62 01 95 10 58 f4 \tvaddpd {rn-sae},%zmm28,%zmm29,%zmm30",}, +{{0x62, 0x01, 0x95, 0x50, 0x58, 0xf4, }, 6, 0, "", "", +"62 01 95 50 58 f4 \tvaddpd {ru-sae},%zmm28,%zmm29,%zmm30",}, +{{0x62, 0x01, 0x95, 0x30, 0x58, 0xf4, }, 6, 0, "", "", +"62 01 95 30 58 f4 \tvaddpd {rd-sae},%zmm28,%zmm29,%zmm30",}, +{{0x62, 0x01, 0x95, 0x70, 0x58, 0xf4, }, 6, 0, "", "", +"62 01 95 70 58 f4 \tvaddpd {rz-sae},%zmm28,%zmm29,%zmm30",}, +{{0x62, 0x61, 0x95, 0x40, 0x58, 0x31, }, 6, 0, "", "", +"62 61 95 40 58 31 \tvaddpd (%rcx),%zmm29,%zmm30",}, +{{0x62, 0x21, 0x95, 0x40, 0x58, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00, }, 11, 0, "", "", +"62 21 95 40 58 b4 f0 23 01 00 00 \tvaddpd 0x123(%rax,%r14,8),%zmm29,%zmm30",}, +{{0x62, 0x61, 0x95, 0x50, 0x58, 0x31, }, 6, 0, "", "", +"62 61 95 50 58 31 \tvaddpd (%rcx){1to8},%zmm29,%zmm30",}, +{{0x62, 0x61, 0x95, 0x40, 0x58, 0x72, 0x7f, }, 7, 0, "", "", +"62 61 95 40 58 72 7f \tvaddpd 0x1fc0(%rdx),%zmm29,%zmm30",}, +{{0x62, 0x61, 0x95, 0x50, 0x58, 0x72, 0x7f, }, 7, 0, "", "", +"62 61 95 50 58 72 7f \tvaddpd 0x3f8(%rdx){1to8},%zmm29,%zmm30",}, +{{0x62, 0xf1, 0x0c, 0x50, 0xc2, 0x6a, 0x7f, 0x08, }, 8, 0, "", "", +"62 f1 0c 50 c2 6a 7f 08 \tvcmpeq_uqps 0x1fc(%rdx){1to16},%zmm30,%k5",}, +{{0x62, 0xb1, 0x97, 0x07, 0xc2, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x01, }, 12, 0, "", "", +"62 b1 97 07 c2 ac f0 23 01 00 00 01 \tvcmpltsd 0x123(%rax,%r14,8),%xmm29,%k5{%k7}",}, +{{0x62, 0x91, 0x97, 0x17, 0xc2, 0xec, 0x02, }, 7, 0, "", "", +"62 91 97 17 c2 ec 02 \tvcmplesd {sae},%xmm28,%xmm29,%k5{%k7}",}, +{{0x62, 0x23, 0x15, 0x07, 0x27, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00, 0x5b, }, 12, 0, "", "", +"62 23 15 07 27 b4 f0 23 01 00 00 5b \tvgetmantss $0x5b,0x123(%rax,%r14,8),%xmm29,%xmm30{%k7}",}, {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", "f3 0f 1b 00 \tbndmk (%rax),%bnd0",}, {{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", @@ -327,19 +1257,19 @@ {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",}, {{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional", -"f2 e8 00 00 00 00 \tbnd callq 3fb <main+0x3fb>",}, +"f2 e8 00 00 00 00 \tbnd callq f22 <main+0xf22>",}, {{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect", "67 f2 ff 10 \tbnd callq *(%eax)",}, {{0xf2, 0xc3, }, 2, 0, "ret", "indirect", "f2 c3 \tbnd retq ",}, {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", -"f2 e9 00 00 00 00 \tbnd jmpq 407 <main+0x407>",}, +"f2 e9 00 00 00 00 \tbnd jmpq f2e <main+0xf2e>",}, {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", -"f2 e9 00 00 00 00 \tbnd jmpq 40d <main+0x40d>",}, +"f2 e9 00 00 00 00 \tbnd jmpq f34 <main+0xf34>",}, {{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect", "67 f2 ff 21 \tbnd jmpq *(%ecx)",}, {{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional", -"f2 0f 85 00 00 00 00 \tbnd jne 418 <main+0x418>",}, +"f2 0f 85 00 00 00 00 \tbnd jne f3f <main+0xf3f>",}, {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "", "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",}, {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "", diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c index 3cd6775..76e0ec3 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-src.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c @@ -25,6 +25,876 @@ int main(void) #ifdef __x86_64__ + /* AVX-512: Instructions with the same op codes as Mask Instructions */ + + asm volatile("cmovno %rax,%rbx"); + asm volatile("cmovno 0x12345678(%rax),%rcx"); + asm volatile("cmovno 0x12345678(%rax),%cx"); + + asm volatile("cmove %rax,%rbx"); + asm volatile("cmove 0x12345678(%rax),%rcx"); + asm volatile("cmove 0x12345678(%rax),%cx"); + + asm volatile("seto 0x12345678(%rax)"); + asm volatile("setno 0x12345678(%rax)"); + asm volatile("setb 0x12345678(%rax)"); + asm volatile("setc 0x12345678(%rax)"); + asm volatile("setnae 0x12345678(%rax)"); + asm volatile("setae 0x12345678(%rax)"); + asm volatile("setnb 0x12345678(%rax)"); + asm volatile("setnc 0x12345678(%rax)"); + asm volatile("sets 0x12345678(%rax)"); + asm volatile("setns 0x12345678(%rax)"); + + /* AVX-512: Mask Instructions */ + + asm volatile("kandw %k7,%k6,%k5"); + asm volatile("kandq %k7,%k6,%k5"); + asm volatile("kandb %k7,%k6,%k5"); + asm volatile("kandd %k7,%k6,%k5"); + + asm volatile("kandnw %k7,%k6,%k5"); + asm volatile("kandnq %k7,%k6,%k5"); + asm volatile("kandnb %k7,%k6,%k5"); + asm volatile("kandnd %k7,%k6,%k5"); + + asm volatile("knotw %k7,%k6"); + asm volatile("knotq %k7,%k6"); + asm volatile("knotb %k7,%k6"); + asm volatile("knotd %k7,%k6"); + + asm volatile("korw %k7,%k6,%k5"); + asm volatile("korq %k7,%k6,%k5"); + asm volatile("korb %k7,%k6,%k5"); + asm volatile("kord %k7,%k6,%k5"); + + asm volatile("kxnorw %k7,%k6,%k5"); + asm volatile("kxnorq %k7,%k6,%k5"); + asm volatile("kxnorb %k7,%k6,%k5"); + asm volatile("kxnord %k7,%k6,%k5"); + + asm volatile("kxorw %k7,%k6,%k5"); + asm volatile("kxorq %k7,%k6,%k5"); + asm volatile("kxorb %k7,%k6,%k5"); + asm volatile("kxord %k7,%k6,%k5"); + + asm volatile("kaddw %k7,%k6,%k5"); + asm volatile("kaddq %k7,%k6,%k5"); + asm volatile("kaddb %k7,%k6,%k5"); + asm volatile("kaddd %k7,%k6,%k5"); + + asm volatile("kunpckbw %k7,%k6,%k5"); + asm volatile("kunpckwd %k7,%k6,%k5"); + asm volatile("kunpckdq %k7,%k6,%k5"); + + asm volatile("kmovw %k6,%k5"); + asm volatile("kmovw (%rcx),%k5"); + asm volatile("kmovw 0x123(%rax,%r14,8),%k5"); + asm volatile("kmovw %k5,(%rcx)"); + asm volatile("kmovw %k5,0x123(%rax,%r14,8)"); + asm volatile("kmovw %eax,%k5"); + asm volatile("kmovw %ebp,%k5"); + asm volatile("kmovw %r13d,%k5"); + asm volatile("kmovw %k5,%eax"); + asm volatile("kmovw %k5,%ebp"); + asm volatile("kmovw %k5,%r13d"); + + asm volatile("kmovq %k6,%k5"); + asm volatile("kmovq (%rcx),%k5"); + asm volatile("kmovq 0x123(%rax,%r14,8),%k5"); + asm volatile("kmovq %k5,(%rcx)"); + asm volatile("kmovq %k5,0x123(%rax,%r14,8)"); + asm volatile("kmovq %rax,%k5"); + asm volatile("kmovq %rbp,%k5"); + asm volatile("kmovq %r13,%k5"); + asm volatile("kmovq %k5,%rax"); + asm volatile("kmovq %k5,%rbp"); + asm volatile("kmovq %k5,%r13"); + + asm volatile("kmovb %k6,%k5"); + asm volatile("kmovb (%rcx),%k5"); + asm volatile("kmovb 0x123(%rax,%r14,8),%k5"); + asm volatile("kmovb %k5,(%rcx)"); + asm volatile("kmovb %k5,0x123(%rax,%r14,8)"); + asm volatile("kmovb %eax,%k5"); + asm volatile("kmovb %ebp,%k5"); + asm volatile("kmovb %r13d,%k5"); + asm volatile("kmovb %k5,%eax"); + asm volatile("kmovb %k5,%ebp"); + asm volatile("kmovb %k5,%r13d"); + + asm volatile("kmovd %k6,%k5"); + asm volatile("kmovd (%rcx),%k5"); + asm volatile("kmovd 0x123(%rax,%r14,8),%k5"); + asm volatile("kmovd %k5,(%rcx)"); + asm volatile("kmovd %k5,0x123(%rax,%r14,8)"); + asm volatile("kmovd %eax,%k5"); + asm volatile("kmovd %ebp,%k5"); + asm volatile("kmovd %r13d,%k5"); + asm volatile("kmovd %k5,%eax"); + asm volatile("kmovd %k5,%ebp"); + asm volatile("kmovd %k5,%r13d"); + + asm volatile("kortestw %k6,%k5"); + asm volatile("kortestq %k6,%k5"); + asm volatile("kortestb %k6,%k5"); + asm volatile("kortestd %k6,%k5"); + + asm volatile("ktestw %k6,%k5"); + asm volatile("ktestq %k6,%k5"); + asm volatile("ktestb %k6,%k5"); + asm volatile("ktestd %k6,%k5"); + + asm volatile("kshiftrw $0x12,%k6,%k5"); + asm volatile("kshiftrq $0x5b,%k6,%k5"); + asm volatile("kshiftlw $0x12,%k6,%k5"); + asm volatile("kshiftlq $0x5b,%k6,%k5"); + + /* AVX-512: Op code 0f 5b */ + asm volatile("vcvtdq2ps %xmm5,%xmm6"); + asm volatile("vcvtqq2ps %zmm29,%ymm6{%k7}"); + asm volatile("vcvtps2dq %xmm5,%xmm6"); + asm volatile("vcvttps2dq %xmm5,%xmm6"); + + /* AVX-512: Op code 0f 6f */ + + asm volatile("movq %mm0,%mm4"); + asm volatile("vmovdqa %ymm4,%ymm6"); + asm volatile("vmovdqa32 %zmm25,%zmm26"); + asm volatile("vmovdqa64 %zmm25,%zmm26"); + asm volatile("vmovdqu %ymm4,%ymm6"); + asm volatile("vmovdqu32 %zmm29,%zmm30"); + asm volatile("vmovdqu64 %zmm25,%zmm26"); + asm volatile("vmovdqu8 %zmm29,%zmm30"); + asm volatile("vmovdqu16 %zmm25,%zmm26"); + + /* AVX-512: Op code 0f 78 */ + + asm volatile("vmread %rax,%rbx"); + asm volatile("vcvttps2udq %zmm25,%zmm26"); + asm volatile("vcvttpd2udq %zmm29,%ymm6{%k7}"); + asm volatile("vcvttsd2usi %xmm6,%rax"); + asm volatile("vcvttss2usi %xmm6,%rax"); + asm volatile("vcvttps2uqq %ymm5,%zmm26{%k7}"); + asm volatile("vcvttpd2uqq %zmm29,%zmm30"); + + /* AVX-512: Op code 0f 79 */ + + asm volatile("vmwrite %rax,%rbx"); + asm volatile("vcvtps2udq %zmm25,%zmm26"); + asm volatile("vcvtpd2udq %zmm29,%ymm6{%k7}"); + asm volatile("vcvtsd2usi %xmm6,%rax"); + asm volatile("vcvtss2usi %xmm6,%rax"); + asm volatile("vcvtps2uqq %ymm5,%zmm26{%k7}"); + asm volatile("vcvtpd2uqq %zmm29,%zmm30"); + + /* AVX-512: Op code 0f 7a */ + + asm volatile("vcvtudq2pd %ymm5,%zmm29{%k7}"); + asm volatile("vcvtuqq2pd %zmm25,%zmm26"); + asm volatile("vcvtudq2ps %zmm29,%zmm30"); + asm volatile("vcvtuqq2ps %zmm25,%ymm26{%k7}"); + asm volatile("vcvttps2qq %ymm25,%zmm26{%k7}"); + asm volatile("vcvttpd2qq %zmm29,%zmm30"); + + /* AVX-512: Op code 0f 7b */ + + asm volatile("vcvtusi2sd %eax,%xmm5,%xmm6"); + asm volatile("vcvtusi2ss %eax,%xmm5,%xmm6"); + asm volatile("vcvtps2qq %ymm5,%zmm26{%k7}"); + asm volatile("vcvtpd2qq %zmm29,%zmm30"); + + /* AVX-512: Op code 0f 7f */ + + asm volatile("movq.s %mm0,%mm4"); + asm volatile("vmovdqa %ymm8,%ymm6"); + asm volatile("vmovdqa32.s %zmm25,%zmm26"); + asm volatile("vmovdqa64.s %zmm25,%zmm26"); + asm volatile("vmovdqu %ymm8,%ymm6"); + asm volatile("vmovdqu32.s %zmm25,%zmm26"); + asm volatile("vmovdqu64.s %zmm25,%zmm26"); + asm volatile("vmovdqu8.s %zmm30,(%rcx)"); + asm volatile("vmovdqu16.s %zmm25,%zmm26"); + + /* AVX-512: Op code 0f db */ + + asm volatile("pand %mm1,%mm2"); + asm volatile("pand %xmm1,%xmm2"); + asm volatile("vpand %ymm4,%ymm6,%ymm2"); + asm volatile("vpandd %zmm24,%zmm25,%zmm26"); + asm volatile("vpandq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f df */ + + asm volatile("pandn %mm1,%mm2"); + asm volatile("pandn %xmm1,%xmm2"); + asm volatile("vpandn %ymm4,%ymm6,%ymm2"); + asm volatile("vpandnd %zmm24,%zmm25,%zmm26"); + asm volatile("vpandnq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f e6 */ + + asm volatile("vcvttpd2dq %xmm1,%xmm2"); + asm volatile("vcvtdq2pd %xmm5,%xmm6"); + asm volatile("vcvtdq2pd %ymm5,%zmm26{%k7}"); + asm volatile("vcvtqq2pd %zmm25,%zmm26"); + asm volatile("vcvtpd2dq %xmm1,%xmm2"); + + /* AVX-512: Op code 0f eb */ + + asm volatile("por %mm4,%mm6"); + asm volatile("vpor %ymm4,%ymm6,%ymm2"); + asm volatile("vpord %zmm24,%zmm25,%zmm26"); + asm volatile("vporq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f ef */ + + asm volatile("pxor %mm4,%mm6"); + asm volatile("vpxor %ymm4,%ymm6,%ymm2"); + asm volatile("vpxord %zmm24,%zmm25,%zmm26"); + asm volatile("vpxorq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 10 */ + + asm volatile("pblendvb %xmm1,%xmm0"); + asm volatile("vpsrlvw %zmm27,%zmm28,%zmm29"); + asm volatile("vpmovuswb %zmm28,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 11 */ + + asm volatile("vpmovusdb %zmm28,%xmm6{%k7}"); + asm volatile("vpsravw %zmm27,%zmm28,%zmm29"); + + /* AVX-512: Op code 0f 38 12 */ + + asm volatile("vpmovusqb %zmm27,%xmm6{%k7}"); + asm volatile("vpsllvw %zmm27,%zmm28,%zmm29"); + + /* AVX-512: Op code 0f 38 13 */ + + asm volatile("vcvtph2ps %xmm3,%ymm5"); + asm volatile("vcvtph2ps %ymm5,%zmm27{%k7}"); + asm volatile("vpmovusdw %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 14 */ + + asm volatile("blendvps %xmm1,%xmm0"); + asm volatile("vpmovusqw %zmm27,%xmm6{%k7}"); + asm volatile("vprorvd %zmm27,%zmm28,%zmm29"); + asm volatile("vprorvq %zmm27,%zmm28,%zmm29"); + + /* AVX-512: Op code 0f 38 15 */ + + asm volatile("blendvpd %xmm1,%xmm0"); + asm volatile("vpmovusqd %zmm27,%ymm6{%k7}"); + asm volatile("vprolvd %zmm27,%zmm28,%zmm29"); + asm volatile("vprolvq %zmm27,%zmm28,%zmm29"); + + /* AVX-512: Op code 0f 38 16 */ + + asm volatile("vpermps %ymm4,%ymm6,%ymm2"); + asm volatile("vpermps %ymm24,%ymm26,%ymm22{%k7}"); + asm volatile("vpermpd %ymm24,%ymm26,%ymm22{%k7}"); + + /* AVX-512: Op code 0f 38 19 */ + + asm volatile("vbroadcastsd %xmm4,%ymm6"); + asm volatile("vbroadcastf32x2 %xmm27,%zmm26"); + + /* AVX-512: Op code 0f 38 1a */ + + asm volatile("vbroadcastf128 (%rcx),%ymm4"); + asm volatile("vbroadcastf32x4 (%rcx),%zmm26"); + asm volatile("vbroadcastf64x2 (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 1b */ + + asm volatile("vbroadcastf32x8 (%rcx),%zmm27"); + asm volatile("vbroadcastf64x4 (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 1f */ + + asm volatile("vpabsq %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 20 */ + + asm volatile("vpmovsxbw %xmm4,%xmm5"); + asm volatile("vpmovswb %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 21 */ + + asm volatile("vpmovsxbd %xmm4,%ymm6"); + asm volatile("vpmovsdb %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 22 */ + + asm volatile("vpmovsxbq %xmm4,%ymm4"); + asm volatile("vpmovsqb %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 23 */ + + asm volatile("vpmovsxwd %xmm4,%ymm4"); + asm volatile("vpmovsdw %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 24 */ + + asm volatile("vpmovsxwq %xmm4,%ymm6"); + asm volatile("vpmovsqw %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 25 */ + + asm volatile("vpmovsxdq %xmm4,%ymm4"); + asm volatile("vpmovsqd %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 26 */ + + asm volatile("vptestmb %zmm27,%zmm28,%k5"); + asm volatile("vptestmw %zmm27,%zmm28,%k5"); + asm volatile("vptestnmb %zmm26,%zmm27,%k5"); + asm volatile("vptestnmw %zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 38 27 */ + + asm volatile("vptestmd %zmm27,%zmm28,%k5"); + asm volatile("vptestmq %zmm27,%zmm28,%k5"); + asm volatile("vptestnmd %zmm26,%zmm27,%k5"); + asm volatile("vptestnmq %zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 38 28 */ + + asm volatile("vpmuldq %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovm2b %k5,%zmm28"); + asm volatile("vpmovm2w %k5,%zmm28"); + + /* AVX-512: Op code 0f 38 29 */ + + asm volatile("vpcmpeqq %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovb2m %zmm28,%k5"); + asm volatile("vpmovw2m %zmm28,%k5"); + + /* AVX-512: Op code 0f 38 2a */ + + asm volatile("vmovntdqa (%rcx),%ymm4"); + asm volatile("vpbroadcastmb2q %k6,%zmm30"); + + /* AVX-512: Op code 0f 38 2c */ + + asm volatile("vmaskmovps (%rcx),%ymm4,%ymm6"); + asm volatile("vscalefps %zmm24,%zmm25,%zmm26"); + asm volatile("vscalefpd %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 2d */ + + asm volatile("vmaskmovpd (%rcx),%ymm4,%ymm6"); + asm volatile("vscalefss %xmm24,%xmm25,%xmm26{%k7}"); + asm volatile("vscalefsd %xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 38 30 */ + + asm volatile("vpmovzxbw %xmm4,%ymm4"); + asm volatile("vpmovwb %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 31 */ + + asm volatile("vpmovzxbd %xmm4,%ymm6"); + asm volatile("vpmovdb %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 32 */ + + asm volatile("vpmovzxbq %xmm4,%ymm4"); + asm volatile("vpmovqb %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 33 */ + + asm volatile("vpmovzxwd %xmm4,%ymm4"); + asm volatile("vpmovdw %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 34 */ + + asm volatile("vpmovzxwq %xmm4,%ymm6"); + asm volatile("vpmovqw %zmm27,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 35 */ + + asm volatile("vpmovzxdq %xmm4,%ymm4"); + asm volatile("vpmovqd %zmm27,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 38 */ + + asm volatile("vpermd %ymm4,%ymm6,%ymm2"); + asm volatile("vpermd %ymm24,%ymm26,%ymm22{%k7}"); + asm volatile("vpermq %ymm24,%ymm26,%ymm22{%k7}"); + + /* AVX-512: Op code 0f 38 38 */ + + asm volatile("vpminsb %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovm2d %k5,%zmm28"); + asm volatile("vpmovm2q %k5,%zmm28"); + + /* AVX-512: Op code 0f 38 39 */ + + asm volatile("vpminsd %xmm1,%xmm2,%xmm3"); + asm volatile("vpminsd %zmm24,%zmm25,%zmm26"); + asm volatile("vpminsq %zmm24,%zmm25,%zmm26"); + asm volatile("vpmovd2m %zmm28,%k5"); + asm volatile("vpmovq2m %zmm28,%k5"); + + /* AVX-512: Op code 0f 38 3a */ + + asm volatile("vpminuw %ymm4,%ymm6,%ymm2"); + asm volatile("vpbroadcastmw2d %k6,%zmm28"); + + /* AVX-512: Op code 0f 38 3b */ + + asm volatile("vpminud %ymm4,%ymm6,%ymm2"); + asm volatile("vpminud %zmm24,%zmm25,%zmm26"); + asm volatile("vpminuq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 3d */ + + asm volatile("vpmaxsd %ymm4,%ymm6,%ymm2"); + asm volatile("vpmaxsd %zmm24,%zmm25,%zmm26"); + asm volatile("vpmaxsq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 3f */ + + asm volatile("vpmaxud %ymm4,%ymm6,%ymm2"); + asm volatile("vpmaxud %zmm24,%zmm25,%zmm26"); + asm volatile("vpmaxuq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 42 */ + + asm volatile("vpmulld %ymm4,%ymm6,%ymm2"); + asm volatile("vpmulld %zmm24,%zmm25,%zmm26"); + asm volatile("vpmullq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 42 */ + + asm volatile("vgetexpps %zmm25,%zmm26"); + asm volatile("vgetexppd %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 43 */ + + asm volatile("vgetexpss %xmm24,%xmm25,%xmm26{%k7}"); + asm volatile("vgetexpsd %xmm28,%xmm29,%xmm30{%k7}"); + + /* AVX-512: Op code 0f 38 44 */ + + asm volatile("vplzcntd %zmm27,%zmm28"); + asm volatile("vplzcntq %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 46 */ + + asm volatile("vpsravd %ymm4,%ymm6,%ymm2"); + asm volatile("vpsravd %zmm24,%zmm25,%zmm26"); + asm volatile("vpsravq %zmm24,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 38 4c */ + + asm volatile("vrcp14ps %zmm25,%zmm26"); + asm volatile("vrcp14pd %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 4d */ + + asm volatile("vrcp14ss %xmm24,%xmm25,%xmm26{%k7}"); + asm volatile("vrcp14sd %xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 38 4e */ + + asm volatile("vrsqrt14ps %zmm25,%zmm26"); + asm volatile("vrsqrt14pd %zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 4f */ + + asm volatile("vrsqrt14ss %xmm24,%xmm25,%xmm26{%k7}"); + asm volatile("vrsqrt14sd %xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 38 59 */ + + asm volatile("vpbroadcastq %xmm4,%xmm6"); + asm volatile("vbroadcasti32x2 %xmm27,%zmm26"); + + /* AVX-512: Op code 0f 38 5a */ + + asm volatile("vbroadcasti128 (%rcx),%ymm4"); + asm volatile("vbroadcasti32x4 (%rcx),%zmm26"); + asm volatile("vbroadcasti64x2 (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 5b */ + + asm volatile("vbroadcasti32x8 (%rcx),%zmm28"); + asm volatile("vbroadcasti64x4 (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 64 */ + + asm volatile("vpblendmd %zmm26,%zmm27,%zmm28"); + asm volatile("vpblendmq %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 65 */ + + asm volatile("vblendmps %zmm24,%zmm25,%zmm26"); + asm volatile("vblendmpd %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 66 */ + + asm volatile("vpblendmb %zmm26,%zmm27,%zmm28"); + asm volatile("vpblendmw %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 75 */ + + asm volatile("vpermi2b %zmm24,%zmm25,%zmm26"); + asm volatile("vpermi2w %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 76 */ + + asm volatile("vpermi2d %zmm26,%zmm27,%zmm28"); + asm volatile("vpermi2q %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 77 */ + + asm volatile("vpermi2ps %zmm26,%zmm27,%zmm28"); + asm volatile("vpermi2pd %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 7a */ + + asm volatile("vpbroadcastb %eax,%xmm30"); + + /* AVX-512: Op code 0f 38 7b */ + + asm volatile("vpbroadcastw %eax,%xmm30"); + + /* AVX-512: Op code 0f 38 7c */ + + asm volatile("vpbroadcastd %eax,%xmm30"); + asm volatile("vpbroadcastq %rax,%zmm30"); + + /* AVX-512: Op code 0f 38 7d */ + + asm volatile("vpermt2b %zmm26,%zmm27,%zmm28"); + asm volatile("vpermt2w %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 7e */ + + asm volatile("vpermt2d %zmm26,%zmm27,%zmm28"); + asm volatile("vpermt2q %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 7f */ + + asm volatile("vpermt2ps %zmm26,%zmm27,%zmm28"); + asm volatile("vpermt2pd %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 83 */ + + asm volatile("vpmultishiftqb %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 88 */ + + asm volatile("vexpandps (%rcx),%zmm26"); + asm volatile("vexpandpd (%rcx),%zmm28"); + + /* AVX-512: Op code 0f 38 89 */ + + asm volatile("vpexpandd (%rcx),%zmm28"); + asm volatile("vpexpandq (%rcx),%zmm26"); + + /* AVX-512: Op code 0f 38 8a */ + + asm volatile("vcompressps %zmm28,(%rcx)"); + asm volatile("vcompresspd %zmm28,(%rcx)"); + + /* AVX-512: Op code 0f 38 8b */ + + asm volatile("vpcompressd %zmm28,(%rcx)"); + asm volatile("vpcompressq %zmm26,(%rcx)"); + + /* AVX-512: Op code 0f 38 8d */ + + asm volatile("vpermb %zmm26,%zmm27,%zmm28"); + asm volatile("vpermw %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 90 */ + + asm volatile("vpgatherdd %xmm2,0x02(%rbp,%xmm7,2),%xmm1"); + asm volatile("vpgatherdq %xmm2,0x04(%rbp,%xmm7,2),%xmm1"); + asm volatile("vpgatherdd 0x7b(%rbp,%zmm27,8),%zmm26{%k1}"); + asm volatile("vpgatherdq 0x7b(%rbp,%ymm27,8),%zmm26{%k1}"); + + /* AVX-512: Op code 0f 38 91 */ + + asm volatile("vpgatherqd %xmm2,0x02(%rbp,%xmm7,2),%xmm1"); + asm volatile("vpgatherqq %xmm2,0x02(%rbp,%xmm7,2),%xmm1"); + asm volatile("vpgatherqd 0x7b(%rbp,%zmm27,8),%ymm26{%k1}"); + asm volatile("vpgatherqq 0x7b(%rbp,%zmm27,8),%zmm26{%k1}"); + + /* AVX-512: Op code 0f 38 a0 */ + + asm volatile("vpscatterdd %zmm28,0x7b(%rbp,%zmm29,8){%k1}"); + asm volatile("vpscatterdq %zmm26,0x7b(%rbp,%ymm27,8){%k1}"); + + /* AVX-512: Op code 0f 38 a1 */ + + asm volatile("vpscatterqd %ymm6,0x7b(%rbp,%zmm29,8){%k1}"); + asm volatile("vpscatterqq %ymm6,0x7b(%rbp,%ymm27,8){%k1}"); + + /* AVX-512: Op code 0f 38 a2 */ + + asm volatile("vscatterdps %zmm28,0x7b(%rbp,%zmm29,8){%k1}"); + asm volatile("vscatterdpd %zmm28,0x7b(%rbp,%ymm27,8){%k1}"); + + /* AVX-512: Op code 0f 38 a3 */ + + asm volatile("vscatterqps %ymm6,0x7b(%rbp,%zmm29,8){%k1}"); + asm volatile("vscatterqpd %zmm28,0x7b(%rbp,%zmm29,8){%k1}"); + + /* AVX-512: Op code 0f 38 b4 */ + + asm volatile("vpmadd52luq %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 b5 */ + + asm volatile("vpmadd52huq %zmm26,%zmm27,%zmm28"); + + /* AVX-512: Op code 0f 38 c4 */ + + asm volatile("vpconflictd %zmm26,%zmm27"); + asm volatile("vpconflictq %zmm26,%zmm27"); + + /* AVX-512: Op code 0f 38 c8 */ + + asm volatile("vexp2ps %zmm29,%zmm30"); + asm volatile("vexp2pd %zmm26,%zmm27"); + + /* AVX-512: Op code 0f 38 ca */ + + asm volatile("vrcp28ps %zmm29,%zmm30"); + asm volatile("vrcp28pd %zmm26,%zmm27"); + + /* AVX-512: Op code 0f 38 cb */ + + asm volatile("vrcp28ss %xmm28,%xmm29,%xmm30{%k7}"); + asm volatile("vrcp28sd %xmm25,%xmm26,%xmm27{%k7}"); + + /* AVX-512: Op code 0f 38 cc */ + + asm volatile("vrsqrt28ps %zmm29,%zmm30"); + asm volatile("vrsqrt28pd %zmm26,%zmm27"); + + /* AVX-512: Op code 0f 38 cd */ + + asm volatile("vrsqrt28ss %xmm28,%xmm29,%xmm30{%k7}"); + asm volatile("vrsqrt28sd %xmm25,%xmm26,%xmm27{%k7}"); + + /* AVX-512: Op code 0f 3a 03 */ + + asm volatile("valignd $0x12,%zmm28,%zmm29,%zmm30"); + asm volatile("valignq $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a 08 */ + + asm volatile("vroundps $0x5,%ymm6,%ymm2"); + asm volatile("vrndscaleps $0x12,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 3a 09 */ + + asm volatile("vroundpd $0x5,%ymm6,%ymm2"); + asm volatile("vrndscalepd $0x12,%zmm25,%zmm26"); + + /* AVX-512: Op code 0f 3a 1a */ + + asm volatile("vroundss $0x5,%xmm4,%xmm6,%xmm2"); + asm volatile("vrndscaless $0x12,%xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 0b */ + + asm volatile("vroundsd $0x5,%xmm4,%xmm6,%xmm2"); + asm volatile("vrndscalesd $0x12,%xmm24,%xmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 18 */ + + asm volatile("vinsertf128 $0x5,%xmm4,%ymm4,%ymm6"); + asm volatile("vinsertf32x4 $0x12,%xmm24,%zmm25,%zmm26{%k7}"); + asm volatile("vinsertf64x2 $0x12,%xmm24,%zmm25,%zmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 19 */ + + asm volatile("vextractf128 $0x5,%ymm4,%xmm4"); + asm volatile("vextractf32x4 $0x12,%zmm25,%xmm26{%k7}"); + asm volatile("vextractf64x2 $0x12,%zmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 1a */ + + asm volatile("vinsertf32x8 $0x12,%ymm25,%zmm26,%zmm27{%k7}"); + asm volatile("vinsertf64x4 $0x12,%ymm28,%zmm29,%zmm30{%k7}"); + + /* AVX-512: Op code 0f 3a 1b */ + + asm volatile("vextractf32x8 $0x12,%zmm29,%ymm30{%k7}"); + asm volatile("vextractf64x4 $0x12,%zmm26,%ymm27{%k7}"); + + /* AVX-512: Op code 0f 3a 1e */ + + asm volatile("vpcmpud $0x12,%zmm29,%zmm30,%k5"); + asm volatile("vpcmpuq $0x12,%zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 3a 1f */ + + asm volatile("vpcmpd $0x12,%zmm29,%zmm30,%k5"); + asm volatile("vpcmpq $0x12,%zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 3a 23 */ + + asm volatile("vshuff32x4 $0x12,%zmm28,%zmm29,%zmm30"); + asm volatile("vshuff64x2 $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a 25 */ + + asm volatile("vpternlogd $0x12,%zmm28,%zmm29,%zmm30"); + asm volatile("vpternlogq $0x12,%zmm28,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 26 */ + + asm volatile("vgetmantps $0x12,%zmm26,%zmm27"); + asm volatile("vgetmantpd $0x12,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 27 */ + + asm volatile("vgetmantss $0x12,%xmm25,%xmm26,%xmm27{%k7}"); + asm volatile("vgetmantsd $0x12,%xmm28,%xmm29,%xmm30{%k7}"); + + /* AVX-512: Op code 0f 3a 38 */ + + asm volatile("vinserti128 $0x5,%xmm4,%ymm4,%ymm6"); + asm volatile("vinserti32x4 $0x12,%xmm24,%zmm25,%zmm26{%k7}"); + asm volatile("vinserti64x2 $0x12,%xmm24,%zmm25,%zmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 39 */ + + asm volatile("vextracti128 $0x5,%ymm4,%xmm6"); + asm volatile("vextracti32x4 $0x12,%zmm25,%xmm26{%k7}"); + asm volatile("vextracti64x2 $0x12,%zmm25,%xmm26{%k7}"); + + /* AVX-512: Op code 0f 3a 3a */ + + asm volatile("vinserti32x8 $0x12,%ymm28,%zmm29,%zmm30{%k7}"); + asm volatile("vinserti64x4 $0x12,%ymm25,%zmm26,%zmm27{%k7}"); + + /* AVX-512: Op code 0f 3a 3b */ + + asm volatile("vextracti32x8 $0x12,%zmm29,%ymm30{%k7}"); + asm volatile("vextracti64x4 $0x12,%zmm26,%ymm27{%k7}"); + + /* AVX-512: Op code 0f 3a 3e */ + + asm volatile("vpcmpub $0x12,%zmm29,%zmm30,%k5"); + asm volatile("vpcmpuw $0x12,%zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 3a 3f */ + + asm volatile("vpcmpb $0x12,%zmm29,%zmm30,%k5"); + asm volatile("vpcmpw $0x12,%zmm26,%zmm27,%k5"); + + /* AVX-512: Op code 0f 3a 43 */ + + asm volatile("vmpsadbw $0x5,%ymm4,%ymm6,%ymm2"); + asm volatile("vdbpsadbw $0x12,%zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 3a 43 */ + + asm volatile("vshufi32x4 $0x12,%zmm25,%zmm26,%zmm27"); + asm volatile("vshufi64x2 $0x12,%zmm28,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 50 */ + + asm volatile("vrangeps $0x12,%zmm25,%zmm26,%zmm27"); + asm volatile("vrangepd $0x12,%zmm28,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 51 */ + + asm volatile("vrangess $0x12,%xmm25,%xmm26,%xmm27"); + asm volatile("vrangesd $0x12,%xmm28,%xmm29,%xmm30"); + + /* AVX-512: Op code 0f 3a 54 */ + + asm volatile("vfixupimmps $0x12,%zmm28,%zmm29,%zmm30"); + asm volatile("vfixupimmpd $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a 55 */ + + asm volatile("vfixupimmss $0x12,%xmm28,%xmm29,%xmm30{%k7}"); + asm volatile("vfixupimmsd $0x12,%xmm25,%xmm26,%xmm27{%k7}"); + + /* AVX-512: Op code 0f 3a 56 */ + + asm volatile("vreduceps $0x12,%zmm26,%zmm27"); + asm volatile("vreducepd $0x12,%zmm29,%zmm30"); + + /* AVX-512: Op code 0f 3a 57 */ + + asm volatile("vreducess $0x12,%xmm25,%xmm26,%xmm27"); + asm volatile("vreducesd $0x12,%xmm28,%xmm29,%xmm30"); + + /* AVX-512: Op code 0f 3a 66 */ + + asm volatile("vfpclassps $0x12,%zmm27,%k5"); + asm volatile("vfpclasspd $0x12,%zmm30,%k5"); + + /* AVX-512: Op code 0f 3a 67 */ + + asm volatile("vfpclassss $0x12,%xmm27,%k5"); + asm volatile("vfpclasssd $0x12,%xmm30,%k5"); + + /* AVX-512: Op code 0f 72 (Grp13) */ + + asm volatile("vprord $0x12,%zmm25,%zmm26"); + asm volatile("vprorq $0x12,%zmm25,%zmm26"); + asm volatile("vprold $0x12,%zmm29,%zmm30"); + asm volatile("vprolq $0x12,%zmm29,%zmm30"); + asm volatile("psrad $0x2,%mm6"); + asm volatile("vpsrad $0x5,%ymm6,%ymm2"); + asm volatile("vpsrad $0x5,%zmm26,%zmm22"); + asm volatile("vpsraq $0x5,%zmm26,%zmm22"); + + /* AVX-512: Op code 0f 38 c6 (Grp18) */ + + asm volatile("vgatherpf0dps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf0dpd 0x7b(%r14,%ymm31,8){%k1}"); + asm volatile("vgatherpf1dps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf1dpd 0x7b(%r14,%ymm31,8){%k1}"); + asm volatile("vscatterpf0dps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf0dpd 0x7b(%r14,%ymm31,8){%k1}"); + asm volatile("vscatterpf1dps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf1dpd 0x7b(%r14,%ymm31,8){%k1}"); + + /* AVX-512: Op code 0f 38 c7 (Grp19) */ + + asm volatile("vgatherpf0qps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf0qpd 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf1qps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vgatherpf1qpd 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf0qps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf0qpd 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf1qps 0x7b(%r14,%zmm31,8){%k1}"); + asm volatile("vscatterpf1qpd 0x7b(%r14,%zmm31,8){%k1}"); + + /* AVX-512: Examples */ + + asm volatile("vaddpd %zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd %zmm28,%zmm29,%zmm30{%k7}"); + asm volatile("vaddpd %zmm28,%zmm29,%zmm30{%k7}{z}"); + asm volatile("vaddpd {rn-sae},%zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd {ru-sae},%zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd {rd-sae},%zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd {rz-sae},%zmm28,%zmm29,%zmm30"); + asm volatile("vaddpd (%rcx),%zmm29,%zmm30"); + asm volatile("vaddpd 0x123(%rax,%r14,8),%zmm29,%zmm30"); + asm volatile("vaddpd (%rcx){1to8},%zmm29,%zmm30"); + asm volatile("vaddpd 0x1fc0(%rdx),%zmm29,%zmm30"); + asm volatile("vaddpd 0x3f8(%rdx){1to8},%zmm29,%zmm30"); + asm volatile("vcmpeq_uqps 0x1fc(%rdx){1to16},%zmm30,%k5"); + asm volatile("vcmpltsd 0x123(%rax,%r14,8),%xmm29,%k5{%k7}"); + asm volatile("vcmplesd {sae},%xmm28,%xmm29,%k5{%k7}"); + asm volatile("vgetmantss $0x5b,0x123(%rax,%r14,8),%xmm29,%xmm30{%k7}"); + /* bndmk m64, bnd */ asm volatile("bndmk (%rax), %bnd0"); @@ -475,6 +1345,921 @@ int main(void) #else /* #ifdef __x86_64__ */ + /* bound r32, mem (same op code as EVEX prefix) */ + + asm volatile("bound %eax, 0x12345678(%ecx)"); + asm volatile("bound %ecx, 0x12345678(%eax)"); + asm volatile("bound %edx, 0x12345678(%eax)"); + asm volatile("bound %ebx, 0x12345678(%eax)"); + asm volatile("bound %esp, 0x12345678(%eax)"); + asm volatile("bound %ebp, 0x12345678(%eax)"); + asm volatile("bound %esi, 0x12345678(%eax)"); + asm volatile("bound %edi, 0x12345678(%eax)"); + asm volatile("bound %ecx, (%eax)"); + asm volatile("bound %eax, (0x12345678)"); + asm volatile("bound %edx, (%ecx,%eax,1)"); + asm volatile("bound %edx, 0x12345678(,%eax,1)"); + asm volatile("bound %edx, (%eax,%ecx,1)"); + asm volatile("bound %edx, (%eax,%ecx,8)"); + asm volatile("bound %edx, 0x12(%eax)"); + asm volatile("bound %edx, 0x12(%ebp)"); + asm volatile("bound %edx, 0x12(%ecx,%eax,1)"); + asm volatile("bound %edx, 0x12(%ebp,%eax,1)"); + asm volatile("bound %edx, 0x12(%eax,%ecx,1)"); + asm volatile("bound %edx, 0x12(%eax,%ecx,8)"); + asm volatile("bound %edx, 0x12345678(%eax)"); + asm volatile("bound %edx, 0x12345678(%ebp)"); + asm volatile("bound %edx, 0x12345678(%ecx,%eax,1)"); + asm volatile("bound %edx, 0x12345678(%ebp,%eax,1)"); + asm volatile("bound %edx, 0x12345678(%eax,%ecx,1)"); + asm volatile("bound %edx, 0x12345678(%eax,%ecx,8)"); + + /* bound r16, mem (same op code as EVEX prefix) */ + + asm volatile("bound %ax, 0x12345678(%ecx)"); + asm volatile("bound %cx, 0x12345678(%eax)"); + asm volatile("bound %dx, 0x12345678(%eax)"); + asm volatile("bound %bx, 0x12345678(%eax)"); + asm volatile("bound %sp, 0x12345678(%eax)"); + asm volatile("bound %bp, 0x12345678(%eax)"); + asm volatile("bound %si, 0x12345678(%eax)"); + asm volatile("bound %di, 0x12345678(%eax)"); + asm volatile("bound %cx, (%eax)"); + asm volatile("bound %ax, (0x12345678)"); + asm volatile("bound %dx, (%ecx,%eax,1)"); + asm volatile("bound %dx, 0x12345678(,%eax,1)"); + asm volatile("bound %dx, (%eax,%ecx,1)"); + asm volatile("bound %dx, (%eax,%ecx,8)"); + asm volatile("bound %dx, 0x12(%eax)"); + asm volatile("bound %dx, 0x12(%ebp)"); + asm volatile("bound %dx, 0x12(%ecx,%eax,1)"); + asm volatile("bound %dx, 0x12(%ebp,%eax,1)"); + asm volatile("bound %dx, 0x12(%eax,%ecx,1)"); + asm volatile("bound %dx, 0x12(%eax,%ecx,8)"); + asm volatile("bound %dx, 0x12345678(%eax)"); + asm volatile("bound %dx, 0x12345678(%ebp)"); + asm volatile("bound %dx, 0x12345678(%ecx,%eax,1)"); + asm volatile("bound %dx, 0x12345678(%ebp,%eax,1)"); + asm volatile("bound %dx, 0x12345678(%eax,%ecx,1)"); + asm volatile("bound %dx, 0x12345678(%eax,%ecx,8)"); + + /* AVX-512: Instructions with the same op codes as Mask Instructions */ + + asm volatile("cmovno %eax,%ebx"); + asm volatile("cmovno 0x12345678(%eax),%ecx"); + asm volatile("cmovno 0x12345678(%eax),%cx"); + + asm volatile("cmove %eax,%ebx"); + asm volatile("cmove 0x12345678(%eax),%ecx"); + asm volatile("cmove 0x12345678(%eax),%cx"); + + asm volatile("seto 0x12345678(%eax)"); + asm volatile("setno 0x12345678(%eax)"); + asm volatile("setb 0x12345678(%eax)"); + asm volatile("setc 0x12345678(%eax)"); + asm volatile("setnae 0x12345678(%eax)"); + asm volatile("setae 0x12345678(%eax)"); + asm volatile("setnb 0x12345678(%eax)"); + asm volatile("setnc 0x12345678(%eax)"); + asm volatile("sets 0x12345678(%eax)"); + asm volatile("setns 0x12345678(%eax)"); + + /* AVX-512: Mask Instructions */ + + asm volatile("kandw %k7,%k6,%k5"); + asm volatile("kandq %k7,%k6,%k5"); + asm volatile("kandb %k7,%k6,%k5"); + asm volatile("kandd %k7,%k6,%k5"); + + asm volatile("kandnw %k7,%k6,%k5"); + asm volatile("kandnq %k7,%k6,%k5"); + asm volatile("kandnb %k7,%k6,%k5"); + asm volatile("kandnd %k7,%k6,%k5"); + + asm volatile("knotw %k7,%k6"); + asm volatile("knotq %k7,%k6"); + asm volatile("knotb %k7,%k6"); + asm volatile("knotd %k7,%k6"); + + asm volatile("korw %k7,%k6,%k5"); + asm volatile("korq %k7,%k6,%k5"); + asm volatile("korb %k7,%k6,%k5"); + asm volatile("kord %k7,%k6,%k5"); + + asm volatile("kxnorw %k7,%k6,%k5"); + asm volatile("kxnorq %k7,%k6,%k5"); + asm volatile("kxnorb %k7,%k6,%k5"); + asm volatile("kxnord %k7,%k6,%k5"); + + asm volatile("kxorw %k7,%k6,%k5"); + asm volatile("kxorq %k7,%k6,%k5"); + asm volatile("kxorb %k7,%k6,%k5"); + asm volatile("kxord %k7,%k6,%k5"); + + asm volatile("kaddw %k7,%k6,%k5"); + asm volatile("kaddq %k7,%k6,%k5"); + asm volatile("kaddb %k7,%k6,%k5"); + asm volatile("kaddd %k7,%k6,%k5"); + + asm volatile("kunpckbw %k7,%k6,%k5"); + asm volatile("kunpckwd %k7,%k6,%k5"); + asm volatile("kunpckdq %k7,%k6,%k5"); + + asm volatile("kmovw %k6,%k5"); + asm volatile("kmovw (%ecx),%k5"); + asm volatile("kmovw 0x123(%eax,%ecx,8),%k5"); + asm volatile("kmovw %k5,(%ecx)"); + asm volatile("kmovw %k5,0x123(%eax,%ecx,8)"); + asm volatile("kmovw %eax,%k5"); + asm volatile("kmovw %ebp,%k5"); + asm volatile("kmovw %k5,%eax"); + asm volatile("kmovw %k5,%ebp"); + + asm volatile("kmovq %k6,%k5"); + asm volatile("kmovq (%ecx),%k5"); + asm volatile("kmovq 0x123(%eax,%ecx,8),%k5"); + asm volatile("kmovq %k5,(%ecx)"); + asm volatile("kmovq %k5,0x123(%eax,%ecx,8)"); + + asm volatile("kmovb %k6,%k5"); + asm volatile("kmovb (%ecx),%k5"); + asm volatile("kmovb 0x123(%eax,%ecx,8),%k5"); + asm volatile("kmovb %k5,(%ecx)"); + asm volatile("kmovb %k5,0x123(%eax,%ecx,8)"); + asm volatile("kmovb %eax,%k5"); + asm volatile("kmovb %ebp,%k5"); + asm volatile("kmovb %k5,%eax"); + asm volatile("kmovb %k5,%ebp"); + + asm volatile("kmovd %k6,%k5"); + asm volatile("kmovd (%ecx),%k5"); + asm volatile("kmovd 0x123(%eax,%ecx,8),%k5"); + asm volatile("kmovd %k5,(%ecx)"); + asm volatile("kmovd %k5,0x123(%eax,%ecx,8)"); + asm volatile("kmovd %eax,%k5"); + asm volatile("kmovd %ebp,%k5"); + asm volatile("kmovd %k5,%eax"); + asm volatile("kmovd %k5,%ebp"); + + asm volatile("kortestw %k6,%k5"); + asm volatile("kortestq %k6,%k5"); + asm volatile("kortestb %k6,%k5"); + asm volatile("kortestd %k6,%k5"); + + asm volatile("ktestw %k6,%k5"); + asm volatile("ktestq %k6,%k5"); + asm volatile("ktestb %k6,%k5"); + asm volatile("ktestd %k6,%k5"); + + asm volatile("kshiftrw $0x12,%k6,%k5"); + asm volatile("kshiftrq $0x5b,%k6,%k5"); + asm volatile("kshiftlw $0x12,%k6,%k5"); + asm volatile("kshiftlq $0x5b,%k6,%k5"); + + /* AVX-512: Op code 0f 5b */ + asm volatile("vcvtdq2ps %xmm5,%xmm6"); + asm volatile("vcvtqq2ps %zmm5,%ymm6{%k7}"); + asm volatile("vcvtps2dq %xmm5,%xmm6"); + asm volatile("vcvttps2dq %xmm5,%xmm6"); + + /* AVX-512: Op code 0f 6f */ + + asm volatile("movq %mm0,%mm4"); + asm volatile("vmovdqa %ymm4,%ymm6"); + asm volatile("vmovdqa32 %zmm5,%zmm6"); + asm volatile("vmovdqa64 %zmm5,%zmm6"); + asm volatile("vmovdqu %ymm4,%ymm6"); + asm volatile("vmovdqu32 %zmm5,%zmm6"); + asm volatile("vmovdqu64 %zmm5,%zmm6"); + asm volatile("vmovdqu8 %zmm5,%zmm6"); + asm volatile("vmovdqu16 %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 78 */ + + asm volatile("vmread %eax,%ebx"); + asm volatile("vcvttps2udq %zmm5,%zmm6"); + asm volatile("vcvttpd2udq %zmm5,%ymm6{%k7}"); + asm volatile("vcvttsd2usi %xmm6,%eax"); + asm volatile("vcvttss2usi %xmm6,%eax"); + asm volatile("vcvttps2uqq %ymm5,%zmm6{%k7}"); + asm volatile("vcvttpd2uqq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 79 */ + + asm volatile("vmwrite %eax,%ebx"); + asm volatile("vcvtps2udq %zmm5,%zmm6"); + asm volatile("vcvtpd2udq %zmm5,%ymm6{%k7}"); + asm volatile("vcvtsd2usi %xmm6,%eax"); + asm volatile("vcvtss2usi %xmm6,%eax"); + asm volatile("vcvtps2uqq %ymm5,%zmm6{%k7}"); + asm volatile("vcvtpd2uqq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 7a */ + + asm volatile("vcvtudq2pd %ymm5,%zmm6{%k7}"); + asm volatile("vcvtuqq2pd %zmm5,%zmm6"); + asm volatile("vcvtudq2ps %zmm5,%zmm6"); + asm volatile("vcvtuqq2ps %zmm5,%ymm6{%k7}"); + asm volatile("vcvttps2qq %ymm5,%zmm6{%k7}"); + asm volatile("vcvttpd2qq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 7b */ + + asm volatile("vcvtusi2sd %eax,%xmm5,%xmm6"); + asm volatile("vcvtusi2ss %eax,%xmm5,%xmm6"); + asm volatile("vcvtps2qq %ymm5,%zmm6{%k7}"); + asm volatile("vcvtpd2qq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 7f */ + + asm volatile("movq.s %mm0,%mm4"); + asm volatile("vmovdqa.s %ymm5,%ymm6"); + asm volatile("vmovdqa32.s %zmm5,%zmm6"); + asm volatile("vmovdqa64.s %zmm5,%zmm6"); + asm volatile("vmovdqu.s %ymm5,%ymm6"); + asm volatile("vmovdqu32.s %zmm5,%zmm6"); + asm volatile("vmovdqu64.s %zmm5,%zmm6"); + asm volatile("vmovdqu8.s %zmm5,%zmm6"); + asm volatile("vmovdqu16.s %zmm5,%zmm6"); + + /* AVX-512: Op code 0f db */ + + asm volatile("pand %mm1,%mm2"); + asm volatile("pand %xmm1,%xmm2"); + asm volatile("vpand %ymm4,%ymm6,%ymm2"); + asm volatile("vpandd %zmm4,%zmm5,%zmm6"); + asm volatile("vpandq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f df */ + + asm volatile("pandn %mm1,%mm2"); + asm volatile("pandn %xmm1,%xmm2"); + asm volatile("vpandn %ymm4,%ymm6,%ymm2"); + asm volatile("vpandnd %zmm4,%zmm5,%zmm6"); + asm volatile("vpandnq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f e6 */ + + asm volatile("vcvttpd2dq %xmm1,%xmm2"); + asm volatile("vcvtdq2pd %xmm5,%xmm6"); + asm volatile("vcvtdq2pd %ymm5,%zmm6{%k7}"); + asm volatile("vcvtqq2pd %zmm5,%zmm6"); + asm volatile("vcvtpd2dq %xmm1,%xmm2"); + + /* AVX-512: Op code 0f eb */ + + asm volatile("por %mm4,%mm6"); + asm volatile("vpor %ymm4,%ymm6,%ymm2"); + asm volatile("vpord %zmm4,%zmm5,%zmm6"); + asm volatile("vporq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f ef */ + + asm volatile("pxor %mm4,%mm6"); + asm volatile("vpxor %ymm4,%ymm6,%ymm2"); + asm volatile("vpxord %zmm4,%zmm5,%zmm6"); + asm volatile("vpxorq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 10 */ + + asm volatile("pblendvb %xmm1,%xmm0"); + asm volatile("vpsrlvw %zmm4,%zmm5,%zmm6"); + asm volatile("vpmovuswb %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 11 */ + + asm volatile("vpmovusdb %zmm5,%xmm6{%k7}"); + asm volatile("vpsravw %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 12 */ + + asm volatile("vpmovusqb %zmm5,%xmm6{%k7}"); + asm volatile("vpsllvw %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 13 */ + + asm volatile("vcvtph2ps %xmm3,%ymm5"); + asm volatile("vcvtph2ps %ymm5,%zmm6{%k7}"); + asm volatile("vpmovusdw %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 14 */ + + asm volatile("blendvps %xmm1,%xmm0"); + asm volatile("vpmovusqw %zmm5,%xmm6{%k7}"); + asm volatile("vprorvd %zmm4,%zmm5,%zmm6"); + asm volatile("vprorvq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 15 */ + + asm volatile("blendvpd %xmm1,%xmm0"); + asm volatile("vpmovusqd %zmm5,%ymm6{%k7}"); + asm volatile("vprolvd %zmm4,%zmm5,%zmm6"); + asm volatile("vprolvq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 16 */ + + asm volatile("vpermps %ymm4,%ymm6,%ymm2"); + asm volatile("vpermps %ymm4,%ymm6,%ymm2{%k7}"); + asm volatile("vpermpd %ymm4,%ymm6,%ymm2{%k7}"); + + /* AVX-512: Op code 0f 38 19 */ + + asm volatile("vbroadcastsd %xmm4,%ymm6"); + asm volatile("vbroadcastf32x2 %xmm7,%zmm6"); + + /* AVX-512: Op code 0f 38 1a */ + + asm volatile("vbroadcastf128 (%ecx),%ymm4"); + asm volatile("vbroadcastf32x4 (%ecx),%zmm6"); + asm volatile("vbroadcastf64x2 (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 1b */ + + asm volatile("vbroadcastf32x8 (%ecx),%zmm6"); + asm volatile("vbroadcastf64x4 (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 1f */ + + asm volatile("vpabsq %zmm4,%zmm6"); + + /* AVX-512: Op code 0f 38 20 */ + + asm volatile("vpmovsxbw %xmm4,%xmm5"); + asm volatile("vpmovswb %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 21 */ + + asm volatile("vpmovsxbd %xmm4,%ymm6"); + asm volatile("vpmovsdb %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 22 */ + + asm volatile("vpmovsxbq %xmm4,%ymm4"); + asm volatile("vpmovsqb %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 23 */ + + asm volatile("vpmovsxwd %xmm4,%ymm4"); + asm volatile("vpmovsdw %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 24 */ + + asm volatile("vpmovsxwq %xmm4,%ymm6"); + asm volatile("vpmovsqw %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 25 */ + + asm volatile("vpmovsxdq %xmm4,%ymm4"); + asm volatile("vpmovsqd %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 26 */ + + asm volatile("vptestmb %zmm5,%zmm6,%k5"); + asm volatile("vptestmw %zmm5,%zmm6,%k5"); + asm volatile("vptestnmb %zmm4,%zmm5,%k5"); + asm volatile("vptestnmw %zmm4,%zmm5,%k5"); + + /* AVX-512: Op code 0f 38 27 */ + + asm volatile("vptestmd %zmm5,%zmm6,%k5"); + asm volatile("vptestmq %zmm5,%zmm6,%k5"); + asm volatile("vptestnmd %zmm4,%zmm5,%k5"); + asm volatile("vptestnmq %zmm4,%zmm5,%k5"); + + /* AVX-512: Op code 0f 38 28 */ + + asm volatile("vpmuldq %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovm2b %k5,%zmm6"); + asm volatile("vpmovm2w %k5,%zmm6"); + + /* AVX-512: Op code 0f 38 29 */ + + asm volatile("vpcmpeqq %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovb2m %zmm6,%k5"); + asm volatile("vpmovw2m %zmm6,%k5"); + + /* AVX-512: Op code 0f 38 2a */ + + asm volatile("vmovntdqa (%ecx),%ymm4"); + asm volatile("vpbroadcastmb2q %k6,%zmm1"); + + /* AVX-512: Op code 0f 38 2c */ + + asm volatile("vmaskmovps (%ecx),%ymm4,%ymm6"); + asm volatile("vscalefps %zmm4,%zmm5,%zmm6"); + asm volatile("vscalefpd %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 2d */ + + asm volatile("vmaskmovpd (%ecx),%ymm4,%ymm6"); + asm volatile("vscalefss %xmm4,%xmm5,%xmm6{%k7}"); + asm volatile("vscalefsd %xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 30 */ + + asm volatile("vpmovzxbw %xmm4,%ymm4"); + asm volatile("vpmovwb %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 31 */ + + asm volatile("vpmovzxbd %xmm4,%ymm6"); + asm volatile("vpmovdb %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 32 */ + + asm volatile("vpmovzxbq %xmm4,%ymm4"); + asm volatile("vpmovqb %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 33 */ + + asm volatile("vpmovzxwd %xmm4,%ymm4"); + asm volatile("vpmovdw %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 34 */ + + asm volatile("vpmovzxwq %xmm4,%ymm6"); + asm volatile("vpmovqw %zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 35 */ + + asm volatile("vpmovzxdq %xmm4,%ymm4"); + asm volatile("vpmovqd %zmm5,%ymm6{%k7}"); + + /* AVX-512: Op code 0f 38 36 */ + + asm volatile("vpermd %ymm4,%ymm6,%ymm2"); + asm volatile("vpermd %ymm4,%ymm6,%ymm2{%k7}"); + asm volatile("vpermq %ymm4,%ymm6,%ymm2{%k7}"); + + /* AVX-512: Op code 0f 38 38 */ + + asm volatile("vpminsb %ymm4,%ymm6,%ymm2"); + asm volatile("vpmovm2d %k5,%zmm6"); + asm volatile("vpmovm2q %k5,%zmm6"); + + /* AVX-512: Op code 0f 38 39 */ + + asm volatile("vpminsd %xmm1,%xmm2,%xmm3"); + asm volatile("vpminsd %zmm4,%zmm5,%zmm6"); + asm volatile("vpminsq %zmm4,%zmm5,%zmm6"); + asm volatile("vpmovd2m %zmm6,%k5"); + asm volatile("vpmovq2m %zmm6,%k5"); + + /* AVX-512: Op code 0f 38 3a */ + + asm volatile("vpminuw %ymm4,%ymm6,%ymm2"); + asm volatile("vpbroadcastmw2d %k6,%zmm6"); + + /* AVX-512: Op code 0f 38 3b */ + + asm volatile("vpminud %ymm4,%ymm6,%ymm2"); + asm volatile("vpminud %zmm4,%zmm5,%zmm6"); + asm volatile("vpminuq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 3d */ + + asm volatile("vpmaxsd %ymm4,%ymm6,%ymm2"); + asm volatile("vpmaxsd %zmm4,%zmm5,%zmm6"); + asm volatile("vpmaxsq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 3f */ + + asm volatile("vpmaxud %ymm4,%ymm6,%ymm2"); + asm volatile("vpmaxud %zmm4,%zmm5,%zmm6"); + asm volatile("vpmaxuq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 40 */ + + asm volatile("vpmulld %ymm4,%ymm6,%ymm2"); + asm volatile("vpmulld %zmm4,%zmm5,%zmm6"); + asm volatile("vpmullq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 42 */ + + asm volatile("vgetexpps %zmm5,%zmm6"); + asm volatile("vgetexppd %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 43 */ + + asm volatile("vgetexpss %xmm4,%xmm5,%xmm6{%k7}"); + asm volatile("vgetexpsd %xmm2,%xmm3,%xmm4{%k7}"); + + /* AVX-512: Op code 0f 38 44 */ + + asm volatile("vplzcntd %zmm5,%zmm6"); + asm volatile("vplzcntq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 46 */ + + asm volatile("vpsravd %ymm4,%ymm6,%ymm2"); + asm volatile("vpsravd %zmm4,%zmm5,%zmm6"); + asm volatile("vpsravq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 4c */ + + asm volatile("vrcp14ps %zmm5,%zmm6"); + asm volatile("vrcp14pd %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 4d */ + + asm volatile("vrcp14ss %xmm4,%xmm5,%xmm6{%k7}"); + asm volatile("vrcp14sd %xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 4e */ + + asm volatile("vrsqrt14ps %zmm5,%zmm6"); + asm volatile("vrsqrt14pd %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 4f */ + + asm volatile("vrsqrt14ss %xmm4,%xmm5,%xmm6{%k7}"); + asm volatile("vrsqrt14sd %xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 38 59 */ + + asm volatile("vpbroadcastq %xmm4,%xmm6"); + asm volatile("vbroadcasti32x2 %xmm7,%zmm6"); + + /* AVX-512: Op code 0f 38 5a */ + + asm volatile("vbroadcasti128 (%ecx),%ymm4"); + asm volatile("vbroadcasti32x4 (%ecx),%zmm6"); + asm volatile("vbroadcasti64x2 (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 5b */ + + asm volatile("vbroadcasti32x8 (%ecx),%zmm6"); + asm volatile("vbroadcasti64x4 (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 64 */ + + asm volatile("vpblendmd %zmm4,%zmm5,%zmm6"); + asm volatile("vpblendmq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 65 */ + + asm volatile("vblendmps %zmm4,%zmm5,%zmm6"); + asm volatile("vblendmpd %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 66 */ + + asm volatile("vpblendmb %zmm4,%zmm5,%zmm6"); + asm volatile("vpblendmw %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 75 */ + + asm volatile("vpermi2b %zmm4,%zmm5,%zmm6"); + asm volatile("vpermi2w %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 76 */ + + asm volatile("vpermi2d %zmm4,%zmm5,%zmm6"); + asm volatile("vpermi2q %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 77 */ + + asm volatile("vpermi2ps %zmm4,%zmm5,%zmm6"); + asm volatile("vpermi2pd %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 7a */ + + asm volatile("vpbroadcastb %eax,%xmm3"); + + /* AVX-512: Op code 0f 38 7b */ + + asm volatile("vpbroadcastw %eax,%xmm3"); + + /* AVX-512: Op code 0f 38 7c */ + + asm volatile("vpbroadcastd %eax,%xmm3"); + + /* AVX-512: Op code 0f 38 7d */ + + asm volatile("vpermt2b %zmm4,%zmm5,%zmm6"); + asm volatile("vpermt2w %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 7e */ + + asm volatile("vpermt2d %zmm4,%zmm5,%zmm6"); + asm volatile("vpermt2q %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 7f */ + + asm volatile("vpermt2ps %zmm4,%zmm5,%zmm6"); + asm volatile("vpermt2pd %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 83 */ + + asm volatile("vpmultishiftqb %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 88 */ + + asm volatile("vexpandps (%ecx),%zmm6"); + asm volatile("vexpandpd (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 89 */ + + asm volatile("vpexpandd (%ecx),%zmm6"); + asm volatile("vpexpandq (%ecx),%zmm6"); + + /* AVX-512: Op code 0f 38 8a */ + + asm volatile("vcompressps %zmm6,(%ecx)"); + asm volatile("vcompresspd %zmm6,(%ecx)"); + + /* AVX-512: Op code 0f 38 8b */ + + asm volatile("vpcompressd %zmm6,(%ecx)"); + asm volatile("vpcompressq %zmm6,(%ecx)"); + + /* AVX-512: Op code 0f 38 8d */ + + asm volatile("vpermb %zmm4,%zmm5,%zmm6"); + asm volatile("vpermw %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 90 */ + + asm volatile("vpgatherdd %xmm2,0x02(%ebp,%xmm7,2),%xmm1"); + asm volatile("vpgatherdq %xmm2,0x04(%ebp,%xmm7,2),%xmm1"); + asm volatile("vpgatherdd 0x7b(%ebp,%zmm7,8),%zmm6{%k1}"); + asm volatile("vpgatherdq 0x7b(%ebp,%ymm7,8),%zmm6{%k1}"); + + /* AVX-512: Op code 0f 38 91 */ + + asm volatile("vpgatherqd %xmm2,0x02(%ebp,%xmm7,2),%xmm1"); + asm volatile("vpgatherqq %xmm2,0x02(%ebp,%xmm7,2),%xmm1"); + asm volatile("vpgatherqd 0x7b(%ebp,%zmm7,8),%ymm6{%k1}"); + asm volatile("vpgatherqq 0x7b(%ebp,%zmm7,8),%zmm6{%k1}"); + + /* AVX-512: Op code 0f 38 a0 */ + + asm volatile("vpscatterdd %zmm6,0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vpscatterdq %zmm6,0x7b(%ebp,%ymm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 a1 */ + + asm volatile("vpscatterqd %ymm6,0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vpscatterqq %ymm6,0x7b(%ebp,%ymm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 a2 */ + + asm volatile("vscatterdps %zmm6,0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterdpd %zmm6,0x7b(%ebp,%ymm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 a3 */ + + asm volatile("vscatterqps %ymm6,0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterqpd %zmm6,0x7b(%ebp,%zmm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 b4 */ + + asm volatile("vpmadd52luq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 b5 */ + + asm volatile("vpmadd52huq %zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 c4 */ + + asm volatile("vpconflictd %zmm5,%zmm6"); + asm volatile("vpconflictq %zmm5,%zmm6"); + + /* AVX-512: Op code 0f 38 c8 */ + + asm volatile("vexp2ps %zmm6,%zmm7"); + asm volatile("vexp2pd %zmm6,%zmm7"); + + /* AVX-512: Op code 0f 38 ca */ + + asm volatile("vrcp28ps %zmm6,%zmm7"); + asm volatile("vrcp28pd %zmm6,%zmm7"); + + /* AVX-512: Op code 0f 38 cb */ + + asm volatile("vrcp28ss %xmm5,%xmm6,%xmm7{%k7}"); + asm volatile("vrcp28sd %xmm5,%xmm6,%xmm7{%k7}"); + + /* AVX-512: Op code 0f 38 cc */ + + asm volatile("vrsqrt28ps %zmm6,%zmm7"); + asm volatile("vrsqrt28pd %zmm6,%zmm7"); + + /* AVX-512: Op code 0f 38 cd */ + + asm volatile("vrsqrt28ss %xmm5,%xmm6,%xmm7{%k7}"); + asm volatile("vrsqrt28sd %xmm5,%xmm6,%xmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 03 */ + + asm volatile("valignd $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("valignq $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 08 */ + + asm volatile("vroundps $0x5,%ymm6,%ymm2"); + asm volatile("vrndscaleps $0x12,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 3a 09 */ + + asm volatile("vroundpd $0x5,%ymm6,%ymm2"); + asm volatile("vrndscalepd $0x12,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 3a 0a */ + + asm volatile("vroundss $0x5,%xmm4,%xmm6,%xmm2"); + asm volatile("vrndscaless $0x12,%xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 0b */ + + asm volatile("vroundsd $0x5,%xmm4,%xmm6,%xmm2"); + asm volatile("vrndscalesd $0x12,%xmm4,%xmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 18 */ + + asm volatile("vinsertf128 $0x5,%xmm4,%ymm4,%ymm6"); + asm volatile("vinsertf32x4 $0x12,%xmm4,%zmm5,%zmm6{%k7}"); + asm volatile("vinsertf64x2 $0x12,%xmm4,%zmm5,%zmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 19 */ + + asm volatile("vextractf128 $0x5,%ymm4,%xmm4"); + asm volatile("vextractf32x4 $0x12,%zmm5,%xmm6{%k7}"); + asm volatile("vextractf64x2 $0x12,%zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 1a */ + + asm volatile("vinsertf32x8 $0x12,%ymm5,%zmm6,%zmm7{%k7}"); + asm volatile("vinsertf64x4 $0x12,%ymm5,%zmm6,%zmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 1b */ + + asm volatile("vextractf32x8 $0x12,%zmm6,%ymm7{%k7}"); + asm volatile("vextractf64x4 $0x12,%zmm6,%ymm7{%k7}"); + + /* AVX-512: Op code 0f 3a 1e */ + + asm volatile("vpcmpud $0x12,%zmm6,%zmm7,%k5"); + asm volatile("vpcmpuq $0x12,%zmm6,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 1f */ + + asm volatile("vpcmpd $0x12,%zmm6,%zmm7,%k5"); + asm volatile("vpcmpq $0x12,%zmm6,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 23 */ + + asm volatile("vshuff32x4 $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vshuff64x2 $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 25 */ + + asm volatile("vpternlogd $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vpternlogq $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 26 */ + + asm volatile("vgetmantps $0x12,%zmm6,%zmm7"); + asm volatile("vgetmantpd $0x12,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 27 */ + + asm volatile("vgetmantss $0x12,%xmm5,%xmm6,%xmm7{%k7}"); + asm volatile("vgetmantsd $0x12,%xmm5,%xmm6,%xmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 38 */ + + asm volatile("vinserti128 $0x5,%xmm4,%ymm4,%ymm6"); + asm volatile("vinserti32x4 $0x12,%xmm4,%zmm5,%zmm6{%k7}"); + asm volatile("vinserti64x2 $0x12,%xmm4,%zmm5,%zmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 39 */ + + asm volatile("vextracti128 $0x5,%ymm4,%xmm6"); + asm volatile("vextracti32x4 $0x12,%zmm5,%xmm6{%k7}"); + asm volatile("vextracti64x2 $0x12,%zmm5,%xmm6{%k7}"); + + /* AVX-512: Op code 0f 3a 3a */ + + asm volatile("vinserti32x8 $0x12,%ymm5,%zmm6,%zmm7{%k7}"); + asm volatile("vinserti64x4 $0x12,%ymm5,%zmm6,%zmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 3b */ + + asm volatile("vextracti32x8 $0x12,%zmm6,%ymm7{%k7}"); + asm volatile("vextracti64x4 $0x12,%zmm6,%ymm7{%k7}"); + + /* AVX-512: Op code 0f 3a 3e */ + + asm volatile("vpcmpub $0x12,%zmm6,%zmm7,%k5"); + asm volatile("vpcmpuw $0x12,%zmm6,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 3f */ + + asm volatile("vpcmpb $0x12,%zmm6,%zmm7,%k5"); + asm volatile("vpcmpw $0x12,%zmm6,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 42 */ + + asm volatile("vmpsadbw $0x5,%ymm4,%ymm6,%ymm2"); + asm volatile("vdbpsadbw $0x12,%zmm4,%zmm5,%zmm6"); + + /* AVX-512: Op code 0f 3a 43 */ + + asm volatile("vshufi32x4 $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vshufi64x2 $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 50 */ + + asm volatile("vrangeps $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vrangepd $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 51 */ + + asm volatile("vrangess $0x12,%xmm5,%xmm6,%xmm7"); + asm volatile("vrangesd $0x12,%xmm5,%xmm6,%xmm7"); + + /* AVX-512: Op code 0f 3a 54 */ + + asm volatile("vfixupimmps $0x12,%zmm5,%zmm6,%zmm7"); + asm volatile("vfixupimmpd $0x12,%zmm5,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 55 */ + + asm volatile("vfixupimmss $0x12,%xmm5,%xmm6,%xmm7{%k7}"); + asm volatile("vfixupimmsd $0x12,%xmm5,%xmm6,%xmm7{%k7}"); + + /* AVX-512: Op code 0f 3a 56 */ + + asm volatile("vreduceps $0x12,%zmm6,%zmm7"); + asm volatile("vreducepd $0x12,%zmm6,%zmm7"); + + /* AVX-512: Op code 0f 3a 57 */ + + asm volatile("vreducess $0x12,%xmm5,%xmm6,%xmm7"); + asm volatile("vreducesd $0x12,%xmm5,%xmm6,%xmm7"); + + /* AVX-512: Op code 0f 3a 66 */ + + asm volatile("vfpclassps $0x12,%zmm7,%k5"); + asm volatile("vfpclasspd $0x12,%zmm7,%k5"); + + /* AVX-512: Op code 0f 3a 67 */ + + asm volatile("vfpclassss $0x12,%xmm7,%k5"); + asm volatile("vfpclasssd $0x12,%xmm7,%k5"); + + /* AVX-512: Op code 0f 72 (Grp13) */ + + asm volatile("vprord $0x12,%zmm5,%zmm6"); + asm volatile("vprorq $0x12,%zmm5,%zmm6"); + asm volatile("vprold $0x12,%zmm5,%zmm6"); + asm volatile("vprolq $0x12,%zmm5,%zmm6"); + asm volatile("psrad $0x2,%mm6"); + asm volatile("vpsrad $0x5,%ymm6,%ymm2"); + asm volatile("vpsrad $0x5,%zmm6,%zmm2"); + asm volatile("vpsraq $0x5,%zmm6,%zmm2"); + + /* AVX-512: Op code 0f 38 c6 (Grp18) */ + + asm volatile("vgatherpf0dps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf0dpd 0x7b(%ebp,%ymm7,8){%k1}"); + asm volatile("vgatherpf1dps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf1dpd 0x7b(%ebp,%ymm7,8){%k1}"); + asm volatile("vscatterpf0dps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf0dpd 0x7b(%ebp,%ymm7,8){%k1}"); + asm volatile("vscatterpf1dps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf1dpd 0x7b(%ebp,%ymm7,8){%k1}"); + + /* AVX-512: Op code 0f 38 c7 (Grp19) */ + + asm volatile("vgatherpf0qps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf0qpd 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf1qps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vgatherpf1qpd 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf0qps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf0qpd 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf1qps 0x7b(%ebp,%zmm7,8){%k1}"); + asm volatile("vscatterpf1qpd 0x7b(%ebp,%zmm7,8){%k1}"); + + /* AVX-512: Examples */ + + asm volatile("vaddpd %zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd %zmm4,%zmm5,%zmm6{%k7}"); + asm volatile("vaddpd %zmm4,%zmm5,%zmm6{%k7}{z}"); + asm volatile("vaddpd {rn-sae},%zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd {ru-sae},%zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd {rd-sae},%zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd {rz-sae},%zmm4,%zmm5,%zmm6"); + asm volatile("vaddpd (%ecx),%zmm5,%zmm6"); + asm volatile("vaddpd 0x123(%eax,%ecx,8),%zmm5,%zmm6"); + asm volatile("vaddpd (%ecx){1to8},%zmm5,%zmm6"); + asm volatile("vaddpd 0x1fc0(%edx),%zmm5,%zmm6"); + asm volatile("vaddpd 0x3f8(%edx){1to8},%zmm5,%zmm6"); + asm volatile("vcmpeq_uqps 0x1fc(%edx){1to16},%zmm6,%k5"); + asm volatile("vcmpltsd 0x123(%eax,%ecx,8),%xmm3,%k5{%k7}"); + asm volatile("vcmplesd {sae},%xmm4,%xmm5,%k5{%k7}"); + asm volatile("vgetmantss $0x5b,0x123(%eax,%ecx,8),%xmm4,%xmm5{%k7}"); + /* bndmk m32, bnd */ asm volatile("bndmk (%eax), %bnd0"); ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder 2016-07-20 8:30 [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Adrian Hunter ` (3 preceding siblings ...) 2016-07-20 8:30 ` [PATCH V2 4/4] perf tools: Add AVX-512 instructions to the new instructions test Adrian Hunter @ 2016-07-20 18:11 ` Masami Hiramatsu 2016-07-21 11:18 ` Adrian Hunter 4 siblings, 1 reply; 18+ messages in thread From: Masami Hiramatsu @ 2016-07-20 18:11 UTC (permalink / raw) To: Adrian Hunter Cc: linux-kernel, Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Masami Hiramatsu, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML On Wed, 20 Jul 2016 11:30:33 +0300 Adrian Hunter <adrian.hunter@intel.com> wrote: > Hi > > Here are patches to add support for Intel's AVX-512 instructions to the > instruction decoder. Also there is a patch to fix vcvtph2ps. > > AVX-512 instructions are documented in Intel Architecture Instruction Set > Extensions Programming Reference (February 2016). > > These patches do not conflict with Dan's removal of pcommit. > > Changes in V2: > > Split patches: separate out perf tools and new instructions test. > Amend decription of 'evo' annotation in x86-opcode-map.txt Thanks for updating! Acked-by: Masami Hiramatsu <mhiramat@kernel.org> for the series :) Thank you, > > > Adrian Hunter (4): > x86/insn: perf tools: Fix vcvtph2ps instruction decoding > x86/insn: Add AVX-512 support to the instruction decoder > perf tools: Add AVX-512 support to the instruction decoder used by Intel PT > perf tools: Add AVX-512 instructions to the new instructions test > > arch/x86/include/asm/inat.h | 17 +- > arch/x86/include/asm/insn.h | 12 +- > arch/x86/lib/insn.c | 18 +- > arch/x86/lib/x86-opcode-map.txt | 263 ++- > arch/x86/tools/gen-insn-attr-x86.awk | 11 +- > tools/perf/arch/x86/tests/insn-x86-dat-32.c | 1018 ++++++++++- > tools/perf/arch/x86/tests/insn-x86-dat-64.c | 940 +++++++++- > tools/perf/arch/x86/tests/insn-x86-dat-src.c | 1789 ++++++++++++++++++++ > .../util/intel-pt-decoder/gen-insn-attr-x86.awk | 11 +- > tools/perf/util/intel-pt-decoder/inat.h | 17 +- > tools/perf/util/intel-pt-decoder/insn.c | 18 +- > tools/perf/util/intel-pt-decoder/insn.h | 12 +- > .../perf/util/intel-pt-decoder/x86-opcode-map.txt | 263 ++- > 13 files changed, 4179 insertions(+), 210 deletions(-) > > > Regards > Adrian -- Masami Hiramatsu <mhiramat@kernel.org> ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder 2016-07-20 18:11 ` [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Masami Hiramatsu @ 2016-07-21 11:18 ` Adrian Hunter 2016-07-21 12:39 ` Arnaldo Carvalho de Melo 0 siblings, 1 reply; 18+ messages in thread From: Adrian Hunter @ 2016-07-21 11:18 UTC (permalink / raw) To: Masami Hiramatsu Cc: linux-kernel, Arnaldo Carvalho de Melo, Jiri Olsa, Dan Williams, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML On 20/07/16 21:11, Masami Hiramatsu wrote: > On Wed, 20 Jul 2016 11:30:33 +0300 > Adrian Hunter <adrian.hunter@intel.com> wrote: > >> Hi >> >> Here are patches to add support for Intel's AVX-512 instructions to the >> instruction decoder. Also there is a patch to fix vcvtph2ps. >> >> AVX-512 instructions are documented in Intel Architecture Instruction Set >> Extensions Programming Reference (February 2016). >> >> These patches do not conflict with Dan's removal of pcommit. >> >> Changes in V2: >> >> Split patches: separate out perf tools and new instructions test. >> Amend decription of 'evo' annotation in x86-opcode-map.txt > > Thanks for updating! > > Acked-by: Masami Hiramatsu <mhiramat@kernel.org> > > for the series :) > > Thank you, Thanks to Masami's quick ack's, I think it would be reasonable to queue these patches for v4.8 unless anyone objects. Arnaldo, if you are willing, please consider queuing these. > >> >> >> Adrian Hunter (4): >> x86/insn: perf tools: Fix vcvtph2ps instruction decoding >> x86/insn: Add AVX-512 support to the instruction decoder >> perf tools: Add AVX-512 support to the instruction decoder used by Intel PT >> perf tools: Add AVX-512 instructions to the new instructions test >> >> arch/x86/include/asm/inat.h | 17 +- >> arch/x86/include/asm/insn.h | 12 +- >> arch/x86/lib/insn.c | 18 +- >> arch/x86/lib/x86-opcode-map.txt | 263 ++- >> arch/x86/tools/gen-insn-attr-x86.awk | 11 +- >> tools/perf/arch/x86/tests/insn-x86-dat-32.c | 1018 ++++++++++- >> tools/perf/arch/x86/tests/insn-x86-dat-64.c | 940 +++++++++- >> tools/perf/arch/x86/tests/insn-x86-dat-src.c | 1789 ++++++++++++++++++++ >> .../util/intel-pt-decoder/gen-insn-attr-x86.awk | 11 +- >> tools/perf/util/intel-pt-decoder/inat.h | 17 +- >> tools/perf/util/intel-pt-decoder/insn.c | 18 +- >> tools/perf/util/intel-pt-decoder/insn.h | 12 +- >> .../perf/util/intel-pt-decoder/x86-opcode-map.txt | 263 ++- >> 13 files changed, 4179 insertions(+), 210 deletions(-) >> >> >> Regards >> Adrian > > ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder 2016-07-21 11:18 ` Adrian Hunter @ 2016-07-21 12:39 ` Arnaldo Carvalho de Melo 0 siblings, 0 replies; 18+ messages in thread From: Arnaldo Carvalho de Melo @ 2016-07-21 12:39 UTC (permalink / raw) To: Adrian Hunter Cc: Masami Hiramatsu, linux-kernel, Jiri Olsa, Dan Williams, Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Andy Lutomirski, X86 ML Em Thu, Jul 21, 2016 at 02:18:34PM +0300, Adrian Hunter escreveu: > On 20/07/16 21:11, Masami Hiramatsu wrote: > > On Wed, 20 Jul 2016 11:30:33 +0300 > > Adrian Hunter <adrian.hunter@intel.com> wrote: > >> Here are patches to add support for Intel's AVX-512 instructions to the > >> instruction decoder. Also there is a patch to fix vcvtph2ps. > >> > >> AVX-512 instructions are documented in Intel Architecture Instruction Set > >> Extensions Programming Reference (February 2016). > >> > >> These patches do not conflict with Dan's removal of pcommit. > >> > >> Changes in V2: > >> > >> Split patches: separate out perf tools and new instructions test. > >> Amend decription of 'evo' annotation in x86-opcode-map.txt > > > > Thanks for updating! > > > > Acked-by: Masami Hiramatsu <mhiramat@kernel.org> > > > > for the series :) > > > > Thank you, > > Thanks to Masami's quick ack's, I think it would be reasonable to queue > these patches for v4.8 unless anyone objects. > > Arnaldo, if you are willing, please consider queuing these. Yeah, I already have it, acked by Masami and Ingo, Just pushed it in my perf/core branch. Thanks, - Arnaldo ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2025-12-02 10:48 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-07-20 8:30 [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Adrian Hunter 2016-07-20 8:30 ` [PATCH V2 1/4] x86/insn: perf tools: Fix vcvtph2ps instruction decoding Adrian Hunter 2016-07-25 18:08 ` [tip:perf/core] " tip-bot for Adrian Hunter 2016-07-20 8:30 ` [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder Adrian Hunter 2016-07-25 18:08 ` [tip:perf/core] " tip-bot for Adrian Hunter 2025-11-30 16:05 ` [PATCH V2 2/4] " Borislav Petkov 2025-12-01 11:25 ` Borislav Petkov 2025-12-01 18:15 ` Adrian Hunter 2025-12-01 19:01 ` Borislav Petkov 2025-12-02 6:26 ` Adrian Hunter 2025-12-02 10:47 ` Borislav Petkov 2016-07-20 8:30 ` [PATCH V2 3/4] perf tools: Add AVX-512 support to the instruction decoder used by Intel PT Adrian Hunter 2016-07-25 18:09 ` [tip:perf/core] " tip-bot for Adrian Hunter 2016-07-20 8:30 ` [PATCH V2 4/4] perf tools: Add AVX-512 instructions to the new instructions test Adrian Hunter 2016-07-25 18:09 ` [tip:perf/core] " tip-bot for Adrian Hunter 2016-07-20 18:11 ` [PATCH V2 0/4] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Masami Hiramatsu 2016-07-21 11:18 ` Adrian Hunter 2016-07-21 12:39 ` Arnaldo Carvalho de Melo
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