[PATCH] perf/x86/intel/uncore: Fix CHA registers configuration procedure for Knights Landing platform

[PATCH] perf/x86/intel/uncore: Fix CHA registers configuration procedure for Knights Landing platform

[hchrzani]

CHA events in Knights Landing platform require programming filter registers properly.
Before change, code lacked mandatory bitset operations for reserved bits.
As a result some events were not counted.

Fixes: 77af003 ('perf/x86/intel/uncore: Add Knights Landing uncore PMU support')
Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
Signed-off-by: Lawrence F Meadows <lawrence.f.meadows@intel.com>
---
 arch/x86/events/intel/uncore_snbep.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index ab2bcaa..47d7216 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -1902,6 +1902,7 @@ static int knl_cha_hw_config(struct intel_uncore_box *box,
 		reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
 			    KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx;
 		reg1->config = event->attr.config1 & knl_cha_filter_mask(idx);
+		reg1->config |= 0x23ull << 32;
 		reg1->idx = idx;
 	}
 	return 0;
-- 
1.8.3.1

Re: [PATCH] perf/x86/intel/uncore: Fix CHA registers configuration procedure for Knights Landing platform

[Thomas Gleixner]

On Fri, 6 May 2016, hchrzani wrote:

> CHA events in Knights Landing platform require programming filter registers properly.
> Before change, code lacked mandatory bitset operations for reserved bits.
> As a result some events were not counted.
> 
> Fixes: 77af003 ('perf/x86/intel/uncore: Add Knights Landing uncore PMU support')
> Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
> Signed-off-by: Lawrence F Meadows <lawrence.f.meadows@intel.com>
> ---
>  arch/x86/events/intel/uncore_snbep.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index ab2bcaa..47d7216 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -1902,6 +1902,7 @@ static int knl_cha_hw_config(struct intel_uncore_box *box,
>  		reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
>  			    KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx;
>  		reg1->config = event->attr.config1 & knl_cha_filter_mask(idx);
> +		reg1->config |= 0x23ull << 32;

Please use proper defines and not some magic hex constants.

Thanks,

	tglx

[PATCH] perf/x86/intel/uncore: Fix CHA registers configuration procedure for Knights Landing platform

[hchrzani]

CHA events in Knights Landing platform require programming filter registers properly.
Remote node, local node and NonNearMemCachable bits should be set to 1 at all times.

Fixes: 77af003 ('perf/x86/intel/uncore: Add Knights Landing uncore PMU support')
Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
Signed-off-by: Lawrence F Meadows <lawrence.f.meadows@intel.com>
---
 arch/x86/events/intel/uncore_snbep.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index ab2bcaa..4b9e294 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -219,6 +219,9 @@
 #define KNL_CHA_MSR_PMON_BOX_FILTER_TID		0x1ff
 #define KNL_CHA_MSR_PMON_BOX_FILTER_STATE	(7 << 18)
 #define KNL_CHA_MSR_PMON_BOX_FILTER_OP		(0xfffffe2aULL << 32)
+#define KNL_CHA_MSR_PMON_BOX_FILER_REMOTE_NODE	(0x1ULL << 32)
+#define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE	(0x1ULL << 33)
+#define KNL_CHA_MSR_PMON_BOX_FILTER_NNC		(0x1ULL << 37)
 
 /* KNL EDC/MC UCLK */
 #define KNL_UCLK_MSR_PMON_CTR0_LOW		0x400
@@ -1902,6 +1905,10 @@ static int knl_cha_hw_config(struct intel_uncore_box *box,
 		reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
 			    KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx;
 		reg1->config = event->attr.config1 & knl_cha_filter_mask(idx);
+
+		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILER_REMOTE_NODE;
+		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE;
+		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC;
 		reg1->idx = idx;
 	}
 	return 0;
-- 
1.8.3.1

Re: [PATCH] perf/x86/intel/uncore: Fix CHA registers configuration procedure for Knights Landing platform

[Ingo Molnar]

* hchrzani <hubert.chrzaniuk@intel.com> wrote:

> CHA events in Knights Landing platform require programming filter registers properly.
> Remote node, local node and NonNearMemCachable bits should be set to 1 at all times.
> 
> Fixes: 77af003 ('perf/x86/intel/uncore: Add Knights Landing uncore PMU support')
> Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
> Signed-off-by: Lawrence F Meadows <lawrence.f.meadows@intel.com>
> ---
>  arch/x86/events/intel/uncore_snbep.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index ab2bcaa..4b9e294 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -219,6 +219,9 @@
>  #define KNL_CHA_MSR_PMON_BOX_FILTER_TID		0x1ff
>  #define KNL_CHA_MSR_PMON_BOX_FILTER_STATE	(7 << 18)
>  #define KNL_CHA_MSR_PMON_BOX_FILTER_OP		(0xfffffe2aULL << 32)
> +#define KNL_CHA_MSR_PMON_BOX_FILER_REMOTE_NODE	(0x1ULL << 32)
> +#define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE	(0x1ULL << 33)
> +#define KNL_CHA_MSR_PMON_BOX_FILTER_NNC		(0x1ULL << 37)
>  
>  /* KNL EDC/MC UCLK */
>  #define KNL_UCLK_MSR_PMON_CTR0_LOW		0x400
> @@ -1902,6 +1905,10 @@ static int knl_cha_hw_config(struct intel_uncore_box *box,
>  		reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
>  			    KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx;
>  		reg1->config = event->attr.config1 & knl_cha_filter_mask(idx);
> +
> +		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILER_REMOTE_NODE;
> +		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE;
> +		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC;

s/FILER/FILTER?

Thanks,

	Ingo

[PATCH v3] perf/x86/intel/uncore: Fix CHA registers configuration

[Hubert Chrzaniuk]

> s/FILER/FILTER?

executed,thanks
hopefully no silly mistakes anymore

[PATCH] perf/x86/intel/uncore: Fix CHA registers configuration procedure for Knights Landing platform

[Hubert Chrzaniuk]

From: hchrzani <hubert.chrzaniuk@intel.com>

CHA events in Knights Landing platform require programming filter registers properly.
Remote node, local node and NonNearMemCachable bits should be set to 1 at all times.

Fixes: 77af003 ('perf/x86/intel/uncore: Add Knights Landing uncore PMU support')
Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
Signed-off-by: Lawrence F Meadows <lawrence.f.meadows@intel.com>
---
 arch/x86/events/intel/uncore_snbep.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index ab2bcaa..b262586 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -219,6 +219,9 @@
 #define KNL_CHA_MSR_PMON_BOX_FILTER_TID		0x1ff
 #define KNL_CHA_MSR_PMON_BOX_FILTER_STATE	(7 << 18)
 #define KNL_CHA_MSR_PMON_BOX_FILTER_OP		(0xfffffe2aULL << 32)
+#define KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE	(0x1ULL << 32)
+#define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE	(0x1ULL << 33)
+#define KNL_CHA_MSR_PMON_BOX_FILTER_NNC		(0x1ULL << 37)
 
 /* KNL EDC/MC UCLK */
 #define KNL_UCLK_MSR_PMON_CTR0_LOW		0x400
@@ -1902,6 +1905,10 @@ static int knl_cha_hw_config(struct intel_uncore_box *box,
 		reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
 			    KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx;
 		reg1->config = event->attr.config1 & knl_cha_filter_mask(idx);
+
+		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE;
+		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE;
+		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC;
 		reg1->idx = idx;
 	}
 	return 0;
-- 
1.8.3.1

[tip:perf/core] perf/x86/intel/uncore: Fix CHA registers configuration procedure for Knights Landing platform

[tip-bot for hchrzani]

Commit-ID:  ec336c879c3b422d2876085be1cbb110e44dc0de
Gitweb:     http://git.kernel.org/tip/ec336c879c3b422d2876085be1cbb110e44dc0de
Author:     hchrzani <hubert.chrzaniuk@intel.com>
AuthorDate: Mon, 9 May 2016 09:36:59 +0200
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 12 May 2016 10:14:30 +0200

perf/x86/intel/uncore: Fix CHA registers configuration procedure for Knights Landing platform

CHA events in Knights Landing platform require programming filter registers properly.
Remote node, local node and NonNearMemCachable bits should be set to 1 at all times.

Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
Signed-off-by: Lawrence F Meadows <lawrence.f.meadows@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: bp@suse.de
Cc: harish.chegondi@intel.com
Cc: hpa@zytor.com
Cc: izumi.taku@jp.fujitsu.com
Cc: kan.liang@intel.com
Cc: lukasz.anaczkowski@intel.com
Cc: vthakkar1994@gmail.com
Fixes: 77af0037de0a ('perf/x86/intel/uncore: Add Knights Landing uncore PMU support')
Link: http://lkml.kernel.org/r/1462779419-17115-2-git-send-email-hubert.chrzaniuk@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/events/intel/uncore_snbep.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index ab2bcaa..b262586 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -219,6 +219,9 @@
 #define KNL_CHA_MSR_PMON_BOX_FILTER_TID		0x1ff
 #define KNL_CHA_MSR_PMON_BOX_FILTER_STATE	(7 << 18)
 #define KNL_CHA_MSR_PMON_BOX_FILTER_OP		(0xfffffe2aULL << 32)
+#define KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE	(0x1ULL << 32)
+#define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE	(0x1ULL << 33)
+#define KNL_CHA_MSR_PMON_BOX_FILTER_NNC		(0x1ULL << 37)
 
 /* KNL EDC/MC UCLK */
 #define KNL_UCLK_MSR_PMON_CTR0_LOW		0x400
@@ -1902,6 +1905,10 @@ static int knl_cha_hw_config(struct intel_uncore_box *box,
 		reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
 			    KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx;
 		reg1->config = event->attr.config1 & knl_cha_filter_mask(idx);
+
+		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE;
+		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE;
+		reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC;
 		reg1->idx = idx;
 	}
 	return 0;