From: Yishai Hadas <yishaih@nvidia.com>
To: <netdev-bot+sashiko@kernel.org>
Cc: <jgg@ziepe.ca>, <leon@kernel.org>, <linux-rdma@vger.kernel.org>,
<netdev@vger.kernel.org>, <saeedm@nvidia.com>,
<tariqt@nvidia.com>, <mbloch@nvidia.com>, <kuba@kernel.org>,
<pabeni@redhat.com>, <edumazet@kernel.org>, <davem@davemloft.net>,
<andrew+netdev@lunn.ch>, <dtatulea@nvidia.com>,
<moshe@nvidia.com>, <maorg@nvidia.com>
Subject: Re: [PATCH rdma-next 19/23] RDMA/mlx5: Clamp log_max_cq_sz shift in CQ size checks
Date: Mon, 9 Nov 2026 12:27:02 +0200 [thread overview]
Message-ID: <05c7526e-90a9-4240-bce3-98ae5e06bc79@nvidia.com> (raw)
In-Reply-To: <179408310459.994134.3829922527726679973@kernel.org>
On 07/11/2026 22:25, netdev-bot+sashiko@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential
> issue(s) to consider.
>
> Critical: 0 · High: 1 · Medium: 0 · Low: 0
>
> If you believe none of the issues are legitimate, please reply to each
> issue of Medium severity or higher and explain why the AI is wrong.
> If any of them are legitimate and you plan to respin, please let patchwork
> know by including "pw-bot: cr" as a separate line at the end of your reply
> (one such reply per series is enough).
>
> - [High] The new `entries > INT_MAX` check only keeps the CQ entry count
> inside an int.
>
> --
>
> RDMA/mlx5: Clamp log_max_cq_sz shift in CQ size checks
>
> This commit computes the CQ size limit with MLX5_CAP_GEN_LOGSZ_U64(), so
> an untrusted log_max_cq_sz no longer causes an undefined shift. The
> requested entry count is now rounded up in 64 bits. Sizes above INT_MAX
> are rejected in the create and resize paths.
>
>> diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/cq.c
>> index f955eb762051d..25344dfba1c12 100644
>> --- a/drivers/infiniband/hw/mlx5/cq.c
>> +++ b/drivers/infiniband/hw/mlx5/cq.c
>
> [ ... ]
>
>> @@ -1226,12 +1237,14 @@ int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
>> int cqe_size;
>> int eqn;
>> int err;
>> + u64 max_cq_entries = MLX5_CAP_GEN_LOGSZ_U64(dev->mdev, log_max_cq_sz);
>>
>> - if (attr->cqe > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
>> + if (attr->cqe > max_cq_entries)
>> return -EINVAL;
>>
>> - entries = roundup_pow_of_two(entries + 1);
>> - if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
>> + entries = cq_roundup_entries(entries);
>> + /* cq->ibcq.cqe and create_cq_kernel() take an int */
>> + if (entries > max_cq_entries || entries > INT_MAX)
>> return -EINVAL;
>
> [Severity: High]
> Is INT_MAX the right bound here? It keeps the entry count inside an int,
> but the CQ buffer's byte size is still computed from it in 32-bit
> arithmetic.
>
> With a device-reported log_max_cq_sz of 26 or more, entries can now be up
> to 2^30. They are then passed to create_cq_kernel() and on to
> alloc_cq_frag_buf():
>
> drivers/infiniband/hw/mlx5/cq.c:alloc_cq_frag_buf() {
> ...
> err = mlx5_frag_buf_alloc_node(dev->mdev,
> nent * cqe_size,
> frag_buf,
> dev->mdev->priv.numa_node);
> ...
> }
>
> Both values are powers of two. So nent * cqe_size wraps to exactly 0 for
> nent >= 2^26 with 64-byte CQEs. With 128-byte CQEs
> (cache_line_size() == 128) it wraps at nent >= 2^25.
>
> With size 0, mlx5_frag_buf_alloc_node() sets npages to 0, and
> kcalloc_node(0, ...) returns ZERO_SIZE_PTR. The function then returns
> success, and buf->nent is still set to the full count.
>
> init_cq_frag_buf() then does:
>
> for (i = 0; i < buf->nent; i++) {
> cqe = mlx5_frag_buf_get_wqe(&buf->fbc, i);
> ...
> }
>
> Won't mlx5_frag_buf_get_wqe() dereference fbc->frags[0].buf through
> ZERO_SIZE_PTR on the first iteration and oops?
>
> mlx5_ib_resize_cq() with udata == NULL has the same INT_MAX-only check.
> It reaches the same code through resize_kernel()->alloc_cq_frag_buf()->
> init_cq_frag_buf().
>
> The user path in mlx5_ib_create_user_cq() has a similar problem.
> create_cq_user() passes this as the minimum umem size:
>
> cq->buf.umem = ib_umem_get_cq_buf_or_va(&dev->ib_dev, attrs,
> ucmd.buf_addr,
> entries * ucmd.cqe_size,
> IB_ACCESS_LOCAL_WRITE);
>
> That is a 32-bit unsigned multiply, and it wraps to 0 the same way. On the
> UMEM-attribute path, the only length check in ib_umem_get_desc_check() is
> umem->length < min_size, so any umem passes. The device is still
> programmed with log_cq_size = ilog2(entries). resize_user() already uses
> (size_t)ucmd.cqe_size * entries for this.
>
> The commit message says a large limit made the CQ size get "truncated
> when passed on as an int". Since create_cq_kernel() still multiplies that
> int by cqe_size, can this truncation still happen?
>
> Should the bound account for the CQE size, for example by rejecting
> entries > INT_MAX / 128? Another option would be to compute the byte size
> in size_t with check_mul_overflow().
>
>>
>> cq->ibcq.cqe = entries - 1;
>
> [ ... ]
>
Right, V1 will compute the buffer size with check_mul_overflow(), using
the real CQE size, in the kernel and the user paths.
Yishai
next prev parent reply other threads:[~2026-11-09 10:27 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 16:39 [PATCH rdma-next 00/23] mlx5: Adversarial mode for confidential computing guests Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 01/23] net/mlx5: Add mlx5_trigger_health_work_force() Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-08 16:17 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 02/23] net/mlx5: Derive adversarial mode from CC guest memory encryption Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-03 16:39 ` [PATCH rdma-next 03/23] net/mlx5: Add capability filtering in adversarial mode Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-09 8:27 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 04/23] net/mlx5: Add macros for reading log-based caps Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-03 16:39 ` [PATCH rdma-next 05/23] RDMA/mlx5: Reject QP transport types not enabled by FW capability Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-03 16:39 ` [PATCH rdma-next 06/23] RDMA/mlx5: Require IB_QPT_DRIVER for the DC vendor QP types Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-09 8:37 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 07/23] RDMA/mlx5: Derive mlx5_ib_adversarial_mode global from mlx5_core adversarial API Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-03 16:39 ` [PATCH rdma-next 08/23] RDMA/core: Suppress kverbs_provider for adversarial_mode devices Yishai Hadas
2026-11-03 19:03 ` Jacob Moroni
2026-11-03 19:07 ` Jason Gunthorpe
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-03 16:39 ` [PATCH rdma-next 09/23] RDMA/mlx5: Remove duplicate mlx5_ib_umr_context struct Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 10/23] RDMA/mlx5: Introduce per-CQ poll_one hook in mlx5_ib_cq Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-03 16:39 ` [PATCH rdma-next 11/23] RDMA/mlx5: Add shadow FIFO infrastructure for UMR completions Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-09 8:50 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 12/23] RDMA/mlx5: Verify UMR CQ polling against a hostile NIC Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-09 9:38 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 13/23] RDMA/mlx5: Keep the UMR QP failed once a forged CQE is detected Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-09 9:48 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 14/23] RDMA/mlx5: Block generic CQ poll path in adversarial mode Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-03 16:39 ` [PATCH rdma-next 15/23] RDMA/core: Set the CQ comp_handler after its poll context is set up Yishai Hadas
2026-11-07 20:24 ` netdev-bot+sashiko
2026-11-09 10:03 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 16/23] RDMA/mlx5: Ignore completion events for a CQ without a handler Yishai Hadas
2026-11-07 20:25 ` netdev-bot+sashiko
2026-11-09 10:09 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 17/23] RDMA/mlx5: Validate EQE port and GSI port before indexing devr.ports[] Yishai Hadas
2026-11-07 20:25 ` netdev-bot+sashiko
2026-11-09 10:18 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 18/23] RDMA/mlx5: Validate firmware RQ/SQ state before sqrq_trans[] lookup Yishai Hadas
2026-11-07 20:25 ` netdev-bot+sashiko
2026-11-09 10:24 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 19/23] RDMA/mlx5: Clamp log_max_cq_sz shift in CQ size checks Yishai Hadas
2026-11-07 20:25 ` netdev-bot+sashiko
2026-11-09 10:27 ` Yishai Hadas [this message]
2026-11-03 16:39 ` [PATCH rdma-next 20/23] RDMA/mlx5: Clamp log_max_* shifts in QP and WQ limit checks Yishai Hadas
2026-11-07 20:25 ` netdev-bot+sashiko
2026-11-09 10:30 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 21/23] RDMA/mlx5: Clamp log_max_* shifts in query_device and ucontext paths Yishai Hadas
2026-11-07 20:25 ` netdev-bot+sashiko
2026-11-09 10:44 ` Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 22/23] RDMA/core: Report and enforce adversarial mode via GET_CONTEXT Yishai Hadas
2026-11-03 16:39 ` [PATCH rdma-next 23/23] RDMA/mlx5: Advertise adversarial mode via ib_device::adversarial_mode Yishai Hadas
2026-11-07 20:25 ` netdev-bot+sashiko
2026-11-09 10:52 ` Yishai Hadas
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