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* mv88e6xxx: 88E6320 external PHY on MDC_PHY/MDIO_PHY - (GPIO 7/8) — is mdio-gpio the right approach?
@ 2026-05-12 11:32 Tiju Jacob
  2026-05-12 12:39 ` Andrew Lunn
  0 siblings, 1 reply; 2+ messages in thread
From: Tiju Jacob @ 2026-05-12 11:32 UTC (permalink / raw)
  To: netdev; +Cc: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean

Hi All,

We have an 88E6320 (marvell,mv88e6085) with an 88E1512 PHY on Port 5.

The PHY's MDIO is wired to the switch's MDC_PHY/MDIO_PHY pins (52/53
=GPIO 7/8), which are separate physical pins from MDC_CPU/MDIO_CPU
(54/55) used by the CPU. GPIO 7/8 read HIGH as inputs confirming the
PHY is alive.

We tested exhaustively at runtime: marvell,mv88e6xxx-mdio-external,
NORMALSMI set and cleared, PHY in internal mdio bus, and all 8 PCTL
modes on GPIO 7/8. In every case the PHY at address 5 was unreachable.

The mv88e6390_g2_scratch_gpio_set_smi() NO_CPU inversion appears
designed for chips where MDC_CPU and MDC_PHY are muxed on the same
pins.
On the 88E6320 they are physically separate, making the inversion
wrong — but even manually correcting NORMALSMI did not help.

Is virtual,mdio-gpio (CONFIG_MDIO_GPIO) over GPIO 7/8 the correct
upstream solution here? Or is there a mechanism to activate the
hardware MDC_PHY/MDIO_PHY master on the 88E6320 that we have missed?

Thanks,
Tiju

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2026-05-12 11:32 mv88e6xxx: 88E6320 external PHY on MDC_PHY/MDIO_PHY - (GPIO 7/8) — is mdio-gpio the right approach? Tiju Jacob
2026-05-12 12:39 ` Andrew Lunn

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