* Re: [PATCH] chelsio 10G (T1/T2)
[not found] <8A71B368A89016469F72CD08050AD334DA55F1@maui.asicdesigners.com>
@ 2006-12-05 19:58 ` Stephen Hemminger
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Hemminger @ 2006-12-05 19:58 UTC (permalink / raw)
To: Felix Marti; +Cc: netdev
On Tue, 5 Dec 2006 10:53:10 -0800
"Felix Marti" <felix@chelsio.com> wrote:
> T1's and T2's implementation of MSI has a bug. I believe to remember
> that it
>
> works with some chipsets but we should disable MSI by default.
Is this really the platform bug, if so it should be handled by the pci quirks
already. Or is this a Chelsio hardware bug?
^ permalink raw reply [flat|nested] 2+ messages in thread
* RE: [PATCH] chelsio 10G (T1/T2)
@ 2006-12-05 20:01 Felix Marti
0 siblings, 0 replies; 2+ messages in thread
From: Felix Marti @ 2006-12-05 20:01 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: netdev
> -----Original Message-----
> From: Stephen Hemminger [mailto:shemminger@osdl.org]
> Sent: Tuesday, December 05, 2006 11:59 AM
> To: Felix Marti
> Cc: netdev@vger.kernel.org
> Subject: Re: [PATCH] chelsio 10G (T1/T2)
>
> On Tue, 5 Dec 2006 10:53:10 -0800
> "Felix Marti" <felix@chelsio.com> wrote:
>
> > T1's and T2's implementation of MSI has a bug. I believe to remember
> > that it
> >
> > works with some chipsets but we should disable MSI by default.
>
>
> Is this really the platform bug, if so it should be handled by the pci
quirks
> already. Or is this a Chelsio hardware bug?
[Felix Marti] Chelsio T1 and T2 hardware bug. - T3 works with MSI as
well as MSI-X.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2006-12-05 19:58 ` [PATCH] chelsio 10G (T1/T2) Stephen Hemminger
2006-12-05 20:01 Felix Marti
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