Re: [PATCH net-next v2 2/2] net: phy: Add Marvell PHY PTP support

[Kory Maincent <kory.maincent@bootlin.com>]

On Tue, 8 Apr 2025 16:49:34 +0100
Simon Horman <horms@kernel.org> wrote:

> On Mon, Apr 07, 2025 at 04:03:01PM +0200, Kory Maincent wrote:
> > From: Russell King <rmk+kernel@armlinux.org.uk>
> > 
> > From: Russell King <rmk+kernel@armlinux.org.uk>
> > 
> > Add PTP basic support for Marvell 88E151x PHYs. These PHYs support
> > timestamping the egress and ingress of packets, but does not support
> > any packet modification.
> > 
> > The PHYs support hardware pins for providing an external clock for the
> > TAI counter, and a separate pin that can be used for event capture or
> > generation of a trigger (either a pulse or periodic).  This code does
> > not support either of these modes.
> > 
> > The driver takes inspiration from the Marvell 88E6xxx DSA and DP83640
> > drivers.  The hardware is very similar to the implementation found in
> > the 88E6xxx DSA driver, but the access methods are very different,
> > although it may be possible to create a library that both can use
> > along with accessor functions.
> > 
> > Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> > 
> > Add support for interruption.
> > Fix L2 PTP encapsulation frame detection.
> > Fix first PTP timestamp being dropped.
> > Fix Kconfig to depends on MARVELL_PHY.
> > Update comments to use kdoc.
> > 
> > Co-developed-by: Kory Maincent <kory.maincent@bootlin.com>
> > Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>  
> 
> Hi Kory,
> 
> Some minor feedback from my side.
> 
> > ---
> > 
> > Russell I don't know which email I should use, so I keep your old SOB.  
> 
> Russell's SOB seems to be missing.

It is, 5 lines higher, but maybe you prefer to have them all together. 

> 
> ...
> 
> > diff --git a/drivers/net/phy/marvell/marvell_tai.c
> > b/drivers/net/phy/marvell/marvell_tai.c  
> 
> ...
> 
> > +/* Read the global time registers using the readplus command */
> > +static u64 marvell_tai_clock_read(const struct cyclecounter *cc)
> > +{
> > +	struct marvell_tai *tai = cc_to_tai(cc);
> > +	struct phy_device *phydev = tai->phydev;
> > +	int err, oldpage, lo, hi;
> > +
> > +	oldpage = phy_select_page(phydev, MARVELL_PAGE_PTP_GLOBAL);
> > +	if (oldpage >= 0) {
> > +		/* 88e151x says to write 0x8e0e */
> > +		ptp_read_system_prets(tai->sts);
> > +		err = __phy_write(phydev, PTPG_READPLUS_COMMAND, 0x8e0e);
> > +		ptp_read_system_postts(tai->sts);
> > +		lo = __phy_read(phydev, PTPG_READPLUS_DATA);
> > +		hi = __phy_read(phydev, PTPG_READPLUS_DATA);
> > +	}  
> 
> If the condition above is not met then err, lo, and hi may be used
> uninitialised below.
> 
> Flagged by W=1 builds with clang 20.1.2, and Smatch.

Indeed thanks!

> > +	tai->caps.max_adj = 1000000;
> > +	tai->caps.adjfine = marvell_tai_adjfine;
> > +	tai->caps.adjtime = marvell_tai_adjtime;
> > +	tai->caps.gettimex64 = marvell_tai_gettimex64;
> > +	tai->caps.settime64 = marvell_tai_settime64;
> > +	tai->caps.do_aux_work = marvell_tai_aux_work;
> > +
> > +	tai->ptp_clock = ptp_clock_register(&tai->caps, &phydev->mdio.dev);
> > +	if (IS_ERR(tai->ptp_clock)) {
> > +		kfree(tai);  
> 
> tai is freed on the line above, but dereferenced on the line below.
> 
> Flagged by Smatch.

Indeed thanks!

Regards,
-- 
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com