Re: Aquantia PHY in OCSGMII mode?

[Vladimir Oltean <vladimir.oltean@nxp.com>]

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On Tue, Aug 05, 2025 at 09:59:57AM +0200, Alexander Wilhelm wrote:
> I have a ping running in the background and can observe that MAC frames and
> TX-RMON packets are continuously increasing. However, the PHY statistics remain
> unchanged. I suspect the current SGMII frames originate from U-Boot, as I load
> the firmware image via `netboot`. These statistics were recorded at 2.5G speed,
> but the same behavior is also visible at 1G.
> 
> Do you think the issue still lies within the MAC driver, or could it be related
> to the Aquantia driver or firmware?

So the claim is that in U-Boot, the exact same link with the exact same
PHY firmware works, right? Yet in Linux, MAC transmit counters increase,
but nothing comes across on the PHY side of the MII link? What about
packets sent from the link partner (the remote board connected to the PHY)?
Do packets sent from that board result in an increase of PHY counters,
and MAC RX counters?

For sure this is the correct port ("ffe4e6000.ethernet" corresponds to fm1-mac4,
port name in U-Boot would be "FM1@DTSEC4")? What SoC is this on? T1 something?
What SRDS_PRTCL_S1 value is in the RCW? I'd like to trace back the steps
in order to establish that the link works at 2.5G with autoneg disabled
on both ends. It seems to me there is either a lack of connectivity
between the MAC used in Linux and the PHY, or a protocol mismatch.

Could you please also apply this PHY debugging patch and let us know
what the Global System Configuration registers contain after the
firmware applies the provisioning?

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From 17b74539f4f1fe2c335505443d797a9e2ae1fab8 Mon Sep 17 00:00:00 2001
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Tue, 5 Aug 2025 12:54:01 +0300
Subject: [PATCH] net: phy: aquantia: dump Global System Configuration
 registers

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/phy/aquantia/aquantia.h      |  5 +++++
 drivers/net/phy/aquantia/aquantia_main.c | 18 ++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/net/phy/aquantia/aquantia.h b/drivers/net/phy/aquantia/aquantia.h
index 0c78bfabace5..9d02f9f0b8b7 100644
--- a/drivers/net/phy/aquantia/aquantia.h
+++ b/drivers/net/phy/aquantia/aquantia.h
@@ -55,10 +55,15 @@
 #define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII	3
 #define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII	4
 #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G	6
+#define VEND1_GLOBAL_CFG_AUTONEG_ENA		BIT(3)
+#define VEND1_GLOBAL_CFG_TRAINING_ENA		BIT(4)
+#define VEND1_GLOBAL_CFG_RESET_ON_TRANSITION	BIT(5)
+#define VEND1_GLOBAL_CFG_SERDES_SILENCE		BIT(6)
 #define VEND1_GLOBAL_CFG_RATE_ADAPT		GENMASK(8, 7)
 #define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0
 #define VEND1_GLOBAL_CFG_RATE_ADAPT_USX		1
 #define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2
+#define VEND1_GLOBAL_CFG_MACSEC_ENABLE		BIT(9)
 
 /* Vendor specific 1, MDIO_MMD_VEND2 */
 #define VEND1_GLOBAL_CONTROL2			0xc001
diff --git a/drivers/net/phy/aquantia/aquantia_main.c b/drivers/net/phy/aquantia/aquantia_main.c
index 77a48635d7bf..72329e328f27 100644
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -987,6 +987,15 @@ static const u16 aqr_global_cfg_regs[] = {
 	VEND1_GLOBAL_CFG_10G
 };
 
+static const int aqr_global_cfg_speeds[] = {
+	SPEED_10,
+	SPEED_100,
+	SPEED_1000,
+	SPEED_2500,
+	SPEED_5000,
+	SPEED_10000,
+};
+
 static int aqr107_fill_interface_modes(struct phy_device *phydev)
 {
 	unsigned long *possible = phydev->possible_interfaces;
@@ -1007,6 +1016,15 @@ static int aqr107_fill_interface_modes(struct phy_device *phydev)
 		serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val);
 		rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val);
 
+		phydev_info(phydev, "Speed %d SerDes mode %d autoneg %d training %d reset on transition %d silence %d rate adapt %d macsec %d\n",
+			    aqr_global_cfg_speeds[i], serdes_mode,
+			    !!(val & VEND1_GLOBAL_CFG_AUTONEG_ENA),
+			    !!(val & VEND1_GLOBAL_CFG_TRAINING_ENA),
+			    !!(val & VEND1_GLOBAL_CFG_RESET_ON_TRANSITION),
+			    !!(val & VEND1_GLOBAL_CFG_SERDES_SILENCE),
+			    rate_adapt,
+			    !!(val & VEND1_GLOBAL_CFG_MACSEC_ENABLE));
+
 		switch (serdes_mode) {
 		case VEND1_GLOBAL_CFG_SERDES_MODE_XFI:
 			if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX)
-- 
2.43.0