From: Alexander Wilhelm <alexander.wilhelm@westermo.com>
To: Vladimir Oltean <vladimir.oltean@nxp.com>
Cc: "Russell King (Oracle)" <linux@armlinux.org.uk>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: Aquantia PHY in OCSGMII mode?
Date: Wed, 8 Oct 2025 15:28:07 +0200 [thread overview]
Message-ID: <aOZm52L7k2bAEovF@FUE-ALEWI-WINX> (raw)
In-Reply-To: <20251008111059.wxf3jgialy36qc6m@skbuf>
On Wed, Oct 08, 2025 at 02:10:59PM +0300, Vladimir Oltean wrote:
[...]
> For that, please break the link again, by making the following changes on top:
>
> 1. Configure IF_MODE=3 (SGMII autoneg format) for 2500base-x:
>
> diff --git a/drivers/net/pcs/pcs-lynx.c b/drivers/net/pcs/pcs-lynx.c
> index a88cbe67cc9d..ea42b8d813f3 100644
> --- a/drivers/net/pcs/pcs-lynx.c
> +++ b/drivers/net/pcs/pcs-lynx.c
> @@ -152,11 +152,10 @@ static int lynx_pcs_config_giga(struct mdio_device *pcs,
> mdiodev_write(pcs, LINK_TIMER_HI, link_timer >> 16);
> }
>
> - if (interface == PHY_INTERFACE_MODE_1000BASEX ||
> - interface == PHY_INTERFACE_MODE_2500BASEX) {
> + if (interface == PHY_INTERFACE_MODE_1000BASEX) {
> if_mode = 0;
> } else {
> - /* SGMII and QSGMII */
> + /* SGMII, QSGMII and (incorrectly) 2500base-x */
> if_mode = IF_MODE_SGMII_EN;
> if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
> if_mode |= IF_MODE_USE_SGMII_AN;
>
> 2. Edit your MAC OF node in the device tree and add:
>
> &mac {
> managed = "in-band-status"; // this
> phy-mode = "2500base-x";
> };
>
> This will reliably cause the same behaviour as before, but with no dependency on U-Boot.
I have the broken 100M link state again (IF_MODE=3). Below are the debug
details I was able to observe:
* With 2.5G link:
mdio_bus 0x0000000ffe4e5000:00: BMSR 0x2d, BMCR 0x1140, ADV 0x41a0, LPA 0xdc01, IF_MODE 0x3
* With 1G link:
mdio_bus 0x0000000ffe4e5000:00: BMSR 0x2d, BMCR 0x1140, ADV 0x41a0, LPA 0xd801, IF_MODE 0x3
* With 100M link:
mdio_bus 0x0000000ffe4e5000:00: BMSR 0x2d, BMCR 0x1140, ADV 0x41a0, LPA 0xd401, IF_MODE 0x3
[...]
> Regarding my patch vs yours, my thoughts on this topic are: the bug is
> old, the PCS driver never worked if the registers were not as expected
> (this is not a regression), and your patch is incomplete if MII_BMCR
> also contains significant differences. I would recommend submitting
> mine, as a new feature to net-next, when it reopens for patches for 6.19.
> I've credited you with Co-developed-by due to the significance of your
> findings. Thanks.
Sure, thank you.
Best regards
Alexander Wilhelm
next prev parent reply other threads:[~2025-10-08 13:28 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-31 14:59 Aquantia PHY in OCSGMII mode? Alexander Wilhelm
2025-07-31 15:14 ` Andrew Lunn
2025-07-31 16:02 ` Russell King (Oracle)
2025-08-01 5:44 ` Alexander Wilhelm
2025-08-04 14:53 ` Andrew Lunn
2025-07-31 17:16 ` Vladimir Oltean
2025-07-31 19:26 ` Russell King (Oracle)
2025-08-01 5:50 ` Alexander Wilhelm
2025-08-01 11:01 ` Vladimir Oltean
2025-08-01 11:54 ` Alexander Wilhelm
2025-08-01 11:58 ` Russell King (Oracle)
2025-08-01 12:06 ` Alexander Wilhelm
2025-08-01 12:23 ` Russell King (Oracle)
2025-08-01 12:36 ` Alexander Wilhelm
2025-08-01 13:04 ` Vladimir Oltean
2025-08-01 14:02 ` Russell King (Oracle)
2025-08-01 14:37 ` Vladimir Oltean
2025-08-04 6:17 ` Alexander Wilhelm
2025-08-04 10:01 ` Vladimir Oltean
2025-08-04 13:01 ` Alexander Wilhelm
2025-08-04 13:41 ` Vladimir Oltean
2025-08-04 14:47 ` Alexander Wilhelm
2025-08-04 16:00 ` Vladimir Oltean
2025-08-04 16:02 ` Vladimir Oltean
2025-08-05 7:59 ` Alexander Wilhelm
2025-08-05 10:20 ` Vladimir Oltean
2025-08-05 12:44 ` Alexander Wilhelm
2025-08-06 14:58 ` Vladimir Oltean
2025-08-07 5:56 ` Alexander Wilhelm
2025-08-27 5:57 ` Alexander Wilhelm
2025-08-27 7:31 ` Vladimir Oltean
2025-08-27 8:41 ` Alexander Wilhelm
2025-08-27 8:47 ` Russell King (Oracle)
2025-08-27 9:03 ` Alexander Wilhelm
2025-08-27 9:13 ` Russell King (Oracle)
2025-08-28 9:28 ` Vladimir Oltean
2025-10-02 5:54 ` Alexander Wilhelm
2025-10-07 14:08 ` Vladimir Oltean
2025-10-08 7:47 ` Alexander Wilhelm
2025-10-08 11:10 ` Vladimir Oltean
2025-10-08 12:52 ` Russell King (Oracle)
2025-10-08 13:00 ` Vladimir Oltean
2025-10-08 13:28 ` Alexander Wilhelm [this message]
2025-10-08 14:55 ` Vladimir Oltean
2025-10-09 6:05 ` Alexander Wilhelm
2025-08-27 8:08 ` Russell King (Oracle)
2025-08-27 8:32 ` Alexander Wilhelm
2025-08-27 8:45 ` Russell King (Oracle)
2025-08-04 14:22 ` Russell King (Oracle)
2025-08-04 14:51 ` Alexander Wilhelm
2025-08-04 14:56 ` Vladimir Oltean
2025-08-01 11:13 ` Vladimir Oltean
2025-08-01 5:53 ` Alexander Wilhelm
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