* [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support
@ 2026-06-07 3:52 Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 01/10] cxgb4: Add T7 register definitions and core structures Potnuri Bharat Teja
` (10 more replies)
0 siblings, 11 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
This patch series introduces base support for the next-generation Chelsio
T7 adapter family into the cxgb4 driver.
T7 follows the previous T6 architecture, bringing significant performance
upgrades to the platform. The new chip comes in single, dual, and 4-port
variants, introducing capabilities for hardware link speeds up to
400Gbps alongside native PCIe Gen5 bus support.
To accommodate the expanded features, multi-core architecture.
This series refactors core driver subsystems while preserving backward
compatibility for legacy hardware:
1. Foundational registers, chip identification tokens, and hardware
constants are introduced to handle expanded microprocessor tracking,
larger SGE contexts, and flexible flash memory configurations.
2. CPL structures and firmware command layouts are upgraded to support the
wider traffic processor filter tuples and high-speed link profiles.
3. The driver's modular design is improved by moving bus-specific setup
routines out of cxgb4_main.c into a dedicated cxgb4_pci module.
4. The core hardware abstraction layer, SGE processing pipelines,
filtering engine, and ethtool management layouts are extended to
correctly target T7 interfaces and configuration profiles.
5. The cudbg library and debugfs diagnostic components are refactored
to output versioned structural dumps, ensuring user-space tools can
seamlessly process T7 operational telemetry.
This series has been tested for compilation and NIC traffic on T7 Chip.
Please review.
Potnuri Bharat Teja (6):
cxgb4: Add T7 register definitions and core structures
cxgb4: Add T7 chip type identification and HW constants
cxgb4: Add T7 CPL messages, FW constants, and PCI IDs
cxgb4: Add versioned structures and scratch buffs
cxgb4: Add T7 indirect regs and update library
cxgb4: Move PCI initialization logic to cxgb4_pci.c
drivers/net/ethernet/chelsio/cxgb4/Makefile | 2 +-
.../net/ethernet/chelsio/cxgb4/cudbg_common.c | 30 +
.../net/ethernet/chelsio/cxgb4/cudbg_entity.h | 147 ++-
drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h | 54 +-
.../ethernet/chelsio/cxgb4/cudbg_indir_reg.h | 43 +
.../chelsio/cxgb4/cudbg_indir_reg_t7.h | 1113 +++++++++++++++++
.../net/ethernet/chelsio/cxgb4/cudbg_lib.c | 902 +++++++++++--
.../net/ethernet/chelsio/cxgb4/cudbg_lib.h | 50 +-
.../ethernet/chelsio/cxgb4/cudbg_lib_common.h | 4 +
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 194 ++-
.../net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c | 16 +
.../net/ethernet/chelsio/cxgb4/cxgb4_pci.c | 370 ++++++
.../net/ethernet/chelsio/cxgb4/cxgb4_pci.h | 36 +
.../net/ethernet/chelsio/cxgb4/t4_chip_type.h | 10 +
drivers/net/ethernet/chelsio/cxgb4/t4_hw.h | 136 +-
drivers/net/ethernet/chelsio/cxgb4/t4_msg.h | 109 +-
.../ethernet/chelsio/cxgb4/t4_pci_id_tbl.h | 21 +
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 478 ++++++-
drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h | 16 +
.../net/ethernet/chelsio/cxgb4/t4_values.h | 15 +-
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | 82 +-
.../net/ethernet/chelsio/cxgb4/t4fw_version.h | 9 +
22 files changed, 3609 insertions(+), 228 deletions(-)
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h
--
2.39.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH net-next v1 01/10] cxgb4: Add T7 register definitions and core structures
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-07 7:02 ` Andrew Lunn
2026-06-07 3:52 ` [PATCH net-next v1 02/10] cxgb4: Add T7 chip type identification and HW constants Potnuri Bharat Teja
` (9 subsequent siblings)
10 siblings, 1 reply; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Prepare the cxgb4 driver for the upcoming T7 adapter family by adding
the required hardware register layouts, macros, and core structural
updates.
Add T7 register addresses and macro strides to t4_regs.h. This includes
the widened 16-byte memory access spacing via T7_PCIE_MEM_ACCESS_REG,
expanded SGE interrupt tracks, and new hardware error bits for timer
overflows and queue ID pauses. Structural macros like MAX_CTRL_QUEUES
are scaled up to support multi-core scaling architectures.
Update cxgb4.h to incorporate these changes into the driver layout:
- Add uniform CH_MSG logging helpers and log-level macro wrappers.
- Expand struct tp_params and ch_filter_tuple with dedicated parameter
shifts and wider filter fields to support advanced traffic engines.
- Turn the adapter devlog parameter into a multi-core array tracking
system and extend SGE descriptor structures to hold hardware physical
doorbells and ring buffer group configurations.
- Expose lifecycle, flash allocation helpers, and low-level CIM, SGE,
and mailbox interface prototypes required by the incoming hardware.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 194 ++++++--
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 478 ++++++++++++++++++-
2 files changed, 625 insertions(+), 47 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index f20f4bc58492..ca657961ae77 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -56,10 +56,28 @@
#include <linux/thermal.h>
#include <asm/io.h>
#include "t4_chip_type.h"
+
+struct adapter;
+enum dev_state {
+ DEV_STATE_UNINIT,
+ DEV_STATE_INIT,
+ DEV_STATE_ERR
+};
+
+/* Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
+ */
+#define CXGB4_MAX_ATIDS 8192U
+
#include "cxgb4_uld.h"
#include "t4fw_api.h"
+#include "t4_values.h"
+#include "cxgb4_pci.h"
+
+#define CH_INFO(adap, fmt, ...) dev_info((adap)->pdev_dev, fmt, ##__VA_ARGS__)
+#define CH_ERR(adap, fmt, ...) dev_err((adap)->pdev_dev, fmt, ##__VA_ARGS__)
+#define CH_WARN(adap, fmt, ...) dev_warn((adap)->pdev_dev, fmt, ##__VA_ARGS__)
+#define CH_ALERT(adap, fmt, ...) dev_alert((adap)->pdev_dev, fmt, ##__VA_ARGS__)
-#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
extern struct list_head adapter_list;
extern struct list_head uld_list;
extern struct mutex uld_mutex;
@@ -121,12 +139,6 @@ enum dev_master {
MASTER_MUST
};
-enum dev_state {
- DEV_STATE_UNINIT,
- DEV_STATE_INIT,
- DEV_STATE_ERR
-};
-
enum cc_pause {
PAUSE_RX = 1 << 0,
PAUSE_TX = 1 << 1,
@@ -136,7 +148,8 @@ enum cc_pause {
enum cc_fec {
FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
FEC_RS = 1 << 1, /* Reed-Solomon */
- FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
+ FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */
+ FEC_FORCE = 1 << 3 /* Forcefully set FEC */
};
enum {
@@ -374,6 +387,7 @@ struct tp_params {
* places we store their offsets here, or a -1 if the field isn't
* present.
*/
+ int ipsecidx_shift;
int fcoe_shift;
int port_shift;
int vnic_shift;
@@ -384,6 +398,13 @@ struct tp_params {
int macmatch_shift;
int matchtype_shift;
int frag_shift;
+ int roce_shift;
+ int synonly_shift;
+ int tcpflags_shift;
+
+ u8 lb_mode; /* Load Balancer Mode */
+ u8 nports; /* # of ports activated by FW */
+ u32 channel_map[NCHAN]; /* saved TP Channel Map from FW */
u64 hash_filter_mask;
};
@@ -412,6 +433,8 @@ struct pf_resources {
};
struct pci_params {
+ u16 vendor_id;
+ u16 device_id;
unsigned char speed;
unsigned char width;
};
@@ -439,7 +462,7 @@ struct adapter_params {
struct vpd_params vpd;
struct pf_resources pfres;
struct pci_params pci;
- struct devlog_params devlog;
+ struct devlog_params devlog[MAX_UP_CORES];
enum pcie_memwin drv_memwin;
unsigned int cim_la_size;
@@ -463,7 +486,7 @@ struct adapter_params {
unsigned char portvec;
enum chip_type chip; /* chip code */
struct arch_specific_params arch; /* chip specific params */
- unsigned char offload;
+ unsigned int offload;
unsigned char crypto; /* HW capability for crypto */
unsigned char ethofld; /* QoS support */
@@ -472,6 +495,7 @@ struct adapter_params {
unsigned int ofldq_wr_cred;
bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
+ bool dev_512sgl_mr; /* support 512 pbl entries per FR MR*/
unsigned int nsched_cls; /* number of traffic classes */
unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
@@ -487,6 +511,12 @@ struct adapter_params {
u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
bool write_cmpl_support; /* FW supports WRITE_CMPL */
+
+ bool tx_sendpath; /* FW supports Tx Sendpath */
+
+ u8 num_up_cores; /* # of enabled uP cores */
+ u32 tid_qid_sel_mask; /* TID based QID selection mask for uP cores */
+ u8 tid_qid_sel_shift; /* TID based QID selection shift for uP cores */
};
/* State needed to monitor the forward progress of SGE Ingress DMA activities
@@ -605,7 +635,7 @@ struct link_config {
enum {
MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
- MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
+ MAX_CTRL_QUEUES = NCHAN * MAX_UP_CORES, /* # of control Tx queues */
};
enum {
@@ -641,7 +671,6 @@ enum {
#define PRIV_FLAGS_ADAP 0
#define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
-struct adapter;
struct sge_rspq;
#include "cxgb4_dcb.h"
@@ -874,6 +903,7 @@ struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
unsigned long tx_cso; /* # of Tx checksum offloads */
unsigned long vlan_ins; /* # of Tx VLAN insertions */
unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
+ u8 group_id;
} ____cacheline_aligned_in_smp;
struct sge_uld_txq { /* state for an SGE offload Tx queue */
@@ -881,8 +911,8 @@ struct sge_uld_txq { /* state for an SGE offload Tx queue */
struct adapter *adap;
struct sk_buff_head sendq; /* list of backpressured packets */
struct tasklet_struct qresume_tsk; /* restarts the queue */
- bool service_ofldq_running; /* service_ofldq() is processing sendq */
- u8 full; /* the Tx ring is full */
+ u8 service_ofldq_running; /* service_ofldq() is processing sendq */
+ u8 full; /* the Tx ring is full */
unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
} ____cacheline_aligned_in_smp;
@@ -892,6 +922,7 @@ struct sge_ctrl_txq { /* state for an SGE control Tx queue */
struct sk_buff_head sendq; /* list of backpressured packets */
struct tasklet_struct qresume_tsk; /* restarts the queue */
u8 full; /* the Tx ring is full */
+ u8 tid_qid_group_id;
} ____cacheline_aligned_in_smp;
struct sge_uld_rxq_info {
@@ -962,6 +993,10 @@ struct sge_eohw_txq {
};
struct sge {
+ void __iomem *tx_db_addr; /* Tx doorbell */
+ void __iomem *rx_db_addr; /* Rx doorbell */
+ u64 db_gts_pa; /* physical address of doorbell and GTS register */
+
struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
struct sge_eth_txq ptptxq;
struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
@@ -1014,6 +1049,29 @@ struct sge {
int nd_msix_idx; /* Index to non-data interrupts MSI-X info */
};
+/*
+ * Return a Response Queue's Ingress Packet Count Interrupt Threshold.
+ * Returns 0 if not enabled.
+ */
+static inline unsigned int rspq_intr_pktcnt(const struct sge *s,
+ const struct sge_rspq *rspq)
+{
+ return ((rspq->intr_params & QINTR_CNT_EN_F) ?
+ s->counter_val[rspq->pktcnt_idx] :
+ 0);
+}
+
+/*
+ * Return a Response Queue's interrupt hold-off time in us. 0 means no timer.
+ */
+static inline unsigned int rspq_intr_timer(const struct sge *s,
+ const struct sge_rspq *rspq)
+{
+ unsigned int timer_idx = QINTR_TIMER_IDX_G(rspq->intr_params);
+
+ return (timer_idx < SGE_NTIMERS ? s->timer_val[timer_idx] : 0);
+}
+
#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
#define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
@@ -1109,7 +1167,9 @@ struct adapter {
struct device *pdev_dev;
const char *name;
unsigned int mbox;
+ struct mbox_chan *mbox_chan;
unsigned int pf;
+ u8 primary_pf;
unsigned int flags;
unsigned int adap_idx;
enum chip_type chip;
@@ -1146,8 +1206,10 @@ struct adapter {
unsigned int rawf_start;
unsigned int rawf_cnt;
struct smt_data *smt;
+
struct cxgb4_uld_info *uld;
void *uld_handle[CXGB4_ULD_MAX];
+
unsigned int num_uld;
unsigned int num_ofld_uld;
struct list_head list_node;
@@ -1179,6 +1241,7 @@ struct adapter {
struct mutex uld_mutex;
struct dentry *debugfs_root;
+ struct dentry *debugfs_multicore[MAX_UP_CORES];
bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
bool trace_rss; /* 1 implies that different RSS flit per filter is
* used per filter else if 0 default RSS flit is
@@ -1297,7 +1360,7 @@ struct ch_sched_flowc {
};
/* Defined bit width of user definable filter tuples
- */
+*/
#define ETHTYPE_BITWIDTH 16
#define FRAG_BITWIDTH 1
#define MACIDX_BITWIDTH 9
@@ -1311,6 +1374,7 @@ struct ch_sched_flowc {
#define IVLAN_BITWIDTH 16
#define OVLAN_BITWIDTH 16
#define ENCAP_VNI_BITWIDTH 24
+#define SYNONLY_BITWIDTH 1
/* Filter matching rules. These consist of a set of ingress packet field
* (value, mask) tuples. The associated ingress packet field matches the
@@ -1341,7 +1405,7 @@ struct ch_filter_tuple {
uint32_t ivlan_vld:1; /* inner VLAN valid */
uint32_t ovlan_vld:1; /* outer VLAN valid */
uint32_t pfvf_vld:1; /* PF/VF valid */
- uint32_t encap_vld:1; /* Encapsulation valid */
+ uint32_t encap_vld:1; /* Encapsulation valid */
uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
uint32_t iport:IPORT_BITWIDTH; /* ingress port */
@@ -1352,7 +1416,8 @@ struct ch_filter_tuple {
uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
- uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */
+ uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */
+ uint32_t synonly:SYNONLY_BITWIDTH; /* SYN packet match only */
/* Uncompressed header matching field rules. These are always
* available for field rules.
@@ -1364,10 +1429,10 @@ struct ch_filter_tuple {
};
/* A filter ioctl command.
- */
+*/
struct ch_filter_specification {
/* Administrative fields for filter.
- */
+ */
uint32_t hitcnts:1; /* count filter hits in TCB */
uint32_t prio:1; /* filter has priority over active/server */
@@ -1375,7 +1440,7 @@ struct ch_filter_specification {
* matching that doesn't exist as a (value, mask) tuple.
*/
uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
- u32 hash:1; /* 0 => wild-card, 1 => exact-match */
+ u32 hash:1; /* 0 => wild-card, 1 => exact-match */
/* Packet dispatch information. Ingress packets which match the
* filter rules will be dropped, passed to the host or switched back
@@ -1390,7 +1455,7 @@ struct ch_filter_specification {
uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
- /* 1 => TCB contains IQ ID */
+ /* 1 => TCB contains IQ ID */
/* Switch proxy/rewrite fields. An ingress packet which matches a
* filter with "switch" set will be looped back out as an egress
@@ -1405,19 +1470,19 @@ struct ch_filter_specification {
uint8_t smac[ETH_ALEN]; /* new source MAC address */
uint16_t vlan; /* VLAN Tag to insert */
- u8 nat_lip[16]; /* local IP to use after NAT'ing */
- u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
- u16 nat_lport; /* local port to use after NAT'ing */
- u16 nat_fport; /* foreign port to use after NAT'ing */
+ u8 nat_lip[16]; /* local IP to use after NAT'ing */
+ u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
+ u16 nat_lport; /* local port to use after NAT'ing */
+ u16 nat_fport; /* foreign port to use after NAT'ing */
- u32 tc_prio; /* TC's filter priority index */
- u64 tc_cookie; /* Unique cookie identifying TC rules */
+ u32 tc_prio; /* TC's filter priority index */
+ u64 tc_cookie; /* Unique cookie identifying TC rules */
/* reservation for future additions */
u8 rsvd[12];
/* Filter rule value/mask pairs.
- */
+ */
struct ch_filter_tuple val;
struct ch_filter_tuple mask;
};
@@ -1582,6 +1647,15 @@ static inline struct adapter *netdev2adap(const struct net_device *dev)
return netdev2pinfo(dev)->adapter;
}
+/**
+ * t4_os_lock_init - initialize spinlock
+ * @lock: the spinlock
+ */
+static inline void t4_os_lock_init(spinlock_t *lock)
+{
+ spin_lock_init(lock);
+}
+
/* Return a version number to identify the type of adapter. The scheme is:
* - bits 0..9: chip version
* - bits 10..15: chip revision
@@ -1608,6 +1682,11 @@ extern char cxgb4_driver_name[];
void t4_os_portmod_changed(struct adapter *adap, int port_id);
void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
+void cxgb4_work_queue(struct workqueue_struct *workq, struct work_struct *work);
+void cxgb4_work_cancel(struct workqueue_struct *workq, struct work_struct *work);
+bool cxgb4_msix_enabled(struct adapter *adap);
+bool cxgb4_msi_enabled(struct adapter *adap);
+struct net_device *cxgb4_port_chan_to_netdev(struct adapter *adap, u8 chan);
void t4_free_sge_resources(struct adapter *adap);
irq_handler_t t4_intr_handler(struct adapter *adap);
netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
@@ -1622,10 +1701,10 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
rspq_flush_handler_t flush_handler, int cong);
int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
struct net_device *dev, struct netdev_queue *netdevq,
- unsigned int iqid, u8 dbqt);
+ unsigned int iqid, u8 dbqt, int index);
int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
struct net_device *dev, unsigned int iqid,
- unsigned int cmplqid);
+ unsigned int cmplqid, int index);
int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
unsigned int cmplqid);
int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
@@ -1731,6 +1810,10 @@ static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
}
+unsigned int t4_pcie_mem_access_base_win_reg(struct adapter *adap, int win);
+unsigned int t4_pcie_mem_access_offset_reg(struct adapter *adap, int win);
+void t4_pcie_mem_access_offset_write(struct adapter *adap, u32 off, int win,
+ u32 pf);
/**
* hash_mac_addr - return the hash value of a MAC address
* @addr: the 48-bit Ethernet MAC address
@@ -1784,6 +1867,9 @@ void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
unsigned int start_idx);
void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
+void t4_record_mbox(struct adapter *adapter, const __be64 *cmd,
+ unsigned int size, int access, int execute);
+
struct fw_filter_wr;
void t4_intr_enable(struct adapter *adapter);
@@ -1866,6 +1952,7 @@ void t4_dump_version_info(struct adapter *adapter);
int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
const u8 *fw_data, unsigned int fw_size,
struct fw_hdr *card_fw, enum dev_state state, int *reset);
+enum chip_type t4_get_chip_type(struct adapter *adap, int ver);
int t4_prep_adapter(struct adapter *adapter);
int t4_shutdown_adapter(struct adapter *adapter);
@@ -1881,6 +1968,7 @@ unsigned int qtimer_val(const struct adapter *adap,
const struct sge_rspq *q);
int t4_init_devlog_params(struct adapter *adapter);
+unsigned int t4_sge_get_qpp(struct adapter *adap, unsigned int qtype);
int t4_init_sge_params(struct adapter *adapter);
int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
@@ -1909,24 +1997,41 @@ void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
+u8 t4_get_tp_port_chan(struct adapter *adap, u8 pidx);
unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
+void t4_pmrx_cache_get_stats(struct adapter *adap, u32 stats[]);
+u8 t4_cim_num_ibq(struct adapter *adap);
+u8 t4_cim_num_obq(struct adapter *adap);
+void t4_read_cimq_cfg_core(struct adapter *adap, u8 coreid, u16 *base,
+ u16 *size, u16 *thres);
int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
size_t n);
+int t4_read_cim_obq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+ size_t n);
int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
size_t n);
+int t4_cim_read_core(struct adapter *adap, u8 group, u8 coreid,
+ unsigned int addr, unsigned int n, unsigned int *valp);
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
unsigned int *valp);
+int t4_cim_write_core(struct adapter *adap, u8 group, u8 coreid,
+ unsigned int addr, unsigned int n,
+ const unsigned int *valp);
int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
const unsigned int *valp);
+int t4_cim_read_la_core(struct adapter *adap, u8 coreid, u32 *la_buf,
+ u32 *wrptr);
int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
unsigned int *pif_req_wrptr,
unsigned int *pif_rsp_wrptr);
void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
+int t4_read_cim_ibq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+ size_t n);
const char *t4_get_port_type_description(enum fw_port_type port_type);
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
void t4_get_port_stats_offset(struct adapter *adap, int idx,
@@ -2016,6 +2121,21 @@ int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
const u8 **addr, bool sleep_ok);
int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
int idx, const u8 *addr, bool persist, u8 *smt_idx);
+int cxgb4_is_primary_pf(struct adapter *adapter);
+struct adapter *cxgb4_adap_alloc(struct device *dev);
+int cxgb4_mbox_log_init(struct adapter *adap);
+void cxgb4_mbox_log_free(struct adapter *adap);
+
+pci_ers_result_t cxgb4_pci_eeh_err_detected(struct pci_dev *pdev,
+ pci_channel_state_t state);
+pci_ers_result_t cxgb4_pci_eeh_slot_reset(struct pci_dev *pdev);
+void cxgb4_pci_eeh_resume(struct pci_dev *pdev);
+void cxgb4_pci_eeh_reset_prepare(struct pci_dev *pdev);
+void cxgb4_pci_eeh_reset_done(struct pci_dev *pdev);
+int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs);
+int cxgb4_adap_probe(struct adapter *adapter);
+void cxgb4_adap_remove(struct adapter *adapter);
+void cxgb4_adap_shutdown(struct adapter *adapter);
int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
bool ucast, u64 vec, bool sleep_ok);
int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
@@ -2057,6 +2177,7 @@ int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
int filter_index, int enable);
void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
int filter_index, int *enabled);
+void t4_set_trace_rss_control(struct adapter *adap, u8 chan, u16 qid);
int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
u32 addr, u32 val);
void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
@@ -2121,6 +2242,12 @@ void cxgb4_write_partial_sgl(const struct sk_buff *skb, struct sge_txq *q,
void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
u16 vlan);
+
+/* Flash Layout helpers */
+int t4_flash_location_start_sec(struct adapter *adap, enum t4_flash_loc loc);
+int t4_flash_location_nsecs(struct adapter *adap, enum t4_flash_loc loc);
+int t4_flash_location_start(struct adapter *adap, enum t4_flash_loc loc);
+int t4_flash_location_size(struct adapter *adap, enum t4_flash_loc loc);
int cxgb4_dcb_enabled(const struct net_device *dev);
int cxgb4_thermal_init(struct adapter *adap);
@@ -2141,6 +2268,12 @@ int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
unsigned int naddr, const u8 **addr, bool sleep_ok);
int cxgb4_init_mps_ref_entries(struct adapter *adap);
void cxgb4_free_mps_ref_entries(struct adapter *adap);
+int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
+ const u8 *addr, const u8 *mask,
+ unsigned int vni, unsigned int vni_mask,
+ u8 dip_hit, u8 lookup_type, bool sleep_ok);
+int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
+ int idx, bool sleep_ok);
int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
int *tcam_idx, const u8 *addr,
bool persistent, u8 *smt_idx);
@@ -2153,4 +2286,5 @@ void cxgb4_port_mirror_free(struct net_device *dev);
#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
int cxgb4_set_ktls_feature(struct adapter *adap, bool enable);
#endif
+bool cxgb4_pcie_relaxed_ordering_enabled(struct adapter *adap);
#endif /* __CXGB4_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index 695916ba0405..535854b18188 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -45,6 +45,7 @@
#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
+#define NUM_UP_TSCH_CHANNEL_INSTANCES 4
#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
@@ -66,6 +67,8 @@
#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define T7_PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+
#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
@@ -109,9 +112,10 @@
#define CIDXINC_M 0xfffU
#define CIDXINC_V(x) ((x) << CIDXINC_S)
-#define SGE_CONTROL_A 0x1008
#define SGE_CONTROL2_A 0x1124
+#define SGE_CONTROL_A 0x1008
+
#define RXPKTCPLMODE_S 18
#define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)
#define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U)
@@ -172,6 +176,7 @@
#define SGE_CTXT_DATA0_A 0x1200
#define SGE_CTXT_DATA5_A 0x1214
+#define SGE_CTXT_DATA6_A 0x1218
#define GLOBALENABLE_S 0
#define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
@@ -232,6 +237,11 @@
#define SGE_INT_CAUSE1_A 0x1024
#define SGE_INT_CAUSE2_A 0x1030
#define SGE_INT_CAUSE3_A 0x103c
+#define SGE_INT_CAUSE4_A 0x10dc
+#define SGE_INT_CAUSE5_A 0x110c
+#define SGE_INT_CAUSE6_A 0x1128
+#define SGE_INT_CAUSE7_A 0x1360
+#define SGE_INT_CAUSE8_A 0x11c8
#define ERR_FLM_DBP_S 31
#define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S)
@@ -265,6 +275,10 @@
#define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S)
#define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U)
+#define ERR_TIMER_ABOVE_MAX_QID_S 23
+#define ERR_TIMER_ABOVE_MAX_QID_V(x) ((x) << ERR_TIMER_ABOVE_MAX_QID_S)
+#define ERR_TIMER_ABOVE_MAX_QID_F ERR_TIMER_ABOVE_MAX_QID_V(1U)
+
#define ERR_CPL_EXCEED_IQE_SIZE_S 22
#define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S)
#define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U)
@@ -273,6 +287,10 @@
#define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S)
#define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U)
+#define ERR_ITP_TIME_PAUSED_S 20
+#define ERR_ITP_TIME_PAUSED_V(x) ((x) << ERR_ITP_TIME_PAUSED_S)
+#define ERR_ITP_TIME_PAUSED_F ERR_ITP_TIME_PAUSED_V(1U)
+
#define ERR_CPL_OPCODE_0_S 19
#define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S)
#define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U)
@@ -305,6 +323,10 @@
#define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S)
#define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U)
+#define ERR_ING_PCIE_CHAN_S 11
+#define ERR_ING_PCIE_CHAN_V(x) ((x) << ERR_ING_PCIE_CHAN_S)
+#define ERR_ING_PCIE_CHAN_F ERR_ING_PCIE_CHAN_V(1U)
+
#define ERR_ING_CTXT_PRIO_S 10
#define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S)
#define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U)
@@ -321,6 +343,10 @@
#define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S)
#define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U)
+#define REG_ADDRESS_ERR_S 6
+#define REG_ADDRESS_ERR_V(x) ((x) << REG_ADDRESS_ERR_S)
+#define REG_ADDRESS_ERR_F REG_ADDRESS_ERR_V(1U)
+
#define INGRESS_SIZE_ERR_S 5
#define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S)
#define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U)
@@ -329,6 +355,14 @@
#define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)
#define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U)
+#define DBP_TBUF_FULL_S 8
+#define DBP_TBUF_FULL_V(x) ((x) << DBP_TBUF_FULL_S)
+#define DBP_TBUF_FULL_F DBP_TBUF_FULL_V(1U)
+
+#define FATAL_WRE_LEN_S 7
+#define FATAL_WRE_LEN_V(x) ((x) << FATAL_WRE_LEN_S)
+#define FATAL_WRE_LEN_F FATAL_WRE_LEN_V(1U)
+
#define SGE_INT_ENABLE3_A 0x1040
#define SGE_FL_BUFFER_SIZE0_A 0x1044
#define SGE_FL_BUFFER_SIZE1_A 0x1048
@@ -406,6 +440,7 @@
#define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)
#define SGE_DBFIFO_STATUS_A 0x10a4
+
#define SGE_DBVFIFO_SIZE_A 0x113c
#define HP_INT_THRESH_S 28
@@ -761,6 +796,7 @@
#define PCIE_NONFAT_ERR_A 0x3010
#define PCIE_CFG_SPACE_REQ_A 0x3060
+
#define PCIE_CFG_SPACE_DATA_A 0x3064
#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
@@ -884,6 +920,9 @@
#define TDUE_V(x) ((x) << TDUE_S)
#define TDUE_F TDUE_V(1U)
+#define PCIE_MEM_ACCESS_OFFSET0_A 0x3708
+#define T7_PCIE_MEM_ACCESS_BASE_WIN_A 0x3700
+
/* SPARE2 register contains 32-bit value at offset 0x6 in Serial INIT
* Configuration flashed on EEPROM. This value corresponds to 32-bit
* Serial Configuration Version information.
@@ -944,6 +983,8 @@
#define MC_BIST_DATA_PATTERN_A 0x760c
#define MC_BIST_STATUS_RDATA_A 0x7688
+#define T7_MC_P_INT_CAUSE_A 0x49320
+#define T7_MC_P_ECC_STATUS_A 0x4932c
/* registers for module MA */
#define MA_EDRAM0_BAR_A 0x77c0
@@ -957,6 +998,11 @@
#define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
#define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
+#define T7_EDRAM0_SIZE_S 0
+#define T7_EDRAM0_SIZE_M 0xffffU
+#define T7_EDRAM0_SIZE_V(x) ((x) << T7_EDRAM0_SIZE_S)
+#define T7_EDRAM0_SIZE_G(x) (((x) >> T7_EDRAM0_SIZE_S) & T7_EDRAM0_SIZE_M)
+
#define MA_EDRAM1_BAR_A 0x77c4
#define EDRAM1_BASE_S 16
@@ -968,6 +1014,11 @@
#define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
#define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
+#define T7_EDRAM1_SIZE_S 0
+#define T7_EDRAM1_SIZE_M 0xffffU
+#define T7_EDRAM1_SIZE_V(x) ((x) << T7_EDRAM1_SIZE_S)
+#define T7_EDRAM1_SIZE_G(x) (((x) >> T7_EDRAM1_SIZE_S) & T7_EDRAM1_SIZE_M)
+
#define MA_EXT_MEMORY_BAR_A 0x77c8
#define EXT_MEM_BASE_S 16
@@ -995,6 +1046,18 @@
#define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
#define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
+#define T7_EXT_MEM1_SIZE_S 0
+#define T7_EXT_MEM1_SIZE_M 0xffffU
+#define T7_EXT_MEM1_SIZE_V(x) ((x) << T7_EXT_MEM1_SIZE_S)
+#define T7_EXT_MEM1_SIZE_G(x) (((x) >> T7_EXT_MEM1_SIZE_S) & T7_EXT_MEM1_SIZE_M)
+
+#define MA_HOST_MEMORY_BAR_A 0x77cc
+
+#define T7_HMA_SIZE_S 0
+#define T7_HMA_SIZE_M 0xffffU
+#define T7_HMA_SIZE_V(x) ((x) << T7_HMA_SIZE_S)
+#define T7_HMA_SIZE_G(x) (((x) >> T7_HMA_SIZE_S) & T7_HMA_SIZE_M)
+
#define MA_EXT_MEMORY0_BAR_A 0x77c8
#define EXT_MEM0_BASE_S 16
@@ -1006,6 +1069,11 @@
#define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
#define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
+#define T7_EXT_MEM0_SIZE_S 0
+#define T7_EXT_MEM0_SIZE_M 0xffffU
+#define T7_EXT_MEM0_SIZE_V(x) ((x) << T7_EXT_MEM0_SIZE_S)
+#define T7_EXT_MEM0_SIZE_G(x) (((x) >> T7_EXT_MEM0_SIZE_S) & T7_EXT_MEM0_SIZE_M)
+
#define MA_TARGET_MEM_ENABLE_A 0x77d8
#define EXT_MEM_ENABLE_S 2
@@ -1028,6 +1096,10 @@
#define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
#define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
+#define MC_SPLIT_S 6
+#define MC_SPLIT_V(x) ((x) << MC_SPLIT_S)
+#define MC_SPLIT_F MC_SPLIT_V(1U)
+
#define MA_INT_CAUSE_A 0x77e0
#define MEM_PERR_INT_CAUSE_S 1
@@ -1053,6 +1125,9 @@
#define MA_PARITY_ERROR_STATUS1_A 0x77f4
#define MA_PARITY_ERROR_STATUS2_A 0x7804
+#define MA_LOCAL_DEBUG_CFG_A 0x78f8
+#define MA_LOCAL_DEBUG_PERF_CFG_A 0x7914
+
/* registers for module EDC_0 */
#define EDC_0_BASE_ADDR 0x7900
@@ -1633,6 +1708,62 @@
#define FCOEMASK_V(x) ((x) << FCOEMASK_S)
#define FCOEMASK_F FCOEMASK_V(1U)
+#define TCPFLAGS_S 13
+#define TCPFLAGS_V(x) ((x) << TCPFLAGS_S)
+#define TCPFLAGS_F TCPFLAGS_V(1U)
+
+#define SYNONLY_S 12
+#define SYNONLY_V(x) ((x) << SYNONLY_S)
+#define SYNONLY_F SYNONLY_V(1U)
+
+#define ROCE_S 11
+#define ROCE_V(x) ((x) << ROCE_S)
+#define ROCE_F ROCE_V(1U)
+
+#define T7_FRAGMENTATION_S 10
+#define T7_FRAGMENTATION_V(x) ((x) << T7_FRAGMENTATION_S)
+#define T7_FRAGMENTATION_F T7_FRAGMENTATION_V(1U)
+
+#define T7_MPSHITTYPE_S 9
+#define T7_MPSHITTYPE_V(x) ((x) << T7_MPSHITTYPE_S)
+#define T7_MPSHITTYPE_F T7_MPSHITTYPE_V(1U)
+
+#define T7_MACMATCH_S 8
+#define T7_MACMATCH_V(x) ((x) << T7_MACMATCH_S)
+#define T7_MACMATCH_F T7_MACMATCH_V(1U)
+
+#define T7_ETHERTYPE_S 7
+#define T7_ETHERTYPE_V(x) ((x) << T7_ETHERTYPE_S)
+#define T7_ETHERTYPE_F T7_ETHERTYPE_V(1U)
+
+#define T7_PROTOCOL_S 6
+#define T7_PROTOCOL_V(x) ((x) << T7_PROTOCOL_S)
+#define T7_PROTOCOL_F T7_PROTOCOL_V(1U)
+
+#define T7_TOS_S 5
+#define T7_TOS_V(x) ((x) << T7_TOS_S)
+#define T7_TOS_F T7_TOS_V(1U)
+
+#define T7_VLAN_S 4
+#define T7_VLAN_V(x) ((x) << T7_VLAN_S)
+#define T7_VLAN_F T7_VLAN_V(1U)
+
+#define T7_VNIC_ID_S 3
+#define T7_VNIC_ID_V(x) ((x) << T7_VNIC_ID_S)
+#define T7_VNIC_ID_F T7_VNIC_ID_V(1U)
+
+#define T7_PORT_S 2
+#define T7_PORT_V(x) ((x) << T7_PORT_S)
+#define T7_PORT_F T7_PORT_V(1U)
+
+#define T7_FCOE_S 1
+#define T7_FCOE_V(x) ((x) << T7_FCOE_S)
+#define T7_FCOE_F T7_FCOE_V(1U)
+
+#define IPSECIDX_S 0
+#define IPSECIDX_V(x) ((x) << IPSECIDX_S)
+#define IPSECIDX_F IPSECIDX_V(1U)
+
#define TP_INGRESS_CONFIG_A 0x141
#define VNIC_S 11
@@ -1670,6 +1801,13 @@
#define TP_MIB_FCOE_BYTE_0_HI_A 0x50
#define TP_MIB_OFD_VLN_DROP_0_A 0x58
#define TP_MIB_USM_PKTS_A 0x5c
+#define TP_CHANNEL_MAP_A 0x27
+
+#define T7_LB_MODE_S 30
+#define T7_LB_MODE_M 0x3U
+#define T7_LB_MODE_V(x) ((x) << T7_LB_MODE_S)
+#define T7_LB_MODE_G(x) (((x) >> T7_LB_MODE_S) & T7_LB_MODE_M)
+
#define TP_MIB_RQE_DFR_PKT_A 0x64
#define ULP_TX_INT_CAUSE_A 0x8dcc
@@ -1745,6 +1883,7 @@
#define PM_TX_STAT_LSB_A 0x8ff0
#define PM_TX_DBG_CTRL_A 0x8ff0
#define PM_TX_DBG_DATA_A 0x8ff4
+#define T7_PM_TX_DBG_STAT_MSB_A 0x10000
#define PM_TX_DBG_STAT_MSB_A 0x1001a
#define PCMD_LEN_OVFL0_S 31
@@ -1907,6 +2046,7 @@
#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
#define MAC_PORT_MAGIC_MACID_LO 0x824
#define MAC_PORT_MAGIC_MACID_HI 0x828
+#define T7_MAC_PORT_TX_TS_VAL_LO 0x88c
#define MAC_PORT_TX_TS_VAL_LO 0x928
#define MAC_PORT_TX_TS_VAL_HI 0x92c
@@ -2084,6 +2224,9 @@
#define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
#define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
+#define T7_MPS_TRC_FILTER_MATCH_CTL_A_A 0xa460
+#define T7_MPS_TRC_FILTER_MATCH_CTL_B_A 0xa480
+#define T7_MPS_T5_TRC_RSS_CONTROL_A 0xa434
#define TFMINPKTSIZE_S 16
#define TFMINPKTSIZE_M 0x1ffU
@@ -2446,6 +2589,7 @@
#define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)
#define TP_RSS_CONFIG_CNG_A 0x7e04
+#define TP_RSS_CONFIG_SRAM_A 0x7e0c
#define TP_RSS_SECRET_KEY0_A 0x40
#define TP_RSS_PF0_CONFIG_A 0x30
#define TP_RSS_PF_MAP_A 0x38
@@ -2591,6 +2735,9 @@
#define GENEVE_V(x) ((x) << GENEVE_S)
#define GENEVE_G(x) (((x) >> GENEVE_S) & GENEVE_M)
+#define T7_MPS_TRC_INT_CAUSE_A 0xa4e4
+#define T7_MPS_RX_VXLAN_TYPE_A 0x1123c
+#define T7_MPS_RX_GENEVE_TYPE_A 0x11240
#define MPS_CLS_TCAM_Y_L_A 0xf000
#define MPS_CLS_TCAM_DATA0_A 0xf000
#define MPS_CLS_TCAM_DATA1_A 0xf004
@@ -2637,6 +2784,9 @@
#define DATAVIDH1_M 0x7fU
#define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)
+#define MPS_CLS_TCAM0_RDATA0_REQ_ID1_A 0xf01c
+#define MPS_CLS_TCAM0_RDATA1_REQ_ID1_A 0xf020
+#define MPS_CLS_TCAM0_RDATA2_REQ_ID1_A 0xf024
#define MPS_CLS_TCAM_RDATA0_REQ_ID1_A 0xf020
#define MPS_CLS_TCAM_RDATA1_REQ_ID1_A 0xf024
#define MPS_CLS_TCAM_RDATA2_REQ_ID1_A 0xf028
@@ -2683,6 +2833,16 @@
#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
+#define T7_CTLTCAMSEL_S 26
+#define T7_CTLTCAMSEL_M 0x3U
+#define T7_CTLTCAMSEL_V(x) ((x) << T7_CTLTCAMSEL_S)
+#define T7_CTLTCAMSEL_G(x) (((x) >> T7_CTLTCAMSEL_S) & T7_CTLTCAMSEL_M)
+
+#define T7_1_CTLTCAMINDEX_S 17
+#define T7_1_CTLTCAMINDEX_M 0x1ffU
+#define T7_1_CTLTCAMINDEX_V(x) ((x) << T7_1_CTLTCAMINDEX_S)
+#define T7_1_CTLTCAMINDEX_G(x) (((x) >> T7_1_CTLTCAMINDEX_S) & T7_1_CTLTCAMINDEX_M)
+
#define MPS_CLS_SRAM_L_A 0xe000
#define T6_MULTILISTEN0_S 26
@@ -2850,6 +3010,21 @@
#define ULP_RX_TDDP_PSZ_A 0x19178
+#define MPS_CLS_TCAM0_RDATA1_REQ_ID1_A 0xf020
+#define MPS_CLS_TCAM0_RDATA0_REQ_ID1_A 0xf01c
+#define MPS_CLS_TCAM0_RDATA2_REQ_ID1_A 0xf024
+#define MPS_T5_CLS_SRAM_L_A 0xe000
+#define MPS_T5_CLS_SRAM_H_A 0xe004
+
+#define SRAMWRN_S 31
+#define SRAMWRN_V(x) ((x) << SRAMWRN_S)
+#define SRAMWRN_F SRAMWRN_V(1U)
+
+#define SRAMINDEX_S 16
+#define SRAMINDEX_M 0x7ffU
+#define SRAMINDEX_V(x) ((x) << SRAMINDEX_S)
+#define SRAMINDEX_G(x) (((x) >> SRAMINDEX_S) & SRAMINDEX_M)
+
/* registers for module SF */
#define SF_DATA_A 0x193f8
#define SF_OP_A 0x193fc
@@ -2873,6 +3048,10 @@
#define OP_V(x) ((x) << OP_S)
#define OP_F OP_V(1U)
+#define QUADREADDISABLE_S 5
+#define QUADREADDISABLE_V(x) ((x) << QUADREADDISABLE_S)
+#define QUADREADDISABLE_F QUADREADDISABLE_V(1U)
+
#define PL_PF_INT_CAUSE_A 0x3c0
#define PFSW_S 3
@@ -2926,6 +3105,50 @@
#define MA_V(x) ((x) << MA_S)
#define MA_F MA_V(1U)
+#define T7_ULP_TX_S 29
+#define T7_ULP_TX_V(x) ((x) << T7_ULP_TX_S)
+#define T7_ULP_TX_F T7_ULP_TX_V(1U)
+
+#define T7_SGE_S 28
+#define T7_SGE_V(x) ((x) << T7_SGE_S)
+#define T7_SGE_F T7_SGE_V(1U)
+
+#define T7_CPL_SWITCH_S 26
+#define T7_CPL_SWITCH_V(x) ((x) << T7_CPL_SWITCH_S)
+#define T7_CPL_SWITCH_F T7_CPL_SWITCH_V(1U)
+
+#define T7_ULP_RX_S 25
+#define T7_ULP_RX_V(x) ((x) << T7_ULP_RX_S)
+#define T7_ULP_RX_F T7_ULP_RX_V(1U)
+
+#define T7_PM_RX_S 24
+#define T7_PM_RX_V(x) ((x) << T7_PM_RX_S)
+#define T7_PM_RX_F T7_PM_RX_V(1U)
+
+#define T7_PM_TX_S 23
+#define T7_PM_TX_V(x) ((x) << T7_PM_TX_S)
+#define T7_PM_TX_F T7_PM_TX_V(1U)
+
+#define T7_MA_S 22
+#define T7_MA_V(x) ((x) << T7_MA_S)
+#define T7_MA_F T7_MA_V(1U)
+
+#define T7_TP_S 21
+#define T7_TP_V(x) ((x) << T7_TP_S)
+#define T7_TP_F T7_TP_V(1U)
+
+#define T7_LE_S 20
+#define T7_LE_V(x) ((x) << T7_LE_S)
+#define T7_LE_F T7_LE_V(1U)
+
+#define T7_EDC1_S 19
+#define T7_EDC1_V(x) ((x) << T7_EDC1_S)
+#define T7_EDC1_F T7_EDC1_V(1U)
+
+#define T7_EDC0_S 18
+#define T7_EDC0_V(x) ((x) << T7_EDC0_S)
+#define T7_EDC0_F T7_EDC0_V(1U)
+
#define TP_S 19
#define TP_V(x) ((x) << TP_S)
#define TP_F TP_V(1U)
@@ -2950,6 +3173,10 @@
#define PCIE_V(x) ((x) << PCIE_S)
#define PCIE_F PCIE_V(1U)
+#define T7_PCIE_S 15
+#define T7_PCIE_V(x) ((x) << T7_PCIE_S)
+#define T7_PCIE_F T7_PCIE_V(1U)
+
#define XGMAC_KR1_S 12
#define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
#define XGMAC_KR1_F XGMAC_KR1_V(1U)
@@ -2995,6 +3222,15 @@
#define MC1_F MC1_V(1U)
#define PL_INT_ENABLE_A 0x19410
+
+#define T7_MC1_S 17
+#define T7_MC1_V(x) ((x) << T7_MC1_S)
+#define T7_MC1_F T7_MC1_V(1U)
+
+#define T7_MC0_S 16
+#define T7_MC0_V(x) ((x) << T7_MC0_S)
+#define T7_MC0_F T7_MC0_V(1U)
+
#define PL_INT_MAP0_A 0x19414
#define PL_RST_A 0x19428
@@ -3012,6 +3248,10 @@
#define FATALPERR_V(x) ((x) << FATALPERR_S)
#define FATALPERR_F FATALPERR_V(1U)
+#define INVALIDACCESS_S 3
+#define INVALIDACCESS_V(x) ((x) << INVALIDACCESS_S)
+#define INVALIDACCESS_F INVALIDACCESS_V(1U)
+
#define PERRVFID_S 0
#define PERRVFID_V(x) ((x) << PERRVFID_S)
#define PERRVFID_F PERRVFID_V(1U)
@@ -3027,22 +3267,6 @@
#define HASHTBLMEMCRCERR_V(x) ((x) << HASHTBLMEMCRCERR_S)
#define HASHTBLMEMCRCERR_F HASHTBLMEMCRCERR_V(1U)
-#define CMDTIDERR_S 22
-#define CMDTIDERR_V(x) ((x) << CMDTIDERR_S)
-#define CMDTIDERR_F CMDTIDERR_V(1U)
-
-#define T6_UNKNOWNCMD_S 3
-#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
-#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)
-
-#define T6_LIP0_S 2
-#define T6_LIP0_V(x) ((x) << T6_LIP0_S)
-#define T6_LIP0_F T6_LIP0_V(1U)
-
-#define T6_LIPMISS_S 1
-#define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
-#define T6_LIPMISS_F T6_LIPMISS_V(1U)
-
#define LE_DB_CONFIG_A 0x19c04
#define LE_DB_ROUTING_TABLE_INDEX_A 0x19c10
#define LE_DB_ACTIVE_TABLE_START_INDEX_A 0x19c10
@@ -3069,6 +3293,134 @@
#define LE_DB_TID_HASHBASE_A 0x19df8
#define T6_LE_DB_HASH_TID_BASE_A 0x19df8
+#define CACHEINTPERR_S 31
+#define CACHEINTPERR_V(x) ((x) << CACHEINTPERR_S)
+#define CACHEINTPERR_F CACHEINTPERR_V(1U)
+
+#define CACHESRAMPERR_S 30
+#define CACHESRAMPERR_V(x) ((x) << CACHESRAMPERR_S)
+#define CACHESRAMPERR_F CACHESRAMPERR_V(1U)
+
+#define CLIPSUBERR_S 29
+#define CLIPSUBERR_V(x) ((x) << CLIPSUBERR_S)
+#define CLIPSUBERR_F CLIPSUBERR_V(1U)
+
+#define CLCAMFIFOERR_S 28
+#define CLCAMFIFOERR_V(x) ((x) << CLCAMFIFOERR_S)
+#define CLCAMFIFOERR_F CLCAMFIFOERR_V(1U)
+
+#define HASHTBLMEMCRCERR_S 27
+#define HASHTBLMEMCRCERR_V(x) ((x) << HASHTBLMEMCRCERR_S)
+#define HASHTBLMEMCRCERR_F HASHTBLMEMCRCERR_V(1U)
+
+#define CTCAMINVLDENT_S 26
+#define CTCAMINVLDENT_V(x) ((x) << CTCAMINVLDENT_S)
+#define CTCAMINVLDENT_F CTCAMINVLDENT_V(1U)
+
+#define TCAMINVLDENT_S 25
+#define TCAMINVLDENT_V(x) ((x) << TCAMINVLDENT_S)
+#define TCAMINVLDENT_F TCAMINVLDENT_V(1U)
+
+#define TOTCNTERR_S 24
+#define TOTCNTERR_V(x) ((x) << TOTCNTERR_S)
+#define TOTCNTERR_F TOTCNTERR_V(1U)
+
+#define CMDPRSRINTERR_S 23
+#define CMDPRSRINTERR_V(x) ((x) << CMDPRSRINTERR_S)
+#define CMDPRSRINTERR_F CMDPRSRINTERR_V(1U)
+
+#define CMDTIDERR_S 22
+#define CMDTIDERR_V(x) ((x) << CMDTIDERR_S)
+#define CMDTIDERR_F CMDTIDERR_V(1U)
+
+#define T6_ACTRGNFULL_S 21
+#define T6_ACTRGNFULL_V(x) ((x) << T6_ACTRGNFULL_S)
+#define T6_ACTRGNFULL_F T6_ACTRGNFULL_V(1U)
+
+#define T6_ACTCNTIPV6TZERO_S 20
+#define T6_ACTCNTIPV6TZERO_V(x) ((x) << T6_ACTCNTIPV6TZERO_S)
+#define T6_ACTCNTIPV6TZERO_F T6_ACTCNTIPV6TZERO_V(1U)
+
+#define T6_ACTCNTIPV4TZERO_S 19
+#define T6_ACTCNTIPV4TZERO_V(x) ((x) << T6_ACTCNTIPV4TZERO_S)
+#define T6_ACTCNTIPV4TZERO_F T6_ACTCNTIPV4TZERO_V(1U)
+
+#define T6_ACTCNTIPV6ZERO_S 18
+#define T6_ACTCNTIPV6ZERO_V(x) ((x) << T6_ACTCNTIPV6ZERO_S)
+#define T6_ACTCNTIPV6ZERO_F T6_ACTCNTIPV6ZERO_V(1U)
+
+#define T6_ACTCNTIPV4ZERO_S 17
+#define T6_ACTCNTIPV4ZERO_V(x) ((x) << T6_ACTCNTIPV4ZERO_S)
+#define T6_ACTCNTIPV4ZERO_F T6_ACTCNTIPV4ZERO_V(1U)
+
+#define MAIFWRINTPERR_S 16
+#define MAIFWRINTPERR_V(x) ((x) << MAIFWRINTPERR_S)
+#define MAIFWRINTPERR_F MAIFWRINTPERR_V(1U)
+
+#define HASHTBLMEMACCERR_S 15
+#define HASHTBLMEMACCERR_V(x) ((x) << HASHTBLMEMACCERR_S)
+#define HASHTBLMEMACCERR_F HASHTBLMEMACCERR_V(1U)
+
+#define TCAMCRCERR_S 14
+#define TCAMCRCERR_V(x) ((x) << TCAMCRCERR_S)
+#define TCAMCRCERR_F TCAMCRCERR_V(1U)
+
+#define TCAMINTPERR_S 13
+#define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)
+#define TCAMINTPERR_F TCAMINTPERR_V(1U)
+
+#define VFSRAMPERR_S 12
+#define VFSRAMPERR_V(x) ((x) << VFSRAMPERR_S)
+#define VFSRAMPERR_F VFSRAMPERR_V(1U)
+
+#define SRVSRAMPERR_S 11
+#define SRVSRAMPERR_V(x) ((x) << SRVSRAMPERR_S)
+#define SRVSRAMPERR_F SRVSRAMPERR_V(1U)
+
+#define SSRAMINTPERR_S 10
+#define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
+#define SSRAMINTPERR_F SSRAMINTPERR_V(1U)
+
+#define CLCAMINTPERR_S 9
+#define CLCAMINTPERR_V(x) ((x) << CLCAMINTPERR_S)
+#define CLCAMINTPERR_F CLCAMINTPERR_V(1U)
+
+#define CLCAMCRCPARERR_S 8
+#define CLCAMCRCPARERR_V(x) ((x) << CLCAMCRCPARERR_S)
+#define CLCAMCRCPARERR_F CLCAMCRCPARERR_V(1U)
+
+#define HASHTBLACCFAIL_S 7
+#define HASHTBLACCFAIL_V(x) ((x) << HASHTBLACCFAIL_S)
+#define HASHTBLACCFAIL_F HASHTBLACCFAIL_V(1U)
+
+#define TCAMACCFAIL_S 6
+#define TCAMACCFAIL_V(x) ((x) << TCAMACCFAIL_S)
+#define TCAMACCFAIL_F TCAMACCFAIL_V(1U)
+
+#define SRVSRAMACCFAIL_S 5
+#define SRVSRAMACCFAIL_V(x) ((x) << SRVSRAMACCFAIL_S)
+#define SRVSRAMACCFAIL_F SRVSRAMACCFAIL_V(1U)
+
+#define CLIPTCAMACCFAIL_S 4
+#define CLIPTCAMACCFAIL_V(x) ((x) << CLIPTCAMACCFAIL_S)
+#define CLIPTCAMACCFAIL_F CLIPTCAMACCFAIL_V(1U)
+
+#define T6_UNKNOWNCMD_S 3
+#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
+#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)
+
+#define T6_LIP0_S 2
+#define T6_LIP0_V(x) ((x) << T6_LIP0_S)
+#define T6_LIP0_F T6_LIP0_V(1U)
+
+#define T6_LIPMISS_S 1
+#define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
+#define T6_LIPMISS_F T6_LIPMISS_V(1U)
+
+#define PIPELINEERR_S 0
+#define PIPELINEERR_V(x) ((x) << PIPELINEERR_S)
+#define PIPELINEERR_F PIPELINEERR_V(1U)
+
#define HASHEN_S 20
#define HASHEN_V(x) ((x) << HASHEN_S)
#define HASHEN_F HASHEN_V(1U)
@@ -3171,6 +3523,7 @@
#define ADDRESS_V(x) ((x) << ADDRESS_S)
#define MAC_PORT_INT_CAUSE_A 0x8dc
+#define T7_MAC_PORT_INT_CAUSE_A 0x86c
#define XGMAC_PORT_INT_CAUSE_A 0x10dc
#define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
@@ -3200,11 +3553,28 @@
#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
+#define MPS_T5_CLS_SRAM_L_A 0xe000
+#define MPS_T5_CLS_SRAM_H_A 0xe004
+
+#define SRAMWRN_S 31
+#define SRAMWRN_V(x) ((x) << SRAMWRN_S)
+#define SRAMWRN_F SRAMWRN_V(1U)
+
+#define SRAMINDEX_S 16
+#define SRAMINDEX_M 0x7ffU
+#define SRAMINDEX_V(x) ((x) << SRAMINDEX_S)
+#define SRAMINDEX_G(x) (((x) >> SRAMINDEX_S) & SRAMINDEX_M)
+
#define T5_PORT0_BASE 0x30000
#define T5_PORT_STRIDE 0x4000
#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
+#define T7_PORT0_BASE 0x30000
+#define T7_PORT_STRIDE 0x2000
+#define T7_PORT_BASE(idx) (T7_PORT0_BASE + (idx) * T7_PORT_STRIDE)
+#define T7_PORT_REG(idx, reg) (T7_PORT_BASE(idx) + (reg))
+
#define MC_0_BASE_ADDR 0x40000
#define MC_1_BASE_ADDR 0x48000
#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
@@ -3248,13 +3618,41 @@
#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
#define HOSTWRITE_F HOSTWRITE_V(1U)
+#define T7_HOSTBUSY_S 31
+#define T7_HOSTBUSY_V(x) ((x) << T7_HOSTBUSY_S)
+#define T7_HOSTBUSY_F T7_HOSTBUSY_V(1U)
+
+#define T7_HOSTWRITE_S 30
+#define T7_HOSTWRITE_V(x) ((x) << T7_HOSTWRITE_S)
+#define T7_HOSTWRITE_F T7_HOSTWRITE_V(1U)
+
+#define HOSTGRPSEL_S 28
+#define HOSTGRPSEL_M 0x3U
+#define HOSTGRPSEL_V(x) ((x) << HOSTGRPSEL_S)
+#define HOSTGRPSEL_G(x) (((x) >> HOSTGRPSEL_S) & HOSTGRPSEL_M)
+
+#define HOSTCORESEL_S 24
+#define HOSTCORESEL_M 0xfU
+#define HOSTCORESEL_V(x) ((x) << HOSTCORESEL_S)
+#define HOSTCORESEL_G(x) (((x) >> HOSTCORESEL_S) & HOSTCORESEL_M)
+
#define CIM_IBQ_DBG_CFG_A 0x7b60
+#define IBQDBGCORE_S 28
+#define IBQDBGCORE_M 0xfU
+#define IBQDBGCORE_V(x) ((x) << IBQDBGCORE_S)
+#define IBQDBGCORE_G(x) (((x) >> IBQDBGCORE_S) & IBQDBGCORE_M)
+
#define IBQDBGADDR_S 16
#define IBQDBGADDR_M 0xfffU
#define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
#define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
+#define T7_IBQDBGADDR_S 12
+#define T7_IBQDBGADDR_M 0x1fffU
+#define T7_IBQDBGADDR_V(x) ((x) << T7_IBQDBGADDR_S)
+#define T7_IBQDBGADDR_G(x) (((x) >> T7_IBQDBGADDR_S) & T7_IBQDBGADDR_M)
+
#define IBQDBGBUSY_S 1
#define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
#define IBQDBGBUSY_F IBQDBGBUSY_V(1U)
@@ -3265,6 +3663,16 @@
#define CIM_OBQ_DBG_CFG_A 0x7b64
+#define OBQDBGCORE_S 28
+#define OBQDBGCORE_M 0xfU
+#define OBQDBGCORE_V(x) ((x) << OBQDBGCORE_S)
+#define OBQDBGCORE_G(x) (((x) >> OBQDBGCORE_S) & OBQDBGCORE_M)
+
+#define T7_OBQDBGADDR_S 12
+#define T7_OBQDBGADDR_M 0x1fffU
+#define T7_OBQDBGADDR_V(x) ((x) << T7_OBQDBGADDR_S)
+#define T7_OBQDBGADDR_G(x) (((x) >> T7_OBQDBGADDR_S) & T7_OBQDBGADDR_M)
+
#define OBQDBGADDR_S 16
#define OBQDBGADDR_M 0xfffU
#define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)
@@ -3329,6 +3737,25 @@
#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)
#define CIM_QUEUE_CONFIG_REF_A 0x7b48
+
+#define CORESELECT_S 6
+#define CORESELECT_M 0xfU
+#define CORESELECT_V(x) ((x) << CORESELECT_S)
+#define CORESELECT_G(x) (((x) >> CORESELECT_S) & CORESELECT_M)
+
+#define T7_OBQSELECT_S 5
+#define T7_OBQSELECT_V(x) ((x) << T7_OBQSELECT_S)
+#define T7_OBQSELECT_F T7_OBQSELECT_V(1U)
+
+#define T7_IBQSELECT_S 4
+#define T7_IBQSELECT_V(x) ((x) << T7_IBQSELECT_S)
+#define T7_IBQSELECT_F T7_IBQSELECT_V(1U)
+
+#define T7_QUENUMSELECT_S 0
+#define T7_QUENUMSELECT_M 0xfU
+#define T7_QUENUMSELECT_V(x) ((x) << T7_QUENUMSELECT_S)
+#define T7_QUENUMSELECT_G(x) (((x) >> T7_QUENUMSELECT_S) & T7_QUENUMSELECT_M)
+
#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
#define CIMQSIZE_S 24
@@ -3383,4 +3810,21 @@
#define QUENUMSELECT_S 0
#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
+#define T7_UP_IBQ_0_SHADOW_RDADDR_A 0x400
+#define T7_UP_OBQ_0_SHADOW_RDADDR_A 0x600
+#define T7_UP_OBQ_0_SHADOW_REALADDR_A 0x704
+
+/* registers for module HMA */
+#define HMA_LOCAL_DEBUG_CFG_A 0x51320
+
+/* registers for module UP */
+#define T7_UP_IBQ_0_SHADOW_RDADDR_A 0x400
+#define T7_UP_OBQ_0_SHADOW_RDADDR_A 0x600
+#define T7_UP_OBQ_0_SHADOW_REALADDR_A 0x704
+
+#define T7_QUEREMFLITS_S 0
+#define T7_QUEREMFLITS_M 0xfffU
+#define T7_QUEREMFLITS_V(x) ((x) << T7_QUEREMFLITS_S)
+#define T7_QUEREMFLITS_G(x) (((x) >> T7_QUEREMFLITS_S) & T7_QUEREMFLITS_M)
+
#endif /* __T4_REGS_H */
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next v1 02/10] cxgb4: Add T7 chip type identification and HW constants
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 01/10] cxgb4: Add T7 register definitions and core structures Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 03/10] cxgb4: Add T7 CPL messages, FW constants, and PCI IDs Potnuri Bharat Teja
` (8 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Introduce the core chip identification infrastructure, hardware limits,
and register layout definitions required to support Chelsio T7 adapters.
Add the CHELSIO_T7 version constant, T7_A0/T7_B0 silicon revision
codes, revision range sentinels, and the is_t7 inline validation helper
to t4_chip_type.h to establish the foundational detection logic.
Extend the hardware specifications within t4_hw.h for the T7 design.
This includes increasing the maximum microprocessor cores to 8, expanding
internal buffer queue allocations to 16, sizing SGE context tracking
structures to 28 bytes, and updating CIM logic analyzer constraints.
Replace legacy flat FLASH constants with a flexible enum t4_flash_loc
table mechanism to allow per-adapter dynamic flash maps, while keeping
existing firmware load path constants for backward compatibility.
Refactor value parameters and field mappings in t4_values.h and t4_tcb.h
to match the T7 architecture. This standardizes mailbox ownership suffix
conventions, implements the narrower 4-bit T7 PCIe memory offset shift,
and inserts explicit tuple boundary markers and width definitions for
expanded hardware filter configurations. Finally, integrate new TCP
Control Block field macros to support advanced T7 TOE states.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../net/ethernet/chelsio/cxgb4/t4_chip_type.h | 10 ++
drivers/net/ethernet/chelsio/cxgb4/t4_hw.h | 136 ++++++++++++------
drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h | 16 +++
.../net/ethernet/chelsio/cxgb4/t4_values.h | 15 +-
4 files changed, 129 insertions(+), 48 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h b/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h
index 721c77577ec5..444675436b01 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h
@@ -39,6 +39,7 @@
#define CHELSIO_T4 0x4
#define CHELSIO_T5 0x5
#define CHELSIO_T6 0x6
+#define CHELSIO_T7 0x7
/* We code the Chelsio T4 Family "Chip Code" as a tuple:
*
@@ -67,6 +68,11 @@ enum chip_type {
T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
T6_FIRST_REV = T6_A0,
T6_LAST_REV = T6_A0,
+
+ T7_A0 = CHELSIO_CHIP_CODE(CHELSIO_T7, 0),
+ T7_B0 = CHELSIO_CHIP_CODE(CHELSIO_T7, 1),
+ T7_FIRST_REV = T7_A0,
+ T7_LAST_REV = T7_B0,
};
static inline int is_t4(enum chip_type chip)
@@ -84,4 +90,8 @@ static inline int is_t6(enum chip_type chip)
return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
}
+static inline int is_t7(enum chip_type chip)
+{
+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T7);
+}
#endif /* __T4_CHIP_TYPE_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
index 63bc956d2037..6c7761b88ca6 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
@@ -54,13 +54,18 @@ enum {
MBOX_LEN = 64, /* mailbox size in bytes */
TRACE_LEN = 112, /* length of trace data and mask */
FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
+ T7_PM_RX_CACHE_NSTATS = 27, /* # of PM Rx Cache stats in T7 */
+ MAX_UP_CORES = 8, /* Max # of uP cores that can be enabled */
};
enum {
CIM_NUM_IBQ = 6, /* # of CIM IBQs */
+ CIM_NUM_IBQ_T7 = 16, /* # of CIM IBQs for T7 */
CIM_NUM_OBQ = 6, /* # of CIM OBQs */
CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
- CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
+ CIM_NUM_OBQ_T7 = 16, /* # of CIM OBQs for T7 adapter */
+ CIMLA_SIZE = (256 * 8), /* 256 rows * ceil(235/32) 32-bit words */
+ CIMLA_SIZE_T6 = (256 * 10), /* 256 rows * ceil(311/32) 32-bit words */
CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
@@ -89,6 +94,7 @@ enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
enum {
SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
SGE_CTXT_SIZE = 24, /* size of SGE context */
+ SGE_CTXT_SIZE_T7 = 28, /* size of SGE context for T7 */
SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
SGE_NDBQTIMERS = 8, /* # of Doorbell Queue Timer values */
@@ -199,89 +205,127 @@ struct rsp_ctrl {
#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
enum {
+ FLASH_FW_START_SEC = 8,
+ FLASH_FW_NSECS = 16,
+ FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
+ FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
+
+ FLASH_CFG_START_SEC = 31,
+ FLASH_CFG_NSECS = 1,
+ FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
+ FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
+
+ FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
+};
+
+enum t4_flash_loc {
/*
* Various Expansion-ROM boot images, etc.
*/
- FLASH_EXP_ROM_START_SEC = 0,
- FLASH_EXP_ROM_NSECS = 6,
- FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
- FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
+ FLASH_LOC_EXP_ROM = 0,
/*
* iSCSI Boot Firmware Table (iBFT) and other driver-related
* parameters ...
*/
- FLASH_IBFT_START_SEC = 6,
- FLASH_IBFT_NSECS = 1,
- FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
- FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
+ FLASH_LOC_IBFT,
/*
* Boot configuration data.
*/
- FLASH_BOOTCFG_START_SEC = 7,
- FLASH_BOOTCFG_NSECS = 1,
- FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
- FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
+ FLASH_LOC_BOOTCFG,
/*
* Location of firmware image in FLASH.
*/
- FLASH_FW_START_SEC = 8,
- FLASH_FW_NSECS = 16,
- FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
- FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
+ FLASH_LOC_FW,
/* Location of bootstrap firmware image in FLASH.
*/
- FLASH_FWBOOTSTRAP_START_SEC = 27,
- FLASH_FWBOOTSTRAP_NSECS = 1,
- FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
- FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
+ FLASH_LOC_FWBOOTSTRAP,
/*
* iSCSI persistent/crash information.
*/
- FLASH_ISCSI_CRASH_START_SEC = 29,
- FLASH_ISCSI_CRASH_NSECS = 1,
- FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
- FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
+ FLASH_LOC_ISCSI_CRASH,
/*
* FCoE persistent/crash information.
*/
- FLASH_FCOE_CRASH_START_SEC = 30,
- FLASH_FCOE_CRASH_NSECS = 1,
- FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
- FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
+ FLASH_LOC_FCOE_CRASH,
/*
- * Location of Firmware Configuration File in FLASH. Since the FPGA
- * "FLASH" is smaller we need to store the Configuration File in a
- * different location -- which will overlap the end of the firmware
- * image if firmware ever gets that large ...
+ * Location of Firmware Configuration File in FLASH.
*/
- FLASH_CFG_START_SEC = 31,
- FLASH_CFG_NSECS = 1,
- FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
- FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
+ FLASH_LOC_CFG,
- /* We don't support FLASH devices which can't support the full
- * standard set of sections which we need for normal
- * operations.
+ /*
+ * CUDBG chip dump.
*/
- FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
+ FLASH_LOC_CUDBG,
- FLASH_FPGA_CFG_START_SEC = 15,
- FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
+ /*
+ * FW chip dump.
+ */
+ FLASH_LOC_CHIP_DUMP,
/*
- * Sectors 32-63 are reserved for FLASH failover.
+ * DPU boot information store.
*/
+ FLASH_LOC_DPU_BOOT,
+
+ /*
+ * DPU peristent information store.
+ */
+ FLASH_LOC_DPU_AREA,
+
+ /*
+ * VPD location.
+ */
+ FLASH_LOC_VPD,
+
+ /*
+ * Backup init/vpd.
+ */
+ FLASH_LOC_VPD_BACKUP,
+
+ /*
+ * Sectors 32-63 for CUDBG.
+ * Backup firmware image.
+ */
+ FLASH_LOC_FW_BACKUP,
+
+ /*
+ * Backup bootstrap firmware image.
+ */
+ FLASH_LOC_FWBOOTSTRAP_BACKUP,
+
+ /*
+ * Backup Location of Firmware Configuration File in FLASH.
+ */
+ FLASH_LOC_CFG_BACK,
+
+ /*
+ * Helper to retrieve info that spans the entire Boot related area.
+ */
+ FLASH_LOC_BOOT_AREA,
+
+ /*
+ * Helper to determine minimum standard set of sections needed for
+ * normal operations.
+ */
+ FLASH_LOC_MIN_SIZE,
+
+ /*
+ * End of FLASH regions.
+ */
+ FLASH_LOC_END
};
-#undef FLASH_START
-#undef FLASH_MAX_SIZE
+struct t4_flash_loc_entry {
+ u16 start_sec;
+ u16 nsecs;
+};
#define SGE_TIMESTAMP_S 0
#define SGE_TIMESTAMP_M 0xfffffffffffffffULL
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h b/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
index 22a0220123ad..1b7fc71dd835 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
@@ -141,4 +141,20 @@
#define TF_NON_OFFLOAD_V(x) ((x) << TF_NON_OFFLOAD_S)
#define TF_NON_OFFLOAD_F TF_NON_OFFLOAD_V(1)
+#define TCB_T_RTT_TS_RECENT_AGE_W 6
+#define TCB_T_RTT_TS_RECENT_AGE_S 0
+#define TCB_T_RTT_TS_RECENT_AGE_M 0xffffffffULL
+#define TCB_T_RTT_TS_RECENT_AGE_V(x) ((x) << TCB_T_RTT_TS_RECENT_AGE_S)
+
+#define TF_MIGRATING_S 0
+#define TF_MIGRATING_V(x) ((x) << TF_MIGRATING_S)
+
+#define TF_RECV_TSTMP_S 53
+#define TF_RECV_TSTMP_V(x) ((__u64)(x) << TF_RECV_TSTMP_S)
+
+#define TF_PEND_CTL1_S 56
+#define TF_PEND_CTL1_V(x) ((__u64)(x) << TF_PEND_CTL1_S)
+
+#define TF_PEND_CTL2_S 57
+#define TF_PEND_CTL2_V(x) ((__u64)(x) << TF_PEND_CTL2_S)
#endif /* __T4_TCB_H */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
index eb1aa82149db..a23527db6c20 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
@@ -119,18 +119,26 @@
/* CIM register field values.
*/
-#define X_MBOWNER_FW 1
-#define X_MBOWNER_PL 2
+#define MBOWNER_FW_X 1
+#define MBOWNER_PL_X 2
/* PCI-E definitions */
#define WINDOW_SHIFT_X 10
#define PCIEOFST_SHIFT_X 10
+#define T7_MEMOFST_SHIFT_X 4
/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
* Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
* selects for a particular field being present. These fields, when present
* in the Compressed Filter Tuple, have the following widths in bits.
*/
+#define FT_FIRST_S FCOE_S
+#define FT_LAST_S FRAGMENTATION_S
+
+#define T7_FT_FIRST_S IPSECIDX_S
+#define T7_FT_LAST_S TCPFLAGS_S
+
+#define FT_IPSECIDX_W 12
#define FT_FCOE_W 1
#define FT_PORT_W 3
#define FT_VNIC_ID_W 17
@@ -141,6 +149,9 @@
#define FT_MACMATCH_W 9
#define FT_MPSHITTYPE_W 3
#define FT_FRAGMENTATION_W 1
+#define FT_ROCE_W 1
+#define FT_SYNONLY_W 1
+#define FT_TCPFLAGS_W 12
/* Some of the Compressed Filter Tuple fields have internal structure. These
* bit shifts/masks describe those structures. All shifts are relative to the
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next v1 03/10] cxgb4: Add T7 CPL messages, FW constants, and PCI IDs
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 01/10] cxgb4: Add T7 register definitions and core structures Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 02/10] cxgb4: Add T7 chip type identification and HW constants Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 04/10] cxgb4: Add versioned structures and scratch buffs Potnuri Bharat Teja
` (7 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Extend the core protocol and firmware messaging interfaces to support the
T7 hardware generation, and register the matching T7 physical PCI IDs.
Update CPL structures within t4_msg.h for the expanded traffic
management pipelines. This introduces the CPL_SET_LE_REQ opcode and
tracking structures for hardware Lookup Engine and TCAM programming.
implements cpl_t7_act_open_req and cpl_t7_act_open_req6 layouts,
remove stale, duplicate legacy macros for CPL_TX_TNL_LSO to clean
up the file.
Expand firmware command definitions within t4fw_api.h and t4fw_version.h
to interact with new T7 engine features. This includes adding multi-core
queue assignment parameters, SWAPMAC and TX_LOOP offload capabilities,
and definitions for next-generation physical interfaces like SFP56,
QSFP56, OSFP, and QSFPDD. The firmware header layout is refactored to
support the T7 chip marker.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/t4_msg.h | 109 ++++++++++++++++--
.../ethernet/chelsio/cxgb4/t4_pci_id_tbl.h | 21 ++++
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | 82 +++++++++++--
.../net/ethernet/chelsio/cxgb4/t4fw_version.h | 9 ++
4 files changed, 203 insertions(+), 18 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
index fed5f93bf620..66a55ddf0c24 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
@@ -88,6 +88,7 @@ enum {
CPL_RDMA_READ_REQ = 0x60,
+ CPL_SET_LE_REQ = 0x80,
CPL_PASS_OPEN_REQ6 = 0x81,
CPL_ACT_OPEN_REQ6 = 0x83,
@@ -544,6 +545,26 @@ struct cpl_t6_act_open_req {
__be32 opt3;
};
+struct cpl_t7_act_open_req {
+ WR_HDR;
+ union opcode_tid ot;
+ __be16 local_port;
+ __be16 peer_port;
+ __be32 local_ip;
+ __be32 peer_ip;
+ __be64 opt0;
+ __be32 iss;
+ __be32 opt2;
+ __be64 params;
+ __be32 rsvd2;
+ __be32 opt3;
+};
+
+#define T7_FILTER_TUPLE_S 1
+#define T7_FILTER_TUPLE_M 0x7FFFFFFFFFFFFFFFULL
+#define T7_FILTER_TUPLE_V(x) ((x) << T7_FILTER_TUPLE_S)
+#define T7_FILTER_TUPLE_G(x) (((x) >> T7_FILTER_TUPLE_S) & T7_FILTER_TUPLE_M)
+
struct cpl_act_open_req6 {
WR_HDR;
union opcode_tid ot;
@@ -590,6 +611,23 @@ struct cpl_t6_act_open_req6 {
__be32 opt3;
};
+struct cpl_t7_act_open_req6 {
+ WR_HDR;
+ union opcode_tid ot;
+ __be16 local_port;
+ __be16 peer_port;
+ __be64 local_ip_hi;
+ __be64 local_ip_lo;
+ __be64 peer_ip_hi;
+ __be64 peer_ip_lo;
+ __be64 opt0;
+ __be32 iss;
+ __be32 opt2;
+ __be64 params;
+ __be32 rsvd2;
+ __be32 opt3;
+};
+
struct cpl_act_open_rpl {
union opcode_tid ot;
__be32 atid_status;
@@ -682,10 +720,20 @@ struct cpl_get_tcb {
#define QUEUENO_S 0
#define QUEUENO_V(x) ((x) << QUEUENO_S)
+#define T7_QUEUENO_S 0
+#define T7_QUEUENO_M 0xFFF
+#define T7_QUEUENO_V(x) ((x) << T7_QUEUENO_S)
+#define T7_QUEUENO_G(x) (((x) >> T7_QUEUENO_S) & T7_QUEUENO_M)
+
#define REPLY_CHAN_S 14
#define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
#define REPLY_CHAN_F REPLY_CHAN_V(1U)
+#define T7_REPLY_CHAN_S 12
+#define T7_REPLY_CHAN_M 0x7
+#define T7_REPLY_CHAN_V(x) ((x) << T7_REPLY_CHAN_S)
+#define T7_REPLY_CHAN_G(x) (((x) >> T7_REPLY_CHAN_S) & T7_REPLY_CHAN_M)
+
#define NO_REPLY_S 15
#define NO_REPLY_V(x) ((x) << NO_REPLY_S)
#define NO_REPLY_F NO_REPLY_V(1U)
@@ -1363,6 +1411,53 @@ struct cpl_smt_write_rpl {
#define SMTW_NORPL_V(x) ((x) << SMTW_NORPL_S)
#define SMTW_NORPL_F SMTW_NORPL_V(1U)
+struct cpl_set_le_req {
+ WR_HDR;
+ union opcode_tid ot;
+ __be16 reply_ctrl;
+ __be16 params;
+ __be64 mask_hi;
+ __be64 mask_lo;
+ __be64 val_hi;
+ __be64 val_lo;
+};
+
+/* cpl_set_le_req.reply_ctrl additional fields */
+#define LE_REQ_RXCHANNEL_S 14
+#define LE_REQ_RXCHANNEL_M 0x1
+#define LE_REQ_RXCHANNEL_V(x) ((x) << LE_REQ_RXCHANNEL_S)
+#define LE_REQ_RXCHANNEL_G(x) (((x) >> LE_REQ_RXCHANNEL_S) & LE_REQ_RXCHANNEL_M)
+#define LE_REQ_RXCHANNEL_F LE_REQ_RXCHANNEL_V(1U)
+
+#define LE_REQ_IP6_S 13
+#define LE_REQ_IP6_V(x) ((x) << LE_REQ_IP6_S)
+#define LE_REQ_IP6_F LE_REQ_IP6_V(1U)
+
+/* cpl_set_le_req.params fields */
+#define LE_CHAN_S 0
+#define LE_CHAN_M 0x3
+#define LE_CHAN_V(x) ((x) << LE_CHAN_S)
+#define LE_CHAN_G(x) (((x) >> LE_CHAN_S) & LE_CHAN_M)
+
+#define LE_OFFSET_S 5
+#define LE_OFFSET_M 0x7
+#define LE_OFFSET_V(x) ((x) << LE_OFFSET_S)
+#define LE_OFFSET_G(x) (((x) >> LE_OFFSET_S) & LE_OFFSET_M)
+
+#define LE_MORE_S 8
+#define LE_MORE_V(x) ((x) << LE_MORE_S)
+#define LE_MORE_F LE_MORE_V(1U)
+
+#define LE_REQSIZE_S 9
+#define LE_REQSIZE_M 0x7
+#define LE_REQSIZE_V(x) ((x) << LE_REQSIZE_S)
+#define LE_REQSIZE_G(x) (((x) >> LE_REQSIZE_S) & LE_REQSIZE_M)
+
+#define LE_REQCMD_S 12
+#define LE_REQCMD_M 0xF
+#define LE_REQCMD_V(x) ((x) << LE_REQCMD_S)
+#define LE_REQCMD_G(x) (((x) >> LE_REQCMD_S) & LE_REQCMD_M)
+
struct cpl_rdma_terminate {
union opcode_tid ot;
__be16 rsvd;
@@ -1631,10 +1726,10 @@ struct cpl_tx_tnl_lso {
(((x) >> CPL_TX_TNL_LSO_IPV6OUT_S) & CPL_TX_TNL_LSO_IPV6OUT_M)
#define CPL_TX_TNL_LSO_IPV6OUT_F CPL_TX_TNL_LSO_IPV6OUT_V(1U)
-#define CPL_TX_TNL_LSO_ETHHDRLEN_S 16
-#define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf
-#define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S)
-#define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \
+#define CPL_TX_TNL_LSO_ETHHDRLEN_S 16
+#define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf
+#define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S)
+#define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \
(((x) >> CPL_TX_TNL_LSO_ETHHDRLEN_S) & CPL_TX_TNL_LSO_ETHHDRLEN_M)
#define CPL_TX_TNL_LSO_IPHDRLEN_S 4
@@ -1719,12 +1814,6 @@ struct cpl_tx_tnl_lso {
#define CPL_TX_TNL_LSO_TNLTYPE_G(x) \
(((x) >> CPL_TX_TNL_LSO_TNLTYPE_S) & CPL_TX_TNL_LSO_TNLTYPE_M)
-#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16
-#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf
-#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
-#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
- (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)
-
#define CPL_TX_TNL_LSO_TNLHDRLEN_S 0
#define CPL_TX_TNL_LSO_TNLHDRLEN_M 0xfff
#define CPL_TX_TNL_LSO_TNLHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TNLHDRLEN_S)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h b/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h
index 0b1b5f9c67d4..d0921b76049d 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h
@@ -220,6 +220,27 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
CH_PCI_ID_TABLE_FENTRY(0x608a), /* Custom T62100-CR */
CH_PCI_ID_TABLE_FENTRY(0x608b), /* Custom T6225-CR */
CH_PCI_ID_TABLE_FENTRY(0x6092), /* Custom T62100-CR-LOM */
+
+ /* T7 adapter */
+ CH_PCI_ID_TABLE_FENTRY(0x7000), /* T7-DBG */
+ CH_PCI_ID_TABLE_FENTRY(0x7001), /* T7250 */
+ CH_PCI_ID_TABLE_FENTRY(0x7002), /* S7250 */
+ CH_PCI_ID_TABLE_FENTRY(0x7003), /* T7450 */
+ CH_PCI_ID_TABLE_FENTRY(0x7004), /* S7450 */
+ CH_PCI_ID_TABLE_FENTRY(0x7005), /* T72200 */
+ CH_PCI_ID_TABLE_FENTRY(0x7006), /* S72200 */
+ CH_PCI_ID_TABLE_FENTRY(0x7007), /* T72200-FH */
+ CH_PCI_ID_TABLE_FENTRY(0x7008), /* T71400 */
+ CH_PCI_ID_TABLE_FENTRY(0x7009), /* S7210-BT */
+ CH_PCI_ID_TABLE_FENTRY(0x700a), /* T7450-RC */
+ CH_PCI_ID_TABLE_FENTRY(0x700b), /* T72200-RC */
+ CH_PCI_ID_TABLE_FENTRY(0x700c), /* T72200-FH-RC */
+ CH_PCI_ID_TABLE_FENTRY(0x700d), /* S72200-OCP3 */
+ CH_PCI_ID_TABLE_FENTRY(0x700e), /* S7450-OCP3 */
+ CH_PCI_ID_TABLE_FENTRY(0x700f), /* S7410-BT-OCP3 */
+ CH_PCI_ID_TABLE_FENTRY(0x7010), /* S7210-BT-A */
+ CH_PCI_ID_TABLE_FENTRY(0x7011), /* T7_MAYRA_7 */
+ CH_PCI_ID_TABLE_FENTRY(0x7012), /* T7-iNIC */
CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
#endif /* __T4_PCI_ID_TBL_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
index 2419459a0b85..e4fb8999daf1 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
@@ -35,6 +35,8 @@
#ifndef _T4FW_INTERFACE_H_
#define _T4FW_INTERFACE_H_
+#include <linux/if_ether.h>
+
enum fw_retval {
FW_SUCCESS = 0, /* completed successfully */
FW_EPERM = 1, /* operation not permitted */
@@ -434,6 +436,13 @@ struct fw_filter2_wr {
#define FW_FILTER_WR_RX_RPL_IQ_G(x) \
(((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
+#define FW_FILTER2_WR_SWAPMAC_S 0
+#define FW_FILTER2_WR_SWAPMAC_M 0x1
+#define FW_FILTER2_WR_SWAPMAC_V(x) ((x) << FW_FILTER2_WR_SWAPMAC_S)
+#define FW_FILTER2_WR_SWAPMAC_G(x) \
+ (((x) >> FW_FILTER2_WR_SWAPMAC_S) & FW_FILTER2_WR_SWAPMAC_M)
+#define FW_FILTER2_WR_SWAPMAC_F FW_FILTER2_WR_SWAPMAC_V(1U)
+
#define FW_FILTER2_WR_FILTER_TYPE_S 1
#define FW_FILTER2_WR_FILTER_TYPE_M 0x1
#define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S)
@@ -460,6 +469,13 @@ struct fw_filter2_wr {
#define FW_FILTER2_WR_ULP_TYPE_G(x) \
(((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
+#define FW_FILTER2_WR_TX_LOOP_S 29
+#define FW_FILTER2_WR_TX_LOOP_M 0x1
+#define FW_FILTER2_WR_TX_LOOP_V(x) ((x) << FW_FILTER2_WR_TX_LOOP_S)
+#define FW_FILTER2_WR_TX_LOOP_G(x) \
+ (((x) >> FW_FILTER2_WR_TX_LOOP_S) & FW_FILTER2_WR_TX_LOOP_M)
+#define FW_FILTER2_WR_TX_LOOP_F FW_FILTER2_WR_TX_LOOP_V(1U)
+
#define FW_FILTER_WR_MACI_S 23
#define FW_FILTER_WR_MACI_M 0x1ff
#define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
@@ -1882,6 +1898,12 @@ struct fw_eq_eth_cmd {
#define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
#define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U)
+#define FW_EQ_ETH_CMD_COREGROUP_S 16
+#define FW_EQ_ETH_CMD_COREGROUP_M 0x3f
+#define FW_EQ_ETH_CMD_COREGROUP_V(x) ((x) << FW_EQ_ETH_CMD_COREGROUP_S)
+#define FW_EQ_ETH_CMD_COREGROUP_G(x) \
+ (((x) >> FW_EQ_ETH_CMD_COREGROUP_S) & FW_EQ_ETH_CMD_COREGROUP_M)
+
#define FW_EQ_ETH_CMD_EQID_S 0
#define FW_EQ_ETH_CMD_EQID_M 0xfffff
#define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
@@ -2010,6 +2032,12 @@ struct fw_eq_ctrl_cmd {
#define FW_EQ_CTRL_CMD_CMPLIQID_S 20
#define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
+#define FW_EQ_CTRL_CMD_COREGROUP_S 16
+#define FW_EQ_CTRL_CMD_COREGROUP_M 0x3f
+#define FW_EQ_CTRL_CMD_COREGROUP_V(x) ((x) << FW_EQ_CTRL_CMD_COREGROUP_S)
+#define FW_EQ_CTRL_CMD_COREGROUP_G(x) \
+ (((x) >> FW_EQ_CTRL_CMD_COREGROUP_S) & FW_EQ_CTRL_CMD_COREGROUP_M)
+
#define FW_EQ_CTRL_CMD_EQID_S 0
#define FW_EQ_CTRL_CMD_EQID_M 0xfffff
#define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S)
@@ -2597,7 +2625,7 @@ struct fw_acl_vlan_cmd {
#define FW_ACL_VLAN_CMD_EN_M 0x1
#define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
#define FW_ACL_VLAN_CMD_EN_G(x) \
- (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M)
+ (((x) >> FW_ACL_VLAN_CMD_EN_S_S) & FW_ACL_VLAN_CMD_EN_M)
#define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U)
#define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7
@@ -3107,8 +3135,26 @@ enum fw_port_type {
FW_PORT_TYPE_SFP28,
FW_PORT_TYPE_KR_SFP28,
FW_PORT_TYPE_KR_XLAUI,
-
- FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
+ /* Applicable on T7 */
+ FW_PORT_TYPE_BARE_LINK_50G = 23, /* No, 1, 50G */
+ FW_PORT_TYPE_BARE_LINK_100G = 24, /* No, 2, 100G/50G */
+ FW_PORT_TYPE_BARE_LINK_200G = 25, /* No, 4, 200G/100G/50G */
+ FW_PORT_TYPE_SFP56 = 26, /* No, 1, 50G/25G */
+ FW_PORT_TYPE_QSFP56 = 27, /* No, 4, 200G/100G/50G/25G */
+ FW_PORT_TYPE_QSFP56_4_50G = 28, /* No, 1, 50G */
+ FW_PORT_TYPE_KR_50G = 29, /* No, 1, 50G */
+ FW_PORT_TYPE_KR2_100G = 30, /* No, 2, 100G/50G */
+ FW_PORT_TYPE_KR4_200G = 31, /* No, 4, 200G/100G/50G */
+ FW_PORT_TYPE_QSFP56_2_50G = 32, /* No, 1, 50G */
+ FW_PORT_TYPE_OSFP = 33, /* No, 8, 400G/200G/100G/50G */
+ FW_PORT_TYPE_QSFPDD = 34, /* No, 8, 400G/200G/100G/50G */
+ FW_PORT_TYPE_OSFP_2_200G = 35, /* No, 4, 200G/100G/50G */
+ FW_PORT_TYPE_QSFP_4_100G = 36, /* No, 2, 100G/50G */
+ FW_PORT_TYPE_QSFPDD_2_200G = 37, /* No, 4, 200G/100G/50G */
+ FW_PORT_TYPE_KR8_400G = 38, /* No, 8, 400G/200G/100G/50G? */
+ FW_PORT_TYPE_MAX,
+
+ FW_PORT_TYPE_NONE = FW_PORT_CMD_PORTTYPE32_M
};
enum fw_port_module_type {
@@ -3119,6 +3165,7 @@ enum fw_port_module_type {
FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
FW_PORT_MOD_TYPE_LRM,
+ FW_PORT_MOD_TYPE_DR,
FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3,
FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2,
FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1,
@@ -3770,13 +3817,17 @@ struct fw_hdr {
__u32 reserved3;
__u32 reserved4;
__be32 flags;
- __be32 reserved6[23];
+ __be32 reserved6[4];
+ __u8 reserved7[3];
+ __u8 dsign_len;
+ __u8 dsign[72]; /* fw binary digital signature */
};
enum fw_hdr_chip {
FW_HDR_CHIP_T4,
FW_HDR_CHIP_T5,
- FW_HDR_CHIP_T6
+ FW_HDR_CHIP_T6,
+ FW_HDR_CHIP_T7
};
#define FW_HDR_FW_VER_MAJOR_S 24
@@ -3888,7 +3939,9 @@ struct fw_devlog_cmd {
__u8 r2[7];
__be32 memtype_devlog_memaddr16_devlog;
__be32 memsize_devlog;
- __be32 r3[2];
+ __u8 num_devlog;
+ __u8 r3[3];
+ __be32 r4;
};
#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28
@@ -3915,8 +3968,14 @@ struct fw_devlog_cmd {
*/
#define PCIE_FW_PF_DEVLOG 7
+#define PCIE_FW_PF_DEVLOG_COUNT_MSB_S 31
+#define PCIE_FW_PF_DEVLOG_COUNT_MSB_M 0x1
+#define PCIE_FW_PF_DEVLOG_COUNT_MSB_V(x) ((x) << PCIE_FW_PF_DEVLOG_COUNT_MSB_S)
+#define PCIE_FW_PF_DEVLOG_COUNT_MSB_G(x) \
+ (((x) >> PCIE_FW_PF_DEVLOG_COUNT_MSB_S) & PCIE_FW_PF_DEVLOG_COUNT_MSB_M)
+
#define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
-#define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
+#define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0x7
#define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
#define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
@@ -3929,8 +3988,15 @@ struct fw_devlog_cmd {
#define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
(((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
+#define PCIE_FW_PF_DEVLOG_COUNT_LSB_S 3
+#define PCIE_FW_PF_DEVLOG_COUNT_LSB_M 0x1
+#define PCIE_FW_PF_DEVLOG_COUNT_LSB_V(x) \
+ ((x) << PCIE_FW_PF_DEVLOG_COUNT_LSB_S)
+#define PCIE_FW_PF_DEVLOG_COUNT_LSB_G(x) \
+ (((x) >> PCIE_FW_PF_DEVLOG_COUNT_LSB_S) & PCIE_FW_PF_DEVLOG_COUNT_LSB_M)
+
#define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0
-#define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf
+#define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0x7
#define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
#define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
(((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h
index a02b1dff403e..d19979c8bfc0 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h
@@ -61,4 +61,13 @@
#define T6FW_MIN_VERSION_MAJOR 0x00
#define T6FW_MIN_VERSION_MINOR 0x00
#define T6FW_MIN_VERSION_MICRO 0x00
+
+#define T7FW_VERSION_MAJOR 0x01
+#define T7FW_VERSION_MINOR 0x19
+#define T7FW_VERSION_MICRO 0x01
+#define T7FW_VERSION_BUILD 0x1B
+
+#define T7FW_MIN_VERSION_MAJOR 0x00
+#define T7FW_MIN_VERSION_MINOR 0x00
+#define T7FW_MIN_VERSION_MICRO 0x00
#endif
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next v1 04/10] cxgb4: Add versioned structures and scratch buffs
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
` (2 preceding siblings ...)
2026-06-07 3:52 ` [PATCH net-next v1 03/10] cxgb4: Add T7 CPL messages, FW constants, and PCI IDs Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 05/10] cxgb4: Add T7 indirect regs and update library Potnuri Bharat Teja
` (6 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Upgrade the cudbg framework to support the expanded address space and
multi-core tracking requirements of T7 adapters.
Refactor the debug layout by replacing flat representations with
versioned structures like cim_ibq_rev1 and sge_ctxt_rev1 embedded with
compatibility headers for user-space parsing tools. Widen memory
description bounds from u32 to u64 to accommodate T7's 64-bit physical
memory footprint, and register 16 new T7-specific debug entity IDs.
A new parameter-passing array is also added to route microprocessor
core IDs and mailbox logging context straight to the capture routines.
Finally, introduce get_scratch_buff and release_scratch_buff management
helpers. These functions carve out transient working space directly from
the tail of the pre-allocated output payload, eliminating the overhead
and memory fragmentation of repetitive kmalloc calls during diagnostic
dump captures.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../net/ethernet/chelsio/cxgb4/cudbg_common.c | 30 ++++
.../net/ethernet/chelsio/cxgb4/cudbg_entity.h | 147 +++++++++++++++---
drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h | 54 ++++++-
.../ethernet/chelsio/cxgb4/cudbg_lib_common.h | 4 +
4 files changed, 216 insertions(+), 19 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_common.c b/drivers/net/ethernet/chelsio/cxgb4/cudbg_common.c
index 175e1a675de5..ccbf402a0a89 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_common.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_common.c
@@ -7,6 +7,36 @@
#include "cudbg_if.h"
#include "cudbg_lib_common.h"
+void release_scratch_buff(struct cudbg_buffer *pscratch_buff,
+ struct cudbg_buffer *pdbg_buff)
+{
+ pdbg_buff->size += pscratch_buff->size;
+ memset(pscratch_buff->data, 0, pscratch_buff->size);
+ pscratch_buff->data = NULL;
+ pscratch_buff->offset = 0;
+ pscratch_buff->size = 0;
+}
+
+int get_scratch_buff(struct cudbg_buffer *pdbg_buff, u32 size,
+ struct cudbg_buffer *pscratch_buff)
+{
+ u32 scratch_offset;
+ int rc = 0;
+
+ scratch_offset = pdbg_buff->size - size;
+ if (pdbg_buff->offset > (int)scratch_offset || pdbg_buff->size < size) {
+ rc = CUDBG_STATUS_NO_MEM;
+ goto err;
+ } else {
+ pscratch_buff->data = (char *)pdbg_buff->data + scratch_offset;
+ pscratch_buff->offset = 0;
+ pscratch_buff->size = size;
+ pdbg_buff->size -= size;
+ }
+err:
+ return rc;
+}
+
int cudbg_get_buff(struct cudbg_init *pdbg_init,
struct cudbg_buffer *pdbg_buff, u32 size,
struct cudbg_buffer *pin_buff)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
index d5218e74284c..bad27fedac63 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
@@ -21,13 +21,58 @@ struct cudbg_mbox_log {
u32 lo[MBOX_LEN / 8];
};
-struct cudbg_cim_qcfg {
- u8 chip;
- u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
- u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
- u16 thres[CIM_NUM_IBQ];
- u32 obq_wr[2 * CIM_NUM_OBQ_T5];
- u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
+#define CUDBG_CIM_IBQ_REV 1
+
+struct cim_ibq_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u8 qid;
+ u8 coreid;
+ u32 data[]; /* Must be last */
+};
+
+#define CUDBG_CIM_OBQ_REV 1
+
+struct cim_obq_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u8 qid;
+ u8 coreid;
+ u32 data[]; /* Must be last */
+};
+
+#define CUDBG_CIM_QCFG_REV 1
+
+enum cudbg_entity_cim_qcfg_qtype {
+ CUDBG_ENTITY_CIM_QCFG_QTYPE_IBQ = 0,
+ CUDBG_ENTITY_CIM_QCFG_QTYPE_OBQ,
+};
+
+struct cim_qcfg_rev1_data {
+ u8 qtype;
+ u8 qid;
+ u16 base;
+ u16 size;
+ u16 thres;
+ u32 obq_wr[2];
+ u32 stat[4];
+};
+
+struct cim_qcfg_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u8 num_cim_ibq;
+ u8 num_cim_obq;
+ u8 coreid;
+ struct cim_qcfg_rev1_data data[]; /* Must be last */
+};
+
+#define CUDBG_CIM_LA_REV 1
+
+struct struct_cim_la_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u8 coreid;
+ u8 ncol;
+ u16 nrow;
+ u32 config;
+ u32 data[]; /* Must be last */
};
struct cudbg_rss_vf_conf {
@@ -50,6 +95,25 @@ struct cudbg_hw_sched {
u32 map;
};
+#define CUDBG_TP_INDIR_REG_REV 1
+#define CUDBG_PM_INDIR_REG_REV 1
+#define CUDBG_MA_INDIR_REG_REV 1
+#define CUDBG_UP_CIM_INDIR_REG_REV 1
+#define CUDBG_HMA_INDIR_REG_REV 1
+
+struct cudbg_indir_reg_data {
+ u32 offset;
+ u32 data;
+};
+
+struct cudbg_indir_reg_entity {
+ struct cudbg_ver_hdr ver_hdr;
+ u32 indir_reg;
+ u32 indir_data;
+ u32 nentries;
+ struct cudbg_indir_reg_data data[];
+};
+
#define SGE_QBASE_DATA_REG_NUM 4
struct sge_qbase_reg_field {
@@ -91,20 +155,20 @@ static const char * const cudbg_region[] = {
"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
"RQUDP region:", "PBL region:", "TXPBL region:",
- "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
- "On-chip queues:"
+ "RRQ region:", "DBVFIFO region:", "ULPRX state:",
+ "ULPTX state:", "On-chip queues:"
};
/* Memory region info relative to current memory (i.e. wrt 0). */
struct cudbg_region_info {
bool exist; /* Does region exists in current memory? */
- u32 start; /* Start wrt 0 */
- u32 end; /* End wrt 0 */
+ u64 start; /* Start wrt 0 */
+ u64 end; /* End wrt 0 */
};
struct cudbg_mem_desc {
- u32 base;
- u32 limit;
+ u64 base;
+ u64 limit;
u32 idx;
};
@@ -187,20 +251,42 @@ struct cudbg_tid_info_region_rev1 {
struct cudbg_ver_hdr ver_hdr;
struct cudbg_tid_info_region tid;
u32 tid_start;
- u32 reserved[16];
+ u32 nhash;
+ u32 clip_base;
+ u32 nclip;
+ u32 route_base;
+ u32 nroute;
+ u32 reserved[11];
};
#define CUDBG_LOWMEM_MAX_CTXT_QIDS 256
#define CUDBG_MAX_FL_QIDS 1024
-struct cudbg_ch_cntxt {
- u32 cntxt_type;
- u32 cntxt_id;
- u32 data[SGE_CTXT_SIZE / 4];
+#define CUDBG_SGE_CTXT_REV 1
+
+struct struct_sge_ctxt_rev1_data {
+ u8 ctxt_type;
+ u8 size;
+ u32 ctxt_id;
+ u32 data[];
+};
+
+struct struct_sge_ctxt_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u32 nentries;
+ struct struct_sge_ctxt_rev1_data data[]; /* Must be last */
};
#define CUDBG_MAX_RPLC_SIZE 128
+struct cudbg_cntxt_field {
+ char *name;
+ u32 start_bit;
+ u32 end_bit;
+ u32 shift;
+ u32 islog2;
+};
+
struct cudbg_mps_tcam {
u64 mask;
u32 rplc[8];
@@ -250,6 +336,8 @@ enum cudbg_le_entry_types {
LE_ET_TCAM_ROUTING = 5,
LE_ET_HASH_CON = 6,
LE_ET_INVALID_TID = 8,
+ /* Reserve for future regions */
+ LE_ET_TCAM_MAX = 16,
};
struct cudbg_tcam {
@@ -349,4 +437,27 @@ struct cudbg_qdesc_info {
#define CUDBG_NUM_PCIE_CONFIG_REGS 0x61
+struct cudbg_letcam_region {
+ u8 type;
+ u32 start;
+ u32 nentries;
+
+ u8 reserved[64];
+};
+
+struct cudbg_letcam {
+ struct cudbg_ver_hdr ver_hdr;
+
+ u8 nregions;
+ u32 region_hdr_size;
+
+ u32 max_tid;
+ u32 tid_data_hdr_size;
+
+ u8 reserved[64];
+};
+
+int cudbg_view_sge_ctxt(u8 ctxt_type, u32 qid, u32 *ctxt_data,
+ struct cudbg_cntxt_field *field,
+ struct cudbg_buffer *cudbg_poutbuf);
#endif /* __CUDBG_ENTITY_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
index c84719e3ca08..dbb0611b6d26 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
@@ -17,6 +17,12 @@
#define CUDBG_MAJOR_VERSION 1
#define CUDBG_MINOR_VERSION 14
+#define CUDBG_MAX_PARAMS 16
+
+enum {
+ CUDBG_UP_COREID_PARAM = 13,
+};
+
enum cudbg_dbg_entity_type {
CUDBG_REG_DUMP = 1,
CUDBG_DEV_LOG = 2,
@@ -71,11 +77,57 @@ enum cudbg_dbg_entity_type {
CUDBG_HMA = 68,
CUDBG_QDESC = 70,
CUDBG_FLASH = 71,
- CUDBG_MAX_ENTITY = 72,
+ CUDBG_CIM_IBQ_TP2 = 73,
+ CUDBG_CIM_IBQ_TP3 = 74,
+ CUDBG_CIM_IBQ_IPC1 = 75,
+ CUDBG_CIM_IBQ_IPC2 = 76,
+ CUDBG_CIM_IBQ_IPC3 = 77,
+ CUDBG_CIM_IBQ_IPC4 = 78,
+ CUDBG_CIM_IBQ_IPC5 = 79,
+ CUDBG_CIM_IBQ_IPC6 = 80,
+ CUDBG_CIM_IBQ_IPC7 = 81,
+ CUDBG_CIM_OBQ_IPC1 = 82,
+ CUDBG_CIM_OBQ_IPC2 = 83,
+ CUDBG_CIM_OBQ_IPC3 = 84,
+ CUDBG_CIM_OBQ_IPC4 = 85,
+ CUDBG_CIM_OBQ_IPC5 = 86,
+ CUDBG_CIM_OBQ_IPC6 = 87,
+ CUDBG_CIM_OBQ_IPC7 = 88,
+ CUDBG_MAX_ENTITY,
+};
+
+struct cudbg_param {
+ u16 param_type;
+ u16 reserved;
+ union {
+ struct {
+ u32 memtype; /* which memory (EDC0, EDC1, MC) */
+ u32 start; /* start of log in firmware memory */
+ u32 size; /* size of log */
+ } devlog_param;
+ struct {
+ struct mbox_cmd_log *log;
+ u16 mbox_cmds;
+ } mboxlog_param;
+ struct {
+ const char *caller_string;
+ u8 os_type;
+ } sw_state_param;
+ struct {
+ u32 itr;
+ } yield_param;
+ u64 time;
+ u8 tcb_bit_param;
+ void *adap;
+ u8 coreid;
+ } u;
};
struct cudbg_init {
struct adapter *adap; /* Pointer to adapter structure */
+ u16 dbg_params_cnt;
+ u16 dbg_reserved;
+ struct cudbg_param dbg_params[CUDBG_MAX_PARAMS];
void *outbuf; /* Output buffer */
u32 outbuf_size; /* Output buffer size */
u8 compress_type; /* Type of compression to use */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib_common.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib_common.h
index 9fac777b0b24..45551f464ac4 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib_common.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib_common.h
@@ -67,6 +67,10 @@ struct cudbg_error {
#define CDUMP_MAX_COMP_BUF_SIZE ((64 * 1024) - 1)
#define CUDBG_CHUNK_SIZE ((CDUMP_MAX_COMP_BUF_SIZE / 1024) * 1024)
+void release_scratch_buff(struct cudbg_buffer *pscratch_buff,
+ struct cudbg_buffer *pdbg_buff);
+int get_scratch_buff(struct cudbg_buffer *pdbg_buff, u32 size,
+ struct cudbg_buffer *pscratch_buff);
int cudbg_get_buff(struct cudbg_init *pdbg_init,
struct cudbg_buffer *pdbg_buff, u32 size,
struct cudbg_buffer *pin_buff);
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next v1 05/10] cxgb4: Add T7 indirect regs and update library
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
` (3 preceding siblings ...)
2026-06-07 3:52 ` [PATCH net-next v1 04/10] cxgb4: Add versioned structures and scratch buffs Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 06/10] cxgb4: Move PCI initialization logic to cxgb4_pci.c Potnuri Bharat Teja
` (5 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Add the T7 indirect register tables and update the cudbg core
collection library to handle T7 diagnostic dumps.
Introduce a per-chip indirect register tracking framework across
cudbg_indir_reg.h and cudbg_indir_reg_t7.h. This adds static address
mapping tables for nine distinct T7 subsystem spaces—including CIM_CTL,
PM_RX/TX, TP_PIO, and MA_LOCAL_DEBUG.
Update cudbg_lib.c, cudbg_lib.h, and cxgb4_cudbg.c to process these new
hardware targets during debugging routines:
- Integrate the scratch buffer subsystem into the CIM IBQ, OBQ, and
QCFG collectors to cleanly generate versioned structures.
- Expand queue ID routing configurations via versioned checks to handle
T7's additional pathways, enabling 16 new debug entities tracking
internal TP and IPC data paths.
- Update indirect dump engines (TP, PM, MA, HMA, and uP) to read from
the new structural register dispatch tables.
- Widen memory offsets to u64, update window access tracking, and scale
the TCAM engine to accommodate the T7 3-TCAM hardware layout.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../ethernet/chelsio/cxgb4/cudbg_indir_reg.h | 43 +
.../chelsio/cxgb4/cudbg_indir_reg_t7.h | 1113 +++++++++++++++++
.../net/ethernet/chelsio/cxgb4/cudbg_lib.c | 902 +++++++++++--
.../net/ethernet/chelsio/cxgb4/cudbg_lib.h | 50 +-
.../net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c | 16 +
5 files changed, 2029 insertions(+), 95 deletions(-)
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h
new file mode 100644
index 000000000000..a33e003c78d5
--- /dev/null
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 Chelsio Communications. All rights reserved.
+ */
+
+#ifndef __CUDBG_INDIR_REG_H__
+#define __CUDBG_INDIR_REG_H__
+
+enum cudbg_indir_type {
+ CUDBG_INDIR_TYPE_CIM_CTL,
+ CUDBG_INDIR_TYPE_PM_RX_DBG_CTRL,
+ CUDBG_INDIR_TYPE_PM_TX_DBG_CTRL,
+ CUDBG_INDIR_TYPE_TP_MIB_INDEX,
+ CUDBG_INDIR_TYPE_TP_PIO_ADDR,
+ CUDBG_INDIR_TYPE_TP_TM_PIO_ADDR,
+ CUDBG_INDIR_TYPE_UP,
+ CUDBG_INDIR_TYPE_HMAT6_LOCAL_DEBUG_CFG,
+ CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_CFG,
+ CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_PERF_CFG,
+ CUDBG_INDIR_TYPE_MAX, /* New members need to be added at end */
+};
+
+struct cudbg_indir_reg {
+ u32 addr;
+};
+
+struct cudbg_indir_type_entry {
+ struct cudbg_indir_reg *reg_arr;
+ u32 nentries;
+};
+
+#include "cudbg_indir_reg_t7.h"
+
+static inline struct cudbg_indir_type_entry *
+cudbg_get_indir_reg_info(u32 chip_ver, enum cudbg_indir_type type)
+{
+ if (chip_ver >= CHELSIO_T7)
+ return &t7_indir_type_arr[type];
+
+ return NULL;
+}
+
+#endif /* __CUDBG_INDIR_REG_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h
new file mode 100644
index 000000000000..a246009ffb8d
--- /dev/null
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_indir_reg_t7.h
@@ -0,0 +1,1113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 Chelsio Communications. All rights reserved.
+ */
+
+#ifndef __CUDBG_INDIR_REG_T7_H__
+#define __CUDBG_INDIR_REG_T7_H__
+
+static struct cudbg_indir_reg t7_cim_ctl[82] = {
+ { .addr = 0x2000 },
+ { .addr = 0x2040 },
+ { .addr = 0x2044 },
+ { .addr = 0x2050 },
+ { .addr = 0x2054 },
+ { .addr = 0x2060 },
+ { .addr = 0x2064 },
+ { .addr = 0x2068 },
+ { .addr = 0x206c },
+ { .addr = 0x2094 },
+ { .addr = 0x2098 },
+ { .addr = 0x209c },
+ { .addr = 0x20a0 },
+ { .addr = 0x20a4 },
+ { .addr = 0x20a8 },
+ { .addr = 0x20ac },
+ { .addr = 0x20b0 },
+ { .addr = 0x20b4 },
+ { .addr = 0x20b8 },
+ { .addr = 0x20bc },
+ { .addr = 0x20c0 },
+ { .addr = 0x20c4 },
+ { .addr = 0x20c8 },
+ { .addr = 0x20cc },
+ { .addr = 0x20d0 },
+ { .addr = 0x20e0 },
+ { .addr = 0x20e4 },
+ { .addr = 0x20e8 },
+ { .addr = 0x20ec },
+ { .addr = 0x20f0 },
+ { .addr = 0x20f4 },
+ { .addr = 0x20f8 },
+ { .addr = 0x20fc },
+ { .addr = 0x2500 },
+ { .addr = 0x2504 },
+ { .addr = 0x2508 },
+ { .addr = 0x250c },
+ { .addr = 0x2510 },
+ { .addr = 0x2514 },
+ { .addr = 0x2518 },
+ { .addr = 0x251c },
+ { .addr = 0x2520 },
+ { .addr = 0x2524 },
+ { .addr = 0x2528 },
+ { .addr = 0x252c },
+ { .addr = 0x2530 },
+ { .addr = 0x2534 },
+ { .addr = 0x2538 },
+ { .addr = 0x253c },
+ { .addr = 0x2540 },
+ { .addr = 0x2600 },
+ { .addr = 0x2604 },
+ { .addr = 0x2608 },
+ { .addr = 0x260c },
+ { .addr = 0x2610 },
+ { .addr = 0x2614 },
+ { .addr = 0x2618 },
+ { .addr = 0x261c },
+ { .addr = 0x2620 },
+ { .addr = 0x2624 },
+ { .addr = 0x2628 },
+ { .addr = 0x262c },
+ { .addr = 0x2630 },
+ { .addr = 0x2634 },
+ { .addr = 0x2638 },
+ { .addr = 0x263c },
+ { .addr = 0x2640 },
+ { .addr = 0x26fc },
+ { .addr = 0x2700 },
+ { .addr = 0x2704 },
+ { .addr = 0x2708 },
+ { .addr = 0x270c },
+ { .addr = 0x2710 },
+ { .addr = 0x2714 },
+ { .addr = 0x2718 },
+ { .addr = 0x271c },
+ { .addr = 0x2720 },
+ { .addr = 0x2724 },
+ { .addr = 0x2728 },
+ { .addr = 0x2780 },
+ { .addr = 0x2784 },
+ { .addr = 0x2788 },
+};
+
+static struct cudbg_indir_reg t7_hmat6_local_debug_cfg[32] = {
+ { .addr = 0xa000 },
+ { .addr = 0xa001 },
+ { .addr = 0xa002 },
+ { .addr = 0xa003 },
+ { .addr = 0xa004 },
+ { .addr = 0xa005 },
+ { .addr = 0xa006 },
+ { .addr = 0xa007 },
+ { .addr = 0xa008 },
+ { .addr = 0xa009 },
+ { .addr = 0xa00a },
+ { .addr = 0xa00b },
+ { .addr = 0xa00c },
+ { .addr = 0xa00d },
+ { .addr = 0xa00e },
+ { .addr = 0xa00f },
+ { .addr = 0xa010 },
+ { .addr = 0xa011 },
+ { .addr = 0xa012 },
+ { .addr = 0xa013 },
+ { .addr = 0xa014 },
+ { .addr = 0xa015 },
+ { .addr = 0xa016 },
+ { .addr = 0xa017 },
+ { .addr = 0xa018 },
+ { .addr = 0xa019 },
+ { .addr = 0xa01a },
+ { .addr = 0xa01b },
+ { .addr = 0xa01c },
+ { .addr = 0xa01d },
+ { .addr = 0xa01e },
+ { .addr = 0xa01f },
+};
+
+static struct cudbg_indir_reg t7_ma_local_debug_cfg[238] = {
+ { .addr = 0xa000 },
+ { .addr = 0xa001 },
+ { .addr = 0xa002 },
+ { .addr = 0xa003 },
+ { .addr = 0xa004 },
+ { .addr = 0xa005 },
+ { .addr = 0xa006 },
+ { .addr = 0xa007 },
+ { .addr = 0xa008 },
+ { .addr = 0xa009 },
+ { .addr = 0xa00a },
+ { .addr = 0xa00b },
+ { .addr = 0xa00c },
+ { .addr = 0xa00d },
+ { .addr = 0xa00e },
+ { .addr = 0xa00f },
+ { .addr = 0xa010 },
+ { .addr = 0xa011 },
+ { .addr = 0xa012 },
+ { .addr = 0xa013 },
+ { .addr = 0xa014 },
+ { .addr = 0xa015 },
+ { .addr = 0xa016 },
+ { .addr = 0xa400 },
+ { .addr = 0xa401 },
+ { .addr = 0xa402 },
+ { .addr = 0xa403 },
+ { .addr = 0xa404 },
+ { .addr = 0xa405 },
+ { .addr = 0xa406 },
+ { .addr = 0xa407 },
+ { .addr = 0xa408 },
+ { .addr = 0xa409 },
+ { .addr = 0xa40a },
+ { .addr = 0xa40b },
+ { .addr = 0xa40c },
+ { .addr = 0xa40d },
+ { .addr = 0xa40e },
+ { .addr = 0xa40f },
+ { .addr = 0xa410 },
+ { .addr = 0xa412 },
+ { .addr = 0xa413 },
+ { .addr = 0xa414 },
+ { .addr = 0xa415 },
+ { .addr = 0xa416 },
+ { .addr = 0xa417 },
+ { .addr = 0xa418 },
+ { .addr = 0xa419 },
+ { .addr = 0xa41a },
+ { .addr = 0xa41b },
+ { .addr = 0xa41c },
+ { .addr = 0xa41d },
+ { .addr = 0xa41e },
+ { .addr = 0xa800 },
+ { .addr = 0xa801 },
+ { .addr = 0xa802 },
+ { .addr = 0xa803 },
+ { .addr = 0xa804 },
+ { .addr = 0xa805 },
+ { .addr = 0xa806 },
+ { .addr = 0xa807 },
+ { .addr = 0xa808 },
+ { .addr = 0xa809 },
+ { .addr = 0xa80a },
+ { .addr = 0xa80b },
+ { .addr = 0xa80c },
+ { .addr = 0xa80d },
+ { .addr = 0xa80e },
+ { .addr = 0xa80f },
+ { .addr = 0xa810 },
+ { .addr = 0xa811 },
+ { .addr = 0xa812 },
+ { .addr = 0xa813 },
+ { .addr = 0xac00 },
+ { .addr = 0xac01 },
+ { .addr = 0xac02 },
+ { .addr = 0xac03 },
+ { .addr = 0xac04 },
+ { .addr = 0xac05 },
+ { .addr = 0xac06 },
+ { .addr = 0xac07 },
+ { .addr = 0xac08 },
+ { .addr = 0xac09 },
+ { .addr = 0xac0a },
+ { .addr = 0xac0b },
+ { .addr = 0xac0c },
+ { .addr = 0xac0d },
+ { .addr = 0xac0e },
+ { .addr = 0xac0f },
+ { .addr = 0xac10 },
+ { .addr = 0xac11 },
+ { .addr = 0xac12 },
+ { .addr = 0xac13 },
+ { .addr = 0xac14 },
+ { .addr = 0xac15 },
+ { .addr = 0xac16 },
+ { .addr = 0xac17 },
+ { .addr = 0xac18 },
+ { .addr = 0xac19 },
+ { .addr = 0xb000 },
+ { .addr = 0xb001 },
+ { .addr = 0xb002 },
+ { .addr = 0xb003 },
+ { .addr = 0xb004 },
+ { .addr = 0xb005 },
+ { .addr = 0xb006 },
+ { .addr = 0xb007 },
+ { .addr = 0xb008 },
+ { .addr = 0xb009 },
+ { .addr = 0xb00a },
+ { .addr = 0xb00b },
+ { .addr = 0xb00c },
+ { .addr = 0xb00d },
+ { .addr = 0xb00e },
+ { .addr = 0xb00f },
+ { .addr = 0xb010 },
+ { .addr = 0xb011 },
+ { .addr = 0xb012 },
+ { .addr = 0xb013 },
+ { .addr = 0xb014 },
+ { .addr = 0xb015 },
+ { .addr = 0xb016 },
+ { .addr = 0xb017 },
+ { .addr = 0xb018 },
+ { .addr = 0xb019 },
+ { .addr = 0xb400 },
+ { .addr = 0xb401 },
+ { .addr = 0xb402 },
+ { .addr = 0xb403 },
+ { .addr = 0xb404 },
+ { .addr = 0xb405 },
+ { .addr = 0xb406 },
+ { .addr = 0xb407 },
+ { .addr = 0xb408 },
+ { .addr = 0xb409 },
+ { .addr = 0xb40a },
+ { .addr = 0xb40b },
+ { .addr = 0xb40c },
+ { .addr = 0xb40d },
+ { .addr = 0xb40e },
+ { .addr = 0xb40f },
+ { .addr = 0xb410 },
+ { .addr = 0xb411 },
+ { .addr = 0xb412 },
+ { .addr = 0xb413 },
+ { .addr = 0xb414 },
+ { .addr = 0xb415 },
+ { .addr = 0xb416 },
+ { .addr = 0xb417 },
+ { .addr = 0xb418 },
+ { .addr = 0xb419 },
+ { .addr = 0xe400 },
+ { .addr = 0xe420 },
+ { .addr = 0xe440 },
+ { .addr = 0xe460 },
+ { .addr = 0xe480 },
+ { .addr = 0xe4a0 },
+ { .addr = 0xe4c0 },
+ { .addr = 0xe4e0 },
+ { .addr = 0xe500 },
+ { .addr = 0xe520 },
+ { .addr = 0xe540 },
+ { .addr = 0xe560 },
+ { .addr = 0xe580 },
+ { .addr = 0xe5a0 },
+ { .addr = 0xe5c0 },
+ { .addr = 0xe5e0 },
+ { .addr = 0xe600 },
+ { .addr = 0xe640 },
+ { .addr = 0xe660 },
+ { .addr = 0xe680 },
+ { .addr = 0xe6a0 },
+ { .addr = 0xe6c0 },
+ { .addr = 0xe6e0 },
+ { .addr = 0xe700 },
+ { .addr = 0xe720 },
+ { .addr = 0xe740 },
+ { .addr = 0xe760 },
+ { .addr = 0xe780 },
+ { .addr = 0xe7a0 },
+ { .addr = 0xe7c0 },
+ { .addr = 0xe800 },
+ { .addr = 0xe820 },
+ { .addr = 0xe840 },
+ { .addr = 0xe860 },
+ { .addr = 0xe880 },
+ { .addr = 0xe8a0 },
+ { .addr = 0xe8c0 },
+ { .addr = 0xe8e0 },
+ { .addr = 0xe900 },
+ { .addr = 0xe920 },
+ { .addr = 0xe940 },
+ { .addr = 0xe960 },
+ { .addr = 0xe980 },
+ { .addr = 0xe9a0 },
+ { .addr = 0xe9c0 },
+ { .addr = 0xe9e0 },
+ { .addr = 0xec00 },
+ { .addr = 0xec20 },
+ { .addr = 0xec40 },
+ { .addr = 0xec60 },
+ { .addr = 0xec80 },
+ { .addr = 0xeca0 },
+ { .addr = 0xecc0 },
+ { .addr = 0xece0 },
+ { .addr = 0xed00 },
+ { .addr = 0xed20 },
+ { .addr = 0xed40 },
+ { .addr = 0xed60 },
+ { .addr = 0xed80 },
+ { .addr = 0xeda0 },
+ { .addr = 0xedc0 },
+ { .addr = 0xede0 },
+ { .addr = 0xee00 },
+ { .addr = 0xee20 },
+ { .addr = 0xee40 },
+ { .addr = 0xee60 },
+ { .addr = 0xee80 },
+ { .addr = 0xeea0 },
+ { .addr = 0xeec0 },
+ { .addr = 0xeee0 },
+ { .addr = 0xef00 },
+ { .addr = 0xef20 },
+ { .addr = 0xf000 },
+ { .addr = 0xf020 },
+ { .addr = 0xf040 },
+ { .addr = 0xf100 },
+ { .addr = 0xf101 },
+ { .addr = 0xf102 },
+ { .addr = 0xf103 },
+ { .addr = 0xf104 },
+ { .addr = 0xf105 },
+ { .addr = 0xf106 },
+ { .addr = 0xf107 },
+ { .addr = 0xf108 },
+ { .addr = 0xf120 },
+ { .addr = 0xf140 },
+ { .addr = 0xf160 },
+};
+
+static struct cudbg_indir_reg t7_ma_local_debug_perf_cfg[4] = {
+ { .addr = 0xa000 },
+ { .addr = 0xa1e0 },
+ { .addr = 0xe000 },
+ { .addr = 0xe1e0 },
+};
+
+static struct cudbg_indir_reg t7_pm_rx_dbg_ctrl[57] = {
+ { .addr = 0x10013 },
+ { .addr = 0x10014 },
+ { .addr = 0x10015 },
+ { .addr = 0x10016 },
+ { .addr = 0x10019 },
+ { .addr = 0x1001a },
+ { .addr = 0x1001b },
+ { .addr = 0x1001c },
+ { .addr = 0x1001d },
+ { .addr = 0x10020 },
+ { .addr = 0x10021 },
+ { .addr = 0x10022 },
+ { .addr = 0x10023 },
+ { .addr = 0x10024 },
+ { .addr = 0x10025 },
+ { .addr = 0x10026 },
+ { .addr = 0x10027 },
+ { .addr = 0x10028 },
+ { .addr = 0x10029 },
+ { .addr = 0x1002a },
+ { .addr = 0x1002b },
+ { .addr = 0x1002c },
+ { .addr = 0x1002d },
+ { .addr = 0x1002e },
+ { .addr = 0x1002f },
+ { .addr = 0x10030 },
+ { .addr = 0x10031 },
+ { .addr = 0x10032 },
+ { .addr = 0x10033 },
+ { .addr = 0x10034 },
+ { .addr = 0x10035 },
+ { .addr = 0x10036 },
+ { .addr = 0x10037 },
+ { .addr = 0x10038 },
+ { .addr = 0x10039 },
+ { .addr = 0x1003a },
+ { .addr = 0x1003b },
+ { .addr = 0x1003c },
+ { .addr = 0x1003d },
+ { .addr = 0x1003e },
+ { .addr = 0x10049 },
+ { .addr = 0x10060 },
+ { .addr = 0x10061 },
+ { .addr = 0x10062 },
+ { .addr = 0x10063 },
+ { .addr = 0x10070 },
+ { .addr = 0x10071 },
+ { .addr = 0x10072 },
+ { .addr = 0x10073 },
+ { .addr = 0x10074 },
+ { .addr = 0x10075 },
+ { .addr = 0x10076 },
+ { .addr = 0x10077 },
+ { .addr = 0x10078 },
+ { .addr = 0x10080 },
+ { .addr = 0x10081 },
+ { .addr = 0x10082 },
+};
+
+static struct cudbg_indir_reg t7_pm_tx_dbg_ctrl[38] = {
+ { .addr = 0x10000 },
+ { .addr = 0x10001 },
+ { .addr = 0x10002 },
+ { .addr = 0x10003 },
+ { .addr = 0x10004 },
+ { .addr = 0x10005 },
+ { .addr = 0x10006 },
+ { .addr = 0x10007 },
+ { .addr = 0x10008 },
+ { .addr = 0x10009 },
+ { .addr = 0x1000a },
+ { .addr = 0x1000b },
+ { .addr = 0x1000c },
+ { .addr = 0x1000d },
+ { .addr = 0x1000e },
+ { .addr = 0x1000f },
+ { .addr = 0x10010 },
+ { .addr = 0x10011 },
+ { .addr = 0x10012 },
+ { .addr = 0x10013 },
+ { .addr = 0x10014 },
+ { .addr = 0x10015 },
+ { .addr = 0x10016 },
+ { .addr = 0x10017 },
+ { .addr = 0x10018 },
+ { .addr = 0x10019 },
+ { .addr = 0x1001a },
+ { .addr = 0x1001b },
+ { .addr = 0x1001c },
+ { .addr = 0x1001d },
+ { .addr = 0x1001e },
+ { .addr = 0x1001f },
+ { .addr = 0x10020 },
+ { .addr = 0x10021 },
+ { .addr = 0x10022 },
+ { .addr = 0x10023 },
+ { .addr = 0x10024 },
+ { .addr = 0x10025 },
+};
+
+static struct cudbg_indir_reg t7_tp_mib_index[130] = {
+ { .addr = 0x0 },
+ { .addr = 0x1 },
+ { .addr = 0x2 },
+ { .addr = 0x3 },
+ { .addr = 0x4 },
+ { .addr = 0x5 },
+ { .addr = 0x6 },
+ { .addr = 0x7 },
+ { .addr = 0x8 },
+ { .addr = 0x9 },
+ { .addr = 0xa },
+ { .addr = 0xb },
+ { .addr = 0xc },
+ { .addr = 0x10 },
+ { .addr = 0x11 },
+ { .addr = 0x12 },
+ { .addr = 0x13 },
+ { .addr = 0x14 },
+ { .addr = 0x15 },
+ { .addr = 0x18 },
+ { .addr = 0x19 },
+ { .addr = 0x1a },
+ { .addr = 0x1b },
+ { .addr = 0x1c },
+ { .addr = 0x1d },
+ { .addr = 0x1e },
+ { .addr = 0x1f },
+ { .addr = 0x20 },
+ { .addr = 0x21 },
+ { .addr = 0x22 },
+ { .addr = 0x23 },
+ { .addr = 0x24 },
+ { .addr = 0x25 },
+ { .addr = 0x26 },
+ { .addr = 0x27 },
+ { .addr = 0x28 },
+ { .addr = 0x29 },
+ { .addr = 0x2a },
+ { .addr = 0x2b },
+ { .addr = 0x2c },
+ { .addr = 0x30 },
+ { .addr = 0x31 },
+ { .addr = 0x32 },
+ { .addr = 0x33 },
+ { .addr = 0x34 },
+ { .addr = 0x35 },
+ { .addr = 0x36 },
+ { .addr = 0x37 },
+ { .addr = 0x38 },
+ { .addr = 0x39 },
+ { .addr = 0x3a },
+ { .addr = 0x3b },
+ { .addr = 0x3c },
+ { .addr = 0x3d },
+ { .addr = 0x3e },
+ { .addr = 0x3f },
+ { .addr = 0x40 },
+ { .addr = 0x41 },
+ { .addr = 0x42 },
+ { .addr = 0x43 },
+ { .addr = 0x44 },
+ { .addr = 0x45 },
+ { .addr = 0x46 },
+ { .addr = 0x47 },
+ { .addr = 0x48 },
+ { .addr = 0x49 },
+ { .addr = 0x4a },
+ { .addr = 0x4b },
+ { .addr = 0x4c },
+ { .addr = 0x4d },
+ { .addr = 0x4e },
+ { .addr = 0x4f },
+ { .addr = 0x50 },
+ { .addr = 0x51 },
+ { .addr = 0x52 },
+ { .addr = 0x53 },
+ { .addr = 0x54 },
+ { .addr = 0x55 },
+ { .addr = 0x56 },
+ { .addr = 0x57 },
+ { .addr = 0x58 },
+ { .addr = 0x59 },
+ { .addr = 0x5a },
+ { .addr = 0x5b },
+ { .addr = 0x5c },
+ { .addr = 0x5d },
+ { .addr = 0x5e },
+ { .addr = 0x5f },
+ { .addr = 0x60 },
+ { .addr = 0x61 },
+ { .addr = 0x62 },
+ { .addr = 0x63 },
+ { .addr = 0x64 },
+ { .addr = 0x65 },
+ { .addr = 0x68 },
+ { .addr = 0x69 },
+ { .addr = 0x6a },
+ { .addr = 0x6b },
+ { .addr = 0x6c },
+ { .addr = 0x6d },
+ { .addr = 0x6e },
+ { .addr = 0x6f },
+ { .addr = 0x70 },
+ { .addr = 0x71 },
+ { .addr = 0x72 },
+ { .addr = 0x73 },
+ { .addr = 0x80 },
+ { .addr = 0x81 },
+ { .addr = 0x82 },
+ { .addr = 0x83 },
+ { .addr = 0x84 },
+ { .addr = 0x85 },
+ { .addr = 0x86 },
+ { .addr = 0x87 },
+ { .addr = 0x88 },
+ { .addr = 0x89 },
+ { .addr = 0x8a },
+ { .addr = 0x8b },
+ { .addr = 0x90 },
+ { .addr = 0x91 },
+ { .addr = 0x92 },
+ { .addr = 0x93 },
+ { .addr = 0x94 },
+ { .addr = 0x95 },
+ { .addr = 0x96 },
+ { .addr = 0x97 },
+ { .addr = 0x98 },
+ { .addr = 0x99 },
+ { .addr = 0x9a },
+ { .addr = 0x9b },
+};
+
+static struct cudbg_indir_reg t7_tp_pio_addr[191] = {
+ { .addr = 0x1c },
+ { .addr = 0x1d },
+ { .addr = 0x1e },
+ { .addr = 0x1f },
+ { .addr = 0x20 },
+ { .addr = 0x21 },
+ { .addr = 0x22 },
+ { .addr = 0x23 },
+ { .addr = 0x24 },
+ { .addr = 0x25 },
+ { .addr = 0x26 },
+ { .addr = 0x27 },
+ { .addr = 0x28 },
+ { .addr = 0x29 },
+ { .addr = 0x2a },
+ { .addr = 0x2b },
+ { .addr = 0x2c },
+ { .addr = 0x2d },
+ { .addr = 0x2e },
+ { .addr = 0x2f },
+ { .addr = 0x30 },
+ { .addr = 0x31 },
+ { .addr = 0x32 },
+ { .addr = 0x33 },
+ { .addr = 0x34 },
+ { .addr = 0x35 },
+ { .addr = 0x36 },
+ { .addr = 0x37 },
+ { .addr = 0x38 },
+ { .addr = 0x39 },
+ { .addr = 0x3a },
+ { .addr = 0x3b },
+ { .addr = 0x40 },
+ { .addr = 0x41 },
+ { .addr = 0x42 },
+ { .addr = 0x43 },
+ { .addr = 0x44 },
+ { .addr = 0x45 },
+ { .addr = 0x46 },
+ { .addr = 0x47 },
+ { .addr = 0x48 },
+ { .addr = 0x49 },
+ { .addr = 0x50 },
+ { .addr = 0x51 },
+ { .addr = 0x52 },
+ { .addr = 0x53 },
+ { .addr = 0x54 },
+ { .addr = 0x55 },
+ { .addr = 0x56 },
+ { .addr = 0x57 },
+ { .addr = 0x58 },
+ { .addr = 0x59 },
+ { .addr = 0x60 },
+ { .addr = 0x61 },
+ { .addr = 0x62 },
+ { .addr = 0x63 },
+ { .addr = 0x64 },
+ { .addr = 0x65 },
+ { .addr = 0x66 },
+ { .addr = 0x67 },
+ { .addr = 0x68 },
+ { .addr = 0x69 },
+ { .addr = 0x6a },
+ { .addr = 0x6b },
+ { .addr = 0x6c },
+ { .addr = 0x6d },
+ { .addr = 0x6f },
+ { .addr = 0x70 },
+ { .addr = 0x71 },
+ { .addr = 0x72 },
+ { .addr = 0x73 },
+ { .addr = 0x74 },
+ { .addr = 0x75 },
+ { .addr = 0x80 },
+ { .addr = 0x81 },
+ { .addr = 0x82 },
+ { .addr = 0x83 },
+ { .addr = 0x84 },
+ { .addr = 0x85 },
+ { .addr = 0x86 },
+ { .addr = 0x87 },
+ { .addr = 0x88 },
+ { .addr = 0x89 },
+ { .addr = 0x8a },
+ { .addr = 0x8b },
+ { .addr = 0x8c },
+ { .addr = 0x8d },
+ { .addr = 0x8e },
+ { .addr = 0x8f },
+ { .addr = 0x90 },
+ { .addr = 0x91 },
+ { .addr = 0x92 },
+ { .addr = 0x93 },
+ { .addr = 0x94 },
+ { .addr = 0x95 },
+ { .addr = 0x96 },
+ { .addr = 0x97 },
+ { .addr = 0x98 },
+ { .addr = 0x99 },
+ { .addr = 0x130 },
+ { .addr = 0x131 },
+ { .addr = 0x132 },
+ { .addr = 0x133 },
+ { .addr = 0x134 },
+ { .addr = 0x135 },
+ { .addr = 0x136 },
+ { .addr = 0x137 },
+ { .addr = 0x138 },
+ { .addr = 0x139 },
+ { .addr = 0x13a },
+ { .addr = 0x13b },
+ { .addr = 0x13c },
+ { .addr = 0x13d },
+ { .addr = 0x13e },
+ { .addr = 0x13f },
+ { .addr = 0x140 },
+ { .addr = 0x141 },
+ { .addr = 0x145 },
+ { .addr = 0x146 },
+ { .addr = 0x147 },
+ { .addr = 0x148 },
+ { .addr = 0x149 },
+ { .addr = 0x14a },
+ { .addr = 0x14b },
+ { .addr = 0x14c },
+ { .addr = 0x14d },
+ { .addr = 0x14e },
+ { .addr = 0x14f },
+ { .addr = 0x150 },
+ { .addr = 0x151 },
+ { .addr = 0x152 },
+ { .addr = 0x153 },
+ { .addr = 0x154 },
+ { .addr = 0x155 },
+ { .addr = 0x156 },
+ { .addr = 0x157 },
+ { .addr = 0x158 },
+ { .addr = 0x159 },
+ { .addr = 0x15a },
+ { .addr = 0x15b },
+ { .addr = 0x160 },
+ { .addr = 0x161 },
+ { .addr = 0x162 },
+ { .addr = 0x164 },
+ { .addr = 0x165 },
+ { .addr = 0x166 },
+ { .addr = 0x168 },
+ { .addr = 0x169 },
+ { .addr = 0x230 },
+ { .addr = 0x231 },
+ { .addr = 0x232 },
+ { .addr = 0x233 },
+ { .addr = 0x234 },
+ { .addr = 0x235 },
+ { .addr = 0x236 },
+ { .addr = 0x237 },
+ { .addr = 0x238 },
+ { .addr = 0x239 },
+ { .addr = 0x23a },
+ { .addr = 0x23b },
+ { .addr = 0x23c },
+ { .addr = 0x23d },
+ { .addr = 0x23e },
+ { .addr = 0x23f },
+ { .addr = 0x240 },
+ { .addr = 0x241 },
+ { .addr = 0x242 },
+ { .addr = 0x243 },
+ { .addr = 0x244 },
+ { .addr = 0x245 },
+ { .addr = 0x246 },
+ { .addr = 0x247 },
+ { .addr = 0x248 },
+ { .addr = 0x24a },
+ { .addr = 0x24b },
+ { .addr = 0x24c },
+ { .addr = 0x24d },
+ { .addr = 0x24e },
+ { .addr = 0x24f },
+ { .addr = 0x250 },
+ { .addr = 0x251 },
+ { .addr = 0x252 },
+ { .addr = 0x253 },
+ { .addr = 0x254 },
+ { .addr = 0x255 },
+ { .addr = 0x256 },
+ { .addr = 0x257 },
+ { .addr = 0x258 },
+ { .addr = 0x259 },
+ { .addr = 0x260 },
+ { .addr = 0x8c0 },
+};
+
+static struct cudbg_indir_reg t7_tp_tm_pio_addr[14] = {
+ { .addr = 0x0 },
+ { .addr = 0x1 },
+ { .addr = 0x2 },
+ { .addr = 0x3 },
+ { .addr = 0x4 },
+ { .addr = 0x5 },
+ { .addr = 0x6 },
+ { .addr = 0x7 },
+ { .addr = 0x8 },
+ { .addr = 0x9 },
+ { .addr = 0xa },
+ { .addr = 0xb },
+ { .addr = 0xc },
+ { .addr = 0xd },
+};
+
+static struct cudbg_indir_reg t7_up[245] = {
+ { .addr = 0x0 },
+ { .addr = 0x4 },
+ { .addr = 0x8 },
+ { .addr = 0xc },
+ { .addr = 0x10 },
+ { .addr = 0x80 },
+ { .addr = 0x84 },
+ { .addr = 0x88 },
+ { .addr = 0x8c },
+ { .addr = 0x90 },
+ { .addr = 0xc0 },
+ { .addr = 0xc4 },
+ { .addr = 0xc8 },
+ { .addr = 0xcc },
+ { .addr = 0xd0 },
+ { .addr = 0xd4 },
+ { .addr = 0x100 },
+ { .addr = 0x104 },
+ { .addr = 0x108 },
+ { .addr = 0x10c },
+ { .addr = 0x110 },
+ { .addr = 0x114 },
+ { .addr = 0x118 },
+ { .addr = 0x11c },
+ { .addr = 0x120 },
+ { .addr = 0x130 },
+ { .addr = 0x140 },
+ { .addr = 0x144 },
+ { .addr = 0x14c },
+ { .addr = 0x200 },
+ { .addr = 0x204 },
+ { .addr = 0x208 },
+ { .addr = 0x20c },
+ { .addr = 0x210 },
+ { .addr = 0x214 },
+ { .addr = 0x218 },
+ { .addr = 0x21c },
+ { .addr = 0x220 },
+ { .addr = 0x224 },
+ { .addr = 0x228 },
+ { .addr = 0x22c },
+ { .addr = 0x230 },
+ { .addr = 0x234 },
+ { .addr = 0x238 },
+ { .addr = 0x23c },
+ { .addr = 0x240 },
+ { .addr = 0x244 },
+ { .addr = 0x250 },
+ { .addr = 0x254 },
+ { .addr = 0x260 },
+ { .addr = 0x264 },
+ { .addr = 0x270 },
+ { .addr = 0x274 },
+ { .addr = 0x400 },
+ { .addr = 0x404 },
+ { .addr = 0x408 },
+ { .addr = 0x40c },
+ { .addr = 0x410 },
+ { .addr = 0x414 },
+ { .addr = 0x418 },
+ { .addr = 0x41c },
+ { .addr = 0x420 },
+ { .addr = 0x424 },
+ { .addr = 0x428 },
+ { .addr = 0x42c },
+ { .addr = 0x430 },
+ { .addr = 0x434 },
+ { .addr = 0x438 },
+ { .addr = 0x43c },
+ { .addr = 0x440 },
+ { .addr = 0x444 },
+ { .addr = 0x448 },
+ { .addr = 0x44c },
+ { .addr = 0x450 },
+ { .addr = 0x454 },
+ { .addr = 0x458 },
+ { .addr = 0x45c },
+ { .addr = 0x460 },
+ { .addr = 0x464 },
+ { .addr = 0x468 },
+ { .addr = 0x46c },
+ { .addr = 0x470 },
+ { .addr = 0x474 },
+ { .addr = 0x478 },
+ { .addr = 0x47c },
+ { .addr = 0x480 },
+ { .addr = 0x484 },
+ { .addr = 0x488 },
+ { .addr = 0x48c },
+ { .addr = 0x490 },
+ { .addr = 0x494 },
+ { .addr = 0x498 },
+ { .addr = 0x49c },
+ { .addr = 0x4a0 },
+ { .addr = 0x4a4 },
+ { .addr = 0x4a8 },
+ { .addr = 0x4ac },
+ { .addr = 0x4b0 },
+ { .addr = 0x4b4 },
+ { .addr = 0x4b8 },
+ { .addr = 0x4bc },
+ { .addr = 0x4c0 },
+ { .addr = 0x4c4 },
+ { .addr = 0x4c8 },
+ { .addr = 0x4cc },
+ { .addr = 0x4d0 },
+ { .addr = 0x4d4 },
+ { .addr = 0x4d8 },
+ { .addr = 0x4dc },
+ { .addr = 0x4e0 },
+ { .addr = 0x4e4 },
+ { .addr = 0x4e8 },
+ { .addr = 0x4ec },
+ { .addr = 0x4f0 },
+ { .addr = 0x4f4 },
+ { .addr = 0x4f8 },
+ { .addr = 0x4fc },
+ { .addr = 0x500 },
+ { .addr = 0x504 },
+ { .addr = 0x510 },
+ { .addr = 0x514 },
+ { .addr = 0x520 },
+ { .addr = 0x524 },
+ { .addr = 0x530 },
+ { .addr = 0x534 },
+ { .addr = 0x540 },
+ { .addr = 0x544 },
+ { .addr = 0x550 },
+ { .addr = 0x554 },
+ { .addr = 0x560 },
+ { .addr = 0x564 },
+ { .addr = 0x570 },
+ { .addr = 0x574 },
+ { .addr = 0x580 },
+ { .addr = 0x584 },
+ { .addr = 0x590 },
+ { .addr = 0x594 },
+ { .addr = 0x5a0 },
+ { .addr = 0x5a4 },
+ { .addr = 0x5b0 },
+ { .addr = 0x5b4 },
+ { .addr = 0x5c0 },
+ { .addr = 0x5c4 },
+ { .addr = 0x5d0 },
+ { .addr = 0x5d4 },
+ { .addr = 0x5e0 },
+ { .addr = 0x5e4 },
+ { .addr = 0x5f0 },
+ { .addr = 0x5f4 },
+ { .addr = 0x600 },
+ { .addr = 0x604 },
+ { .addr = 0x608 },
+ { .addr = 0x60c },
+ { .addr = 0x610 },
+ { .addr = 0x614 },
+ { .addr = 0x618 },
+ { .addr = 0x61c },
+ { .addr = 0x620 },
+ { .addr = 0x624 },
+ { .addr = 0x628 },
+ { .addr = 0x62c },
+ { .addr = 0x630 },
+ { .addr = 0x634 },
+ { .addr = 0x638 },
+ { .addr = 0x63c },
+ { .addr = 0x640 },
+ { .addr = 0x644 },
+ { .addr = 0x648 },
+ { .addr = 0x64c },
+ { .addr = 0x650 },
+ { .addr = 0x654 },
+ { .addr = 0x658 },
+ { .addr = 0x65c },
+ { .addr = 0x660 },
+ { .addr = 0x664 },
+ { .addr = 0x668 },
+ { .addr = 0x66c },
+ { .addr = 0x670 },
+ { .addr = 0x674 },
+ { .addr = 0x678 },
+ { .addr = 0x67c },
+ { .addr = 0x680 },
+ { .addr = 0x684 },
+ { .addr = 0x688 },
+ { .addr = 0x68c },
+ { .addr = 0x690 },
+ { .addr = 0x694 },
+ { .addr = 0x698 },
+ { .addr = 0x69c },
+ { .addr = 0x6a0 },
+ { .addr = 0x6a4 },
+ { .addr = 0x6a8 },
+ { .addr = 0x6ac },
+ { .addr = 0x6b0 },
+ { .addr = 0x6b4 },
+ { .addr = 0x6b8 },
+ { .addr = 0x6bc },
+ { .addr = 0x6c0 },
+ { .addr = 0x6c4 },
+ { .addr = 0x6c8 },
+ { .addr = 0x6cc },
+ { .addr = 0x6d0 },
+ { .addr = 0x6d4 },
+ { .addr = 0x6d8 },
+ { .addr = 0x6dc },
+ { .addr = 0x6e0 },
+ { .addr = 0x6e4 },
+ { .addr = 0x6e8 },
+ { .addr = 0x6ec },
+ { .addr = 0x6f0 },
+ { .addr = 0x6f4 },
+ { .addr = 0x6f8 },
+ { .addr = 0x6fc },
+ { .addr = 0x700 },
+ { .addr = 0x704 },
+ { .addr = 0x710 },
+ { .addr = 0x714 },
+ { .addr = 0x720 },
+ { .addr = 0x724 },
+ { .addr = 0x730 },
+ { .addr = 0x734 },
+ { .addr = 0x740 },
+ { .addr = 0x744 },
+ { .addr = 0x750 },
+ { .addr = 0x754 },
+ { .addr = 0x760 },
+ { .addr = 0x764 },
+ { .addr = 0x770 },
+ { .addr = 0x774 },
+ { .addr = 0x780 },
+ { .addr = 0x784 },
+ { .addr = 0x790 },
+ { .addr = 0x794 },
+ { .addr = 0x7a0 },
+ { .addr = 0x7a4 },
+ { .addr = 0x7b0 },
+ { .addr = 0x7b4 },
+ { .addr = 0x7c0 },
+ { .addr = 0x7c4 },
+ { .addr = 0x7d0 },
+ { .addr = 0x7d4 },
+ { .addr = 0x7e0 },
+ { .addr = 0x7e4 },
+ { .addr = 0x7f0 },
+ { .addr = 0x7f4 },
+};
+
+static struct cudbg_indir_type_entry t7_indir_type_arr[CUDBG_INDIR_TYPE_MAX] = {
+ [CUDBG_INDIR_TYPE_CIM_CTL] = {
+ .reg_arr = t7_cim_ctl,
+ .nentries = ARRAY_SIZE(t7_cim_ctl),
+ },
+ [CUDBG_INDIR_TYPE_HMAT6_LOCAL_DEBUG_CFG] = {
+ .reg_arr = t7_hmat6_local_debug_cfg,
+ .nentries = ARRAY_SIZE(t7_hmat6_local_debug_cfg),
+ },
+ [CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_CFG] = {
+ .reg_arr = t7_ma_local_debug_cfg,
+ .nentries = ARRAY_SIZE(t7_ma_local_debug_cfg),
+ },
+ [CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_PERF_CFG] = {
+ .reg_arr = t7_ma_local_debug_perf_cfg,
+ .nentries = ARRAY_SIZE(t7_ma_local_debug_perf_cfg),
+ },
+ [CUDBG_INDIR_TYPE_PM_RX_DBG_CTRL] = {
+ .reg_arr = t7_pm_rx_dbg_ctrl,
+ .nentries = ARRAY_SIZE(t7_pm_rx_dbg_ctrl),
+ },
+ [CUDBG_INDIR_TYPE_PM_TX_DBG_CTRL] = {
+ .reg_arr = t7_pm_tx_dbg_ctrl,
+ .nentries = ARRAY_SIZE(t7_pm_tx_dbg_ctrl),
+ },
+ [CUDBG_INDIR_TYPE_TP_MIB_INDEX] = {
+ .reg_arr = t7_tp_mib_index,
+ .nentries = ARRAY_SIZE(t7_tp_mib_index),
+ },
+ [CUDBG_INDIR_TYPE_TP_PIO_ADDR] = {
+ .reg_arr = t7_tp_pio_addr,
+ .nentries = ARRAY_SIZE(t7_tp_pio_addr),
+ },
+ [CUDBG_INDIR_TYPE_TP_TM_PIO_ADDR] = {
+ .reg_arr = t7_tp_tm_pio_addr,
+ .nentries = ARRAY_SIZE(t7_tp_tm_pio_addr),
+ },
+ [CUDBG_INDIR_TYPE_UP] = {
+ .reg_arr = t7_up,
+ .nentries = ARRAY_SIZE(t7_up),
+ },
+};
+
+#endif /* __CUDBG_INDIR_REG_T7_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
index 557c591a6ce3..a55e0a09a25e 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
@@ -15,6 +15,7 @@
#include "cudbg_lib.h"
#include "cudbg_zlib.h"
#include "cxgb4_tc_mqprio.h"
+#include "cudbg_indir_reg.h"
static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
@@ -198,7 +199,7 @@ u32 cudbg_get_entity_length(struct adapter *adap, u32 entity)
}
break;
case CUDBG_DEV_LOG:
- len = adap->params.devlog.size;
+ len = adap->params.devlog[0].size;
break;
case CUDBG_CIM_LA:
if (is_t6(adap->params.chip)) {
@@ -214,7 +215,7 @@ u32 cudbg_get_entity_length(struct adapter *adap, u32 entity)
len = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
break;
case CUDBG_CIM_QCFG:
- len = sizeof(struct cudbg_cim_qcfg);
+ len = sizeof(struct cim_qcfg_rev1);
break;
case CUDBG_CIM_IBQ_TP0:
case CUDBG_CIM_IBQ_TP1:
@@ -350,7 +351,9 @@ u32 cudbg_get_entity_length(struct adapter *adap, u32 entity)
len = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;
break;
case CUDBG_DUMP_CONTEXT:
- len = cudbg_dump_context_size(adap);
+ len = cudbg_dump_context_size(adap, (CHELSIO_CHIP_VERSION(adap->params.chip) >=
+ CHELSIO_T7) ? SGE_CTXT_SIZE_T7 :
+ SGE_CTXT_SIZE);
break;
case CUDBG_MPS_TCAM:
len = sizeof(struct cudbg_mps_tcam) *
@@ -822,7 +825,7 @@ int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init,
if (is_t4(padap->params.chip))
buf_size = T4_REGMAP_SIZE;
- else if (is_t5(padap->params.chip) || is_t6(padap->params.chip))
+ else
buf_size = T5_REGMAP_SIZE;
rc = cudbg_get_buff(pdbg_init, dbg_buff, buf_size, &temp_buff);
@@ -839,15 +842,20 @@ int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init,
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
struct devlog_params *dparams;
+ u8 coreid = 0;
int rc = 0;
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
+ dparams = &padap->params.devlog[coreid];
rc = t4_init_devlog_params(padap);
if (rc < 0) {
cudbg_err->sys_err = rc;
return rc;
}
- dparams = &padap->params.devlog;
rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff);
if (rc)
return rc;
@@ -875,39 +883,52 @@ int cudbg_collect_cim_la(struct cudbg_init *pdbg_init,
struct cudbg_error *cudbg_err)
{
struct adapter *padap = pdbg_init->adap;
+ struct struct_cim_la_rev1 *cim_la_buff;
struct cudbg_buffer temp_buff = { 0 };
+ u8 ncol, coreid = 0;
int size, rc;
u32 cfg = 0;
+ u16 nrow;
- if (is_t6(padap->params.chip)) {
- size = padap->params.cim_la_size / 10 + 1;
- size *= 10 * sizeof(u32);
- } else {
- size = padap->params.cim_la_size / 8;
- size *= 8 * sizeof(u32);
- }
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6)
+ ncol = 10;
+ else
+ ncol = 8;
- size += sizeof(cfg);
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
+ nrow = padap->params.cim_la_size / ncol;
+ size = sizeof(*cim_la_buff) + padap->params.cim_la_size * sizeof(u32);
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
if (rc)
return rc;
- rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
+ cim_la_buff = (void *)temp_buff.data;
+ cim_la_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ cim_la_buff->ver_hdr.revision = CUDBG_CIM_LA_REV;
+ cim_la_buff->ver_hdr.size = sizeof(*cim_la_buff) -
+ sizeof(struct cudbg_ver_hdr);
+
+ rc = t4_cim_read_core(padap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1, &cfg);
if (rc) {
cudbg_err->sys_err = rc;
cudbg_put_buff(pdbg_init, &temp_buff);
return rc;
}
- memcpy((char *)temp_buff.data, &cfg, sizeof(cfg));
- rc = t4_cim_read_la(padap,
- (u32 *)((char *)temp_buff.data + sizeof(cfg)),
- NULL);
+ rc = t4_cim_read_la_core(padap, coreid, cim_la_buff->data, NULL);
if (rc < 0) {
cudbg_err->sys_err = rc;
cudbg_put_buff(pdbg_init, &temp_buff);
return rc;
}
+
+ cim_la_buff->coreid = coreid;
+ cim_la_buff->config = cfg;
+ cim_la_buff->ncol = ncol;
+ cim_la_buff->nrow = nrow;
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
@@ -931,41 +952,160 @@ int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
+static void cudbg_cim_qcfg_copy(struct cim_qcfg_rev1_data *data, u8 num_cim_ibq,
+ u8 num_cim_obq, u16 *base, u16 *size,
+ u16 *thres, u32 *stat, u32 *obq_wr)
+{
+ u8 i = 0;
+
+ while (i < num_cim_ibq) {
+ data->qtype = CUDBG_ENTITY_CIM_QCFG_QTYPE_IBQ;
+ data->qid = i;
+ data->base = *base;
+ data->size = *size;
+ data->thres = *thres;
+ memcpy(data->stat, stat, sizeof(data->stat));
+
+ stat += ARRAY_SIZE(data->stat);
+ thres++;
+ size++;
+ base++;
+ data++;
+ i++;
+ }
+
+ while (i < num_cim_ibq + num_cim_obq) {
+ data->qtype = CUDBG_ENTITY_CIM_QCFG_QTYPE_OBQ;
+ data->qid = i - num_cim_ibq;
+ data->base = *base;
+ data->size = *size;
+ memcpy(data->stat, stat, sizeof(data->stat));
+ memcpy(data->obq_wr, obq_wr, sizeof(data->obq_wr));
+
+ obq_wr += ARRAY_SIZE(data->obq_wr);
+ stat += ARRAY_SIZE(data->stat);
+ size++;
+ base++;
+ data++;
+ i++;
+ }
+}
+
+static int cudbg_collect_cim_qcfg_t5(struct cudbg_init *pdbg_init,
+ struct cim_qcfg_rev1_data *data,
+ u8 num_cim_ibq, u8 num_cim_obq)
+{
+ u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
+ struct adapter *padap = pdbg_init->adap;
+ u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
+ u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
+ u32 obq_wr[2 * CIM_NUM_OBQ_T5];
+ u16 thres[CIM_NUM_IBQ];
+ int ret;
+
+ ret = t4_cim_read(padap, UP_IBQ_0_SHADOW_RDADDR_A,
+ 4 * (num_cim_ibq + num_cim_obq), stat);
+ if (ret < 0)
+ return ret;
+
+ ret = t4_cim_read(padap, UP_OBQ_0_SHADOW_REALADDR_A, 2 * num_cim_obq,
+ obq_wr);
+ if (ret < 0)
+ return ret;
+
+ t4_read_cimq_cfg(padap, base, size, thres);
+
+ cudbg_cim_qcfg_copy(data, num_cim_ibq, num_cim_obq, base, size, thres,
+ stat, obq_wr);
+ return 0;
+}
+
+static int cudbg_collect_cim_qcfg_t7(struct cudbg_init *pdbg_init, u8 coreid,
+ struct cim_qcfg_rev1_data *data,
+ u8 num_cim_ibq, u8 num_cim_obq)
+{
+ u32 stat[4 * (CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7)];
+ u16 base[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+ u16 size[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+ struct adapter *padap = pdbg_init->adap;
+ u32 obq_wr[2 * CIM_NUM_OBQ_T7];
+ u16 thres[CIM_NUM_IBQ_T7];
+ u32 addr;
+ int ret;
+ u8 i;
+
+ ret = t4_cim_read_core(padap, 1, coreid, T7_UP_IBQ_0_SHADOW_RDADDR_A,
+ 4 * num_cim_ibq, stat);
+ if (ret < 0)
+ return ret;
+
+ ret = t4_cim_read_core(padap, 1, coreid, T7_UP_OBQ_0_SHADOW_RDADDR_A,
+ 4 * num_cim_obq, &stat[4 * num_cim_ibq]);
+ if (ret < 0)
+ return ret;
+
+ addr = T7_UP_OBQ_0_SHADOW_REALADDR_A;
+ for (i = 0; i < num_cim_obq * 2; i++, addr += 8) {
+ ret = t4_cim_read_core(padap, 1, coreid, addr, 1, &obq_wr[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ t4_read_cimq_cfg_core(padap, coreid, base, size, thres);
+
+ cudbg_cim_qcfg_copy(data, num_cim_ibq, num_cim_obq, base, size, thres,
+ stat, obq_wr);
+ return 0;
+}
+
int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
+ struct cim_qcfg_rev1 *cim_qcfg_buff;
+ u8 num_cim_ibq, num_cim_obq, coreid = 0;
struct adapter *padap = pdbg_init->adap;
+ struct cim_qcfg_rev1_data *data;
struct cudbg_buffer temp_buff = { 0 };
- struct cudbg_cim_qcfg *cim_qcfg_data;
+ u32 size;
int rc;
- rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_cim_qcfg),
- &temp_buff);
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
+ num_cim_ibq = t4_cim_num_ibq(padap);
+ num_cim_obq = t4_cim_num_obq(padap);
+ size = sizeof(*cim_qcfg_buff) +
+ ((num_cim_ibq + num_cim_obq) * sizeof(*data));
+
+ rc = get_scratch_buff(dbg_buff, size, &temp_buff);
if (rc)
return rc;
- cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data;
- cim_qcfg_data->chip = padap->params.chip;
- rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
- ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
- if (rc) {
- cudbg_err->sys_err = rc;
- cudbg_put_buff(pdbg_init, &temp_buff);
- return rc;
- }
+ cim_qcfg_buff = (void *)((u8 *)temp_buff.data + temp_buff.offset);
+ cim_qcfg_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ cim_qcfg_buff->ver_hdr.revision = CUDBG_CIM_QCFG_REV;
+ cim_qcfg_buff->ver_hdr.size = sizeof(*cim_qcfg_buff) -
+ sizeof(struct cudbg_ver_hdr);
- rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
- ARRAY_SIZE(cim_qcfg_data->obq_wr),
- cim_qcfg_data->obq_wr);
+ cim_qcfg_buff->num_cim_ibq = num_cim_ibq;
+ cim_qcfg_buff->num_cim_obq = num_cim_obq;
+ cim_qcfg_buff->coreid = coreid;
+ data = cim_qcfg_buff->data;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ rc = cudbg_collect_cim_qcfg_t7(pdbg_init, coreid, data,
+ num_cim_ibq, num_cim_obq);
+ else
+ rc = cudbg_collect_cim_qcfg_t5(pdbg_init, data, num_cim_ibq,
+ num_cim_obq);
if (rc) {
cudbg_err->sys_err = rc;
cudbg_put_buff(pdbg_init, &temp_buff);
return rc;
}
- t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
- cim_qcfg_data->thres);
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
@@ -973,20 +1113,38 @@ static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err, int qid)
{
+ struct cim_ibq_rev1 *cim_ibq_buff;
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
int no_of_read_words, rc = 0;
+ u8 coreid = 0;
u32 qsize;
+ if (qid >= t4_cim_num_ibq(padap))
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
/* collect CIM IBQ */
qsize = CIM_IBQ_SIZE * 4 * sizeof(u32);
- rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
+ rc = get_scratch_buff(dbg_buff, sizeof(*cim_ibq_buff) + qsize,
+ &temp_buff);
if (rc)
return rc;
+ cim_ibq_buff = (void *)((u8 *)temp_buff.data + temp_buff.offset);
+ cim_ibq_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ cim_ibq_buff->ver_hdr.revision = CUDBG_CIM_IBQ_REV;
+ cim_ibq_buff->ver_hdr.size = sizeof(*cim_ibq_buff) -
+ sizeof(struct cudbg_ver_hdr);
+ cim_ibq_buff->qid = qid;
+ cim_ibq_buff->coreid = coreid;
/* t4_read_cim_ibq will return no. of read words or error */
- no_of_read_words = t4_read_cim_ibq(padap, qid,
- (u32 *)temp_buff.data, qsize);
+ no_of_read_words = t4_read_cim_ibq_core(padap, coreid, qid,
+ cim_ibq_buff->data, qsize);
+
/* no_of_read_words is less than or equal to 0 means error */
if (no_of_read_words <= 0) {
if (!no_of_read_words)
@@ -1014,10 +1172,39 @@ int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init,
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1);
}
+int cudbg_collect_cim_ibq_tp2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T6)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2);
+}
+
+int cudbg_collect_cim_ibq_tp3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T6)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3);
+}
+
int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4);
+
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2);
}
@@ -1025,6 +1212,11 @@ int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5);
+
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3);
}
@@ -1032,6 +1224,11 @@ int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 6);
+
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4);
}
@@ -1039,9 +1236,63 @@ int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
+ struct adapter *padap = pdbg_init->adap;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 7);
+
return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5);
}
+int cudbg_collect_cim_ibq_ipc1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 9);
+}
+
+int cudbg_collect_cim_ibq_ipc2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 10);
+}
+
+int cudbg_collect_cim_ibq_ipc3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 11);
+}
+
+int cudbg_collect_cim_ibq_ipc4(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 12);
+}
+
+int cudbg_collect_cim_ibq_ipc5(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 13);
+}
+
+int cudbg_collect_cim_ibq_ipc6(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 14);
+}
+
+int cudbg_collect_cim_ibq_ipc7(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 15);
+}
+
u32 cudbg_cim_obq_size(struct adapter *padap, int qid)
{
u32 value;
@@ -1057,20 +1308,38 @@ static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err, int qid)
{
+ struct cim_obq_rev1 *cim_obq_buff;
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
int no_of_read_words, rc = 0;
+ u8 coreid = 0;
u32 qsize;
+ if (qid >= t4_cim_num_obq(padap))
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
/* collect CIM OBQ */
- qsize = cudbg_cim_obq_size(padap, qid);
- rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
+ qsize = cudbg_cim_obq_size(padap, qid);
+ rc = get_scratch_buff(dbg_buff, sizeof(*cim_obq_buff) + qsize,
+ &temp_buff);
if (rc)
return rc;
+ cim_obq_buff = (void *)((u8 *)temp_buff.data + temp_buff.offset);
+ cim_obq_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ cim_obq_buff->ver_hdr.revision = CUDBG_CIM_OBQ_REV;
+ cim_obq_buff->ver_hdr.size = sizeof(*cim_obq_buff) -
+ sizeof(struct cudbg_ver_hdr);
+ cim_obq_buff->qid = qid;
+ cim_obq_buff->coreid = coreid;
/* t4_read_cim_obq will return no. of read words or error */
- no_of_read_words = t4_read_cim_obq(padap, qid,
- (u32 *)temp_buff.data, qsize);
+ no_of_read_words = t4_read_cim_obq_core(padap, coreid, qid,
+ (u32 *)temp_buff.data, qsize);
+
/* no_of_read_words is less than or equal to 0 means error */
if (no_of_read_words <= 0) {
if (!no_of_read_words)
@@ -1140,6 +1409,55 @@ int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init,
return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7);
}
+int cudbg_collect_cim_obq_ipc1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 9);
+}
+
+int cudbg_collect_cim_obq_ipc2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 10);
+}
+
+int cudbg_collect_cim_obq_ipc3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 11);
+}
+
+int cudbg_collect_cim_obq_ipc4(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 12);
+}
+
+int cudbg_collect_cim_obq_ipc5(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 13);
+}
+
+int cudbg_collect_cim_obq_ipc6(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 14);
+}
+
+int cudbg_collect_cim_obq_ipc7(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 15);
+}
+
static int cudbg_meminfo_get_mem_index(struct adapter *padap,
struct cudbg_meminfo *mem_info,
u8 mem_type, u8 *idx)
@@ -1231,7 +1549,7 @@ static int cudbg_get_mem_region(struct adapter *padap,
*/
static int cudbg_get_mem_relative(struct adapter *padap,
struct cudbg_meminfo *meminfo,
- u8 mem_type, u32 *out_base, u32 *out_end)
+ u8 mem_type, u64 *out_base, u64 *out_end)
{
u8 mc_idx;
int rc;
@@ -1316,7 +1634,7 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
/* Set up initial PCI-E Memory Window to cover the start of our
* transfer.
*/
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
/* Transfer data from the adapter */
while (len > 0) {
@@ -1331,7 +1649,7 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
if (offset == mem_aperture) {
pos += mem_aperture;
offset = 0;
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
}
}
@@ -1349,7 +1667,7 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
if (offset == mem_aperture) {
pos += mem_aperture;
offset = 0;
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
}
}
@@ -1653,6 +1971,33 @@ int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
+static void *cudbg_collect_indir_reg_init(struct cudbg_indir_reg_entity *e,
+ u16 rev, u32 indir_reg,
+ u32 indir_data, u32 nentries)
+{
+ struct cudbg_ver_hdr *ver_hdr = &e->ver_hdr;
+
+ ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
+ ver_hdr->revision = rev;
+ ver_hdr->size = sizeof(*e) - sizeof(*ver_hdr);
+
+ e->indir_reg = indir_reg;
+ e->indir_data = indir_data;
+ e->nentries = nentries;
+ return e;
+}
+
+static void *cudbg_collect_indir_reg_init_next(struct cudbg_indir_reg_entity *e,
+ u16 rev, u32 indir_reg,
+ u32 indir_data, u32 nentries)
+{
+ struct cudbg_indir_reg_entity *n;
+
+ n = (void *)((u8 *)e + (sizeof(*e) + sizeof(e->data[0]) * e->nentries));
+ return cudbg_collect_indir_reg_init(n, rev, indir_reg, indir_data,
+ nentries);
+}
+
int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
@@ -1663,6 +2008,77 @@ int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
int i, rc, n = 0;
u32 size;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path — new indir reg framework */
+ struct cudbg_indir_reg_entity *tp_tm_entity, *tp_pio_entity;
+ struct cudbg_indir_reg_entity *tp_mib_entity;
+ const struct cudbg_indir_type_entry *tp_tm_arr;
+ const struct cudbg_indir_type_entry *tp_pio_arr;
+ const struct cudbg_indir_type_entry *tp_mib_arr;
+ struct cudbg_indir_reg_data *reg_data;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ tp_tm_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_TP_TM_PIO_ADDR);
+ tp_pio_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_TP_PIO_ADDR);
+ tp_mib_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_TP_MIB_INDEX);
+
+ if (!tp_tm_arr || !tp_pio_arr || !tp_mib_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ size = sizeof(*tp_tm_entity) + sizeof(*tp_pio_entity) +
+ sizeof(*tp_mib_entity) + sizeof(*reg_data) *
+ (tp_tm_arr->nentries + tp_pio_arr->nentries +
+ tp_mib_arr->nentries);
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ tp_tm_entity = cudbg_collect_indir_reg_init((void *)temp_buff.data,
+ CUDBG_TP_INDIR_REG_REV,
+ TP_TM_PIO_ADDR_A,
+ TP_TM_PIO_DATA_A,
+ tp_tm_arr->nentries);
+
+ tp_pio_entity = cudbg_collect_indir_reg_init_next(tp_tm_entity,
+ CUDBG_TP_INDIR_REG_REV,
+ TP_PIO_ADDR_A,
+ TP_PIO_DATA_A,
+ tp_pio_arr->nentries);
+
+ tp_mib_entity = cudbg_collect_indir_reg_init_next(tp_pio_entity,
+ CUDBG_TP_INDIR_REG_REV,
+ TP_MIB_INDEX_A,
+ TP_MIB_DATA_A,
+ tp_mib_arr->nentries);
+
+ reg_data = tp_tm_entity->data;
+ for (i = 0; i < tp_tm_entity->nentries; i++, reg_data++) {
+ reg_data->offset = tp_tm_arr->reg_arr[i].addr;
+ t4_tp_tm_pio_read(pdbg_init->adap, ®_data->data, 1,
+ reg_data->offset, true);
+ }
+
+ reg_data = tp_pio_entity->data;
+ for (i = 0; i < tp_pio_entity->nentries; i++, reg_data++) {
+ reg_data->offset = tp_pio_arr->reg_arr[i].addr;
+ t4_tp_pio_read(pdbg_init->adap, ®_data->data, 1,
+ reg_data->offset, true);
+ }
+
+ reg_data = tp_mib_entity->data;
+ for (i = 0; i < tp_mib_entity->nentries; i++, reg_data++) {
+ reg_data->offset = tp_mib_arr->reg_arr[i].addr;
+ t4_tp_mib_read(pdbg_init->adap, ®_data->data, 1,
+ reg_data->offset, true);
+ }
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ }
+
+ /* T5/T6 path */
if (is_t5(padap->params.chip))
n = sizeof(t5_tp_pio_array) +
sizeof(t5_tp_tm_pio_array) +
@@ -2061,6 +2477,37 @@ int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
+static void cudbg_collect_indir_reg(struct adapter *padap,
+ struct cudbg_indir_reg_entity *e,
+ const struct cudbg_indir_type_entry *arr,
+ u16 rev, u32 indir_reg, u32 indir_data)
+{
+ struct cudbg_indir_reg_entity *entity;
+ struct cudbg_indir_reg_data *reg_data;
+ u32 i;
+
+ entity = cudbg_collect_indir_reg_init(e, rev, indir_reg, indir_data,
+ arr->nentries);
+ reg_data = entity->data;
+ for (i = 0; i < entity->nentries; i++, reg_data++) {
+ reg_data->offset = arr->reg_arr[i].addr;
+ t4_read_indirect(padap, entity->indir_reg, entity->indir_data,
+ ®_data->data, 1, reg_data->offset);
+ }
+}
+
+static void
+cudbg_collect_indir_reg_next(struct adapter *padap,
+ struct cudbg_indir_reg_entity *e,
+ const struct cudbg_indir_type_entry *arr, u16 rev,
+ u32 indir_reg, u32 indir_data)
+{
+ struct cudbg_indir_reg_entity *n;
+
+ n = (void *)((u8 *)e + (sizeof(*e) + sizeof(e->data[0]) * e->nentries));
+ cudbg_collect_indir_reg(padap, n, arr, rev, indir_reg, indir_data);
+}
+
int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
@@ -2071,6 +2518,46 @@ int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
int i, rc, n;
u32 size;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path — new indir reg framework */
+ const struct cudbg_indir_type_entry *pm_rx_arr, *pm_tx_arr;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ pm_rx_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_PM_RX_DBG_CTRL);
+ pm_tx_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_PM_TX_DBG_CTRL);
+
+ if (!pm_rx_arr || !pm_tx_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ size = sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) *
+ pm_rx_arr->nentries;
+ size += sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) *
+ pm_tx_arr->nentries;
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ cudbg_collect_indir_reg(padap, (void *)temp_buff.data,
+ pm_rx_arr, CUDBG_PM_INDIR_REG_REV,
+ PM_RX_DBG_CTRL_A,
+ PM_RX_DBG_CTRL_A + 4);
+
+ cudbg_collect_indir_reg_next(padap, (void *)temp_buff.data,
+ pm_tx_arr, CUDBG_PM_INDIR_REG_REV,
+ PM_TX_DBG_CTRL_A,
+ PM_TX_DBG_CTRL_A + 4);
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ }
+
+ /* T5/T6 path */
n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
size = sizeof(struct ireg_buf) * n * 2;
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
@@ -2255,7 +2742,7 @@ static int cudbg_sge_ctxt_check_valid(u32 *buf, int type)
return buf[index] & (1U << bit);
}
-static int cudbg_get_ctxt_region_info(struct adapter *padap,
+static int cudbg_get_ctxt_region_info(struct adapter *padap, u8 sge_ctxt_size,
struct cudbg_region_info *ctx_info,
u8 *mem_type)
{
@@ -2303,7 +2790,7 @@ static int cudbg_get_ctxt_region_info(struct adapter *padap,
/* Get number of data freelist queues */
flq = HDRSTARTFLQ_G(value);
ctx_info[CTXT_FLM].exist = true;
- ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE;
+ ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * sge_ctxt_size;
/* The number of CONM contexts are same as number of freelist
* queues.
@@ -2314,7 +2801,7 @@ static int cudbg_get_ctxt_region_info(struct adapter *padap,
return 0;
}
-int cudbg_dump_context_size(struct adapter *padap)
+int cudbg_dump_context_size(struct adapter *padap, u8 sge_ctxt_size)
{
struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
u8 mem_type[CTXT_INGRESS + 1] = { 0 };
@@ -2322,7 +2809,7 @@ int cudbg_dump_context_size(struct adapter *padap)
int rc;
/* Get max valid qid for each type of queue */
- rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
+ rc = cudbg_get_ctxt_region_info(padap, sge_ctxt_size, region_info, mem_type);
if (rc)
return rc;
@@ -2330,14 +2817,14 @@ int cudbg_dump_context_size(struct adapter *padap)
if (!region_info[i].exist) {
if (i == CTXT_EGRESS || i == CTXT_INGRESS)
size += CUDBG_LOWMEM_MAX_CTXT_QIDS *
- SGE_CTXT_SIZE;
+ sge_ctxt_size;
continue;
}
size += (region_info[i].end - region_info[i].start + 1) /
- SGE_CTXT_SIZE;
+ sge_ctxt_size;
}
- return size * sizeof(struct cudbg_ch_cntxt);
+ return size * sizeof(struct struct_sge_ctxt_rev1_data);
}
static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
@@ -2359,13 +2846,14 @@ static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
}
-static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid,
- u8 ctxt_type,
- struct cudbg_ch_cntxt **out_buff)
+static u32 cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u8 sge_ctxt_size,
+ u32 max_qid, u8 ctxt_type,
+ struct struct_sge_ctxt_rev1 *ctxt_buff,
+ struct struct_sge_ctxt_rev1_data **out_buff)
{
- struct cudbg_ch_cntxt *buff = *out_buff;
+ struct struct_sge_ctxt_rev1_data *buff = *out_buff;
+ u32 j, total_size = 0;
int rc;
- u32 j;
for (j = 0; j < max_qid; j++) {
cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data);
@@ -2373,18 +2861,25 @@ static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid,
if (!rc)
continue;
- buff->cntxt_type = ctxt_type;
- buff->cntxt_id = j;
+ buff->ctxt_type = ctxt_type;
+ buff->ctxt_id = j;
+ buff->size = sge_ctxt_size;
+ total_size += sizeof(*buff);
+ ctxt_buff->nentries++;
buff++;
if (ctxt_type == CTXT_FLM) {
cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data);
- buff->cntxt_type = CTXT_CNM;
- buff->cntxt_id = j;
+ buff->ctxt_type = CTXT_CNM;
+ buff->ctxt_id = j;
+ buff->size = sge_ctxt_size;
+ total_size += sizeof(*buff);
+ ctxt_buff->nentries++;
buff++;
}
}
*out_buff = buff;
+ return total_size;
}
int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
@@ -2393,27 +2888,40 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
{
struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
struct adapter *padap = pdbg_init->adap;
- u32 j, size, max_ctx_size, max_ctx_qid;
+ struct struct_sge_ctxt_rev1 *ctxt_buff;
+ struct struct_sge_ctxt_rev1_data *buff;
+ u32 j, size, max_ctx_size, max_ctx_qid, total_size = 0;
u8 mem_type[CTXT_INGRESS + 1] = { 0 };
struct cudbg_buffer temp_buff = { 0 };
- struct cudbg_ch_cntxt *buff;
+ u8 i, k, sge_ctxt_size;
u8 *ctx_buf;
- u8 i, k;
int rc;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7)
+ sge_ctxt_size = SGE_CTXT_SIZE_T7;
+ else
+ sge_ctxt_size = SGE_CTXT_SIZE;
+
/* Get max valid qid for each type of queue */
- rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
+ rc = cudbg_get_ctxt_region_info(padap, sge_ctxt_size, region_info, mem_type);
if (rc)
return rc;
- rc = cudbg_dump_context_size(padap);
+ rc = cudbg_dump_context_size(padap, sge_ctxt_size);
if (rc <= 0)
return CUDBG_STATUS_ENTITY_NOT_FOUND;
size = rc;
- rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ rc = get_scratch_buff(dbg_buff, size + sizeof(*ctxt_buff), &temp_buff);
if (rc)
return rc;
+ ctxt_buff = (void *)temp_buff.data;
+ ctxt_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ ctxt_buff->ver_hdr.revision = CUDBG_SGE_CTXT_REV;
+ ctxt_buff->ver_hdr.size = sizeof(*ctxt_buff) -
+ sizeof(struct cudbg_ver_hdr);
+ ctxt_buff->nentries = 0;
+ total_size = sizeof(*ctxt_buff);
/* Get buffer with enough space to read the biggest context
* region in memory.
@@ -2429,7 +2937,7 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
return -ENOMEM;
}
- buff = (struct cudbg_ch_cntxt *)temp_buff.data;
+ buff = (void *)ctxt_buff->data;
/* Collect EGRESS and INGRESS context data.
* In case of failures, fallback to collecting via FW or
@@ -2438,13 +2946,13 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
if (!region_info[i].exist) {
max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
- cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
- &buff);
+ cudbg_get_sge_ctxt_fw(pdbg_init, sge_ctxt_size, max_ctx_qid, i,
+ ctxt_buff, &buff);
continue;
}
max_ctx_size = region_info[i].end - region_info[i].start + 1;
- max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
+ max_ctx_qid = max_ctx_size / sge_ctxt_size;
/* If firmware is not attached/alive, use backdoor register
* access to collect dump.
@@ -2459,8 +2967,8 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
if (rc || !is_fw_attached(pdbg_init)) {
max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
- cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
- &buff);
+ cudbg_get_sge_ctxt_fw(pdbg_init, sge_ctxt_size, max_ctx_qid, i,
+ ctxt_buff, &buff);
continue;
}
@@ -2468,21 +2976,24 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
__be64 *dst_off;
u64 *src_off;
- src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE);
+ src_off = (u64 *)(ctx_buf + j * sge_ctxt_size);
dst_off = (__be64 *)buff->data;
/* The data is stored in 64-bit cpu order. Convert it
* to big endian before parsing.
*/
- for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++)
+ for (k = 0; k < sge_ctxt_size / sizeof(u64); k++)
dst_off[k] = cpu_to_be64(src_off[k]);
rc = cudbg_sge_ctxt_check_valid(buff->data, i);
if (!rc)
continue;
- buff->cntxt_type = i;
- buff->cntxt_id = j;
+ buff->ctxt_type = i;
+ buff->ctxt_id = j;
+ buff->size = sge_ctxt_size;
+ total_size += sizeof(*buff);
+ ctxt_buff->nentries++;
buff++;
}
}
@@ -2492,11 +3003,11 @@ int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
/* Collect FREELIST and CONGESTION MANAGER contexts */
max_ctx_size = region_info[CTXT_FLM].end -
region_info[CTXT_FLM].start + 1;
- max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
+ max_ctx_qid = max_ctx_size / sge_ctxt_size;
/* Since FLM and CONM are 1-to-1 mapped, the below function
* will fetch both FLM and CONM contexts.
*/
- cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff);
+ cudbg_get_sge_ctxt_fw(pdbg_init, sge_ctxt_size, max_ctx_qid, CTXT_FLM, ctxt_buff, &buff);
return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
}
@@ -2544,7 +3055,72 @@ static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init,
u32 ctl, data2;
int rc = 0;
- if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* CtlReqID - 1: use Host Driver Requester ID
+ * CtlCmdType - 0: Read, 1: Write
+ * CtlXYBitSel- 0: Y bit, 1: X bit
+ ####### for T6 ######
+ * CtlTcamSel - 26:25 Control bit. 0: TCAM0, 1: TCAM1.
+ * CtlTcamIndex - 24:17 Control bits. Index of TCAM location to be accessed.
+
+ ####### for T7B ######
+ * CtlTcamSel - 27:26 Control bit. 0: TCAM0, 1: TCAM1, 2: TCAM2.
+ * CtlTcamIndex - 25:17 Control bits. Index of TCAM location to be accessed.
+ */
+
+ /* Read tcamy */
+ ctl = (CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0));
+ if (idx < 512)
+ ctl |= T7_1_CTLTCAMINDEX_V(idx) | T7_CTLTCAMSEL_V(0);
+ else if (idx < 1024)
+ ctl |= T7_1_CTLTCAMINDEX_V(idx - 512) |
+ T7_CTLTCAMSEL_V(1);
+ else /* idx 1024 to 1535 */
+ ctl |= T7_1_CTLTCAMINDEX_V(idx - 1024) |
+ T7_CTLTCAMSEL_V(2);
+
+ t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
+ val = t4_read_reg(padap, MPS_CLS_TCAM0_RDATA1_REQ_ID1_A);
+ tcamy = DMACH_G(val) << 32;
+ tcamy |= t4_read_reg(padap, MPS_CLS_TCAM0_RDATA0_REQ_ID1_A);
+ data2 = t4_read_reg(padap, MPS_CLS_TCAM0_RDATA2_REQ_ID1_A);
+ tcam->lookup_type = DATALKPTYPE_G(data2);
+
+ /* 0 - Outer header, 1 - Inner header
+ * [71:48] bit locations are overloaded for
+ * outer vs. inner lookup types.
+ */
+ if (tcam->lookup_type &&
+ tcam->lookup_type != DATALKPTYPE_M) {
+ /* Inner header VNI */
+ tcam->vniy =
+ (((data2 & DATAVIDH2_F) | (DATAVIDH1_G(data2)))
+ << 16) |
+ VIDL_G(val);
+ tcam->dip_hit = data2 & DATADIPHIT_F;
+ } else {
+ tcam->vlan_vld = data2 & DATAVIDH2_F;
+ tcam->ivlan = VIDL_G(val);
+ }
+
+ tcam->port_num = DATAPORTNUM_G(data2);
+
+ /* Read tcamx. Change the control param */
+ ctl |= CTLXYBITSEL_V(1);
+ t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
+ val = t4_read_reg(padap, MPS_CLS_TCAM0_RDATA1_REQ_ID1_A);
+ tcamx = DMACH_G(val) << 32;
+ tcamx |= t4_read_reg(padap, MPS_CLS_TCAM0_RDATA0_REQ_ID1_A);
+ data2 = t4_read_reg(padap, MPS_CLS_TCAM0_RDATA2_REQ_ID1_A);
+ if (tcam->lookup_type &&
+ tcam->lookup_type != DATALKPTYPE_M) {
+ /* Inner header VNI mask */
+ tcam->vnix =
+ (((data2 & DATAVIDH2_F) | (DATAVIDH1_G(data2)))
+ << 16) |
+ VIDL_G(val);
+ }
+ } else if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
/* CtlReqID - 1: use Host Driver Requester ID
* CtlCmdType - 0: Read, 1: Write
* CtlTcamSel - 0: TCAM0, 1: TCAM1
@@ -2602,13 +3178,24 @@ static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init,
if (tcamx & tcamy)
return rc;
- tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
- tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
+ /* t7b changes MPS_T5_CLS_SRAM_H_A to indirect register */
+ if (is_t7(padap->params.chip)) {
+ u32 tmp_ctl = 0;
- if (is_t5(padap->params.chip))
- tcam->repli = (tcam->cls_lo & REPLICATE_F);
- else if (is_t6(padap->params.chip))
+ tmp_ctl |= SRAMWRN_V(0) |
+ SRAMINDEX_V(idx & SRAMINDEX_M);
+ t4_write_reg(padap, MPS_T5_CLS_SRAM_H_A, tmp_ctl);
+ tcam->cls_lo = t4_read_reg(padap, MPS_T5_CLS_SRAM_L_A);
+ tcam->cls_hi = t4_read_reg(padap, MPS_T5_CLS_SRAM_H_A);
+ } else {
+ tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
+ tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
+ }
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
tcam->repli = (tcam->cls_lo & T6_REPLICATE_F);
+ else
+ tcam->repli = (tcam->cls_lo & REPLICATE_F);
if (tcam->repli) {
struct fw_ldst_cmd ldst_cmd;
@@ -2966,20 +3553,62 @@ int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
{
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
- struct ireg_buf *ma_indr;
- int i, rc, n;
- u32 size, j;
+ int i, j, rc, n;
+ u32 size;
if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
return CUDBG_STATUS_ENTITY_NOT_FOUND;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path — new indir reg framework */
+ const struct cudbg_indir_type_entry *ma_arr, *ma_perf_arr;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ ma_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_CFG);
+ ma_perf_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_MA_LOCAL_DEBUG_PERF_CFG);
+
+ if (!ma_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ size = sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) * ma_arr->nentries;
+
+ if (ma_perf_arr)
+ size += sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) *
+ ma_perf_arr->nentries;
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ cudbg_collect_indir_reg(padap, (void *)temp_buff.data,
+ ma_arr, CUDBG_MA_INDIR_REG_REV,
+ MA_LOCAL_DEBUG_CFG_A,
+ MA_LOCAL_DEBUG_CFG_A + 4);
+
+ if (ma_perf_arr)
+ cudbg_collect_indir_reg_next(padap, (void *)temp_buff.data, ma_perf_arr,
+ CUDBG_MA_INDIR_REG_REV,
+ MA_LOCAL_DEBUG_PERF_CFG_A,
+ MA_LOCAL_DEBUG_PERF_CFG_A + 4);
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ }
+
+ /* T6 path */
n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
size = sizeof(struct ireg_buf) * n * 2;
+
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
if (rc)
return rc;
- ma_indr = (struct ireg_buf *)temp_buff.data;
+ struct ireg_buf *ma_indr = (struct ireg_buf *)temp_buff.data;
for (i = 0; i < n; i++) {
struct ireg_field *ma_fli = &ma_indr->tp_pio;
u32 *buff = ma_indr->outbuf;
@@ -3094,9 +3723,67 @@ int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
else if (is_t6(padap->params.chip))
n = sizeof(t6_up_cim_reg_array) /
((IREG_NUM_ELEM + 1) * sizeof(u32));
- else
+ else if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path — new indir reg framework */
+ const struct cudbg_indir_type_entry *cim_arr, *up_arr;
+ struct cudbg_indir_reg_entity *cim_entity, *up_entity;
+ struct cudbg_indir_reg_data *reg_data;
+ u8 coreid = 0, groupid = 0;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ cim_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_CIM_CTL);
+ up_arr = cudbg_get_indir_reg_info(chip_ver, CUDBG_INDIR_TYPE_UP);
+
+ if (!cim_arr || !up_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ if (pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].param_type ==
+ CUDBG_UP_COREID_PARAM)
+ coreid = pdbg_init->dbg_params[CUDBG_UP_COREID_PARAM].u.coreid;
+
+ size = sizeof(*cim_entity) + sizeof(*up_entity) +
+ sizeof(*reg_data) * (cim_arr->nentries + up_arr->nentries);
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ cim_entity = cudbg_collect_indir_reg_init((void *)temp_buff.data,
+ CUDBG_UP_CIM_INDIR_REG_REV,
+ CIM_HOST_ACC_CTRL_A,
+ CIM_HOST_ACC_DATA_A,
+ cim_arr->nentries);
+
+ up_entity = cudbg_collect_indir_reg_init_next(cim_entity,
+ CUDBG_UP_CIM_INDIR_REG_REV,
+ CIM_HOST_ACC_CTRL_A,
+ CIM_HOST_ACC_DATA_A,
+ up_arr->nentries);
+
+ reg_data = cim_entity->data;
+ for (i = 0; i < cim_entity->nentries; i++, reg_data++) {
+ reg_data->offset = cim_arr->reg_arr[i].addr;
+ t4_cim_read_core(padap, groupid, coreid,
+ reg_data->offset, 1, ®_data->data);
+ }
+
+ groupid = 1; /* T7 UP uses groupid 1 */
+
+ reg_data = up_entity->data;
+ for (i = 0; i < up_entity->nentries; i++, reg_data++) {
+ reg_data->offset = up_arr->reg_arr[i].addr;
+ t4_cim_read_core(padap, groupid, coreid,
+ reg_data->offset, 1, ®_data->data);
+ }
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ } else {
return CUDBG_STATUS_NOT_IMPLEMENTED;
+ }
+ /* T5/T6 path */
size = sizeof(struct ireg_buf) * n;
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
if (rc)
@@ -3275,20 +3962,47 @@ int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init,
{
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
- struct ireg_buf *hma_indr;
int i, rc, n;
u32 size;
if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
return CUDBG_STATUS_ENTITY_NOT_FOUND;
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T7) {
+ /* T7 path — new indir reg framework */
+ const struct cudbg_indir_type_entry *hma_arr;
+ u32 chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(padap->params.chip);
+ hma_arr = cudbg_get_indir_reg_info(chip_ver,
+ CUDBG_INDIR_TYPE_HMAT6_LOCAL_DEBUG_CFG);
+ if (!hma_arr)
+ return CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ size = sizeof(struct cudbg_indir_reg_entity) +
+ sizeof(struct cudbg_indir_reg_data) * hma_arr->nentries;
+
+ rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
+ if (rc)
+ return rc;
+
+ cudbg_collect_indir_reg(padap, (void *)temp_buff.data,
+ hma_arr, CUDBG_HMA_INDIR_REG_REV,
+ HMA_LOCAL_DEBUG_CFG_A,
+ HMA_LOCAL_DEBUG_CFG_A + 4);
+
+ return cudbg_write_and_release_buff(pdbg_init, &temp_buff,
+ dbg_buff);
+ }
+
+ /* T6 path */
n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
size = sizeof(struct ireg_buf) * n;
rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
if (rc)
return rc;
- hma_indr = (struct ireg_buf *)temp_buff.data;
+ struct ireg_buf *hma_indr = (struct ireg_buf *)temp_buff.data;
for (i = 0; i < n; i++) {
struct ireg_field *hma_fli = &hma_indr->tp_pio;
u32 *buff = hma_indr->outbuf;
@@ -3581,7 +4295,7 @@ int cudbg_collect_flash(struct cudbg_init *pdbg_init,
u32 addr, i;
int rc;
- addr = FLASH_EXP_ROM_START;
+ addr = FLASH_LOC_EXP_ROM;
for (i = 0; i < count; i += SF_PAGE_SIZE) {
n = min_t(u32, count - i, SF_PAGE_SIZE);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
index d6d6cd298930..debc9fa630ee 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
@@ -165,13 +165,61 @@ int cudbg_collect_qdesc(struct cudbg_init *pdbg_init,
int cudbg_collect_flash(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_tp2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_tp3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc4(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc5(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc6(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_ibq_ipc7(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc4(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc5(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc6(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_obq_ipc7(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
u32 cudbg_get_entity_length(struct adapter *adap, u32 entity);
struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i);
void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,
struct cudbg_entity_hdr *entity_hdr);
u32 cudbg_cim_obq_size(struct adapter *padap, int qid);
-int cudbg_dump_context_size(struct adapter *padap);
+int cudbg_dump_context_size(struct adapter *padap, u8 sge_ctxt_size);
int cudbg_fill_meminfo(struct adapter *padap,
struct cudbg_meminfo *meminfo_buff);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
index dd66b244466d..08597b9e99cf 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
@@ -64,6 +64,22 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
{ CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect },
{ CUDBG_PBT_TABLE, cudbg_collect_pbt_tables },
{ CUDBG_HMA_INDIRECT, cudbg_collect_hma_indirect },
+ { CUDBG_CIM_IBQ_TP2, cudbg_collect_cim_ibq_tp2 },
+ { CUDBG_CIM_IBQ_TP3, cudbg_collect_cim_ibq_tp3 },
+ { CUDBG_CIM_IBQ_IPC1, cudbg_collect_cim_ibq_ipc1 },
+ { CUDBG_CIM_IBQ_IPC2, cudbg_collect_cim_ibq_ipc2 },
+ { CUDBG_CIM_IBQ_IPC3, cudbg_collect_cim_ibq_ipc3 },
+ { CUDBG_CIM_IBQ_IPC4, cudbg_collect_cim_ibq_ipc4 },
+ { CUDBG_CIM_IBQ_IPC5, cudbg_collect_cim_ibq_ipc5 },
+ { CUDBG_CIM_IBQ_IPC6, cudbg_collect_cim_ibq_ipc6 },
+ { CUDBG_CIM_IBQ_IPC7, cudbg_collect_cim_ibq_ipc7 },
+ { CUDBG_CIM_OBQ_IPC1, cudbg_collect_cim_obq_ipc1 },
+ { CUDBG_CIM_OBQ_IPC2, cudbg_collect_cim_obq_ipc2 },
+ { CUDBG_CIM_OBQ_IPC3, cudbg_collect_cim_obq_ipc3 },
+ { CUDBG_CIM_OBQ_IPC4, cudbg_collect_cim_obq_ipc4 },
+ { CUDBG_CIM_OBQ_IPC5, cudbg_collect_cim_obq_ipc5 },
+ { CUDBG_CIM_OBQ_IPC6, cudbg_collect_cim_obq_ipc6 },
+ { CUDBG_CIM_OBQ_IPC7, cudbg_collect_cim_obq_ipc7 },
};
static const struct cxgb4_collect_entity cxgb4_collect_flash_dump[] = {
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next v1 06/10] cxgb4: Move PCI initialization logic to cxgb4_pci.c
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
` (4 preceding siblings ...)
2026-06-07 3:52 ` [PATCH net-next v1 05/10] cxgb4: Add T7 indirect regs and update library Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 07/10] cxgb4: Extend hardware abstraction layer for T7 logs Potnuri Bharat Teja
` (4 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Refactor the core driver initialization framework by extracting all
PCI-specific configurations out of cxgb4_main.c into a new module
in cxgb4_pci.c and cxgb4_pci.h.
This structural separation isolates mechanical bus logic from general
driver workflows:
- Move resource allocation subroutines to manage BAR0 mappings and
register physical SGE doorbell pointers.
- Relocate chip identification, BAR2 mappings, DMA masking, primary PF
election, and firmware handshake wrappers into independent bus paths.
- Consolidate MSI/MSI-X vectors, VPD reading, config-space access
wrappers, EEH error handlers, and driver probe, remove, and shutdown
hooks.
- Shift the pci_device_id table and MODULE_DEVICE_TABLE exports
directly to the new file, leaving only global MODULE_FIRMWARE tags
behind in cxgb4_main.c.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/Makefile | 2 +-
.../net/ethernet/chelsio/cxgb4/cxgb4_pci.c | 370 ++++++++++++++++++
.../net/ethernet/chelsio/cxgb4/cxgb4_pci.h | 36 ++
3 files changed, 407 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c
create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h
diff --git a/drivers/net/ethernet/chelsio/cxgb4/Makefile b/drivers/net/ethernet/chelsio/cxgb4/Makefile
index a4b4d475abf8..08aef803a14a 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/Makefile
+++ b/drivers/net/ethernet/chelsio/cxgb4/Makefile
@@ -9,7 +9,7 @@ cxgb4-objs := cxgb4_main.o l2t.o smt.o t4_hw.o sge.o clip_tbl.o cxgb4_ethtool.o
cxgb4_uld.o srq.o sched.o cxgb4_filter.o cxgb4_tc_u32.o \
cxgb4_ptp.o cxgb4_tc_flower.o cxgb4_cudbg.o cxgb4_mps.o \
cudbg_common.o cudbg_lib.o cudbg_zlib.o cxgb4_tc_mqprio.o \
- cxgb4_tc_matchall.o
+ cxgb4_tc_matchall.o cxgb4_pci.o
cxgb4-$(CONFIG_CHELSIO_T4_DCB) += cxgb4_dcb.o
cxgb4-$(CONFIG_CHELSIO_T4_FCOE) += cxgb4_fcoe.o
cxgb4-$(CONFIG_DEBUG_FS) += cxgb4_debugfs.o
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c
new file mode 100644
index 000000000000..9c6ad229432c
--- /dev/null
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.c
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * This file is part of the Chelsio T4/T5/T6/T7 Ethernet driver for Linux.
+ *
+ * Copyright (C) 2026 Chelsio Communications. All rights reserved.
+ *
+ */
+
+#include <linux/crash_dump.h>
+
+#include "cxgb4.h"
+#include "t4_regs.h"
+
+#include "cxgb4_pci.h"
+
+static void cxgb4_pci_set_primary_pf(struct adapter *adap)
+{
+ adap->primary_pf = CXGB4_UNIFIED_PF;
+}
+
+int cxgb4_pci_resource_init(struct adapter *adap)
+{
+ struct pci_dev *pdev = adap->pdev;
+ int ret;
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ /* Just info, some other driver may have claimed the device. */
+ dev_info(adap->pdev_dev, "cannot obtain PCI resources\n");
+ return ret;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ dev_err(adap->pdev_dev, "cannot enable PCI device\n");
+ goto out_release_regions;
+ }
+
+ adap->regs = pci_ioremap_bar(pdev, 0);
+ if (!adap->regs) {
+ dev_err(adap->pdev_dev, "cannot map device registers\n");
+ ret = -ENOMEM;
+ goto out_disable_device;
+ }
+
+ adap->sge.tx_db_addr = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
+ adap->sge.rx_db_addr = adap->regs + MYPF_REG(SGE_PF_GTS_A);
+
+ adap->name = pci_name(pdev);
+ cxgb4_pci_set_primary_pf(adap);
+ return 0;
+
+out_disable_device:
+ pci_disable_device(pdev);
+
+out_release_regions:
+ pci_release_regions(pdev);
+ return ret;
+}
+
+void cxgb4_pci_resource_free(struct adapter *adap)
+{
+ struct pci_dev *pdev = adap->pdev;
+
+ iounmap(adap->regs);
+ if ((adap->flags & CXGB4_DEV_ENABLED))
+ pci_disable_device(pdev);
+ pci_release_regions(pdev);
+}
+
+int cxgb4_pci_chip_init(struct adapter *adap)
+{
+ struct pci_dev *pdev = adap->pdev;
+ u16 device_id;
+ u32 whoami;
+ u8 func;
+ int ret;
+
+ /*
+ * Note that we use the PL_WHOAMI register to figure out to which PF
+ * we're actually attached rather than PCI_FUNC(pdev->devfn). We do
+ * this because we could be operating within a Virtual Machine where,
+ * say, PF4 has been inserted via some form of "PCI Pass Through"
+ * resulting in the VM PCI Device having a completely different PCI
+ * Function Number, say, PF0. However, there are many communications
+ * with the firmware (and the hardware) where we need to use the
+ * actual Physical Function Number and we can get this from the
+ * PL_WHOAMI register ...
+ */
+ whoami = t4_read_reg(adap, PL_WHOAMI_A);
+ pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
+ ret = t4_get_chip_type(adap, CHELSIO_PCI_ID_VER(device_id));
+ if (ret < 0)
+ return ret;
+
+ adap->params.chip = ret;
+ func = CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5 ?
+ SOURCEPF_G(whoami) :
+ T6_SOURCEPF_G(whoami);
+
+ adap->mbox = func;
+ adap->pf = func;
+
+ ret = cxgb4_mbox_log_init(adap);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * If we're not the MASTER Physical Function, there's not much more
+ * we need to do.
+ */
+ if (!cxgb4_is_primary_pf(adap)) {
+ /* We must be a PCIe SR-IOV Virtual Function. We won't be
+ * doing any DMA, but we will be offering VF Management
+ * services ...
+ */
+ pci_disable_device(pdev);
+ pci_save_state(pdev); /* to restore SR-IOV later */
+ return 0;
+ }
+
+ ret = dma_set_mask_and_coherent(adap->pdev_dev, DMA_BIT_MASK(64));
+ if (ret) {
+ dev_err(adap->pdev_dev, "no usable DMA configuration\n");
+ goto out_free_mbox_log;
+ }
+
+ pci_set_master(pdev);
+ pci_save_state(pdev);
+
+ if (!is_t4(adap->params.chip)) {
+ adap->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
+ pci_resource_len(pdev, 2));
+ if (!adap->bar2) {
+ dev_err(adap->pdev_dev,
+ "cannot map device bar2 region\n");
+ ret = -ENOMEM;
+ goto out_free_mbox_log;
+ }
+
+ t4_write_reg(adap, SGE_STAT_CFG_A,
+ STATSOURCE_T5_V(7) | (is_t5(adap->params.chip) ?
+ STATMODE_V(0) :
+ T6_STATMODE_V(0)));
+ }
+
+ /* check for PCI Express bandwidth capabiltites */
+ pcie_print_link_status(pdev);
+
+ /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
+ pdev->needs_freset = 1;
+
+ return 0;
+
+out_free_mbox_log:
+ cxgb4_mbox_log_free(adap);
+ return ret;
+}
+
+void cxgb4_pci_chip_free(struct adapter *adap)
+{
+ if (!is_t4(adap->params.chip)) {
+ if (adap->bar2)
+ iounmap(adap->bar2);
+ }
+
+ cxgb4_mbox_log_free(adap);
+}
+
+void cxgb4_pci_setup_memwin(struct adapter *adap)
+{
+ u32 nic_win_base = t4_get_util_window(adap);
+
+ t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
+}
+
+void cxgb4_pci_setup_memwin_rdma(struct adapter *adap)
+{
+ unsigned int sz_kb;
+ u32 start;
+
+ if (!adap->vres.ocq.size)
+ return;
+
+ start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
+ start &= PCI_BASE_ADDRESS_MEM_MASK;
+ start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
+ sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> WINDOW_SHIFT_X;
+
+ /*
+ * Set up RDMA memory window for accessing adapter memory
+ * ranges. (Read back MA register to ensure that changes
+ * propagate before we attempt to use the new values.)
+ */
+ t4_write_reg(adap, t4_pcie_mem_access_base_win_reg(adap, MEMWIN_RDMA),
+ start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
+ t4_pcie_mem_access_offset_write(adap, adap->vres.ocq.start, MEMWIN_RDMA,
+ 0);
+}
+
+void cxgb4_pci_fw_free(struct adapter *adap)
+{
+ t4_fw_bye(adap, adap->mbox);
+}
+
+int cxgb4_pci_fw_init(struct adapter *adap, enum dev_state *state)
+{
+ int ret;
+
+ /* Contact FW, advertising Master capability */
+ ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, state);
+ if (ret < 0 && is_kdump_kernel())
+ ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MUST,
+ state);
+ if (ret < 0) {
+ dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
+ ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+int cxgb4_pci_device_id(struct adapter *adap)
+{
+ return adap->pdev->device;
+}
+
+bool cxgb4_pci_msix_enabled(struct adapter *adap)
+{
+ if (!pci_dev_msi_enabled(adap->pdev))
+ return false;
+
+ return adap->pdev->msix_enabled;
+}
+
+bool cxgb4_pci_msi_enabled(struct adapter *adap)
+{
+ if (!pci_dev_msi_enabled(adap->pdev))
+ return false;
+
+ return adap->pdev->msi_enabled;
+}
+
+int cxgb4_pci_write_config_word(struct adapter *adap, int where, u16 val)
+{
+ return pci_write_config_word(adap->pdev, where, val);
+}
+
+ssize_t cxgb4_pci_read_vpd(struct adapter *adap, loff_t pos, size_t count,
+ void *buf)
+{
+ return pci_read_vpd(adap->pdev, pos, count, buf);
+}
+
+ssize_t cxgb4_pci_write_vpd(struct adapter *adap, loff_t pos, size_t count,
+ const void *buf)
+{
+ return pci_write_vpd(adap->pdev, pos, count, buf);
+}
+
+#if !defined(CHELSIO_T4_DIAGS) && defined(CONFIG_PCI_IOV)
+int cxgb4_pci_iov_configure(struct adapter *adap, int num_vfs)
+{
+ return cxgb4_iov_configure(adap->pdev, num_vfs);
+}
+
+static int cxgb4_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
+{
+ if (pci_is_bridge(pdev))
+ return -EOPNOTSUPP;
+
+ return cxgb4_pci_iov_configure(pci_get_drvdata(pdev), num_vfs);
+}
+#endif
+
+static int cxgb4_pci_init_one(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ struct adapter *adap;
+ int ret;
+
+ if (pci_is_bridge(pdev))
+ return 0;
+
+ adap = cxgb4_adap_alloc(&pdev->dev);
+ if (!adap) {
+ dev_err(&pdev->dev, "FAIL - Adapter alloc\n");
+ return -ENOMEM;
+ }
+
+ pci_set_drvdata(pdev, adap);
+
+ adap->pdev = pdev;
+ adap->pdev_dev = &pdev->dev;
+
+ ret = cxgb4_adap_probe(adap);
+ if (ret < 0)
+ goto out_err;
+
+ return 0;
+
+out_err:
+ pci_set_drvdata(pdev, NULL);
+ return ret;
+}
+
+static void cxgb4_pci_remove_one(struct pci_dev *pdev)
+{
+ if (pci_is_bridge(pdev))
+ return;
+
+ cxgb4_adap_remove(pci_get_drvdata(pdev));
+ pci_set_drvdata(pdev, NULL);
+}
+
+static void cxgb4_pci_shutdown_one(struct pci_dev *pdev)
+{
+ if (pci_is_bridge(pdev))
+ return;
+
+ cxgb4_adap_shutdown(pci_get_drvdata(pdev));
+}
+
+#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
+static const struct pci_device_id cxgb4_pci_tbl[] = {
+
+#define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
+#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
+
+#define CH_PCI_ID_TABLE_ENTRY(devid) \
+ { PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF }
+
+#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
+ { 0, } \
+}
+
+#include "t4_pci_id_tbl.h"
+
+static const struct pci_error_handlers cxgb4_pci_eeh = {
+ .error_detected = cxgb4_pci_eeh_err_detected,
+ .slot_reset = cxgb4_pci_eeh_slot_reset,
+ .resume = cxgb4_pci_eeh_resume,
+ .reset_prepare = cxgb4_pci_eeh_reset_prepare,
+ .reset_done = cxgb4_pci_eeh_reset_done,
+};
+
+static struct pci_driver cxgb4_pci_driver = {
+ .name = KBUILD_MODNAME,
+ .id_table = cxgb4_pci_tbl,
+ .probe = cxgb4_pci_init_one,
+ .remove = cxgb4_pci_remove_one,
+ .shutdown = cxgb4_pci_shutdown_one,
+#if !defined(CHELSIO_T4_DIAGS) && defined(CONFIG_PCI_IOV)
+ .sriov_configure = cxgb4_pci_sriov_configure,
+#endif
+ .err_handler = &cxgb4_pci_eeh,
+};
+
+int cxgb4_pci_driver_register(void)
+{
+ return pci_register_driver(&cxgb4_pci_driver);
+}
+
+void cxgb4_pci_driver_unregister(void)
+{
+ pci_unregister_driver(&cxgb4_pci_driver);
+}
+
+MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h
new file mode 100644
index 000000000000..4f4c56a90ba2
--- /dev/null
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_pci.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 Chelsio Communications. All rights reserved.
+ */
+
+#ifndef __CXGB4_PCI_H__
+#define __CXGB4_PCI_H__
+
+#define CXGB4_UNIFIED_PF 0x4
+
+int cxgb4_pci_resource_init(struct adapter *adap);
+void cxgb4_pci_resource_free(struct adapter *adap);
+int cxgb4_pci_chip_init(struct adapter *adap);
+void cxgb4_pci_chip_free(struct adapter *adap);
+void cxgb4_pci_setup_memwin(struct adapter *adap);
+void cxgb4_pci_setup_memwin_rdma(struct adapter *adap);
+void cxgb4_pci_fw_free(struct adapter *adap);
+int cxgb4_pci_fw_init(struct adapter *adap, enum dev_state *state);
+int cxgb4_pci_device_id(struct adapter *adap);
+bool cxgb4_pci_msix_enabled(struct adapter *adap);
+bool cxgb4_pci_msi_enabled(struct adapter *adap);
+int cxgb4_pci_read_config_word(struct adapter *adap, int where, u16 *val);
+int cxgb4_pci_write_config_word(struct adapter *adap, int where, u16 val);
+ssize_t cxgb4_pci_read_vpd(struct adapter *adap, loff_t pos, size_t count,
+ void *buf);
+ssize_t cxgb4_pci_write_vpd(struct adapter *adap, loff_t pos, size_t count,
+ const void *buf);
+int cxgb4_pci_memory_rw(struct adapter *adap, int win, u64 addr, u64 len,
+ void *buf, int dir);
+#if !defined(CHELSIO_T4_DIAGS) && defined(CONFIG_PCI_IOV)
+int cxgb4_pci_iov_configure(struct adapter *adap, int num_vfs);
+#endif
+
+int cxgb4_pci_driver_register(void);
+void cxgb4_pci_driver_unregister(void);
+#endif /* __CXGB4_PCI_H__ */
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next v1 07/10] cxgb4: Extend hardware abstraction layer for T7 logs
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
` (5 preceding siblings ...)
2026-06-07 3:52 ` [PATCH net-next v1 06/10] cxgb4: Move PCI initialization logic to cxgb4_pci.c Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 08/10] cxgb4: Update driver lifecycle and peripherals for T7 Potnuri Bharat Teja
` (3 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Update the core hardware abstraction layer within t4_hw.c to implement
full register dispatching, multi-core memory mapping, and interface
diagnostics for T7 adapters.
Expand the driver low-level access routines to support T7 layouts:
- Implement 64-bit PCIe memory window address tracking using offset
shifts, and route flash geometry queries via a dynamic per-adapter
mapping table.
- Update chip identification logic to decode T7 silicon revisions using
the PL_REV register, sizing structural limits to accommodate 256
VFs and wider TCAM layouts.
- Upgrade the firmware developer log parser devlog to automatically
shard tracking buffers across the expanded microprocessor cores.
- Introduce multi-core debugging interfaces for CIM, enabling explicit
host-group and host-core target reads and writes for internal queues
and LA buffers.
- Integrate TP channel routing, SGE queues-per-page QPP mappings, PM
RX cache metrics, and interrupt handler pathways unique to T7.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 2484 ++++++++++++++++----
1 file changed, 2048 insertions(+), 436 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index 171750fad44f..d161bc56f2eb 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -234,9 +234,8 @@ static void fw_asrt(struct adapter *adap, u32 mbox_addr)
* @access: the time (ms) needed to access the Firmware Mailbox
* @execute: the time (ms) the command spent being executed
*/
-static void t4_record_mbox(struct adapter *adapter,
- const __be64 *cmd, unsigned int size,
- int access, int execute)
+void t4_record_mbox(struct adapter *adapter, const __be64 *cmd,
+ unsigned int size, int access, int execute)
{
struct mbox_cmd_log *log = adapter->mbox_log;
struct mbox_cmd *entry;
@@ -305,7 +304,9 @@ int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
* If the device is off-line, as in EEH, commands will time out.
* Fail them early so we don't waste time waiting.
*/
- if (adap->pdev->error_state != pci_channel_io_normal)
+ struct pci_dev *pdev = adap->pdev;
+
+ if (pdev->error_state != pci_channel_io_normal)
return -EIO;
/* If we have a negative timeout, that implies that we can't sleep. */
@@ -483,6 +484,39 @@ static int t4_edc_err_read(struct adapter *adap, int idx)
return 0;
}
+unsigned int t4_pcie_mem_access_base_win_reg(struct adapter *adap, int win)
+{
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ return T7_PCIE_MEM_ACCESS_REG(T7_PCIE_MEM_ACCESS_BASE_WIN_A,
+ win);
+ return PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win);
+}
+
+unsigned int t4_pcie_mem_access_offset_reg(struct adapter *adap, int win)
+{
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ return T7_PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET0_A,
+ win);
+
+ return PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win);
+}
+
+void t4_pcie_mem_access_offset_write(struct adapter *adap, u32 off, int win,
+ u32 pf)
+{
+ u32 reg = t4_pcie_mem_access_offset_reg(adap, win);
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ off >>= T7_MEMOFST_SHIFT_X;
+ t4_write_reg64(adap, reg, off | pf);
+ t4_read_reg64(adap, reg); /* Flush */
+ return;
+ }
+
+ t4_write_reg(adap, reg, off | pf);
+ t4_read_reg(adap, reg); /* Flush */
+}
+
/**
* t4_memory_rw_init - Get memory window relative offset, base, and size.
* @adap: the adapter
@@ -497,7 +531,7 @@ static int t4_edc_err_read(struct adapter *adap, int idx)
int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
u32 *mem_base, u32 *mem_aperture)
{
- u32 edc_size, mc_size, mem_reg;
+ u64 edc_size, mc_size, mem_reg;
/* Offset into the region of memory which is being accessed
* MEM_EDC0 = 0
@@ -506,15 +540,14 @@ int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
* MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
* MEM_HMA = 4
*/
- edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
+ edc_size = T7_EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
if (mtype == MEM_HMA) {
*mem_off = 2 * (edc_size * 1024 * 1024);
} else if (mtype != MEM_MC1) {
*mem_off = (mtype * (edc_size * 1024 * 1024));
} else {
- mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
- MA_EXT_MEMORY0_BAR_A));
- *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
+ mc_size = T7_EXT_MEM0_SIZE_G(t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A));
+ *mem_off = ((u64)(MEM_MC0 * edc_size + mc_size)) * 1024 * 1024;
}
/* Each PCI-E Memory Window is programmed with a window size -- or
@@ -525,14 +558,13 @@ int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
* space. For T4 this is an absolute PCI-E Bus Address. For T5
* the address is relative to BAR0.
*/
- mem_reg = t4_read_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
- win));
+ mem_reg = t4_read_reg(adap, t4_pcie_mem_access_base_win_reg(adap, win));
+
/* a dead adapter will return 0xffffffff for PIO reads */
if (mem_reg == 0xffffffff)
return -ENXIO;
- *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
+ *mem_aperture = 1ULL << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
*mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
if (is_t4(adap->params.chip))
*mem_base -= adap->t4_bar0;
@@ -540,26 +572,6 @@ int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
return 0;
}
-/**
- * t4_memory_update_win - Move memory window to specified address.
- * @adap: the adapter
- * @win: PCI-E Memory Window to use
- * @addr: location to move.
- *
- * Move memory window to specified address.
- */
-void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
-{
- t4_write_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
- addr);
- /* Read it back to ensure that changes propagate before we
- * attempt to use the new value.
- */
- t4_read_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
-}
-
/**
* t4_memory_rw_residual - Read/Write residual data.
* @adap: the adapter
@@ -652,7 +664,7 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
/* Set up initial PCI-E Memory Window to cover the start of our
* transfer.
*/
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
/* Transfer data to/from the adapter as long as there's an integral
* number of 32-bit transfers to complete.
@@ -707,7 +719,7 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
if (offset == mem_aperture) {
pos += mem_aperture;
offset = 0;
- t4_memory_update_win(adap, win, pos | win_pf);
+ t4_pcie_mem_access_offset_write(adap, pos, win, win_pf);
}
}
@@ -811,12 +823,10 @@ u32 t4_get_util_window(struct adapter *adap)
*/
void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
{
- t4_write_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
+ t4_write_reg(adap, t4_pcie_mem_access_base_win_reg(adap, window),
memwin_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
- t4_read_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
+ t4_read_reg(adap, t4_pcie_mem_access_base_win_reg(adap, window));
}
/**
@@ -835,6 +845,7 @@ unsigned int t4_get_regs_len(struct adapter *adapter)
case CHELSIO_T5:
case CHELSIO_T6:
+ case CHELSIO_T7:
return T5_REGMAP_SIZE;
}
@@ -2637,6 +2648,648 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
0x51300, 0x51324,
};
+ static const unsigned int t7_reg_ranges[] = {
+ 0x1008, 0x101c,
+ 0x1024, 0x10a8,
+ 0x10b4, 0x10f8,
+ 0x1100, 0x1114,
+ 0x111c, 0x112c,
+ 0x1138, 0x113c,
+ 0x1144, 0x115c,
+ 0x1180, 0x1184,
+ 0x1190, 0x1194,
+ 0x11a0, 0x11a4,
+ 0x11b0, 0x11d0,
+ 0x11fc, 0x1278,
+ 0x1280, 0x1368,
+ 0x1700, 0x172c,
+ 0x173c, 0x1760,
+ 0x1800, 0x18fc,
+ 0x3000, 0x3044,
+ 0x30a4, 0x30b0,
+ 0x30b8, 0x30d8,
+ 0x30e0, 0x30e8,
+ 0x3140, 0x357c,
+ 0x35a8, 0x35cc,
+ 0x35e0, 0x35ec,
+ 0x3600, 0x37fc,
+ 0x3804, 0x3818,
+ 0x3880, 0x388c,
+ 0x3900, 0x3904,
+ 0x3910, 0x3978,
+ 0x3980, 0x399c,
+ 0x4700, 0x4720,
+ 0x4728, 0x475c,
+ 0x480c, 0x4814,
+ 0x4890, 0x489c,
+ 0x48a4, 0x48ac,
+ 0x48b8, 0x48bc,
+ 0x4900, 0x4924,
+ 0x4ffc, 0x4ffc,
+ 0x5500, 0x5624,
+ 0x56c4, 0x56ec,
+ 0x56f4, 0x5720,
+ 0x5728, 0x575c,
+ 0x580c, 0x5814,
+ 0x5890, 0x589c,
+ 0x58a4, 0x58ac,
+ 0x58b8, 0x58bc,
+ 0x5940, 0x598c,
+ 0x59b0, 0x59c8,
+ 0x59d0, 0x59dc,
+ 0x59fc, 0x5a18,
+ 0x5a60, 0x5a6c,
+ 0x5a80, 0x5a8c,
+ 0x5a94, 0x5a9c,
+ 0x5b94, 0x5bec,
+ 0x5bf8, 0x5bfc,
+ 0x5c10, 0x5c40,
+ 0x5c4c, 0x5e48,
+ 0x5e50, 0x5e94,
+ 0x5ea0, 0x5eb0,
+ 0x5ec0, 0x5ec0,
+ 0x5ec8, 0x5ed0,
+ 0x5ee0, 0x5ee0,
+ 0x5ef0, 0x5ef0,
+ 0x5f00, 0x5f04,
+ 0x5f0c, 0x5f10,
+ 0x5f20, 0x5f78,
+ 0x5f84, 0x5f88,
+ 0x5f90, 0x5fd8,
+ 0x6000, 0x6020,
+ 0x6028, 0x6030,
+ 0x6044, 0x609c,
+ 0x60a8, 0x60ac,
+ 0x60b8, 0x60ec,
+ 0x6100, 0x6104,
+ 0x6118, 0x611c,
+ 0x6150, 0x6150,
+ 0x6180, 0x61b8,
+ 0x7700, 0x77a8,
+ 0x77b0, 0x7888,
+ 0x78cc, 0x7970,
+ 0x7b00, 0x7b00,
+ 0x7b08, 0x7b0c,
+ 0x7b24, 0x7b84,
+ 0x7b8c, 0x7c2c,
+ 0x7c34, 0x7c40,
+ 0x7c48, 0x7c68,
+ 0x7c70, 0x7c7c,
+ 0x7d00, 0x7ddc,
+ 0x7de4, 0x7e38,
+ 0x7e40, 0x7e44,
+ 0x7e4c, 0x7e74,
+ 0x7e80, 0x7ee0,
+ 0x7ee8, 0x7f0c,
+ 0x7f20, 0x7f5c,
+ 0x8dc0, 0x8de8,
+ 0x8df8, 0x8e04,
+ 0x8e10, 0x8e30,
+ 0x8e7c, 0x8ee8,
+ 0x8f88, 0x8f88,
+ 0x8f90, 0x8fb0,
+ 0x8fb8, 0x9058,
+ 0x9074, 0x90f8,
+ 0x9100, 0x912c,
+ 0x9138, 0x9188,
+ 0x9400, 0x9414,
+ 0x9430, 0x9440,
+ 0x9454, 0x9454,
+ 0x945c, 0x947c,
+ 0x9498, 0x94b8,
+ 0x9600, 0x9600,
+ 0x9608, 0x9638,
+ 0x9640, 0x9704,
+ 0x9710, 0x971c,
+ 0x9800, 0x9804,
+ 0x9854, 0x9854,
+ 0x9c00, 0x9c6c,
+ 0x9c80, 0x9cec,
+ 0x9d00, 0x9d6c,
+ 0x9d80, 0x9dec,
+ 0x9e00, 0x9e6c,
+ 0x9e80, 0x9eec,
+ 0x9f00, 0x9f6c,
+ 0x9f80, 0x9fec,
+ 0xa000, 0xa06c,
+ 0xa080, 0xa0ec,
+ 0xa100, 0xa16c,
+ 0xa180, 0xa1ec,
+ 0xa200, 0xa26c,
+ 0xa280, 0xa2ec,
+ 0xa300, 0xa36c,
+ 0xa380, 0xa458,
+ 0xa460, 0xa4f8,
+ 0xd000, 0xd03c,
+ 0xd100, 0xd134,
+ 0xd200, 0xd214,
+ 0xd220, 0xd234,
+ 0xd240, 0xd254,
+ 0xd260, 0xd274,
+ 0xd280, 0xd294,
+ 0xd2a0, 0xd2b4,
+ 0xd2c0, 0xd2d4,
+ 0xd2e0, 0xd2f4,
+ 0xd300, 0xd31c,
+ 0xdfc0, 0xdfe0,
+ 0xe000, 0xe00c,
+ 0xf000, 0xf008,
+ 0xf010, 0xf06c,
+ 0x11000, 0x11014,
+ 0x11048, 0x11120,
+ 0x11130, 0x11144,
+ 0x11174, 0x11178,
+ 0x11190, 0x111a0,
+ 0x111e4, 0x112f0,
+ 0x11300, 0x1133c,
+ 0x11408, 0x1146c,
+ 0x12000, 0x12004,
+ 0x12060, 0x122c4,
+ 0x19040, 0x1906c,
+ 0x19078, 0x19080,
+ 0x1908c, 0x190e8,
+ 0x190f0, 0x190f8,
+ 0x19100, 0x19110,
+ 0x19120, 0x19124,
+ 0x19150, 0x19194,
+ 0x1919c, 0x191a0,
+ 0x191ac, 0x191c8,
+ 0x191d0, 0x191e4,
+ 0x19250, 0x19250,
+ 0x19258, 0x19268,
+ 0x19278, 0x19278,
+ 0x19280, 0x192b0,
+ 0x192bc, 0x192f0,
+ 0x19300, 0x19308,
+ 0x19310, 0x19318,
+ 0x19320, 0x19328,
+ 0x19330, 0x19330,
+ 0x19348, 0x1934c,
+ 0x193f8, 0x19428,
+ 0x19430, 0x19444,
+ 0x1944c, 0x1946c,
+ 0x19474, 0x1947c,
+ 0x19488, 0x194cc,
+ 0x194f0, 0x194f8,
+ 0x19c00, 0x19c48,
+ 0x19c50, 0x19c80,
+ 0x19c94, 0x19c98,
+ 0x19ca0, 0x19cdc,
+ 0x19ce4, 0x19cf8,
+ 0x19d00, 0x19d30,
+ 0x19d50, 0x19d80,
+ 0x19d94, 0x19d98,
+ 0x19da0, 0x19de0,
+ 0x19df0, 0x19e10,
+ 0x19e50, 0x19e6c,
+ 0x19ea0, 0x19ebc,
+ 0x19ec4, 0x19ef4,
+ 0x19f04, 0x19f2c,
+ 0x19f34, 0x19f34,
+ 0x19f40, 0x19f50,
+ 0x19f90, 0x19fb4,
+ 0x19fbc, 0x19fbc,
+ 0x19fc4, 0x19fc8,
+ 0x19fd0, 0x19fe4,
+ 0x1a000, 0x1a004,
+ 0x1a010, 0x1a06c,
+ 0x1a0b0, 0x1a0e4,
+ 0x1a0ec, 0x1a108,
+ 0x1a114, 0x1a130,
+ 0x1a138, 0x1a1c4,
+ 0x1a1fc, 0x1a29c,
+ 0x1a2a8, 0x1a2b8,
+ 0x1a2c0, 0x1a388,
+ 0x1a398, 0x1a3ac,
+ 0x1e008, 0x1e00c,
+ 0x1e040, 0x1e044,
+ 0x1e04c, 0x1e04c,
+ 0x1e284, 0x1e290,
+ 0x1e2c0, 0x1e2c0,
+ 0x1e2e0, 0x1e2e4,
+ 0x1e300, 0x1e384,
+ 0x1e3c0, 0x1e3c8,
+ 0x1e408, 0x1e40c,
+ 0x1e440, 0x1e444,
+ 0x1e44c, 0x1e44c,
+ 0x1e684, 0x1e690,
+ 0x1e6c0, 0x1e6c0,
+ 0x1e6e0, 0x1e6e4,
+ 0x1e700, 0x1e784,
+ 0x1e7c0, 0x1e7c8,
+ 0x1e808, 0x1e80c,
+ 0x1e840, 0x1e844,
+ 0x1e84c, 0x1e84c,
+ 0x1ea84, 0x1ea90,
+ 0x1eac0, 0x1eac0,
+ 0x1eae0, 0x1eae4,
+ 0x1eb00, 0x1eb84,
+ 0x1ebc0, 0x1ebc8,
+ 0x1ec08, 0x1ec0c,
+ 0x1ec40, 0x1ec44,
+ 0x1ec4c, 0x1ec4c,
+ 0x1ee84, 0x1ee90,
+ 0x1eec0, 0x1eec0,
+ 0x1eee0, 0x1eee4,
+ 0x1ef00, 0x1ef84,
+ 0x1efc0, 0x1efc8,
+ 0x1f008, 0x1f00c,
+ 0x1f040, 0x1f044,
+ 0x1f04c, 0x1f04c,
+ 0x1f284, 0x1f290,
+ 0x1f2c0, 0x1f2c0,
+ 0x1f2e0, 0x1f2e4,
+ 0x1f300, 0x1f384,
+ 0x1f3c0, 0x1f3c8,
+ 0x1f408, 0x1f40c,
+ 0x1f440, 0x1f444,
+ 0x1f44c, 0x1f44c,
+ 0x1f684, 0x1f690,
+ 0x1f6c0, 0x1f6c0,
+ 0x1f6e0, 0x1f6e4,
+ 0x1f700, 0x1f784,
+ 0x1f7c0, 0x1f7c8,
+ 0x1f808, 0x1f80c,
+ 0x1f840, 0x1f844,
+ 0x1f84c, 0x1f84c,
+ 0x1fa84, 0x1fa90,
+ 0x1fac0, 0x1fac0,
+ 0x1fae0, 0x1fae4,
+ 0x1fb00, 0x1fb84,
+ 0x1fbc0, 0x1fbc8,
+ 0x1fc08, 0x1fc0c,
+ 0x1fc40, 0x1fc44,
+ 0x1fc4c, 0x1fc4c,
+ 0x1fe84, 0x1fe90,
+ 0x1fec0, 0x1fec0,
+ 0x1fee0, 0x1fee4,
+ 0x1ff00, 0x1ff84,
+ 0x1ffc0, 0x1ffc8,
+ 0x30000, 0x30038,
+ 0x30100, 0x3017c,
+ 0x30190, 0x301a0,
+ 0x301a8, 0x301b8,
+ 0x301c4, 0x301c8,
+ 0x301d0, 0x301e0,
+ 0x30200, 0x30344,
+ 0x30400, 0x304b4,
+ 0x304c0, 0x3052c,
+ 0x30540, 0x3065c,
+ 0x30800, 0x30848,
+ 0x30850, 0x308a8,
+ 0x308b8, 0x308c0,
+ 0x308cc, 0x308dc,
+ 0x30900, 0x30904,
+ 0x3090c, 0x30914,
+ 0x3091c, 0x30928,
+ 0x30930, 0x3093c,
+ 0x30944, 0x30948,
+ 0x30954, 0x30974,
+ 0x3097c, 0x30980,
+ 0x30a00, 0x30a20,
+ 0x30a38, 0x30a3c,
+ 0x30a50, 0x30a50,
+ 0x30a80, 0x30a80,
+ 0x30a88, 0x30aa8,
+ 0x30ab0, 0x30ab4,
+ 0x30ac8, 0x30ad4,
+ 0x30b28, 0x30b84,
+ 0x30b98, 0x30bb8,
+ 0x30c98, 0x30d14,
+ 0x31000, 0x31020,
+ 0x31038, 0x3103c,
+ 0x31050, 0x31050,
+ 0x31080, 0x31080,
+ 0x31088, 0x310a8,
+ 0x310b0, 0x310b4,
+ 0x310c8, 0x310d4,
+ 0x31128, 0x31184,
+ 0x31198, 0x311b8,
+ 0x32000, 0x32038,
+ 0x32100, 0x3217c,
+ 0x32190, 0x321a0,
+ 0x321a8, 0x321b8,
+ 0x321c4, 0x321c8,
+ 0x321d0, 0x321e0,
+ 0x32200, 0x32344,
+ 0x32400, 0x324b4,
+ 0x324c0, 0x3252c,
+ 0x32540, 0x3265c,
+ 0x32800, 0x32848,
+ 0x32850, 0x328a8,
+ 0x328b8, 0x328c0,
+ 0x328cc, 0x328dc,
+ 0x32900, 0x32904,
+ 0x3290c, 0x32914,
+ 0x3291c, 0x32928,
+ 0x32930, 0x3293c,
+ 0x32944, 0x32948,
+ 0x32954, 0x32974,
+ 0x3297c, 0x32980,
+ 0x32a00, 0x32a20,
+ 0x32a38, 0x32a3c,
+ 0x32a50, 0x32a50,
+ 0x32a80, 0x32a80,
+ 0x32a88, 0x32aa8,
+ 0x32ab0, 0x32ab4,
+ 0x32ac8, 0x32ad4,
+ 0x32b28, 0x32b84,
+ 0x32b98, 0x32bb8,
+ 0x32c98, 0x32d14,
+ 0x33000, 0x33020,
+ 0x33038, 0x3303c,
+ 0x33050, 0x33050,
+ 0x33080, 0x33080,
+ 0x33088, 0x330a8,
+ 0x330b0, 0x330b4,
+ 0x330c8, 0x330d4,
+ 0x33128, 0x33184,
+ 0x33198, 0x331b8,
+ 0x34000, 0x34038,
+ 0x34100, 0x3417c,
+ 0x34190, 0x341a0,
+ 0x341a8, 0x341b8,
+ 0x341c4, 0x341c8,
+ 0x341d0, 0x341e0,
+ 0x34200, 0x34344,
+ 0x34400, 0x344b4,
+ 0x344c0, 0x3452c,
+ 0x34540, 0x3465c,
+ 0x34800, 0x34848,
+ 0x34850, 0x348a8,
+ 0x348b8, 0x348c0,
+ 0x348cc, 0x348dc,
+ 0x34900, 0x34904,
+ 0x3490c, 0x34914,
+ 0x3491c, 0x34928,
+ 0x34930, 0x3493c,
+ 0x34944, 0x34948,
+ 0x34954, 0x34974,
+ 0x3497c, 0x34980,
+ 0x34a00, 0x34a20,
+ 0x34a38, 0x34a3c,
+ 0x34a50, 0x34a50,
+ 0x34a80, 0x34a80,
+ 0x34a88, 0x34aa8,
+ 0x34ab0, 0x34ab4,
+ 0x34ac8, 0x34ad4,
+ 0x34b28, 0x34b84,
+ 0x34b98, 0x34bb8,
+ 0x34c98, 0x34d14,
+ 0x35000, 0x35020,
+ 0x35038, 0x3503c,
+ 0x35050, 0x35050,
+ 0x35080, 0x35080,
+ 0x35088, 0x350a8,
+ 0x350b0, 0x350b4,
+ 0x350c8, 0x350d4,
+ 0x35128, 0x35184,
+ 0x35198, 0x351b8,
+ 0x36000, 0x36038,
+ 0x36100, 0x3617c,
+ 0x36190, 0x361a0,
+ 0x361a8, 0x361b8,
+ 0x361c4, 0x361c8,
+ 0x361d0, 0x361e0,
+ 0x36200, 0x36344,
+ 0x36400, 0x364b4,
+ 0x364c0, 0x3652c,
+ 0x36540, 0x3665c,
+ 0x36800, 0x36848,
+ 0x36850, 0x368a8,
+ 0x368b8, 0x368c0,
+ 0x368cc, 0x368dc,
+ 0x36900, 0x36904,
+ 0x3690c, 0x36914,
+ 0x3691c, 0x36928,
+ 0x36930, 0x3693c,
+ 0x36944, 0x36948,
+ 0x36954, 0x36974,
+ 0x3697c, 0x36980,
+ 0x36a00, 0x36a20,
+ 0x36a38, 0x36a3c,
+ 0x36a50, 0x36a50,
+ 0x36a80, 0x36a80,
+ 0x36a88, 0x36aa8,
+ 0x36ab0, 0x36ab4,
+ 0x36ac8, 0x36ad4,
+ 0x36b28, 0x36b84,
+ 0x36b98, 0x36bb8,
+ 0x36c98, 0x36d14,
+ 0x37000, 0x37020,
+ 0x37038, 0x3703c,
+ 0x37050, 0x37050,
+ 0x37080, 0x37080,
+ 0x37088, 0x370a8,
+ 0x370b0, 0x370b4,
+ 0x370c8, 0x370d4,
+ 0x37128, 0x37184,
+ 0x37198, 0x371b8,
+ 0x38000, 0x380b0,
+ 0x380b8, 0x38130,
+ 0x38140, 0x38140,
+ 0x38150, 0x38154,
+ 0x38160, 0x381c4,
+ 0x381d0, 0x38204,
+ 0x3820c, 0x38214,
+ 0x3821c, 0x3822c,
+ 0x38244, 0x38244,
+ 0x38254, 0x38274,
+ 0x3827c, 0x38280,
+ 0x38300, 0x38304,
+ 0x3830c, 0x38314,
+ 0x3831c, 0x3832c,
+ 0x38344, 0x38344,
+ 0x38354, 0x38374,
+ 0x3837c, 0x38380,
+ 0x38400, 0x38424,
+ 0x38438, 0x3843c,
+ 0x38480, 0x38480,
+ 0x384a8, 0x384a8,
+ 0x384b0, 0x384b4,
+ 0x384c8, 0x38514,
+ 0x38600, 0x3860c,
+ 0x3861c, 0x38624,
+ 0x38900, 0x38924,
+ 0x38938, 0x3893c,
+ 0x38980, 0x38980,
+ 0x389a8, 0x389a8,
+ 0x389b0, 0x389b4,
+ 0x389c8, 0x38a14,
+ 0x38b00, 0x38b0c,
+ 0x38b1c, 0x38b24,
+ 0x38e00, 0x38e00,
+ 0x38e18, 0x38e20,
+ 0x38e38, 0x38e40,
+ 0x38e58, 0x38e60,
+ 0x38e78, 0x38e80,
+ 0x38e98, 0x38ea0,
+ 0x38eb8, 0x38ec0,
+ 0x38ed8, 0x38ee0,
+ 0x38ef8, 0x38f08,
+ 0x38f10, 0x38f2c,
+ 0x38f80, 0x38ffc,
+ 0x39080, 0x39080,
+ 0x39088, 0x39090,
+ 0x39100, 0x39108,
+ 0x39120, 0x39128,
+ 0x39140, 0x39148,
+ 0x39160, 0x39168,
+ 0x39180, 0x39188,
+ 0x391a0, 0x391a8,
+ 0x391c0, 0x391c8,
+ 0x391e0, 0x391e8,
+ 0x39200, 0x39200,
+ 0x39208, 0x39240,
+ 0x39300, 0x39300,
+ 0x39308, 0x39340,
+ 0x39400, 0x39400,
+ 0x39408, 0x39440,
+ 0x39500, 0x39500,
+ 0x39508, 0x39540,
+ 0x39600, 0x39600,
+ 0x39608, 0x39640,
+ 0x39700, 0x39700,
+ 0x39708, 0x39740,
+ 0x39800, 0x39800,
+ 0x39808, 0x39840,
+ 0x39900, 0x39900,
+ 0x39908, 0x39940,
+ 0x39a00, 0x39a04,
+ 0x39a10, 0x39a14,
+ 0x39a1c, 0x39aa8,
+ 0x39b00, 0x39ecc,
+ 0x3a000, 0x3a004,
+ 0x3a050, 0x3a084,
+ 0x3a090, 0x3a09c,
+ 0x3a93c, 0x3a93c,
+ 0x3b93c, 0x3b93c,
+ 0x3c93c, 0x3c93c,
+ 0x3d93c, 0x3d93c,
+ 0x3e000, 0x3e020,
+ 0x3e03c, 0x3e05c,
+ 0x3e100, 0x3e120,
+ 0x3e13c, 0x3e15c,
+ 0x3e200, 0x3e220,
+ 0x3e23c, 0x3e25c,
+ 0x3e300, 0x3e320,
+ 0x3e33c, 0x3e35c,
+ 0x3f000, 0x3f034,
+ 0x3f100, 0x3f130,
+ 0x3f200, 0x3f218,
+ 0x44000, 0x44014,
+ 0x44020, 0x44028,
+ 0x44030, 0x44030,
+ 0x44100, 0x44114,
+ 0x44120, 0x44128,
+ 0x44130, 0x44130,
+ 0x44200, 0x44214,
+ 0x44220, 0x44228,
+ 0x44230, 0x44230,
+ 0x44300, 0x44314,
+ 0x44320, 0x44328,
+ 0x44330, 0x44330,
+ 0x44400, 0x44414,
+ 0x44420, 0x44428,
+ 0x44430, 0x44430,
+ 0x44500, 0x44514,
+ 0x44520, 0x44528,
+ 0x44530, 0x44530,
+ 0x44714, 0x44718,
+ 0x44730, 0x44730,
+ 0x447c0, 0x447c0,
+ 0x447f0, 0x447f0,
+ 0x447f8, 0x447fc,
+ 0x45000, 0x45014,
+ 0x45020, 0x45028,
+ 0x45030, 0x45030,
+ 0x45100, 0x45114,
+ 0x45120, 0x45128,
+ 0x45130, 0x45130,
+ 0x45200, 0x45214,
+ 0x45220, 0x45228,
+ 0x45230, 0x45230,
+ 0x45300, 0x45314,
+ 0x45320, 0x45328,
+ 0x45330, 0x45330,
+ 0x45400, 0x45414,
+ 0x45420, 0x45428,
+ 0x45430, 0x45430,
+ 0x45500, 0x45514,
+ 0x45520, 0x45528,
+ 0x45530, 0x45530,
+ 0x45714, 0x45718,
+ 0x45730, 0x45730,
+ 0x457c0, 0x457c0,
+ 0x457f0, 0x457f0,
+ 0x457f8, 0x457fc,
+ 0x46000, 0x46010,
+ 0x46020, 0x46034,
+ 0x46040, 0x46050,
+ 0x46060, 0x46088,
+ 0x47000, 0x4709c,
+ 0x470c0, 0x470d4,
+ 0x47100, 0x471a8,
+ 0x471b0, 0x471e8,
+ 0x47200, 0x47210,
+ 0x4721c, 0x47230,
+ 0x47238, 0x47238,
+ 0x47240, 0x472ac,
+ 0x472d0, 0x472f4,
+ 0x47300, 0x47310,
+ 0x47318, 0x47348,
+ 0x47350, 0x47354,
+ 0x47380, 0x47388,
+ 0x47390, 0x47394,
+ 0x47400, 0x47448,
+ 0x47450, 0x47458,
+ 0x47500, 0x4751c,
+ 0x47530, 0x4754c,
+ 0x47560, 0x4757c,
+ 0x47590, 0x475ac,
+ 0x47600, 0x47630,
+ 0x47640, 0x47644,
+ 0x47660, 0x4769c,
+ 0x47700, 0x47710,
+ 0x47740, 0x47750,
+ 0x4775c, 0x4779c,
+ 0x477b0, 0x477bc,
+ 0x477c4, 0x477c8,
+ 0x477d4, 0x477fc,
+ 0x48000, 0x48004,
+ 0x48018, 0x4801c,
+ 0x49304, 0x49320,
+ 0x4932c, 0x4932c,
+ 0x49334, 0x493f0,
+ 0x49400, 0x49410,
+ 0x49460, 0x494f4,
+ 0x50000, 0x50084,
+ 0x50090, 0x500cc,
+ 0x50300, 0x50384,
+ 0x50400, 0x50404,
+ 0x50800, 0x50884,
+ 0x50890, 0x508cc,
+ 0x50b00, 0x50b84,
+ 0x50c00, 0x50c04,
+ 0x51000, 0x51020,
+ 0x51028, 0x510c4,
+ 0x51104, 0x51108,
+ 0x51200, 0x51274,
+ 0x51300, 0x51324,
+ 0x51400, 0x51548,
+ 0x51550, 0x51554,
+ 0x5155c, 0x51584,
+ 0x5158c, 0x515c8,
+ 0x515f0, 0x515f4,
+ 0x58000, 0x58004,
+ 0x58018, 0x5801c,
+ 0x59304, 0x59320,
+ 0x5932c, 0x5932c,
+ 0x59334, 0x593f0,
+ 0x59400, 0x59410,
+ 0x59460, 0x594f4,
+ };
+
u32 *buf_end = (u32 *)((char *)buf + buf_size);
const unsigned int *reg_ranges;
int reg_ranges_size, range;
@@ -2661,6 +3314,11 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
break;
+ case CHELSIO_T7:
+ reg_ranges = t7_reg_ranges;
+ reg_ranges_size = ARRAY_SIZE(t7_reg_ranges);
+ break;
+
default:
dev_err(adap->pdev_dev,
"Unsupported chip version %d\n", chip_version);
@@ -2730,7 +3388,8 @@ int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
int t4_seeprom_wp(struct adapter *adapter, bool enable)
{
unsigned int v = enable ? 0xc : 0;
- int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
+
+ int ret = cxgb4_pci_write_vpd(adapter, EEPROM_STAT_ADDR, 4, &v);
return ret < 0 ? ret : 0;
}
@@ -2754,13 +3413,13 @@ int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
/* Card information normally starts at VPD_BASE but early cards had
* it at 0.
*/
- ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val);
+ ret = cxgb4_pci_read_vpd(adapter, VPD_BASE, 1, &base_val);
if (ret < 0)
goto out;
addr = base_val == PCI_VPD_LRDT_ID_STRING ? VPD_BASE : VPD_BASE_OLD;
- ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
+ ret = cxgb4_pci_read_vpd(adapter, addr, VPD_LEN, vpd);
if (ret < 0)
goto out;
@@ -2898,6 +3557,121 @@ int t4_get_pfres(struct adapter *adapter)
return 0;
}
+/* Flash Layout {start sector, # of sectors} for T4/T5/T6 adapters */
+static const struct t4_flash_loc_entry t4_flash_loc_arr[] = {
+ [FLASH_LOC_EXP_ROM] = { 0, 6 },
+ [FLASH_LOC_IBFT] = { 6, 1 },
+ [FLASH_LOC_BOOTCFG] = { 7, 1 },
+ [FLASH_LOC_FW] = { 8, 16 },
+ [FLASH_LOC_FWBOOTSTRAP] = { 27, 1 },
+ [FLASH_LOC_ISCSI_CRASH] = { 29, 1 },
+ [FLASH_LOC_FCOE_CRASH] = { 30, 1 },
+ [FLASH_LOC_CFG] = { 31, 1 },
+ [FLASH_LOC_CUDBG] = { 32, 32 },
+ [FLASH_LOC_BOOT_AREA] = { 0, 8 }, /* Spans complete Boot Area */
+ [FLASH_LOC_MIN_SIZE] = { 0, 32 }, /* Spans minimum required sections */
+ [FLASH_LOC_END] = { 0, 64 }, /* Spans the entire Serial Flash*/
+};
+
+/* Flash Layout {start sector, # of sectors} for T7 adapters */
+static const struct t4_flash_loc_entry t7_flash_loc_arr[] = {
+ [FLASH_LOC_VPD] = { 0, 1 },
+ [FLASH_LOC_FWBOOTSTRAP] = { 1, 1 },
+ [FLASH_LOC_FW] = { 2, 29 },
+ [FLASH_LOC_CFG] = { 31, 1 },
+ [FLASH_LOC_EXP_ROM] = { 32, 15 },
+ [FLASH_LOC_IBFT] = { 47, 1 },
+ [FLASH_LOC_BOOTCFG] = { 48, 1 },
+ [FLASH_LOC_ISCSI_CRASH] = { 62, 1 },
+ [FLASH_LOC_FCOE_CRASH] = { 63, 1 },
+ [FLASH_LOC_VPD_BACKUP] = { 64, 1 },
+ [FLASH_LOC_FWBOOTSTRAP_BACKUP] = { 65, 1 },
+ [FLASH_LOC_FW_BACKUP] = { 66, 29 },
+ [FLASH_LOC_CFG_BACK] = { 95, 1 },
+ [FLASH_LOC_CUDBG] = { 96, 48 },
+ [FLASH_LOC_CHIP_DUMP] = { 144, 48 },
+ [FLASH_LOC_BOOT_AREA] = { 32,
+ 17 }, /* Spans complete UEFI/PXE Boot Area */
+ [FLASH_LOC_MIN_SIZE] = { 0, 32 }, /* Spans minimum required sections */
+ [FLASH_LOC_END] = { 0, 256 }, /* Spans the entire Serial Flash*/
+};
+
+static const struct t4_flash_loc_entry *
+t4_flash_location_entry_get(struct adapter *adap, enum t4_flash_loc loc)
+{
+ const struct t4_flash_loc_entry *arr;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ arr = t7_flash_loc_arr;
+ else
+ arr = t4_flash_loc_arr;
+
+ return arr[loc].nsecs ? &arr[loc] : NULL;
+}
+
+int t4_flash_location_start_sec(struct adapter *adap, enum t4_flash_loc loc)
+{
+ const struct t4_flash_loc_entry *entry;
+
+ entry = t4_flash_location_entry_get(adap, loc);
+ if (!entry)
+ return -ENOENT;
+
+ return entry->start_sec;
+}
+
+int t4_flash_location_nsecs(struct adapter *adap, enum t4_flash_loc loc)
+{
+ const struct t4_flash_loc_entry *entry;
+
+ entry = t4_flash_location_entry_get(adap, loc);
+ if (!entry)
+ return -ENOENT;
+
+ return entry->nsecs;
+}
+
+int t4_flash_location_start(struct adapter *adap, enum t4_flash_loc loc)
+{
+ int ret = t4_flash_location_start_sec(adap, loc);
+
+ if (ret < 0)
+ return ret;
+
+ return FLASH_START(ret);
+}
+
+int t4_flash_location_size(struct adapter *adap, enum t4_flash_loc loc)
+{
+ int ret = t4_flash_location_nsecs(adap, loc);
+
+ if (ret < 0)
+ return ret;
+
+ return FLASH_MAX_SIZE(ret);
+}
+
+static int t4_flash_location_end(struct adapter *adap, enum t4_flash_loc loc)
+{
+ int ret = t4_flash_location_size(adap, loc);
+
+ if (ret < 0)
+ return ret;
+
+ return t4_flash_location_start(adap, loc) + ret;
+}
+
+static bool t4_flash_location_in_range(struct adapter *adap,
+ enum t4_flash_loc loc, u32 addr)
+{
+ int ret = t4_flash_location_end(adap, loc);
+
+ if (ret < 0)
+ return false;
+
+ return addr >= t4_flash_location_start(adap, loc) && addr < ret;
+}
+
/* serial flash and firmware constants */
enum {
SF_ATTEMPTS = 10, /* max retries for SF operations */
@@ -2933,8 +3707,15 @@ static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
return -EINVAL;
if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
return -EBUSY;
- t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
- SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
+ if (is_t7(adapter->params.chip))
+ t4_write_reg(adapter, SF_OP_A, QUADREADDISABLE_F |
+ SF_LOCK_V(lock) | SF_CONT_V(cont) |
+ BYTECNT_V(byte_cnt - 1));
+ else
+ t4_write_reg(adapter, SF_OP_A,
+ SF_LOCK_V(lock) | SF_CONT_V(cont) |
+ BYTECNT_V(byte_cnt - 1));
+
ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
if (!ret)
*valp = t4_read_reg(adapter, SF_DATA_A);
@@ -3107,8 +3888,12 @@ static int t4_write_flash(struct adapter *adapter, unsigned int addr,
*/
int t4_get_fw_version(struct adapter *adapter, u32 *vers)
{
- return t4_read_flash(adapter, FLASH_FW_START +
- offsetof(struct fw_hdr, fw_ver), 1,
+ int ret = t4_flash_location_start(adapter, FLASH_LOC_FW);
+
+ if (ret < 0)
+ return ret;
+
+ return t4_read_flash(adapter, ret + offsetof(struct fw_hdr, fw_ver), 1,
vers, 0);
}
@@ -3121,8 +3906,12 @@ int t4_get_fw_version(struct adapter *adapter, u32 *vers)
*/
int t4_get_bs_version(struct adapter *adapter, u32 *vers)
{
- return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
- offsetof(struct fw_hdr, fw_ver), 1,
+ int ret = t4_flash_location_start(adapter, FLASH_LOC_FWBOOTSTRAP);
+
+ if (ret < 0)
+ return ret;
+
+ return t4_read_flash(adapter, ret + offsetof(struct fw_hdr, fw_ver), 1,
vers, 0);
}
@@ -3135,12 +3924,17 @@ int t4_get_bs_version(struct adapter *adapter, u32 *vers)
*/
int t4_get_tp_version(struct adapter *adapter, u32 *vers)
{
- return t4_read_flash(adapter, FLASH_FW_START +
- offsetof(struct fw_hdr, tp_microcode_ver),
- 1, vers, 0);
-}
+ int ret = t4_flash_location_start(adapter, FLASH_LOC_FW);
-/**
+ if (ret < 0)
+ return ret;
+
+ return t4_read_flash(adapter,
+ ret + offsetof(struct fw_hdr, tp_microcode_ver), 1,
+ vers, 0);
+}
+
+/**
* t4_get_exprom_version - return the Expansion ROM version (if any)
* @adap: the adapter
* @vers: where to place the version
@@ -3160,9 +3954,13 @@ int t4_get_exprom_version(struct adapter *adap, u32 *vers)
sizeof(u32))];
int ret;
- ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
- ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
- 0);
+ ret = t4_flash_location_start(adap, FLASH_LOC_EXP_ROM);
+ if (ret < 0)
+ return ret;
+
+ ret = t4_read_flash(adap, ret, ARRAY_SIZE(exprom_header_buf),
+ exprom_header_buf, 0);
+
if (ret)
return ret;
@@ -3360,9 +4158,9 @@ void t4_dump_version_info(struct adapter *adapter)
*/
int t4_check_fw_version(struct adapter *adap)
{
- int i, ret, major, minor, micro;
- int exp_major, exp_minor, exp_micro;
unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
+ int exp_major, exp_minor, exp_micro;
+ int i, ret, major, minor, micro;
ret = t4_get_fw_version(adap, &adap->params.fw_vers);
/* Try multiple times before returning error */
@@ -3392,6 +4190,11 @@ int t4_check_fw_version(struct adapter *adap)
exp_minor = T6FW_MIN_VERSION_MINOR;
exp_micro = T6FW_MIN_VERSION_MICRO;
break;
+ case CHELSIO_T7:
+ exp_major = T7FW_MIN_VERSION_MAJOR;
+ exp_minor = T7FW_MIN_VERSION_MINOR;
+ exp_micro = T7FW_MIN_VERSION_MICRO;
+ break;
default:
dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
adap->chip);
@@ -3470,10 +4273,12 @@ int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
const struct fw_hdr *drv_fw;
drv_fw = &fw_info->fw_hdr;
+ ret = t4_flash_location_start(adap, FLASH_LOC_FW);
+ if (ret < 0)
+ return ret;
/* Read the header of the firmware on the card */
- ret = t4_read_flash(adap, FLASH_FW_START,
- sizeof(*card_fw) / sizeof(uint32_t),
+ ret = t4_read_flash(adap, ret, sizeof(*card_fw) / sizeof(uint32_t),
(uint32_t *)card_fw, 1);
if (ret == 0) {
card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
@@ -3585,10 +4390,16 @@ static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
*/
unsigned int t4_flash_cfg_addr(struct adapter *adapter)
{
- if (adapter->params.sf_size == 0x100000)
- return FLASH_FPGA_CFG_START;
+ int ret = t4_flash_location_end(adapter, FLASH_LOC_CFG);
+
+ /*
+ * If the device FLASH isn't large enough to hold a Firmware
+ * Configuration File, return an error.
+ */
+ if (ret < 0 || adapter->params.sf_size < ret)
+ return -ENOSPC;
else
- return FLASH_CFG_START;
+ return t4_flash_location_start(adapter, FLASH_LOC_CFG);
}
/* Return TRUE if the specified firmware matches the adapter. I.e. T4
@@ -3604,7 +4415,9 @@ static bool t4_fw_matches_chip(const struct adapter *adap,
*/
if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
(is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
- (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
+ (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6) ||
+ (is_t7(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T7))
+
return true;
dev_err(adap->pdev_dev,
@@ -3623,16 +4436,17 @@ static bool t4_fw_matches_chip(const struct adapter *adap,
*/
int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
{
- u32 csum;
- int ret, addr;
- unsigned int i;
- u8 first_page[SF_PAGE_SIZE];
- const __be32 *p = (const __be32 *)fw_data;
- const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
- unsigned int fw_start_sec = FLASH_FW_START_SEC;
- unsigned int fw_size = FLASH_FW_MAX_SIZE;
- unsigned int fw_start = FLASH_FW_START;
+ const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
+ const __be32 *p = (const __be32 *)fw_data;
+ u8 first_page[SF_PAGE_SIZE];
+ unsigned int fw_start_sec;
+ enum t4_flash_loc loc;
+ unsigned int fw_start;
+ unsigned int fw_size;
+ unsigned int i;
+ int ret, addr;
+ u32 csum;
if (!size) {
dev_err(adap->pdev_dev, "FW image has no data\n");
@@ -3648,6 +4462,20 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
"FW image size differs from size in FW header\n");
return -EINVAL;
}
+
+ loc = FLASH_LOC_FW;
+ ret = t4_flash_location_size(adap, loc);
+ if (ret < 0) {
+ dev_err(adap->pdev_dev,
+ "Error finding Flash location (%u). ret: %d\n", loc,
+ ret);
+ return ret;
+ }
+
+ fw_size = ret;
+ fw_start_sec = t4_flash_location_start_sec(adap, loc);
+ fw_start = t4_flash_location_start(adap, loc);
+
if (size > fw_size) {
dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
fw_size);
@@ -4289,7 +5117,6 @@ static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
int fatal = 0;
unsigned int mask = 0;
unsigned int status = t4_read_reg(adapter, reg);
-
for ( ; acts->mask; ++acts) {
if (!(status & acts->mask))
continue;
@@ -4305,7 +5132,7 @@ static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
mask |= acts->mask;
}
status &= mask;
- if (status) /* clear processed interrupts */
+ if (status) /* clear processed interrupts */
t4_write_reg(adapter, reg, status);
return fatal;
}
@@ -4440,7 +5267,17 @@ static void tp_intr_handler(struct adapter *adapter)
{ 0 }
};
- if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
+ static const struct intr_info t7_tp_intr_info[] = {
+ { 0xbfffffff, "TP parity error", -1, 1 },
+ { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
+ { 0 }
+ };
+ u32 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
+
+ if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A,
+ chip_ver >= CHELSIO_T7 ? t7_tp_intr_info :
+ tp_intr_info))
+
t4_fatal_err(adapter);
}
@@ -4484,6 +5321,53 @@ static void sge_intr_handler(struct adapter *adapter)
{ 0 }
};
+ static struct intr_info cause_sge_intr_info[] = {
+ { ERR_FLM_DBP_F,
+ "DBP pointer delivery for invalid context or QID", -1, 0, 0 },
+ { ERR_FLM_IDMA1_F | ERR_FLM_IDMA0_F,
+ "Invalid QID or header request by IDMA", -1, 0, 0 },
+ { ERR_FLM_HINT_F, "FLM hint is for invalid context or QID", -1,
+ 0, 0 },
+ { ERR_PCIE_ERROR3_F, "SGE PCIe error for DBP thread 3", -1, 0,
+ 0 },
+ { ERR_PCIE_ERROR2_F, "SGE PCIe error for DBP thread 2", -1, 0,
+ 0 },
+ { ERR_PCIE_ERROR1_F, "SGE PCIe error for DBP thread 1", -1, 0,
+ 0 },
+ { ERR_PCIE_ERROR0_F, "SGE PCIe error for DBP thread 0", -1, 0,
+ 0 },
+ { ERR_TIMER_ABOVE_MAX_QID_F,
+ "SGE GTS with timer 0-5 for IQID > 1023", -1, 0, 0 },
+ { ERR_CPL_EXCEED_IQE_SIZE_F,
+ "SGE received CPL exceeding IQE size", -1, 0, 0 },
+ { ERR_INVALID_CIDX_INC_F, "SGE GTS CIDX increment too large",
+ -1, 0, 0 },
+ { ERR_ITP_TIME_PAUSED_F, "SGE ITP error", -1, 0, 0 },
+ { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0, 0 },
+ { ERR_DROPPED_DB_F, "SGE DB dropped", -1, 0, 0 },
+ { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
+ "SGE IQID > 1023 received CPL for FL", -1, 0, 0 },
+ { ERR_BAD_DB_PIDX3_F | ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
+ ERR_BAD_DB_PIDX0_F,
+ "SGE DBP pidx increment too large", -1, 0, 0 },
+ { ERR_ING_PCIE_CHAN_F, "SGE Ingress PCIe channel mismatch", -1,
+ 0, 0 },
+ { ERR_ING_CTXT_PRIO_F,
+ "Ingress context manager priority user error", -1, 0, 0 },
+ { ERR_EGR_CTXT_PRIO_F,
+ "Egress context manager priority user error", -1, 0, 0 },
+ { DBP_TBUF_FULL_F, "SGE DBP tbuf full", -1, 0, 0 },
+ { FATAL_WRE_LEN_F, "SGE WRE packet less than advertized length",
+ -1, 0, 0 },
+ { REG_ADDRESS_ERR_F, "Undefined SGE register accessed", -1, 0,
+ 0 },
+ { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0, 0 },
+ { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0, 0 },
+ { 0x0000000f, "SGE context access for invalid queue", -1, 0,
+ 0 },
+ { 0 }
+ };
+
perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
if (perr) {
v |= perr;
@@ -4498,6 +5382,18 @@ static void sge_intr_handler(struct adapter *adapter)
perr);
}
+ perr = t4_read_reg(adapter, SGE_INT_CAUSE4_A);
+ if (perr) {
+ v |= perr;
+ dev_alert(adapter->pdev_dev, "SGE Cause4 Parity Error %#x\n",
+ perr);
+ }
+
+ v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
+ v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
+ t4t5_sge_intr_info);
+
if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
/* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
@@ -4509,10 +5405,13 @@ static void sge_intr_handler(struct adapter *adapter)
}
}
- v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
- v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
- t4t5_sge_intr_info);
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T6)
+ v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE6_A, cause_sge_intr_info);
+
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T7) {
+ v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE7_A, cause_sge_intr_info);
+ v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE8_A, cause_sge_intr_info);
+ }
err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
if (err & ERROR_QID_VALID_F) {
@@ -4710,6 +5609,11 @@ static void cplsw_intr_handler(struct adapter *adapter)
t4_fatal_err(adapter);
}
+#define T6_LE_PERRCRC_MASK (PIPELINEERR_F | CLIPTCAMACCFAIL_F | \
+ SRVSRAMACCFAIL_F | CLCAMCRCPARERR_F | CLCAMINTPERR_F | SSRAMINTPERR_F | \
+ SRVSRAMPERR_F | VFSRAMPERR_F | TCAMINTPERR_F | TCAMCRCERR_F | \
+ HASHTBLMEMACCERR_F | MAIFWRINTPERR_F | HASHTBLMEMCRCERR_F)
+
/*
* LE interrupt handler.
*/
@@ -4725,20 +5629,33 @@ static void le_intr_handler(struct adapter *adap)
{ 0 }
};
- static struct intr_info t6_le_intr_info[] = {
- { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
- { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
- { CMDTIDERR_F, "LE cmd tid error", -1, 1 },
- { TCAMINTPERR_F, "LE parity error", -1, 1 },
+ static const struct intr_info t6_le_intr_details[] = {
+ { CACHEINTPERR_F, "Parity error in cache module", -1, 1 },
+ { CACHESRAMPERR_F, "Parity error in data sram ", -1, 1 },
+ { CLIPSUBERR_F, "LE CLIP CAM reverse substitution error", -1, 1 },
+ { CLCAMFIFOERR_F, "LE CLIP CAM internal FIFO error", -1, 1 },
+ { CTCAMINVLDENT_F, "Invalid IPv6 CLIP TCAM entry", -1, 0 },
+ { TCAMINVLDENT_F, "Invalid IPv6 TCAM entry", -1, 0 },
+ { TOTCNTERR_F, "LE total active < TCAM count", -1, 1 },
+ { CMDPRSRINTERR_F, "LE internal error in parser", -1, 1 },
+ { CMDTIDERR_F, "Incorrect tid in LE command", -1, 1 },
+ { T6_ACTRGNFULL_F, "LE active region full", -1, 0 },
+ { T6_ACTCNTIPV6TZERO_F, "LE IPv6 active open TCAM counter -ve", -1, 0 },
+ { T6_ACTCNTIPV4TZERO_F, "LE IPv4 active open TCAM counter -ve", -1, 0 },
+ { T6_ACTCNTIPV6ZERO_F, "LE IPv6 active open counter -ve", -1, 0 },
+ { T6_ACTCNTIPV4ZERO_F, "LE IPv4 active open counter -ve", -1, 0 },
+ { HASHTBLACCFAIL_F, "Hash table read error (proto conflict)", -1, 1 },
+ { TCAMACCFAIL_F, "LE TCAM access failure", -1, 1 },
{ T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
- { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
- { HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 },
+ { T6_LIP0_F, "LE found 0 LIP during CLIP substitution", -1, 0 },
+ { T6_LIPMISS_F, "LE CLIP lookup miss", -1, 0 },
+ { T6_LE_PERRCRC_MASK, "LE parity/CRC error", -1, 1 },
{ 0 }
};
if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
(chip <= CHELSIO_T5) ?
- le_intr_info : t6_le_intr_info))
+ le_intr_info : t6_le_intr_details))
t4_fatal_err(adap);
}
@@ -4801,15 +5718,18 @@ static void mps_intr_handler(struct adapter *adapter)
{ 0 }
};
+ int chip = CHELSIO_CHIP_VERSION(adapter->params.chip);
int fat;
fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
mps_rx_intr_info) +
t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
- is_t6(adapter->params.chip)
- ? t6_mps_tx_intr_info
- : mps_tx_intr_info) +
- t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
+ chip > CHELSIO_T5 ? t6_mps_tx_intr_info :
+ mps_tx_intr_info) +
+ t4_handle_intr_status(adapter,
+ chip >= CHELSIO_T7 ?
+ T7_MPS_TRC_INT_CAUSE_A :
+ MPS_TRC_INT_CAUSE_A,
mps_trc_intr_info) +
t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
mps_stat_sram_intr_info) +
@@ -4845,13 +5765,21 @@ static void mem_intr_handler(struct adapter *adapter, int idx)
if (is_t4(adapter->params.chip)) {
addr = MC_INT_CAUSE_A;
cnt_addr = MC_ECC_STATUS_A;
+ } else if (is_t7(adapter->params.chip)) {
+ addr = T7_MC_P_INT_CAUSE_A;
+ cnt_addr = T7_MC_P_ECC_STATUS_A;
} else {
addr = MC_P_INT_CAUSE_A;
cnt_addr = MC_P_ECC_STATUS_A;
}
} else {
- addr = MC_REG(MC_P_INT_CAUSE_A, 1);
- cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
+ if (is_t7(adapter->params.chip)) {
+ addr = MC_REG(T7_MC_P_INT_CAUSE_A, 1);
+ cnt_addr = MC_REG(T7_MC_P_ECC_STATUS_A, 1);
+ } else {
+ addr = MC_REG(MC_P_INT_CAUSE_A, 1);
+ cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
+ }
}
v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
@@ -4939,6 +5867,17 @@ static void ncsi_intr_handler(struct adapter *adap)
t4_fatal_err(adap);
}
+static u32 t4_port_reg(struct adapter *adap, u8 port, u32 reg)
+{
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ return T7_PORT_REG(port, reg);
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T4)
+ return T5_PORT_REG(port, reg);
+
+ return PORT_REG(port, reg);
+}
+
/*
* XGMAC interrupt handler.
*/
@@ -4946,10 +5885,13 @@ static void xgmac_intr_handler(struct adapter *adap, int port)
{
u32 v, int_cause_reg;
- if (is_t4(adap->params.chip))
- int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ int_cause_reg =
+ t4_port_reg(adap, port, T7_MAC_PORT_INT_CAUSE_A);
+ else if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T4)
+ int_cause_reg = t4_port_reg(adap, port, MAC_PORT_INT_CAUSE_A);
else
- int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
+ int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
v = t4_read_reg(adap, int_cause_reg);
@@ -4973,6 +5915,7 @@ static void xgmac_intr_handler(struct adapter *adap, int port)
static void pl_intr_handler(struct adapter *adap)
{
static const struct intr_info pl_intr_info[] = {
+ { INVALIDACCESS_F, "Invalid Access", -1, 0 },
{ FATALPERR_F, "T4 fatal parity error", -1, 1 },
{ PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
{ 0 }
@@ -4984,9 +5927,13 @@ static void pl_intr_handler(struct adapter *adap)
#define PF_INTR_MASK (PFSW_F)
#define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
- EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
- CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
+ EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
+ CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
+#define GLBL_T7_INTR_MASK \
+ (CIM_F | MPS_F | PL_F | T7_PCIE_F | T7_MC0_F | T7_EDC0_F | T7_EDC1_F | \
+ T7_LE_F | T7_TP_F | T7_MA_F | T7_PM_TX_F | T7_PM_RX_F | T7_ULP_RX_F | \
+ T7_CPL_SWITCH_F | T7_SGE_F | T7_ULP_TX_F | SF_F)
/**
* t4_slow_intr_handler - control path interrupt handler
* @adapter: the adapter
@@ -5001,12 +5948,17 @@ int t4_slow_intr_handler(struct adapter *adapter)
* set when the corresponding PL_INT_ENABLE bit isn't set. It's
* easiest just to mask that case here.
*/
+ u32 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
u32 cause = raw_cause & enable;
+ u32 mask;
+
+ mask = chip_ver >= CHELSIO_T7 ? GLBL_T7_INTR_MASK : GLBL_INTR_MASK;
- if (!(cause & GLBL_INTR_MASK))
+ if (!(cause & mask))
return 0;
+
if (cause & CIM_F)
cim_intr_handler(adapter);
if (cause & MPS_F)
@@ -5025,37 +5977,67 @@ int t4_slow_intr_handler(struct adapter *adapter)
xgmac_intr_handler(adapter, 2);
if (cause & XGMAC_KR1_F)
xgmac_intr_handler(adapter, 3);
- if (cause & PCIE_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_PCIE_F : PCIE_F;
+ if (cause & mask)
pcie_intr_handler(adapter);
- if (cause & MC_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_MC0_F : MC_F;
+ if (cause & mask)
mem_intr_handler(adapter, MEM_MC);
- if (is_t5(adapter->params.chip) && (cause & MC1_F))
- mem_intr_handler(adapter, MEM_MC1);
- if (cause & EDC0_F)
+ if (chip_ver != CHELSIO_T4 && chip_ver != CHELSIO_T6) {
+ mask = chip_ver >= CHELSIO_T7 ? T7_MC1_F : MC1_F;
+ if (cause & mask)
+ mem_intr_handler(adapter, MEM_MC1);
+ }
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_EDC0_F : EDC0_F;
+ if (cause & mask)
mem_intr_handler(adapter, MEM_EDC0);
- if (cause & EDC1_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_EDC1_F : EDC1_F;
+ if (cause & mask)
mem_intr_handler(adapter, MEM_EDC1);
- if (cause & LE_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_LE_F : LE_F;
+ if (cause & mask)
le_intr_handler(adapter);
- if (cause & TP_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_TP_F : TP_F;
+ if (cause & mask)
tp_intr_handler(adapter);
- if (cause & MA_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_MA_F : MA_F;
+ if (cause & mask)
ma_intr_handler(adapter);
- if (cause & PM_TX_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_PM_TX_F : PM_TX_F;
+ if (cause & mask)
pmtx_intr_handler(adapter);
- if (cause & PM_RX_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_PM_RX_F : PM_RX_F;
+ if (cause & mask)
pmrx_intr_handler(adapter);
- if (cause & ULP_RX_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_ULP_RX_F : ULP_RX_F;
+ if (cause & mask)
ulprx_intr_handler(adapter);
- if (cause & CPL_SWITCH_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_CPL_SWITCH_F : CPL_SWITCH_F;
+ if (cause & mask)
cplsw_intr_handler(adapter);
- if (cause & SGE_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_SGE_F : SGE_F;
+ if (cause & mask)
sge_intr_handler(adapter);
- if (cause & ULP_TX_F)
+
+ mask = chip_ver >= CHELSIO_T7 ? T7_ULP_TX_F : ULP_TX_F;
+ if (cause & mask)
ulptx_intr_handler(adapter);
/* Clear the interrupts just processed for which we are the master. */
- t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
+ mask = chip_ver >= CHELSIO_T7 ? GLBL_T7_INTR_MASK : GLBL_INTR_MASK;
+ t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & mask);
(void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
return 1;
}
@@ -5082,6 +6064,8 @@ void t4_intr_enable(struct adapter *adapter)
if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
+ else
+ val = ERR_PCIE_ERROR0_F | ERR_PCIE_ERROR1_F | FATAL_WRE_LEN_F;
t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
@@ -5105,9 +6089,6 @@ void t4_intr_disable(struct adapter *adapter)
{
u32 whoami, pf;
- if (pci_channel_offline(adapter->pdev))
- return;
-
whoami = t4_read_reg(adapter, PL_WHOAMI_A);
pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
@@ -5245,12 +6226,55 @@ int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
}
+/*
+ * t7_wait_sram_done - wait until an operation is completed
+ * @adapter: the adapter performing the operation
+ * @reg: the register to check for completion
+ * @result_reg: register that holds the result value
+ * @attempts: number of check iterations
+ * @delay: delay in usecs between iterations
+ * @valp: where to store the value of the result register at completion time
+ *
+ * Waits until a specific bit in @reg is cleared, checking up to
+ * @attempts times.Once the bit is cleared, reads from @result_reg
+ * and stores the value in @valp if it is not NULL. Returns 0 if the
+ * operation completes successfully and -EAGAIN if it times out.
+ */
+static int t7_wait_sram_done(struct adapter *adap, int reg, int result_reg,
+ int attempts, int delay, u32 *valp)
+{
+ while (1) {
+ u32 val = t4_read_reg(adap, reg);
+
+ /* Check if SramStart (bit 19) is cleared */
+ if (!(val & (1 << 19))) {
+ if (valp)
+ *valp = t4_read_reg(adap, result_reg);
+ return 0;
+ }
+
+ if (--attempts == 0)
+ return -EAGAIN;
+
+ if (delay)
+ udelay(delay);
+ }
+}
+
/* Read an RSS table row */
static int rd_rss_row(struct adapter *adap, int row, u32 *val)
{
- t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
- return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
- 5, 0, val);
+ int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ if (chip_ver < CHELSIO_T7) {
+ t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
+ return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A,
+ LKPTBLROWVLD_F, 1, 5, 0, val);
+ } else {
+ t4_write_reg(adap, TP_RSS_CONFIG_SRAM_A, 0xB0000 | row);
+ return t7_wait_sram_done(adap, TP_RSS_CONFIG_SRAM_A,
+ TP_RSS_LKP_TABLE_A, 5, 0, val);
+ }
}
/**
@@ -5680,6 +6704,7 @@ void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
{
t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
sleep_ok);
+
}
/**
@@ -5939,11 +6964,21 @@ void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
int idx, int enable)
{
- int i, ofst = idx * 4;
+ int chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ u32 match_ctl_a, match_ctl_b;
u32 data_reg, mask_reg, cfg;
+ int i, ofst = idx;
+
+ if (chip >= CHELSIO_T7) {
+ match_ctl_a = T7_MPS_TRC_FILTER_MATCH_CTL_A_A + ofst * 4;
+ match_ctl_b = T7_MPS_TRC_FILTER_MATCH_CTL_B_A + ofst * 4;
+ } else {
+ match_ctl_a = MPS_TRC_FILTER_MATCH_CTL_A_A + ofst * 4;
+ match_ctl_b = MPS_TRC_FILTER_MATCH_CTL_B_A + ofst * 4;
+ }
if (!enable) {
- t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
+ t4_write_reg(adap, match_ctl_a, 0);
return 0;
}
@@ -5970,20 +7005,20 @@ int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
return -EINVAL;
/* stop the tracer we'll be changing */
- t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
+ t4_write_reg(adap, match_ctl_a, 0);
- idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
- data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
- mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
+ ofst *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
+ data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
+ mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
t4_write_reg(adap, data_reg, tp->data[i]);
t4_write_reg(adap, mask_reg, ~tp->mask[i]);
}
- t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
+ t4_write_reg(adap, match_ctl_b,
TFCAPTUREMAX_V(tp->snap_len) |
TFMINPKTSIZE_V(tp->min_len));
- t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
+ t4_write_reg(adap, match_ctl_b,
TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
(is_t4(adap->params.chip) ?
TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
@@ -6005,12 +7040,21 @@ int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
int *enabled)
{
- u32 ctla, ctlb;
- int i, ofst = idx * 4;
+ int chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ u32 match_ctl_a, match_ctl_b, ctla, ctlb;
u32 data_reg, mask_reg;
+ int i, ofst = idx;
+
+ if (chip >= CHELSIO_T7) {
+ match_ctl_a = T7_MPS_TRC_FILTER_MATCH_CTL_A_A + ofst * 4;
+ match_ctl_b = T7_MPS_TRC_FILTER_MATCH_CTL_B_A + ofst * 4;
+ } else {
+ match_ctl_a = MPS_TRC_FILTER_MATCH_CTL_A_A + ofst * 4;
+ match_ctl_b = MPS_TRC_FILTER_MATCH_CTL_B_A + ofst * 4;
+ }
- ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
- ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
+ ctla = t4_read_reg(adap, match_ctl_a);
+ ctlb = t4_read_reg(adap, match_ctl_b);
if (is_t4(adap->params.chip)) {
*enabled = !!(ctla & TFEN_F);
@@ -6026,7 +7070,7 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
tp->skip_ofst = TFOFFSET_G(ctla);
tp->skip_len = TFLENGTH_G(ctla);
- ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
+ ofst *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
@@ -6036,6 +7080,37 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
}
}
+/**
+ * t4_set_trace_rss_control - configure the trace rss control register
+ * @adap: the adapter
+ * @chan: the channel number for RSS control
+ * @qid: queue number
+ *
+ * Configures the MPS tracing RSS control parameter for specified
+ * @chan channel and @qid queue number.
+ */
+void t4_set_trace_rss_control(struct adapter *adap, u8 chan, u16 qid)
+{
+ int chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ u32 mps_trc_rss_control;
+
+ switch (chip) {
+ case CHELSIO_T4:
+ mps_trc_rss_control = MPS_TRC_RSS_CONTROL_A;
+ break;
+ case CHELSIO_T5:
+ case CHELSIO_T6:
+ mps_trc_rss_control = MPS_T5_TRC_RSS_CONTROL_A;
+ break;
+ case CHELSIO_T7:
+ mps_trc_rss_control = T7_MPS_T5_TRC_RSS_CONTROL_A;
+ break;
+ }
+
+ t4_write_reg(adap, mps_trc_rss_control,
+ RSSCONTROL_V(chan) | QUEUENUMBER_V(qid));
+}
+
/**
* t4_pmtx_get_stats - returns the HW stats from PMTX
* @adap: the adapter
@@ -6046,8 +7121,9 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
*/
void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
{
- int i;
+ int chip = CHELSIO_CHIP_VERSION(adap->params.chip);
u32 data[2];
+ int i;
for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
@@ -6057,7 +7133,9 @@ void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
} else {
t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
PM_TX_DBG_DATA_A, data, 2,
- PM_TX_DBG_STAT_MSB_A);
+ chip >= CHELSIO_T7 ?
+ T7_PM_TX_DBG_STAT_MSB_A :
+ PM_TX_DBG_STAT_MSB_A);
cycles[i] = (((u64)data[0] << 32) | data[1]);
}
}
@@ -6090,6 +7168,25 @@ void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
}
}
+/**
+ * t4_pmrx_cache_get_stats - returns the HW PMRX cache stats
+ * @adap: the adapter
+ * @stats: where to store the statistics
+ *
+ * Returns performance statistics of PMRX cache.
+ */
+void t4_pmrx_cache_get_stats(struct adapter *adap, u32 stats[])
+{
+ u8 i, j;
+
+ for (i = 0, j = 0; i < T7_PM_RX_CACHE_NSTATS / 3; i++, j += 3) {
+ t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0x100 + i);
+ stats[j] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
+ t4_read_indirect(adap, PM_RX_DBG_CTRL_A, PM_RX_DBG_DATA_A,
+ &stats[j + 1], 2, PM_RX_DBG_STAT_MSB_A);
+ }
+}
+
/**
* compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
* @adapter: the adapter
@@ -6112,8 +7209,10 @@ static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
case CHELSIO_T5:
switch (nports) {
case 1: return 0xf;
- case 2: return 3 << (2 * pidx);
- case 4: return 1 << pidx;
+ case 2:
+ return 3 << (2 * pidx);
+ case 4:
+ return 1 << pidx;
}
break;
@@ -6122,6 +7221,14 @@ static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
case 2: return 1 << (2 * pidx);
}
break;
+ case CHELSIO_T7:
+ switch (nports) {
+ case 1:
+ case 2:
+ case 4:
+ return 1 << pidx;
+ }
+ break;
}
dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
@@ -6197,36 +7304,87 @@ unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
}
/**
- * t4_get_tp_e2c_map - return the E2C channel map associated with a port
- * @adapter: the adapter
- * @pidx: the port index
+* t4_get_num_ports - Save the FW initialized # of active ports from registers.
+* @adap: the adapter
+*
+* Save the number of FW initialized active ports from hardware registers.
+* For <= T6, the number of active ports is same as available from MPS.
+* For > T6, the number of active ports is based on configured TP Load
+* Balancer Mode. This function must be called after FW is initialized
+* to ensure the TP Load Balancer Mode had been configured for > T6.
+*/
+static void t4_get_tp_num_ports(struct adapter *adap)
+{
+ u32 val = 0;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ t4_tp_pio_read(adap, &val, 1, TP_CHANNEL_MAP_A, false);
+ adap->params.tp.lb_mode = T7_LB_MODE_G(val);
+
+ switch (adap->params.tp.lb_mode) {
+ case 0:
+ adap->params.tp.nports = 4;
+ break;
+ case 2:
+ adap->params.tp.nports = 2;
+ break;
+ default:
+ adap->params.tp.nports = 1;
+ break;
+ }
+ } else {
+ val = t4_read_reg(adap, MPS_CMN_CTL_A);
+ adap->params.tp.lb_mode = 0;
+ adap->params.tp.nports = 1 << NUMPORTS_G(val);
+ }
+}
+
+/*
+ * t4_get_tp_channel_map - fetch and save the configured TP Channel Map
+ * @adap: the adapter
+ *
+ * Fetch and save the configured TP Channel Map.
*/
-static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
+static void t4_get_tp_channel_map(struct adapter *adap)
{
- unsigned int nports;
u32 param, val = 0;
int ret;
+ u8 i;
- nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
- if (pidx >= nports) {
- CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
- pidx, nports);
- return 0;
- }
-
- /* FW version >= 1.16.44.0 can determine E2C channel map using
- * FW_PARAMS_PARAM_DEV_TPCHMAP API.
- */
- param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
- FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
- ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
- 0, 1, ¶m, &val);
+ param = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
+ FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP);
+ ret = t4_query_params_ns(adap, adap->mbox, adap->pf, 0, 1, ¶m,
+ &val);
if (!ret)
- return (val >> (8 * pidx)) & 0xff;
+ for (i = 0; i < NCHAN; i++)
+ adap->params.tp.channel_map[i] = (val >> (8 * i)) &
+ 0xff;
+}
- return 0;
+/*
+ * t4_get_tp_port_chan - Get the associated TP channel for the port
+ * @adap: the adapter
+ * @pidx: the port ID for which to get the TP channel
+ *
+ * Get the associated TP channel for the port.
+ */
+u8 t4_get_tp_port_chan(struct adapter *adap, u8 pidx)
+{
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T6)
+ return pidx;
+
+ return adap->params.tp.channel_map[pidx];
}
+/**
+ * t4_get_tp_e2c_map - return the E2C channel map associated with a port
+ * @adapter: the adapter
+ * @pidx: the port index
+ */
+static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
+{
+ return adapter->params.tp.channel_map[pidx];
+}
/**
* t4_get_tp_ch_map - return TP ingress channels associated with a port
* @adap: the adapter
@@ -6239,13 +7397,7 @@ static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
{
unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
- unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
-
- if (pidx >= nports) {
- dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
- pidx, nports);
- return 0;
- }
+ u8 nports = adap->params.tp.nports;
switch (chip_version) {
case CHELSIO_T4:
@@ -6256,8 +7408,10 @@ unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
*/
switch (nports) {
case 1: return 0xf;
- case 2: return 3 << (2 * pidx);
- case 4: return 1 << pidx;
+ case 2:
+ return 3 << (2 * pidx);
+ case 4:
+ return 1 << pidx;
}
break;
@@ -6267,6 +7421,14 @@ unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
case 2: return 1 << pidx;
}
break;
+ case CHELSIO_T7:
+ switch (nports) {
+ case 1:
+ case 2:
+ case 4:
+ return 1 << pidx;
+ }
+ break;
}
dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
@@ -6280,37 +7442,76 @@ unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
*/
const char *t4_get_port_type_description(enum fw_port_type port_type)
{
- static const char *const port_type_description[] = {
- "Fiber_XFI",
- "Fiber_XAUI",
- "BT_SGMII",
- "BT_XFI",
- "BT_XAUI",
- "KX4",
- "CX4",
- "KX",
- "KR",
- "SFP",
- "BP_AP",
- "BP4_AP",
- "QSFP_10G",
- "QSA",
- "QSFP",
- "BP40_BA",
- "KR4_100G",
- "CR4_QSFP",
- "CR_QSFP",
- "CR2_QSFP",
- "SFP28",
- "KR_SFP28",
- "KR_XLAUI"
- };
+ static const char *const port_type_description[] = { "Fiber_XFI",
+ "Fiber_XAUI",
+ "BT_SGMII",
+ "BT_XFI",
+ "BT_XAUI",
+ "KX4",
+ "CX4",
+ "KX",
+ "KR",
+ "SFP",
+ "BP_AP",
+ "BP4_AP",
+ "QSFP_10G",
+ "QSA",
+ "QSFP",
+ "BP40_BA",
+ "KR4_100G",
+ "CR4_QSFP",
+ "CR_QSFP",
+ "CR2_QSFP",
+ "SFP28",
+ "KR_SFP28",
+ "KR_XLAUI",
+ "BARE_LINK_50G",
+ "BARE_LINK_100G",
+ "BARE_LINK_200G",
+ "SFP56",
+ "QSFP56",
+ "QSFP56_4_50G",
+ "KR_50G",
+ "KR2_100G",
+ "KR4_200G",
+ "QSFP56_2_50G",
+ "OSFP",
+ "QSFPDD",
+ "OSFP_2_200G",
+ "QSFP_4_100G",
+ "QSFPDD_2_200G",
+ "KR8_400G" };
if (port_type < ARRAY_SIZE(port_type_description))
return port_type_description[port_type];
return "UNKNOWN";
}
+static u64 t4_get_port_stats_lb_mode(struct adapter *adap, int idx, u32 reg)
+{
+ u8 i, n, start;
+ u64 s = 0;
+
+ start = t4_get_tp_port_chan(adap, idx);
+
+ switch (adap->params.tp.lb_mode) {
+ case 0:
+ n = 1;
+ break;
+ case 2:
+ n = 2;
+ break;
+ default:
+ n = 4;
+ break;
+ }
+
+ for (i = 0; i < n; i++)
+ s += t4_read_reg64(adap, t4_port_reg(adap, start + i, reg));
+
+ return s;
+}
+
/**
* t4_get_port_stats_offset - collect port stats relative to a previous
* snapshot
@@ -6343,13 +7544,11 @@ void t4_get_port_stats_offset(struct adapter *adap, int idx,
*/
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
{
- u32 bgmap = t4_get_mps_bg_map(adap, idx);
u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
+ u32 bgmap = t4_get_mps_bg_map(adap, idx);
#define GET_STAT(name) \
- t4_read_reg64(adap, \
- (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
- T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
+ t4_get_port_stats_lb_mode(adap, idx, MPS_PORT_STAT_##name##_L);
#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
p->tx_octets = GET_STAT(TX_PORT_BYTES);
@@ -6443,10 +7642,7 @@ void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
u32 bgmap = t4_get_mps_bg_map(adap, idx);
#define GET_STAT(name) \
- t4_read_reg64(adap, \
- (is_t4(adap->params.chip) ? \
- PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
- T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
+ t4_get_port_stats_lb_mode(adap, idx, MPS_PORT_STAT_LB_PORT_##name##_L);
#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
p->octets = GET_STAT(BYTES);
@@ -6727,6 +7923,7 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state)
break;
case CHELSIO_T6:
+ case CHELSIO_T7:
sge_idma_decode = (const char **)t6_decode;
sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
break;
@@ -8054,18 +9251,23 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
*
* Returns a negative error number or the number of filters freed.
*/
-int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
- unsigned int viid, unsigned int naddr,
- const u8 **addr, bool sleep_ok)
+int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
+ unsigned int naddr, const u8 **addr, bool sleep_ok)
{
int offset, ret = 0;
struct fw_vi_mac_cmd c;
unsigned int nfilters = 0;
- unsigned int max_naddr = is_t4(adap->params.chip) ?
- NUM_MPS_CLS_SRAM_L_INSTANCES :
- NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
+ unsigned int max_naddr = 0;
unsigned int rem = naddr;
+ if (is_t4(adap->params.chip))
+ max_naddr = NUM_MPS_CLS_SRAM_L_INSTANCES;
+ else if (is_t7(adap->params.chip))
+ /* In T7 there 3 TCAM each of 512 size*/
+ max_naddr = NUM_MPS_T5_CLS_SRAM_L_INSTANCES * 3;
+ else
+ max_naddr = NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
+
if (naddr > max_naddr)
return -EINVAL;
@@ -8681,7 +9883,7 @@ void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
lc->link_down_rc = linkdnrc;
dev_warn_ratelimited(adapter->pdev_dev,
"Port %d link down, reason: %s\n",
- pi->tx_chan,
+ pi->lport,
t4_link_down_rc_str(linkdnrc));
}
lc->link_ok = link_ok;
@@ -8757,7 +9959,7 @@ int t4_update_port_info(struct port_info *pi)
memset(&port_cmd, 0, sizeof(port_cmd));
port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
FW_CMD_REQUEST_F | FW_CMD_READ_F |
- FW_PORT_CMD_PORTID_V(pi->tx_chan));
+ FW_PORT_CMD_PORTID_V(pi->lport));
port_cmd.action_to_len16 = cpu_to_be32(
FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
? FW_PORT_ACTION_GET_PORT_INFO
@@ -8795,7 +9997,7 @@ int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
memset(&port_cmd, 0, sizeof(port_cmd));
port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
FW_CMD_REQUEST_F | FW_CMD_READ_F |
- FW_PORT_CMD_PORTID_V(pi->tx_chan));
+ FW_PORT_CMD_PORTID_V(pi->lport));
action = (fw_caps == FW_CAPS16
? FW_PORT_ACTION_GET_PORT_INFO
: FW_PORT_ACTION_GET_PORT_INFO32);
@@ -8955,14 +10157,17 @@ static int t4_get_flash_params(struct adapter *adap)
* to the preexisting code. All flash parts have 64KB sectors.
*/
static struct flash_desc supported_flash[] = {
- { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
+ { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
};
unsigned int part, manufacturer;
unsigned int density, size = 0;
+ int ret, min_size;
u32 flashid = 0;
- int ret;
+ min_size = t4_flash_location_end(adap, FLASH_LOC_MIN_SIZE);
+ if (min_size < 0)
+ return min_size;
/* Issue a Read ID Command to the Flash part. We decode supported
* Flash parts and their sizes from this. There's a newer Query
* Command which can retrieve detailed geometry information but many
@@ -9096,43 +10301,64 @@ static int t4_get_flash_params(struct adapter *adap)
adap->params.sf_nsec = size / SF_SEC_SIZE;
found:
- if (adap->params.sf_size < FLASH_MIN_SIZE)
+ if (adap->params.sf_size < min_size)
dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
- flashid, adap->params.sf_size, FLASH_MIN_SIZE);
+ flashid, adap->params.sf_size, min_size);
return 0;
}
/**
- * t4_prep_adapter - prepare SW and HW for operation
- * @adapter: the adapter
- *
- * Initialize adapter SW state for the various HW modules, set initial
- * values for some adapter tunables, take PHYs out of reset, and
- * initialize the MDIO interface.
+ * t4_get_chip_type - Determine chip type from device ID
+ * @adap: the adapter
+ * @ver: adapter version
+ */
+enum chip_type t4_get_chip_type(struct adapter *adap, int ver)
+{
+ u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
+
+ switch (ver) {
+ case CHELSIO_T4:
+ return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
+ case CHELSIO_T5:
+ return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
+ case CHELSIO_T6:
+ return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
+ case CHELSIO_T7:
+ return CHELSIO_CHIP_CODE(CHELSIO_T7, pl_rev);
+ default:
+ break;
+ }
+ return -EINVAL;
+}
+
+/**
+ * t4_prep_adapter - prepare SW and HW for operation
+ * @adapter: the adapter
+ *
+ * Initialize adapter SW state for the various HW modules, set initial
+ * values for some adapter tunables, take PHYs out of reset, and
+ * initialize the MDIO interface.
*/
int t4_prep_adapter(struct adapter *adapter)
{
int ret, ver;
- uint16_t device_id;
- u32 pl_rev;
+ u16 device_id;
get_pci_mode(adapter, &adapter->params.pci);
- pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
-
ret = t4_get_flash_params(adapter);
if (ret < 0) {
dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
return ret;
}
-
/* Retrieve adapter's device ID
*/
- pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
- ver = device_id >> 12;
- adapter->params.chip = 0;
+ pci_read_config_word(adapter->pdev, PCI_DEVICE_ID,
+ &adapter->params.pci.device_id);
+ pci_read_config_word(adapter->pdev, PCI_VENDOR_ID,
+ &adapter->params.pci.vendor_id);
+ ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
switch (ver) {
case CHELSIO_T4:
- adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
adapter->params.arch.sge_fl_db = DBPRIO_F;
adapter->params.arch.mps_tcam_size =
NUM_MPS_CLS_SRAM_L_INSTANCES;
@@ -9144,9 +10370,9 @@ int t4_prep_adapter(struct adapter *adapter)
* MPS can have 4 priority per port.
*/
adapter->params.arch.cng_ch_bits_log = 2;
+ adapter->params.cim_la_size = CIMLA_SIZE;
break;
case CHELSIO_T5:
- adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
adapter->params.arch.mps_tcam_size =
NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
@@ -9155,9 +10381,9 @@ int t4_prep_adapter(struct adapter *adapter)
adapter->params.arch.pm_stats_cnt = PM_NSTATS;
adapter->params.arch.vfcount = 128;
adapter->params.arch.cng_ch_bits_log = 2;
+ adapter->params.cim_la_size = CIMLA_SIZE;
break;
case CHELSIO_T6:
- adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
adapter->params.arch.sge_fl_db = 0;
adapter->params.arch.mps_tcam_size =
NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
@@ -9169,6 +10395,25 @@ int t4_prep_adapter(struct adapter *adapter)
* MPS can have 8 priority per port.
*/
adapter->params.arch.cng_ch_bits_log = 3;
+ adapter->params.cim_la_size = CIMLA_SIZE_T6;
+ break;
+ case CHELSIO_T7:
+ adapter->params.arch.sge_fl_db = 0;
+ adapter->params.arch.mps_tcam_size =
+ is_t7(adapter->params.chip)
+ /* In T7 there 3 TCAM each of 512 size*/
+ ?
+ NUM_MPS_T5_CLS_SRAM_L_INSTANCES * 3 :
+ NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
+ adapter->params.arch.mps_rplc_size = 256;
+ adapter->params.arch.nchan = NCHAN;
+ adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
+ adapter->params.arch.vfcount = 256;
+ /* Congestion map will be for 4 channels so that
+ * MPS can have 4 priority per port.
+ */
+ adapter->params.arch.cng_ch_bits_log = 2;
+ adapter->params.cim_la_size = CIMLA_SIZE_T6;
break;
default:
dev_err(adapter->pdev_dev, "Device %d is not supported\n",
@@ -9186,9 +10431,11 @@ int t4_prep_adapter(struct adapter *adapter)
adapter->params.portvec = 1;
adapter->params.vpd.cclk = 50000;
- /* Set PCIe completion timeout to 4 seconds. */
- pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
- PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
+ ret = t4_get_flash_params(adapter);
+ if (ret < 0) {
+ dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
+ return ret;
+ }
return 0;
}
@@ -9211,9 +10458,12 @@ int t4_shutdown_adapter(struct adapter *adapter)
t4_intr_disable(adapter);
t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
for_each_port(adapter, port) {
- u32 a_port_cfg = is_t4(adapter->params.chip) ?
- PORT_REG(port, XGMAC_PORT_CFG_A) :
- T5_PORT_REG(port, MAC_PORT_CFG_A);
+ u32 a_port_cfg;
+
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T4)
+ a_port_cfg = t4_port_reg(adapter, port, MAC_PORT_CFG_A);
+ else
+ a_port_cfg = PORT_REG(port, XGMAC_PORT_CFG_A);
t4_write_reg(adapter, a_port_cfg,
t4_read_reg(adapter, a_port_cfg)
@@ -9323,10 +10573,10 @@ int t4_bar2_sge_qregs(struct adapter *adapter,
*/
int t4_init_devlog_params(struct adapter *adap)
{
- struct devlog_params *dparams = &adap->params.devlog;
- u32 pf_dparams;
- unsigned int devlog_meminfo;
+ struct devlog_params *dparams = adap->params.devlog;
+ u32 nentries128, size, start, pf_dparams;
struct fw_devlog_cmd devlog_cmd;
+ u8 i, memtype, ncount;
int ret;
/* If we're dealing with newer firmware, the Device Log Parameters
@@ -9336,16 +10586,13 @@ int t4_init_devlog_params(struct adapter *adap)
pf_dparams =
t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
if (pf_dparams) {
- unsigned int nentries, nentries128;
-
- dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
- dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
-
+ ncount = ((PCIE_FW_PF_DEVLOG_COUNT_MSB_G(pf_dparams) << 1) |
+ PCIE_FW_PF_DEVLOG_COUNT_LSB_G(pf_dparams));
+ memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
+ start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
- nentries = (nentries128 + 1) * 128;
- dparams->size = nentries * sizeof(struct fw_devlog_e);
-
- return 0;
+ size = (nentries128 + 1) * 128 * sizeof(struct fw_devlog_e);
+ goto out_copy;
}
/* Otherwise, ask the firmware for its Device Log Parameters.
@@ -9359,15 +10606,41 @@ int t4_init_devlog_params(struct adapter *adap)
if (ret)
return ret;
- devlog_meminfo =
- be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
- dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
- dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
- dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
+ pf_dparams = be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
+ memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(pf_dparams);
+ start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(pf_dparams) << 4;
+ size = be32_to_cpu(devlog_cmd.memsize_devlog);
+ ncount = 0;
+
+out_copy:
+ adap->params.num_up_cores = 1 << ncount;
+ for (i = 0; i < adap->params.num_up_cores; i++) {
+ dparams[i].memtype = memtype;
+ dparams[i].start = start;
+ dparams[i].size = size / adap->params.num_up_cores;
+ start += dparams[i].size;
+ }
return 0;
}
+/*
+ * t4_sge_get_qpp - get the number of Egress or Ingress queues per page
+ * @adap: the adapter
+ * @qtype: Egress or Ingress queue map register to read
+ *
+ * Fetches the number of Egress or Ingress queues per page.
+ */
+unsigned int t4_sge_get_qpp(struct adapter *adap, unsigned int qtype)
+{
+ unsigned int s_qpp, qpp;
+
+ s_qpp = (QUEUESPERPAGEPF0_S +
+ (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adap->pf);
+ qpp = t4_read_reg(adap, qtype);
+ return ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
+}
+
/**
* t4_init_sge_params - initialize adap->params.sge
* @adapter: the adapter
@@ -9377,8 +10650,7 @@ int t4_init_devlog_params(struct adapter *adap)
int t4_init_sge_params(struct adapter *adapter)
{
struct sge_params *sge_params = &adapter->params.sge;
- u32 hps, qpp;
- unsigned int s_hps, s_qpp;
+ u32 hps, s_hps;
/* Extract the SGE Page Size for our PF.
*/
@@ -9389,13 +10661,10 @@ int t4_init_sge_params(struct adapter *adapter)
/* Extract the SGE Egress and Ingess Queues Per Page for our PF.
*/
- s_qpp = (QUEUESPERPAGEPF0_S +
- (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
- qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
- sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
- qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
- sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
-
+ sge_params->eq_qpp =
+ t4_sge_get_qpp(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
+ sge_params->iq_qpp =
+ t4_sge_get_qpp(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
return 0;
}
@@ -9411,7 +10680,6 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
u32 param, val, v;
int chan, ret;
-
v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
adap->params.tp.tre = TIMERRESOLUTION_G(v);
adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
@@ -9420,6 +10688,12 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
for (chan = 0; chan < NCHAN; chan++)
adap->params.tp.tx_modq[chan] = chan;
+ /* Save the number of ports activated by FW */
+ t4_get_tp_num_ports(adap);
+
+ /* Save the TP Channel Map from FW */
+ t4_get_tp_channel_map(adap);
+
/* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
* Configuration.
*/
@@ -9476,21 +10750,62 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
* shift positions of several elements of the Compressed Filter Tuple
* for this adapter which we need frequently ...
*/
- adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
- adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
- adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
- adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
- adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
- adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
- PROTOCOL_F);
- adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
- ETHERTYPE_F);
- adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
- MACMATCH_F);
- adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
- MPSHITTYPE_F);
- adap->params.tp.frag_shift = t4_filter_field_shift(adap,
- FRAGMENTATION_F);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ adap->params.tp.ipsecidx_shift =
+ t4_filter_field_shift(adap, IPSECIDX_F);
+ adap->params.tp.fcoe_shift =
+ t4_filter_field_shift(adap, T7_FCOE_F);
+ adap->params.tp.port_shift =
+ t4_filter_field_shift(adap, T7_PORT_F);
+ adap->params.tp.vnic_shift =
+ t4_filter_field_shift(adap, T7_VNIC_ID_F);
+ adap->params.tp.vlan_shift =
+ t4_filter_field_shift(adap, T7_VLAN_F);
+ adap->params.tp.tos_shift =
+ t4_filter_field_shift(adap, T7_TOS_F);
+ adap->params.tp.protocol_shift =
+ t4_filter_field_shift(adap, T7_PROTOCOL_F);
+ adap->params.tp.ethertype_shift =
+ t4_filter_field_shift(adap, T7_ETHERTYPE_F);
+ adap->params.tp.macmatch_shift =
+ t4_filter_field_shift(adap, T7_MACMATCH_F);
+ adap->params.tp.matchtype_shift =
+ t4_filter_field_shift(adap, T7_MPSHITTYPE_F);
+ adap->params.tp.frag_shift =
+ t4_filter_field_shift(adap, T7_FRAGMENTATION_F);
+ adap->params.tp.synonly_shift =
+ t4_filter_field_shift(adap, SYNONLY_F);
+ adap->params.tp.tcpflags_shift =
+ t4_filter_field_shift(adap, TCPFLAGS_F);
+ } else {
+ adap->params.tp.fcoe_shift =
+ t4_filter_field_shift(adap, FCOE_F);
+ adap->params.tp.port_shift =
+ t4_filter_field_shift(adap, PORT_F);
+ adap->params.tp.vnic_shift =
+ t4_filter_field_shift(adap, VNIC_ID_F);
+ adap->params.tp.vlan_shift =
+ t4_filter_field_shift(adap, VLAN_F);
+ adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
+ adap->params.tp.protocol_shift =
+ t4_filter_field_shift(adap, PROTOCOL_F);
+ adap->params.tp.ethertype_shift =
+ t4_filter_field_shift(adap, ETHERTYPE_F);
+ adap->params.tp.macmatch_shift =
+ t4_filter_field_shift(adap, MACMATCH_F);
+ adap->params.tp.matchtype_shift =
+ t4_filter_field_shift(adap, MPSHITTYPE_F);
+ adap->params.tp.frag_shift =
+ t4_filter_field_shift(adap, FRAGMENTATION_F);
+
+ /* Following fields are not supported in T6 and older
+ * NICs.
+ */
+ adap->params.tp.ipsecidx_shift = -1;
+ adap->params.tp.roce_shift = -1;
+ adap->params.tp.synonly_shift = -1;
+ adap->params.tp.tcpflags_shift = -1;
+ }
/* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
* represents the presence of an Outer VLAN instead of a VNIC ID.
@@ -9512,7 +10827,7 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
*
* Return the shift position of a filter field within the Compressed
* Filter Tuple. The filter field is specified via its selection bit
- * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
+ * within TP_VLAN_PRI_MAL (filter mode). E.g. VLAN_F.
*/
int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
{
@@ -9523,6 +10838,54 @@ int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
if ((filter_mode & filter_sel) == 0)
return -1;
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
+ switch (filter_mode & sel) {
+ case IPSECIDX_F:
+ field_shift += FT_IPSECIDX_W;
+ break;
+ case T7_FCOE_F:
+ field_shift += FT_FCOE_W;
+ break;
+ case T7_PORT_F:
+ field_shift += FT_PORT_W;
+ break;
+ case T7_VNIC_ID_F:
+ field_shift += FT_VNIC_ID_W;
+ break;
+ case T7_VLAN_F:
+ field_shift += FT_VLAN_W;
+ break;
+ case T7_TOS_F:
+ field_shift += FT_TOS_W;
+ break;
+ case T7_PROTOCOL_F:
+ field_shift += FT_PROTOCOL_W;
+ break;
+ case T7_ETHERTYPE_F:
+ field_shift += FT_ETHERTYPE_W;
+ break;
+ case T7_MACMATCH_F:
+ field_shift += FT_MACMATCH_W;
+ break;
+ case T7_MPSHITTYPE_F:
+ field_shift += FT_MPSHITTYPE_W;
+ break;
+ case T7_FRAGMENTATION_F:
+ field_shift += FT_FRAGMENTATION_W;
+ break;
+ case SYNONLY_F:
+ field_shift += FT_SYNONLY_W;
+ break;
+ case TCPFLAGS_F:
+ field_shift += FT_TCPFLAGS_W;
+ break;
+ }
+ }
+
+ goto out;
+ }
+
for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
switch (filter_mode & sel) {
case FCOE_F:
@@ -9557,6 +10920,8 @@ int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
break;
}
}
+
+out:
return field_shift;
}
@@ -9668,7 +11033,7 @@ int t4_init_portinfo(struct port_info *pi, int mbox,
return ret;
pi->viid = ret;
- pi->tx_chan = port;
+ pi->tx_chan = t4_get_tp_port_chan(pi->adapter, port);
pi->lport = port;
pi->rss_size = rss_size;
pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
@@ -9714,6 +11079,101 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
return 0;
}
+u8 t4_cim_num_ibq(struct adapter *adap)
+{
+ unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ return chip_ver >= CHELSIO_T7 ? CIM_NUM_IBQ_T7 : CIM_NUM_IBQ;
+}
+
+u8 t4_cim_num_obq(struct adapter *adap)
+{
+ unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ if (chip_ver >= CHELSIO_T7)
+ return CIM_NUM_OBQ_T7;
+
+ if (chip_ver > CHELSIO_T4)
+ return CIM_NUM_OBQ_T5;
+
+ return CIM_NUM_OBQ;
+}
+
+static void t4_read_cimq_cfg_ibq_core(struct adapter *adap, u8 coreid, u32 qid,
+ u16 *base, u16 *size, u16 *thres)
+{
+ unsigned int v, m;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ v = T7_IBQSELECT_F | T7_QUENUMSELECT_V(qid) |
+ CORESELECT_V(coreid);
+ /* value is in 512-byte units */
+ m = 512;
+ } else {
+ v = IBQSELECT_F | QUENUMSELECT_V(qid);
+ /* value is in 256-byte units */
+ m = 256;
+ }
+
+ t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, v);
+ v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
+ if (base)
+ *base = CIMQBASE_G(v) * m;
+ if (size)
+ *size = CIMQSIZE_G(v) * m;
+ if (thres)
+ *thres = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
+}
+
+static void t4_read_cimq_cfg_obq_core(struct adapter *adap, u8 coreid, u32 qid,
+ u16 *base, u16 *size)
+{
+ unsigned int v, m;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ v = T7_OBQSELECT_F | T7_QUENUMSELECT_V(qid) |
+ CORESELECT_V(coreid);
+ /* value is in 512-byte units */
+ m = 512;
+ } else {
+ v = OBQSELECT_F | QUENUMSELECT_V(qid);
+ /* value is in 256-byte units */
+ m = 256;
+ }
+
+ t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, v);
+ v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
+ if (base)
+ *base = CIMQBASE_G(v) * m;
+ if (size)
+ *size = CIMQSIZE_G(v) * m;
+}
+
+/**
+ * t4_read_cimq_cfg_core - read CIM queue configuration on specific core
+ * @adap: the adapter
+ * @coreid: the uP coreid
+ * @base: holds the queue base addresses in bytes
+ * @size: holds the queue sizes in bytes
+ * @thres: holds the queue full thresholds in bytes
+ *
+ * Returns the current configuration of the CIM queues, starting with
+ * the IBQs, then the OBQs, on a specific @coreid.
+ */
+void t4_read_cimq_cfg_core(struct adapter *adap, u8 coreid, u16 *base,
+ u16 *size, u16 *thres)
+{
+ unsigned int cim_num_ibq = t4_cim_num_ibq(adap);
+ unsigned int cim_num_obq = t4_cim_num_obq(adap);
+ unsigned int i;
+
+ for (i = 0; i < cim_num_ibq; i++, base++, size++, thres++)
+ t4_read_cimq_cfg_ibq_core(adap, coreid, i, base, size, thres);
+
+ for (i = 0; i < cim_num_obq; i++, base++, size++)
+ t4_read_cimq_cfg_obq_core(adap, coreid, i, base, size);
+}
+
int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
u16 *mirror_viid)
{
@@ -9742,114 +11202,206 @@ int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
*/
void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
{
- unsigned int i, v;
- int cim_num_obq = is_t4(adap->params.chip) ?
- CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
+ t4_read_cimq_cfg_core(adap, 0, base, size, thres);
+}
- for (i = 0; i < CIM_NUM_IBQ; i++) {
- t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
- QUENUMSELECT_V(i));
- v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
- /* value is in 256-byte units */
- *base++ = CIMQBASE_G(v) * 256;
- *size++ = CIMQSIZE_G(v) * 256;
- *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
- }
- for (i = 0; i < cim_num_obq; i++) {
- t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
- QUENUMSELECT_V(i));
- v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
- /* value is in 256-byte units */
- *base++ = CIMQBASE_G(v) * 256;
- *size++ = CIMQSIZE_G(v) * 256;
- }
+static int t4_read_cim_ibq_data_core(struct adapter *adap, u8 coreid, u32 addr,
+ u32 *data)
+{
+ int ret, attempts;
+ unsigned int v;
+
+ /* It might take 3-10ms before the IBQ debug read access is allowed.
+ * Wait for 1 Sec with a delay of 1 usec.
+ */
+ attempts = 1000000;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ v = T7_IBQDBGADDR_V(addr) | IBQDBGCORE_V(coreid);
+ else
+ v = IBQDBGADDR_V(addr);
+
+ t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, v | IBQDBGEN_F);
+ ret = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
+ attempts, 1);
+ if (ret)
+ return ret;
+
+ *data = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
+ return 0;
}
/**
- * t4_read_cim_ibq - read the contents of a CIM inbound queue
- * @adap: the adapter
- * @qid: the queue index
- * @data: where to store the queue contents
- * @n: capacity of @data in 32-bit words
+ * t4_read_cim_ibq_core - read the contents of a CIM inbound queue on
+ * specific core
+ * @adap: the adapter
+ * @coreid: the uP coreid
+ * @qid: the queue index
+ * @data: where to store the queue contents
+ * @n: capacity of @data in 32-bit words
*
- * Reads the contents of the selected CIM queue starting at address 0 up
- * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
- * error and the number of 32-bit words actually read on success.
+ * Reads the contents of the selected CIM queue starting at address 0 up
+ * to the capacity of @data on a specific @coreid. @n must be a multiple
+ * of 4. Returns < 0 on error and the number of 32-bit words actually
+ * read on success.
*/
-int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+int t4_read_cim_ibq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+ size_t n)
{
- int i, err, attempts;
- unsigned int addr;
- const unsigned int nwords = CIM_IBQ_SIZE * 4;
+ unsigned int cim_num_ibq = t4_cim_num_ibq(adap);
+ u16 i, addr, nwords;
+ int ret;
- if (qid > 5 || (n & 3))
+ if (qid > (cim_num_ibq - 1) || (n & 3))
return -EINVAL;
- addr = qid * nwords;
+ t4_read_cimq_cfg_ibq_core(adap, coreid, qid, &addr, &nwords, NULL);
+ addr >>= sizeof(u16);
+ nwords >>= sizeof(u16);
if (n > nwords)
n = nwords;
- /* It might take 3-10ms before the IBQ debug read access is allowed.
- * Wait for 1 Sec with a delay of 1 usec.
- */
- attempts = 1000000;
-
- for (i = 0; i < n; i++, addr++) {
- t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
- IBQDBGEN_F);
- err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
- attempts, 1);
- if (err)
- return err;
- *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
+ for (i = 0; i < n; i++, addr++, data++) {
+ ret = t4_read_cim_ibq_data_core(adap, coreid, addr, data);
+ if (ret < 0)
+ return ret;
}
+
t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
return i;
}
-/**
- * t4_read_cim_obq - read the contents of a CIM outbound queue
- * @adap: the adapter
- * @qid: the queue index
- * @data: where to store the queue contents
- * @n: capacity of @data in 32-bit words
+/*
+ * t4_read_cim_ibq - read the contents of a CIM inbound queue
+ * @adap: the adapter
+ * @qid: the queue index
+ * @data: where to store the queue contents
+ * @n: capacity of @data in 32-bit words
*
- * Reads the contents of the selected CIM queue starting at address 0 up
- * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
- * error and the number of 32-bit words actually read on success.
+ * Reads the contents of the selected CIM queue starting at address 0 up
+ * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
+ * error and the number of 32-bit words actually read on success.
*/
-int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+{
+ return t4_read_cim_ibq_core(adap, 0, qid, data, n);
+}
+
+static int t4_read_cim_obq_data_core(struct adapter *adap, u8 coreid, u32 addr,
+ u32 *data)
+{
+ unsigned int v;
+ int ret;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ v = T7_OBQDBGADDR_V(addr) | OBQDBGCORE_V(coreid);
+ else
+ v = OBQDBGADDR_V(addr);
+
+ t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, v | OBQDBGEN_F);
+ ret = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0, 2, 1);
+ if (ret)
+ return ret;
+
+ *data = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
+ return 0;
+}
+
+/*
+ * t4_read_cim_obq_core - read the contents of a CIM outbound queue on
+ * specific core
+ * @adap: the adapter
+ * @coreid: the uP coreid
+ * @qid: the queue index
+ * @data: where to store the queue contents
+ * @n: capacity of @data in 32-bit words
+ *
+ * Reads the contents of the selected CIM queue starting at address 0 up
+ * to the capacity of @data on specific @coreid. @n must be a multiple
+ * of 4. Returns < 0 on error and the number of 32-bit words actually
+ * read on success.
+ */
+int t4_read_cim_obq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+ size_t n)
{
- int i, err;
- unsigned int addr, v, nwords;
- int cim_num_obq = is_t4(adap->params.chip) ?
- CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
+ unsigned int cim_num_obq = t4_cim_num_obq(adap);
+ u16 i, addr, nwords;
+ int ret;
if ((qid > (cim_num_obq - 1)) || (n & 3))
return -EINVAL;
- t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
- QUENUMSELECT_V(qid));
- v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
-
- addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
- nwords = CIMQSIZE_G(v) * 64; /* same */
+ t4_read_cimq_cfg_obq_core(adap, coreid, qid, &addr, &nwords);
+ addr >>= sizeof(u16);
+ nwords >>= sizeof(u16);
if (n > nwords)
n = nwords;
-
- for (i = 0; i < n; i++, addr++) {
- t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
- OBQDBGEN_F);
- err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
- 2, 1);
- if (err)
- return err;
- *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
+ for (i = 0; i < n; i++, addr++, data++) {
+ ret = t4_read_cim_obq_data_core(adap, coreid, addr, data);
+ if (ret < 0)
+ return ret;
}
+
t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
return i;
}
+/*
+ * t4_read_cim_obq - read the contents of a CIM outbound queue
+ * @adap: the adapter
+ * @qid: the queue index
+ * @data: where to store the queue contents
+ * @n: capacity of @data in 32-bit words
+ *
+ * Reads the contents of the selected CIM queue starting at address 0 up
+ * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
+ * error and the number of 32-bit words actually read on success.
+ */
+int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+{
+ return t4_read_cim_obq_core(adap, 0, qid, data, n);
+}
+
+/*
+ * t4_cim_read_core - read a block from CIM internal address space
+ * of a control register group on specific core.
+ * @adap: the adapter
+ * @group: the control register group to select for read
+ * @coreid: the uP coreid
+ * @addr: the start address within the CIM address space
+ * @n: number of words to read
+ * @valp: where to store the result
+ *
+ * Reads a block of 4-byte words from the CIM intenal address space
+ * of a control register @group on a specific @coreid.
+ */
+int t4_cim_read_core(struct adapter *adap, u8 group, u8 coreid,
+ unsigned int addr, unsigned int n, unsigned int *valp)
+{
+ unsigned int hostbusy, v = 0;
+ int ret = 0;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ hostbusy = T7_HOSTBUSY_F;
+ v = HOSTGRPSEL_V(group) | HOSTCORESEL_V(coreid);
+ } else {
+ hostbusy = HOSTBUSY_F;
+ }
+
+ if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & hostbusy)
+ return -EBUSY;
+
+ for (; !ret && n--; addr += 4) {
+ t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | v);
+ ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, hostbusy, 0, 5,
+ 2);
+ if (!ret)
+ *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
+ }
+
+ return ret;
+}
+
/**
* t4_cim_read - read a block from CIM internal address space
* @adap: the adapter
@@ -9862,18 +11414,48 @@ int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
unsigned int *valp)
{
+ return t4_cim_read_core(adap, 0, 0, addr, n, valp);
+}
+
+/**
+ * t4_cim_write_core - write a block into CIM internal address space
+ * of a control register group on specific core.
+ * @adap: the adapter
+ * @group: the control register group to select for write
+ * @coreid: the uP coreid
+ * @addr: the start address within the CIM address space
+ * @n: number of words to write
+ * @valp: set of values to write
+ *
+ * Writes a block of 4-byte words into the CIM intenal address space
+ * of a control register @group on a specific @coreid.
+ */
+int t4_cim_write_core(struct adapter *adap, u8 group, u8 coreid,
+ unsigned int addr, unsigned int n,
+ const unsigned int *valp)
+{
+ unsigned int hostbusy, v;
int ret = 0;
- if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ hostbusy = T7_HOSTBUSY_F;
+ v = T7_HOSTWRITE_F | HOSTGRPSEL_V(group) |
+ HOSTCORESEL_V(coreid);
+ } else {
+ hostbusy = HOSTBUSY_F;
+ v = HOSTWRITE_F;
+ }
+
+ if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & hostbusy)
return -EBUSY;
for ( ; !ret && n--; addr += 4) {
- t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
- ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
- 0, 5, 2);
- if (!ret)
- *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
+ t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
+ t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | v);
+ ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, hostbusy, 0, 5,
+ 2);
}
+
return ret;
}
@@ -9889,52 +11471,40 @@ int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
const unsigned int *valp)
{
- int ret = 0;
-
- if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
- return -EBUSY;
-
- for ( ; !ret && n--; addr += 4) {
- t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
- t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
- ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
- 0, 5, 2);
- }
- return ret;
-}
-
-static int t4_cim_write1(struct adapter *adap, unsigned int addr,
- unsigned int val)
-{
- return t4_cim_write(adap, addr, 1, &val);
+ return t4_cim_write_core(adap, 0, 0, addr, n, valp);
}
/**
- * t4_cim_read_la - read CIM LA capture buffer
- * @adap: the adapter
- * @la_buf: where to store the LA data
- * @wrptr: the HW write pointer within the capture buffer
+ * t4_cim_read_la_core - read CIM LA capture buffer on specific core
+ * @adap: the adapter
+ * @coreid: uP coreid
+ * @la_buf: where to store the LA data
+ * @wrptr: the HW write pointer within the capture buffet4_init_portinfor
*
- * Reads the contents of the CIM LA buffer with the most recent entry at
- * the end of the returned data and with the entry at @wrptr first.
- * We try to leave the LA in the running state we find it in.
+ * Reads the contents of the CIM LA buffer on a specific @coreid
+ * with the most recent entry at the end of the returned data
+ * and with the entry at @wrptr first. We try to leave the LA
+ * in the running state we find it in.
*/
-int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
+int t4_cim_read_la_core(struct adapter *adap, u8 coreid, u32 *la_buf,
+ u32 *wrptr)
{
- int i, ret;
unsigned int cfg, val, idx;
+ int i, ret;
- ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1, &cfg);
if (ret)
return ret;
- if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
- ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
+ if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
+ val = 0;
+ ret = t4_cim_write_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1,
+ &val);
if (ret)
return ret;
}
- ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1, &val);
if (ret)
goto restart;
@@ -9943,25 +11513,29 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
*wrptr = idx;
for (i = 0; i < adap->params.cim_la_size; i++) {
- ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
- UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
+ val = UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F;
+ ret = t4_cim_write_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1,
+ &val);
if (ret)
break;
- ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1,
+ &val);
if (ret)
break;
if (val & UPDBGLARDEN_F) {
ret = -ETIMEDOUT;
break;
}
- ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_DATA_A, 1,
+ &la_buf[i]);
if (ret)
break;
/* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
* identify the 32-bit portion of the full 312-bit data
*/
- if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
+ if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
+ (idx & 0xf) >= 9)
idx = (idx & 0xff0) + 0x10;
else
idx++;
@@ -9970,14 +11544,33 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
}
restart:
if (cfg & UPDBGLAEN_F) {
- int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
- cfg & ~UPDBGLARDEN_F);
+ int r;
+
+ val = cfg & ~UPDBGLARDEN_F;
+ r = t4_cim_write_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1,
+ &val);
if (!ret)
ret = r;
}
+
return ret;
}
+/**
+ * t4_cim_read_la - read CIM LA capture buffer
+ * @adap: the adapter
+ * @la_buf: where to store the LA data
+ * @wrptr: the HW write pointer within the capture buffer
+ *
+ * Reads the contents of the CIM LA buffer with the most recent entry at
+ * the end of the returned data and with the entry at @wrptr first.
+ * We try to leave the LA in the running state we find it in.
+ */
+int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
+{
+ return t4_cim_read_la_core(adap, 0, la_buf, wrptr);
+}
+
/**
* t4_tp_read_la - read TP LA capture buffer
* @adap: the adapter
@@ -10162,10 +11755,10 @@ void t4_idma_monitor(struct adapter *adapter,
*/
int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
{
+ unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
+ unsigned int flash_cfg_start_sec, flash_cfg_size;
int ret, i, n, cfg_addr;
unsigned int addr;
- unsigned int flash_cfg_start_sec;
- unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
cfg_addr = t4_flash_cfg_addr(adap);
if (cfg_addr < 0)
@@ -10174,14 +11767,15 @@ int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
addr = cfg_addr;
flash_cfg_start_sec = addr / SF_SEC_SIZE;
- if (size > FLASH_CFG_MAX_SIZE) {
+ flash_cfg_size = t4_flash_location_size(adap, FLASH_LOC_CFG);
+
+ if (size > flash_cfg_size) {
dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
- FLASH_CFG_MAX_SIZE);
+ flash_cfg_size);
return -EFBIG;
}
- i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
- sf_sec_size);
+ i = DIV_ROUND_UP(flash_cfg_size, sf_sec_size); /* # of sectors spanned */
ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
flash_cfg_start_sec + i - 1);
/* If size == 0 then we're simply erasing the FLASH sectors associated
@@ -10345,6 +11939,8 @@ int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ data[6] = be32_to_cpu(c.u.idctxt.ctxt_data6);
}
return ret;
}
@@ -10363,13 +11959,21 @@ int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
enum ctxt_type ctype, u32 *data)
{
int i, ret;
+ u32 end;
t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
- if (!ret)
- for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
- *data++ = t4_read_reg(adap, i);
- return ret;
+ if (ret)
+ return ret;
+
+ end = CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7 ?
+ SGE_CTXT_DATA6_A :
+ SGE_CTXT_DATA5_A;
+
+ for (i = SGE_CTXT_DATA0_A; i <= end; i += 4)
+ *data++ = t4_read_reg(adap, i);
+
+ return 0;
}
int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
@@ -10416,19 +12020,23 @@ int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
* Reads the I2C data from the indicated device and location.
*/
int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
- unsigned int devid, unsigned int offset,
- unsigned int len, u8 *buf)
+ unsigned int devid, unsigned int offset, unsigned int len,
+ u8 *buf)
{
struct fw_ldst_cmd ldst_cmd, ldst_rpl;
unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
int ret = 0;
- if (len > I2C_PAGE_SIZE)
+ if (len > I2C_PAGE_SIZE) {
+ dev_err(adap->pdev_dev, "Incorrect page size len %d\n", len);
return -EINVAL;
+ }
/* Dont allow reads that spans multiple pages */
- if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
+ if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE) {
+ dev_err(adap->pdev_dev, "Read across the page\n");
return -EINVAL;
+ }
memset(&ldst_cmd, 0, sizeof(ldst_cmd));
ldst_cmd.op_to_addrspace =
@@ -10581,16 +12189,17 @@ int t4_load_boot(struct adapter *adap, u8 *boot_data,
unsigned int boot_sector = (boot_addr * 1024);
struct cxgb4_pci_exp_rom_header *header;
struct cxgb4_pcir_data *pcir_header;
- int pcir_offset;
+ int pcir_offset, ret, addr;
unsigned int i;
u16 device_id;
- int ret, addr;
- /**
- * Make sure the boot image does not encroach on the firmware region
+ /*
+ * Make sure the boot image does not exceed its available space.
*/
- if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
- dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
+ if (!t4_flash_location_in_range(adap, FLASH_LOC_BOOT_AREA,
+ boot_sector + size)) {
+ dev_err(adap->pdev_dev,
+ "boot data is larger than available BOOT area\n");
return -EFBIG;
}
@@ -10632,7 +12241,9 @@ int t4_load_boot(struct adapter *adap, u8 *boot_data,
* and Boot configuration data sections. These 3 boot sections span
* sectors 0 to 7 in flash and live right before the FW image location.
*/
- i = DIV_ROUND_UP(size ? size : FLASH_FW_START, sf_sec_size);
+ i = DIV_ROUND_UP(size ? size :
+ t4_flash_location_size(adap, FLASH_LOC_BOOT_AREA),
+ sf_sec_size);
ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
(boot_sector >> 16) + i - 1);
@@ -10693,35 +12304,37 @@ int t4_load_boot(struct adapter *adap, u8 *boot_data,
*/
static int t4_flash_bootcfg_addr(struct adapter *adapter)
{
+ int ret = t4_flash_location_end(adapter, FLASH_LOC_BOOTCFG);
/**
* If the device FLASH isn't large enough to hold a Firmware
* Configuration File, return an error.
*/
- if (adapter->params.sf_size <
- FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
+ if (ret < 0 || adapter->params.sf_size < ret)
return -ENOSPC;
- return FLASH_BOOTCFG_START;
+ return t4_flash_location_start(adapter, FLASH_LOC_BOOTCFG);
}
int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
{
unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
+ unsigned int boot_cfg_start_sec, boot_cfg_size;
struct cxgb4_bootcfg_data *header;
- unsigned int flash_cfg_start_sec;
- unsigned int addr, npad;
int ret, i, n, cfg_addr;
+ unsigned int addr, npad;
cfg_addr = t4_flash_bootcfg_addr(adap);
if (cfg_addr < 0)
return cfg_addr;
addr = cfg_addr;
- flash_cfg_start_sec = addr / SF_SEC_SIZE;
+ boot_cfg_start_sec = addr / SF_SEC_SIZE;
+ boot_cfg_size = t4_flash_location_size(adap, FLASH_LOC_BOOTCFG);
- if (size > FLASH_BOOTCFG_MAX_SIZE) {
- dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n",
- FLASH_BOOTCFG_MAX_SIZE);
+ if (size > boot_cfg_size) {
+ dev_err(adap->pdev_dev,
+ "bootcfg file too large, max is %u bytes\n",
+ boot_cfg_size);
return -EFBIG;
}
@@ -10732,10 +12345,9 @@ int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
goto out;
}
- i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,
- sf_sec_size);
- ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
- flash_cfg_start_sec + i - 1);
+ i = DIV_ROUND_UP(boot_cfg_size, sf_sec_size); /* # of sectors spanned */
+ ret = t4_flash_erase_sectors(adap, boot_cfg_start_sec,
+ boot_cfg_start_sec + i - 1);
/**
* If size == 0 then we're simply erasing the FLASH sectors associated
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next v1 08/10] cxgb4: Update driver lifecycle and peripherals for T7
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
` (6 preceding siblings ...)
2026-06-07 3:52 ` [PATCH net-next v1 07/10] cxgb4: Extend hardware abstraction layer for T7 logs Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 09/10] cxgb4: Update debugfs interface for T7 versioned structures Potnuri Bharat Teja
` (2 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Adapt primary driver entry points and peripheral sub-modules like MPS,
PTP, and ethtool to handle high-speed link profiles and telemetry
changes required by T7 adapters.
Integrate T7 parameters into main driver and peripheral workflows:
- Update driver description string and export global MODULE_FIRMWARE
tags for T7 firmware images, while adding support for 200G/400G link
modes and modern media modules.
- Implement modular workqueue management helpers, transition port
selection logic to use logical port references lport, and fix DCB
channels for T7 channel maps.
- Add dynamic tracking wrappers inside the MPS layer to manage
encapsulated MAC filters alongside logical index reference counting.
- Upgrade PTP telemetry to parse 64-bit hardware timestamps from the
dedicated T7 port register tracks.
- Expand ethtool interface to support SFP56/QSFP56 configurations,
redirect EEPROM routines through systemic PCI wrappers, and add full
RSS hash key get and set configurations.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../ethernet/chelsio/cxgb4/cxgb4_ethtool.c | 71 +-
.../net/ethernet/chelsio/cxgb4/cxgb4_main.c | 1059 ++++++++---------
.../net/ethernet/chelsio/cxgb4/cxgb4_mps.c | 52 +
.../net/ethernet/chelsio/cxgb4/cxgb4_ptp.c | 25 +-
4 files changed, 617 insertions(+), 590 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
index 0092bc16f887..283cc065471e 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
@@ -14,6 +14,7 @@
#include "cxgb4_tc_flower.h"
#define EEPROM_MAGIC 0x38E2F10C
+#define RSS_HASH_KEY_SIZE 40
static u32 get_msglevel(struct net_device *dev)
{
@@ -358,7 +359,7 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
int i;
u64 *p0;
- t4_get_port_stats_offset(adapter, pi->tx_chan,
+ t4_get_port_stats_offset(adapter, pi->lport,
(struct port_stats *)data,
&pi->stats_base);
@@ -440,10 +441,13 @@ static int from_fw_port_mod_type(enum fw_port_type port_type,
port_type == FW_PORT_TYPE_CR4_QSFP ||
port_type == FW_PORT_TYPE_CR_QSFP ||
port_type == FW_PORT_TYPE_CR2_QSFP ||
- port_type == FW_PORT_TYPE_SFP28) {
+ port_type == FW_PORT_TYPE_SFP28 ||
+ port_type == FW_PORT_TYPE_SFP56 ||
+ port_type == FW_PORT_TYPE_QSFP56) {
if (mod_type == FW_PORT_MOD_TYPE_LR ||
mod_type == FW_PORT_MOD_TYPE_SR ||
mod_type == FW_PORT_MOD_TYPE_ER ||
+ mod_type == FW_PORT_MOD_TYPE_DR ||
mod_type == FW_PORT_MOD_TYPE_LRM)
return PORT_FIBRE;
else if (mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
@@ -597,6 +601,20 @@ static void fw_caps_to_lmm(enum fw_port_type port_type,
FW_CAPS_TO_LMM(SPEED_50G, 50000baseSR2_Full);
break;
+ case FW_PORT_TYPE_SFP56:
+ SET_LMM(FIBRE);
+ FW_CAPS_TO_LMM(SPEED_50G, 50000baseSR2_Full);
+ FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
+ break;
+
+ case FW_PORT_TYPE_QSFP56:
+ SET_LMM(FIBRE);
+ FW_CAPS_TO_LMM(SPEED_200G, 200000baseSR2_Full);
+ FW_CAPS_TO_LMM(SPEED_100G, 100000baseCR4_Full);
+ FW_CAPS_TO_LMM(SPEED_50G, 50000baseSR2_Full);
+ FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
+ break;
+
case FW_PORT_TYPE_KR4_100G:
case FW_PORT_TYPE_CR4_QSFP:
SET_LMM(FIBRE);
@@ -1193,7 +1211,7 @@ static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
int vaddr = t4_eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
if (vaddr >= 0)
- vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
+ vaddr = cxgb4_pci_read_vpd(adap, vaddr, sizeof(u32), v);
return vaddr < 0 ? vaddr : 0;
}
@@ -1202,7 +1220,7 @@ static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
int vaddr = t4_eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
if (vaddr >= 0)
- vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
+ vaddr = cxgb4_pci_write_vpd(adap, vaddr, sizeof(u32), &v);
return vaddr < 0 ? vaddr : 0;
}
@@ -1576,6 +1594,11 @@ static int get_ts_info(struct net_device *dev, struct kernel_ethtool_ts_info *ts
return 0;
}
+static u32 get_rss_key_size(struct net_device *dev)
+{
+ return RSS_HASH_KEY_SIZE;
+}
+
static u32 get_rss_table_size(struct net_device *dev)
{
const struct port_info *pi = netdev_priv(dev);
@@ -1592,6 +1615,17 @@ static int get_rss_table(struct net_device *dev,
rxfh->hfunc = ETH_RSS_HASH_TOP;
if (!rxfh->indir)
return 0;
+
+ if (rxfh->key) {
+ u32 key[10];
+
+ t4_read_rss_key(pi->adapter, key, true);
+
+ /* RSS hash keys are read in order TP_RSS_SECRET_KEY9..0 */
+ for (int i = 0; i < 10; i++)
+ ((u32 *)rxfh->key)[i] = be32_to_cpu(key[9 - i]);
+ }
+
while (n--)
rxfh->indir[n] = pi->rss[n];
return 0;
@@ -1607,10 +1641,19 @@ static int set_rss_table(struct net_device *dev,
/* We require at least one supported parameter to be changed and no
* change in any of the unsupported parameters
*/
- if (rxfh->key ||
- (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
- rxfh->hfunc != ETH_RSS_HASH_TOP))
+ if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
+ rxfh->hfunc != ETH_RSS_HASH_TOP)
return -EOPNOTSUPP;
+
+ if (rxfh->key) {
+ u32 key[10];
+
+ /* RSS hash keys are written in order TP_RSS_SECRET_KEY9..0 */
+ for (int i = 0; i < 10; i++)
+ key[i] = cpu_to_be32(((u32 *)rxfh->key)[9 - i]);
+ t4_write_rss_key(pi->adapter, key, -1, true);
+ }
+
if (!rxfh->indir)
return 0;
@@ -1629,7 +1672,6 @@ static struct filter_entry *cxgb4_get_filter_entry(struct adapter *adap,
u32 ftid)
{
struct tid_info *t = &adap->tids;
-
if (ftid >= t->hpftid_base && ftid < t->hpftid_base + t->nhpftids)
return &t->hpftid_tab[ftid - t->hpftid_base];
@@ -2022,12 +2064,12 @@ static int cxgb4_get_module_info(struct net_device *dev,
case FW_PORT_TYPE_SFP:
case FW_PORT_TYPE_QSA:
case FW_PORT_TYPE_SFP28:
- ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ ret = t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, SFF_8472_COMP_ADDR,
SFF_8472_COMP_LEN, &sff8472_comp);
if (ret)
return ret;
- ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ ret = t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, SFP_DIAG_TYPE_ADDR,
SFP_DIAG_TYPE_LEN, &sff_diag_type);
if (ret)
@@ -2050,7 +2092,7 @@ static int cxgb4_get_module_info(struct net_device *dev,
case FW_PORT_TYPE_CR_QSFP:
case FW_PORT_TYPE_CR2_QSFP:
case FW_PORT_TYPE_CR4_QSFP:
- ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ ret = t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, SFF_REV_ADDR,
SFF_REV_LEN, &sff_rev);
/* For QSFP type ports, revision value >= 3
@@ -2083,14 +2125,14 @@ static int cxgb4_get_module_eeprom(struct net_device *dev,
memset(data, 0, eprom->len);
if (offset + len <= I2C_PAGE_SIZE)
- return t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ return t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, offset, len, data);
/* offset + len spans 0xa0 and 0xa1 pages */
if (offset <= I2C_PAGE_SIZE) {
/* read 0xa0 page */
len = I2C_PAGE_SIZE - offset;
- ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
+ ret = t4_i2c_rd(adapter, adapter->mbox, pi->lport,
I2C_DEV_ADDR_A0, offset, len, data);
if (ret)
return ret;
@@ -2101,7 +2143,7 @@ static int cxgb4_get_module_eeprom(struct net_device *dev,
len = eprom->len - len;
}
/* Read additional optical diagnostics from page 0xa2 if supported */
- return t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan, I2C_DEV_ADDR_A2,
+ return t4_i2c_rd(adapter, adapter->mbox, pi->lport, I2C_DEV_ADDR_A2,
offset, len, &data[eprom->len - len]);
}
@@ -2205,6 +2247,7 @@ static const struct ethtool_ops cxgb_ethtool_ops = {
.get_rxnfc = get_rxnfc,
.set_rxnfc = set_rxnfc,
.get_rx_ring_count = get_rx_ring_count,
+ .get_rxfh_key_size = get_rss_key_size,
.get_rxfh_indir_size = get_rss_table_size,
.get_rxfh = get_rss_table,
.set_rxfh = set_rss_table,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 6df98fca932f..18f2a7e20b62 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -92,40 +92,20 @@
char cxgb4_driver_name[] = KBUILD_MODNAME;
-#define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
+#define DRV_DESC "Chelsio T4/T5/T6/T7 Network Driver"
#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
-/* Macros needed to support the PCI Device ID Table ...
- */
-#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
- static const struct pci_device_id cxgb4_pci_tbl[] = {
-#define CXGB4_UNIFIED_PF 0x4
-
-#define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
-
-/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
- * called for both.
- */
-#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
-
-#define CH_PCI_ID_TABLE_ENTRY(devid) \
- { PCI_VDEVICE(CHELSIO, (devid)), .driver_data = CXGB4_UNIFIED_PF }
-
-#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
- { } \
- }
-
-#include "t4_pci_id_tbl.h"
-
#define FW4_FNAME "cxgb4/t4fw.bin"
#define FW5_FNAME "cxgb4/t5fw.bin"
#define FW6_FNAME "cxgb4/t6fw.bin"
+#define FW7_FNAME "cxgb4/t7fw.bin"
#define FW4_CFNAME "cxgb4/t4-config.txt"
#define FW5_CFNAME "cxgb4/t5-config.txt"
#define FW6_CFNAME "cxgb4/t6-config.txt"
+#define FW7_CFNAME "cxgb4/t7-config.txt"
#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
#define PHY_AQ1202_DEVICEID 0x4409
@@ -134,10 +114,10 @@ char cxgb4_driver_name[] = KBUILD_MODNAME;
MODULE_DESCRIPTION(DRV_DESC);
MODULE_AUTHOR("Chelsio Communications");
MODULE_LICENSE("Dual BSD/GPL");
-MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
MODULE_FIRMWARE(FW4_FNAME);
MODULE_FIRMWARE(FW5_FNAME);
MODULE_FIRMWARE(FW6_FNAME);
+MODULE_FIRMWARE(FW7_FNAME);
/*
* The driver uses the best interrupt scheme available on a platform in the
@@ -171,18 +151,20 @@ static int rx_dma_offset = 2;
* queue. Select between the kernel provided function (select_queue=0) or user
* cxgb_select_queue function (select_queue=1)
*
- * Default: select_queue=0
+ * Default: select_queue=1
*/
-static int select_queue;
+static int select_queue = 1;
module_param(select_queue, int, 0644);
MODULE_PARM_DESC(select_queue,
"Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
static struct dentry *cxgb4_debugfs_root;
+static const struct net_device_ops cxgb4_netdev_ops;
LIST_HEAD(adapter_list);
DEFINE_MUTEX(uld_mutex);
LIST_HEAD(uld_list);
+struct cxgb4_uld_info cxgb4_ulds[CXGB4_ULD_MAX];
static int cfg_queues(struct adapter *adap);
@@ -218,6 +200,12 @@ static void link_report(struct net_device *dev)
case 100000:
s = "100Gbps";
break;
+ case 200000:
+ s = "200Gbps";
+ break;
+ case 400000:
+ s = "400Gbps";
+ break;
default:
pr_info("%s: unsupported speed: %d\n",
dev->name, p->link_cfg.speed);
@@ -305,7 +293,8 @@ void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
void t4_os_portmod_changed(struct adapter *adap, int port_id)
{
static const char *mod_str[] = {
- NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
+ NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM",
+ "LR_SIMPLEX", "DR"
};
struct net_device *dev = adap->port[port_id];
@@ -333,6 +322,40 @@ void t4_os_portmod_changed(struct adapter *adap, int port_id)
pi->link_cfg.redo_l1cfg = netif_running(dev);
}
+void cxgb4_work_queue(struct workqueue_struct *workq, struct work_struct *work)
+{
+ if (!workq)
+ return;
+
+ queue_work(workq, work);
+}
+
+void cxgb4_work_cancel(struct workqueue_struct *workq, struct work_struct *work)
+{
+ if (!workq)
+ return;
+
+ cancel_work_sync(work);
+}
+
+static void cxgb4_workqueues_destroy(struct adapter *adap)
+{
+ if (adap->workq) {
+ flush_workqueue(adap->workq);
+ destroy_workqueue(adap->workq);
+ adap->workq = NULL;
+ }
+}
+
+static int cxgb4_workqueues_create(struct adapter *adap)
+{
+ adap->workq = create_singlethread_workqueue("cxgb4");
+ if (!adap->workq)
+ return -ENOMEM;
+
+ return 0;
+}
+
int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
module_param(dbfifo_int_thresh, int, 0644);
MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
@@ -517,7 +540,7 @@ static int link_start(struct net_device *dev)
ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
dev->dev_addr, true, &pi->smt_idx);
if (ret == 0)
- ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
+ ret = t4_link_l1cfg(pi->adapter, mb, pi->lport,
&pi->link_cfg);
if (ret == 0) {
local_bh_disable();
@@ -534,9 +557,17 @@ static int link_start(struct net_device *dev)
static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
{
int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
- struct net_device *dev = adap->port[adap->chan_map[port]];
- int old_dcb_enabled = cxgb4_dcb_enabled(dev);
- int new_dcb_enabled;
+ int old_dcb_enabled, new_dcb_enabled;
+ struct net_device *dev;
+
+ dev = cxgb4_port_chan_to_netdev(adap, port);
+ if (!dev) {
+ dev_warn(adap->pdev_dev,
+ "Could not get netdevice for handling dcb_rpl for port %d\n", port);
+ return;
+ }
+
+ old_dcb_enabled = cxgb4_dcb_enabled(dev);
cxgb4_dcb_handle_fw_update(adap, pcmd);
new_dcb_enabled = cxgb4_dcb_enabled(dev);
@@ -579,7 +610,6 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
struct sge_txq *txq;
txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
- txq->restarts++;
if (txq->q_type == CXGB4_TXQ_ETH) {
struct sge_eth_txq *eq;
@@ -588,6 +618,7 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
} else {
struct sge_uld_txq *oq;
+ txq->restarts++;
oq = container_of(txq, struct sge_uld_txq, q);
tasklet_schedule(&oq->qresume_tsk);
}
@@ -608,7 +639,7 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
struct net_device *dev;
int dcbxdis, state_input;
- dev = q->adap->port[q->adap->chan_map[port]];
+ dev = cxgb4_port_chan_to_netdev(q->adap, port);
dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
: !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
@@ -959,7 +990,7 @@ void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q)
/* 0-increment GTS to start the timer and enable interrupts */
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
SEINTARM_V(q->intr_params) |
- INGRESSQID_V(q->cntxt_id));
+ INGRESSQID_V(q->cntxt_id) | CIDXINC_V(0));
}
/*
@@ -1047,7 +1078,7 @@ static int setup_sge_queues(struct adapter *adap)
struct sge_uld_rxq_info *rxq_info = NULL;
struct sge *s = &adap->sge;
unsigned int cmplqid = 0;
- int err, i, j, msix = 0;
+ int err, i, j, k, msix = 0;
if (is_uld(adap))
rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
@@ -1079,8 +1110,7 @@ static int setup_sge_queues(struct adapter *adap)
msix, &q->fl,
t4_ethrx_handler,
NULL,
- t4_get_tp_ch_map(adap,
- pi->tx_chan));
+ t4_get_tp_ch_map(adap, pi->lport));
if (err)
goto freeout;
q->rspq.idx = j;
@@ -1092,7 +1122,7 @@ static int setup_sge_queues(struct adapter *adap)
err = t4_sge_alloc_eth_txq(adap, t, dev,
netdev_get_tx_queue(dev, j),
q->rspq.cntxt_id,
- !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
+ !!(adap->flags & CXGB4_SGE_DBQ_TIMER), j);
if (err)
goto freeout;
}
@@ -1105,25 +1135,26 @@ static int setup_sge_queues(struct adapter *adap)
if (rxq_info)
cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
- err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
- s->fw_evtq.cntxt_id, cmplqid);
- if (err)
- goto freeout;
+ /* Allocate at least num_up_cores control queues per port */
+ j = i * adap->params.num_up_cores;
+ for (k = 0; k < adap->params.num_up_cores; k++, j++) {
+ err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[j], adap->port[i],
+ s->fw_evtq.cntxt_id, cmplqid, k);
+ if (err)
+ goto freeout;
+ }
}
if (!is_t4(adap->params.chip)) {
err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
netdev_get_tx_queue(adap->port[0], 0)
- , s->fw_evtq.cntxt_id, false);
+ , s->fw_evtq.cntxt_id, false, 0);
if (err)
goto freeout;
}
- t4_write_reg(adap, is_t4(adap->params.chip) ?
- MPS_TRC_RSS_CONTROL_A :
- MPS_T5_TRC_RSS_CONTROL_A,
- RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
- QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
+ t4_set_trace_rss_control(adap, netdev2pinfo(adap->port[0])->tx_chan,
+ s->ethrxq[0].rspq.abs_id);
return 0;
freeout:
dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
@@ -1286,17 +1317,6 @@ static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
return err;
}
-static int setup_debugfs(struct adapter *adap)
-{
- if (IS_ERR_OR_NULL(adap->debugfs_root))
- return -1;
-
-#ifdef CONFIG_DEBUG_FS
- t4_setup_debugfs(adap);
-#endif
- return 0;
-}
-
static void cxgb4_port_mirror_free_rxq(struct adapter *adap,
struct sge_eth_rxq *mirror_rxq)
{
@@ -2118,14 +2138,28 @@ EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
* cxgb4_port_chan - get the HW channel of a port
* @dev: the net device for the port
*
- * Return the HW Tx channel of the given port.
+ * Return the HW channel of the given port.
*/
unsigned int cxgb4_port_chan(const struct net_device *dev)
{
- return netdev2pinfo(dev)->tx_chan;
+ return netdev2pinfo(dev)->lport;
}
EXPORT_SYMBOL(cxgb4_port_chan);
+struct net_device *cxgb4_port_chan_to_netdev(struct adapter *adap, u8 chan)
+{
+ struct port_info *pi;
+ u8 i;
+
+ for_each_port(adap, i) {
+ pi = adap2pinfo(adap, i);
+ if (pi->lport == chan)
+ return adap->port[pi->port_id];
+ }
+
+ return NULL;
+}
+
/**
* cxgb4_port_e2cchan - get the HW c-channel of a port
* @dev: the net device for the port
@@ -2252,70 +2286,26 @@ EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
{
- u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
- u32 edc0_end, edc1_end, mc0_end, mc1_end;
- u32 offset, memtype, memaddr;
- struct adapter *adap;
- u32 hma_size = 0;
+ struct adapter *adap = netdev2adap(dev);
+ unsigned long mtype = 0;
+ u32 params[7], val[7];
+ u32 offset;
int ret;
- adap = netdev2adap(dev);
-
offset = ((stag >> 8) * 32) + adap->vres.stag.start;
+ if (offset >= (adap->vres.stag.start + adap->vres.stag.size))
+ goto err;
- /* Figure out where the offset lands in the Memory Type/Address scheme.
- * This code assumes that the memory is laid out starting at offset 0
- * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
- * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
- * MC0, and some have both MC0 and MC1.
- */
- size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
- edc0_size = EDRAM0_SIZE_G(size) << 20;
- size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
- edc1_size = EDRAM1_SIZE_G(size) << 20;
- size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
- mc0_size = EXT_MEM0_SIZE_G(size) << 20;
-
- if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
- hma_size = EXT_MEM1_SIZE_G(size) << 20;
- }
- edc0_end = edc0_size;
- edc1_end = edc0_end + edc1_size;
- mc0_end = edc1_end + mc0_size;
-
- if (offset < edc0_end) {
- memtype = MEM_EDC0;
- memaddr = offset;
- } else if (offset < edc1_end) {
- memtype = MEM_EDC1;
- memaddr = offset - edc0_end;
- } else {
- if (hma_size && (offset < (edc1_end + hma_size))) {
- memtype = MEM_HMA;
- memaddr = offset - edc1_end;
- } else if (offset < mc0_end) {
- memtype = MEM_MC0;
- memaddr = offset - edc1_end;
- } else if (is_t5(adap->params.chip)) {
- size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
- mc1_size = EXT_MEM1_SIZE_G(size) << 20;
- mc1_end = mc0_end + mc1_size;
- if (offset < mc1_end) {
- memtype = MEM_MC1;
- memaddr = offset - mc0_end;
- } else {
- /* offset beyond the end of any memory */
- goto err;
- }
- } else {
- /* T4/T6 only has a single memory channel */
- goto err;
- }
- }
+ params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
+ FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
+ if (ret != 0)
+ goto err;
+
+ mtype = FW_PARAMS_PARAM_Y_G(val[0]);
spin_lock(&adap->win0_lock);
- ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
+ ret = t4_memory_rw(adap, MEMWIN_NIC, mtype, offset, 32, tpte, T4_MEMORY_READ);
spin_unlock(&adap->win0_lock);
return ret;
@@ -2357,8 +2347,6 @@ int cxgb4_bar2_sge_qregs(struct net_device *dev,
}
EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
-static struct pci_driver cxgb4_driver;
-
static void check_neigh_update(struct neighbour *neigh)
{
const struct device *parent;
@@ -2367,7 +2355,7 @@ static void check_neigh_update(struct neighbour *neigh)
if (is_vlan_dev(netdev))
netdev = vlan_dev_real_dev(netdev);
parent = netdev->dev.parent;
- if (parent && parent->driver == &cxgb4_driver.driver)
+ if (parent && netdev->netdev_ops == &cxgb4_netdev_ops)
t4_l2t_update(dev_get_drvdata(parent), neigh);
}
@@ -2393,7 +2381,6 @@ static struct notifier_block cxgb4_netevent_nb = {
static void drain_db_fifo(struct adapter *adap, int usecs)
{
u32 v1, v2, lp_count, hp_count;
-
do {
v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
@@ -2608,7 +2595,7 @@ void t4_db_full(struct adapter *adap)
notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
- queue_work(adap->workq, &adap->db_full_task);
+ cxgb4_work_queue(adap->workq, &adap->db_full_task);
}
}
@@ -2618,7 +2605,7 @@ void t4_db_dropped(struct adapter *adap)
disable_dbs(adap);
notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
}
- queue_work(adap->workq, &adap->db_drop_task);
+ cxgb4_work_queue(adap->workq, &adap->db_drop_task);
}
void t4_register_netevent_notifier(void)
@@ -2639,10 +2626,14 @@ static void detach_ulds(struct adapter *adap)
mutex_lock(&uld_mutex);
list_del(&adap->list_node);
- for (i = 0; i < CXGB4_ULD_MAX; i++)
- if (adap->uld && adap->uld[i].handle)
+ for (i = 0; i < CXGB4_ULD_MAX; i++) {
+ mutex_lock(&adap->uld_mutex);
+ if (adap->uld[i].handle) {
adap->uld[i].state_change(adap->uld[i].handle,
- CXGB4_STATE_DETACH);
+ CXGB4_STATE_DETACH);
+ }
+ mutex_unlock(&adap->uld_mutex);
+ }
if (netevent_registered && list_empty(&adapter_list)) {
unregister_netevent_notifier(&cxgb4_netevent_nb);
@@ -2655,12 +2646,12 @@ static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
{
unsigned int i;
- mutex_lock(&uld_mutex);
- for (i = 0; i < CXGB4_ULD_MAX; i++)
+ for (i = 0; i < CXGB4_ULD_MAX; i++) {
+ mutex_lock(&adap->uld_mutex);
if (adap->uld && adap->uld[i].handle)
- adap->uld[i].state_change(adap->uld[i].handle,
- new_state);
- mutex_unlock(&uld_mutex);
+ adap->uld[i].state_change(adap->uld[i].handle, new_state);
+ mutex_unlock(&adap->uld_mutex);
+ }
}
#if IS_ENABLED(CONFIG_IPV6)
@@ -2669,7 +2660,6 @@ static int cxgb4_inet6addr_handler(struct notifier_block *this,
{
struct inet6_ifaddr *ifa = data;
struct net_device *event_dev = ifa->idev->dev;
- const struct device *parent = NULL;
#if IS_ENABLED(CONFIG_BONDING)
struct adapter *adap;
#endif
@@ -2695,10 +2685,7 @@ static int cxgb4_inet6addr_handler(struct notifier_block *this,
}
#endif
- if (event_dev)
- parent = event_dev->dev.parent;
-
- if (parent && parent->driver == &cxgb4_driver.driver) {
+ if (event_dev && event_dev->netdev_ops == &cxgb4_netdev_ops) {
switch (event) {
case NETDEV_UP:
cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
@@ -2768,7 +2755,6 @@ static int cxgb_up(struct adapter *adap)
err = -ENOMEM;
goto irq_err;
}
-
err = request_irq(adap->msix_info[s->nd_msix_idx].vec,
t4_nondata_intr, 0,
adap->msix_info[s->nd_msix_idx].desc, adap);
@@ -2779,10 +2765,13 @@ static int cxgb_up(struct adapter *adap)
if (err)
goto irq_err_free_nd_msix;
} else {
+ unsigned long flags = 0;
+
+ if (!cxgb4_msix_enabled(adap) && !cxgb4_msi_enabled(adap))
+ flags = IRQF_SHARED;
+
err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
- (adap->flags & CXGB4_USING_MSI) ? 0
- : IRQF_SHARED,
- adap->port[0]->name, adap);
+ flags, adap->port[0]->name, adap);
if (err)
goto irq_err;
}
@@ -2812,9 +2801,9 @@ static int cxgb_up(struct adapter *adap)
static void cxgb_down(struct adapter *adapter)
{
- cancel_work_sync(&adapter->tid_release_task);
- cancel_work_sync(&adapter->db_full_task);
- cancel_work_sync(&adapter->db_drop_task);
+ cxgb4_work_cancel(adapter->workq, &adapter->tid_release_task);
+ cxgb4_work_cancel(adapter->workq, &adapter->db_full_task);
+ cxgb4_work_cancel(adapter->workq, &adapter->db_drop_task);
adapter->tid_release_task_busy = false;
adapter->tid_release_head = NULL;
@@ -3008,7 +2997,7 @@ static void cxgb_get_stats(struct net_device *dev,
spin_unlock(&adapter->stats_lock);
return;
}
- t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
+ t4_get_port_stats_offset(adapter, p->lport, &stats,
&p->stats_base);
spin_unlock(&adapter->stats_lock);
@@ -3347,7 +3336,7 @@ static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
SCHED_CLASS_MODE_CLASS,
SCHED_CLASS_RATEUNIT_BITS,
SCHED_CLASS_RATEMODE_ABS,
- pi->tx_chan, class_id, 0,
+ pi->lport, class_id, 0,
max_tx_rate * 1000, 0, pktsize, 0);
if (ret) {
dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
@@ -3731,16 +3720,21 @@ static int cxgb_udp_tunnel_unset_port(struct net_device *netdev,
struct port_info *pi = netdev_priv(netdev);
struct adapter *adapter = pi->adapter;
u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
+ u32 chip_ver, reg;
int ret = 0, i;
+ chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
+
switch (ti->type) {
case UDP_TUNNEL_TYPE_VXLAN:
adapter->vxlan_port = 0;
- t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
+ reg = chip_ver >= CHELSIO_T7 ?
+ T7_MPS_RX_VXLAN_TYPE_A : MPS_RX_VXLAN_TYPE_A;
break;
case UDP_TUNNEL_TYPE_GENEVE:
adapter->geneve_port = 0;
- t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
+ reg = chip_ver >= CHELSIO_T7 ? T7_MPS_RX_GENEVE_TYPE_A :
+ MPS_RX_GENEVE_TYPE_A;
break;
default:
return -EINVAL;
@@ -3757,13 +3751,13 @@ static int cxgb_udp_tunnel_unset_port(struct net_device *netdev,
match_all_mac, match_all_mac,
adapter->rawf_start + pi->port_id,
1, pi->port_id, false);
- if (ret < 0) {
- netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
- i);
- return ret;
- }
+ if (ret < 0)
+ netdev_info(netdev,
+ "RAW MAC Filter free failed for port %d, UDP port %u, ret: %d\n",
+ i, be16_to_cpu(ti->port), ret);
}
+ t4_write_reg(adapter, reg, 0);
return 0;
}
@@ -3774,18 +3768,26 @@ static int cxgb_udp_tunnel_set_port(struct net_device *netdev,
struct port_info *pi = netdev_priv(netdev);
struct adapter *adapter = pi->adapter;
u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
+ u32 chip_ver, reg, val;
+ __be16 *port_save;
int i, ret;
+ chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
+
switch (ti->type) {
case UDP_TUNNEL_TYPE_VXLAN:
adapter->vxlan_port = ti->port;
- t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
- VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
+ port_save = &adapter->vxlan_port;
+ reg = chip_ver >= CHELSIO_T7 ? T7_MPS_RX_VXLAN_TYPE_A :
+ MPS_RX_VXLAN_TYPE_A;
+ val = VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F;
break;
case UDP_TUNNEL_TYPE_GENEVE:
adapter->geneve_port = ti->port;
- t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
- GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
+ port_save = &adapter->geneve_port;
+ reg = chip_ver >= CHELSIO_T7 ?
+ T7_MPS_RX_GENEVE_TYPE_A : MPS_RX_GENEVE_TYPE_A;
+ val = GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F;
break;
default:
return -EINVAL;
@@ -3806,13 +3808,27 @@ static int cxgb_udp_tunnel_set_port(struct net_device *netdev,
adapter->rawf_start + pi->port_id,
1, pi->port_id, false);
if (ret < 0) {
- netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
- be16_to_cpu(ti->port));
- return ret;
+ netdev_info(netdev,
+ "RAW MAC Filter alloc failed for port %d, UDP port %u, ret: %d\n",
+ i, be16_to_cpu(ti->port), ret);
+ goto out_free;
}
}
+ *port_save = ti->port;
+ t4_write_reg(adapter, reg, val);
return 0;
+
+out_free:
+ while (i-- > 0) {
+ pi = adap2pinfo(adapter, i);
+ t4_free_raw_mac_filt(adapter, pi->viid, match_all_mac,
+ match_all_mac,
+ adapter->rawf_start + pi->port_id,
+ 1, pi->port_id, false);
+ }
+
+ return ret;
}
static const struct udp_tunnel_nic_info cxgb_udp_tunnels = {
@@ -3853,30 +3869,30 @@ static netdev_features_t cxgb_fix_features(struct net_device *dev,
}
static const struct net_device_ops cxgb4_netdev_ops = {
- .ndo_open = cxgb_open,
- .ndo_stop = cxgb_close,
- .ndo_start_xmit = t4_start_xmit,
- .ndo_select_queue = cxgb_select_queue,
- .ndo_get_stats64 = cxgb_get_stats,
- .ndo_set_rx_mode = cxgb_set_rxmode,
- .ndo_set_mac_address = cxgb_set_mac_addr,
- .ndo_set_features = cxgb_set_features,
- .ndo_validate_addr = eth_validate_addr,
- .ndo_eth_ioctl = cxgb_ioctl,
- .ndo_change_mtu = cxgb_change_mtu,
+ .ndo_open = cxgb_open,
+ .ndo_stop = cxgb_close,
+ .ndo_start_xmit = t4_start_xmit,
+ .ndo_select_queue = cxgb_select_queue,
+ .ndo_get_stats64 = cxgb_get_stats,
+ .ndo_set_rx_mode = cxgb_set_rxmode,
+ .ndo_set_mac_address = cxgb_set_mac_addr,
+ .ndo_set_features = cxgb_set_features,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_eth_ioctl = cxgb_ioctl,
+ .ndo_change_mtu = cxgb_change_mtu,
#ifdef CONFIG_NET_POLL_CONTROLLER
- .ndo_poll_controller = cxgb_netpoll,
+ .ndo_poll_controller = cxgb_netpoll,
#endif
#ifdef CONFIG_CHELSIO_T4_FCOE
- .ndo_fcoe_enable = cxgb_fcoe_enable,
- .ndo_fcoe_disable = cxgb_fcoe_disable,
+ .ndo_fcoe_enable = cxgb_fcoe_enable,
+ .ndo_fcoe_disable = cxgb_fcoe_disable,
#endif /* CONFIG_CHELSIO_T4_FCOE */
- .ndo_set_tx_maxrate = cxgb_set_tx_maxrate,
- .ndo_setup_tc = cxgb_setup_tc,
- .ndo_features_check = cxgb_features_check,
- .ndo_fix_features = cxgb_fix_features,
- .ndo_hwtstamp_get = cxgb_hwtstamp_get,
- .ndo_hwtstamp_set = cxgb_hwtstamp_set,
+ .ndo_set_tx_maxrate = cxgb_set_tx_maxrate,
+ .ndo_setup_tc = cxgb_setup_tc,
+ .ndo_features_check = cxgb_features_check,
+ .ndo_fix_features = cxgb_fix_features,
+ .ndo_hwtstamp_get = cxgb_hwtstamp_get,
+ .ndo_hwtstamp_set = cxgb_hwtstamp_set,
};
#ifdef CONFIG_PCI_IOV
@@ -3937,35 +3953,7 @@ void t4_fatal_err(struct adapter *adap)
netif_carrier_off(dev);
}
dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
- queue_work(adap->workq, &adap->fatal_err_notify_task);
-}
-
-static void setup_memwin(struct adapter *adap)
-{
- u32 nic_win_base = t4_get_util_window(adap);
-
- t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
-}
-
-static void setup_memwin_rdma(struct adapter *adap)
-{
- if (adap->vres.ocq.size) {
- u32 start;
- unsigned int sz_kb;
-
- start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
- start &= PCI_BASE_ADDRESS_MEM_MASK;
- start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
- sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
- t4_write_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
- start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
- t4_write_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
- adap->vres.ocq.start);
- t4_read_reg(adap,
- PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
- }
+ cxgb4_work_queue(adap->workq, &adap->fatal_err_notify_task);
}
/* HMA Definitions */
@@ -3975,6 +3963,9 @@ static void setup_memwin_rdma(struct adapter *adap)
#define HMA_PAGE_SIZE PAGE_SIZE
+/* HW supports max 16M page size */
+#define HMA_MAX_PAGE_SIZE (16UL << 20)
+
#define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */
#define HMA_PAGE_ORDER \
@@ -4025,7 +4016,9 @@ static int adap_config_hma(struct adapter *adapter)
unsigned int i, j, k;
u32 param, hma_size;
unsigned int ncmds;
+ unsigned int nents;
size_t page_size;
+ u32 best_page_size;
u32 page_order;
int node, ret;
@@ -4097,16 +4090,33 @@ static int adap_config_hma(struct adapter *adapter)
}
adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
- adapter->hma.phy_addr = kzalloc_objs(dma_addr_t, sgt->nents);
+ best_page_size = HMA_MAX_PAGE_SIZE;
+ for_each_sg(sgl, iter, sgt->nents, i) {
+ if (!is_power_of_2(sg_dma_len(iter))) {
+ best_page_size =
+ min(page_size << page_order, HMA_MAX_PAGE_SIZE);
+ break;
+ }
+
+ if (sg_dma_len(iter) < best_page_size)
+ best_page_size = sg_dma_len(iter);
+ }
+
+ nents = (hma_size << 20) / best_page_size;
+ adapter->hma.phy_addr = kcalloc(nents, sizeof(dma_addr_t), GFP_KERNEL);
if (unlikely(!adapter->hma.phy_addr))
goto free_hma;
+ k = 0;
for_each_sg(sgl, iter, sgt->nents, i) {
- newpage = sg_page(iter);
- adapter->hma.phy_addr[i] = sg_dma_address(iter);
+ u32 npages = sg_dma_len(iter) / best_page_size;
+
+ for (j = 0; j < npages; j++)
+ adapter->hma.phy_addr[k++] =
+ sg_dma_address(iter) + (j * best_page_size);
}
- ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
+ ncmds = DIV_ROUND_UP(nents, HMA_MAX_ADDR_IN_CMD);
/* Pass on the addresses to firmware */
for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
struct fw_hma_cmd hma_cmd;
@@ -4121,7 +4131,7 @@ static int adap_config_hma(struct adapter *adapter)
* addresses
*/
if (i == ncmds - 1) {
- naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
+ naddr = nents % HMA_MAX_ADDR_IN_CMD;
naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
}
memset(&hma_cmd, 0, sizeof(hma_cmd));
@@ -4140,8 +4150,7 @@ static int adap_config_hma(struct adapter *adapter)
/* Total Page size specified in units of 4K */
hma_cmd.addr_size_pkd =
- htonl(FW_HMA_CMD_ADDR_SIZE_V
- ((page_size << page_order) >> 12));
+ htonl(FW_HMA_CMD_ADDR_SIZE_V(best_page_size >> 12));
/* Fill the 5 addresses */
for (j = 0; j < naddr; j++) {
@@ -4285,7 +4294,7 @@ static int adap_init0_tweaks(struct adapter *adapter)
* Process module parameters which affect early initialization.
*/
if (rx_dma_offset != 2 && rx_dma_offset != 0) {
- dev_err(&adapter->pdev->dev,
+ dev_err(adapter->pdev_dev,
"Ignoring illegal rx_dma_offset=%d, using 2\n",
rx_dma_offset);
rx_dma_offset = 2;
@@ -4356,9 +4365,9 @@ static struct info_10gbt_phy_fw {
{ 0, NULL, NULL },
};
-static struct info_10gbt_phy_fw *find_phy_info(int devid)
+static struct info_10gbt_phy_fw *find_phy_info(struct adapter *adap)
{
- int i;
+ int i, devid = cxgb4_pci_device_id(adap);
for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
if (phy_info_array[i].phy_fw_id == devid)
@@ -4374,13 +4383,13 @@ static struct info_10gbt_phy_fw *find_phy_info(int devid)
*/
static int adap_init0_phy(struct adapter *adap)
{
+ struct info_10gbt_phy_fw *phy_info;
const struct firmware *phyf;
int ret;
- struct info_10gbt_phy_fw *phy_info;
/* Use the device ID to determine which PHY file to flash.
*/
- phy_info = find_phy_info(adap->pdev->device);
+ phy_info = find_phy_info(adap);
if (!phy_info) {
dev_warn(adap->pdev_dev,
"No PHY Firmware file found for this PHY\n");
@@ -4444,14 +4453,15 @@ static int adap_init0_phy(struct adapter *adap)
*/
static int adap_init0_config(struct adapter *adapter, int reset)
{
+ unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
char *fw_config_file, fw_config_file_path[256];
u32 finiver, finicsum, cfcsum, param, val;
struct fw_caps_config_cmd caps_cmd;
unsigned long mtype = 0, maddr = 0;
const struct firmware *cf;
char *config_name = NULL;
- int config_issued = 0;
- int ret;
+ int ret, config_issued = 0;
+ int devid = 0;
/*
* Reset device if necessary.
@@ -4468,7 +4478,8 @@ static int adap_init0_config(struct adapter *adapter, int reset)
* to be performed after any global adapter RESET above since some
* PHYs only have local RAM copies of the PHY firmware.
*/
- if (is_10gbt_device(adapter->pdev->device)) {
+ devid = cxgb4_pci_device_id(adapter);
+ if (is_10gbt_device(devid)) {
ret = adap_init0_phy(adapter);
if (ret < 0)
goto bye;
@@ -4478,7 +4489,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
* then use that. Otherwise, use the configuration file stored
* in the adapter flash ...
*/
- switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
+ switch (chip_ver) {
case CHELSIO_T4:
fw_config_file = FW4_CFNAME;
break;
@@ -4488,9 +4499,12 @@ static int adap_init0_config(struct adapter *adapter, int reset)
case CHELSIO_T6:
fw_config_file = FW6_CFNAME;
break;
+ case CHELSIO_T7:
+ fw_config_file = FW7_CFNAME;
+ break;
default:
dev_err(adapter->pdev_dev, "Device %d is not supported\n",
- adapter->pdev->device);
+ devid);
ret = -EINVAL;
goto bye;
}
@@ -4507,9 +4521,10 @@ static int adap_init0_config(struct adapter *adapter, int reset)
"/lib/firmware/%s", fw_config_file);
config_name = fw_config_file_path;
- if (cf->size >= FLASH_CFG_MAX_SIZE)
+ ret = t4_flash_location_size(adapter, FLASH_LOC_CFG);
+ if (ret < 0 || cf->size >= ret) {
ret = -ENOMEM;
- else {
+ } else {
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
ret = t4_query_params(adapter, adapter->mbox,
@@ -4653,7 +4668,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
dev_err(adapter->pdev_dev,
"HMA configuration failed with error %d\n", ret);
- if (is_t6(adapter->params.chip)) {
+ if (chip_ver >= CHELSIO_T6) {
adap_config_hpfilter(adapter);
ret = setup_ppod_edram(adapter);
if (!ret)
@@ -4731,7 +4746,23 @@ static struct fw_info fw_info_array[] = {
.intfver_iscsi = FW_INTFVER(T6, ISCSI),
.intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
.intfver_fcoe = FW_INTFVER(T6, FCOE),
- },
+ },
+ }, {
+ .chip = CHELSIO_T7,
+ .fs_name = FW7_CFNAME,
+ .fw_mod_name = FW7_FNAME,
+ .fw_hdr = {
+ .chip = FW_HDR_CHIP_T7,
+ .fw_ver = __cpu_to_be32(FW_VERSION(T7)),
+ .intfver_nic = FW_INTFVER(T7, NIC),
+ .intfver_vnic = FW_INTFVER(T7, VNIC),
+ .intfver_ofld = FW_INTFVER(T7, OFLD),
+ .intfver_ri = FW_INTFVER(T7, RI),
+ .intfver_iscsipdu = FW_INTFVER(T7, ISCSIPDU),
+ .intfver_iscsi = FW_INTFVER(T7, ISCSI),
+ .intfver_fcoepdu = FW_INTFVER(T7, FCOEPDU),
+ .intfver_fcoe = FW_INTFVER(T7, FCOE),
+ },
}
};
@@ -4752,12 +4783,11 @@ static struct fw_info *find_fw_info(int chip)
*/
static int adap_init0(struct adapter *adap, int vpd_skip)
{
+ unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
struct fw_caps_config_cmd caps_cmd;
- u32 params[7], val[7];
+ u32 port_vec, v, params[7], val[7];
enum dev_state state;
- u32 v, port_vec;
- int reset = 1;
- int ret;
+ int ret, reset;
/* Grab Firmware Device Log parameters as early as possible so we have
* access to it for debugging, etc.
@@ -4766,14 +4796,10 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
if (ret < 0)
return ret;
- /* Contact FW, advertising Master capability */
- ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
- is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
- if (ret < 0) {
- dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
- ret);
+ ret = cxgb4_pci_fw_init(adap, &state);
+ if (ret < 0)
return ret;
- }
+
if (ret == adap->mbox)
adap->flags |= CXGB4_MASTER_PF;
@@ -4791,20 +4817,20 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
if (ret)
state = DEV_STATE_UNINIT;
if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
- struct fw_info *fw_info;
- struct fw_hdr *card_fw;
const struct firmware *fw;
const u8 *fw_data = NULL;
unsigned int fw_size = 0;
+ struct fw_info *fw_info;
+ struct fw_hdr *card_fw;
/* This is the firmware whose headers the driver was compiled
* against
*/
- fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
+ fw_info = find_fw_info(chip_ver);
if (fw_info == NULL) {
dev_err(adap->pdev_dev,
"unable to get firmware info for chip %d.\n",
- CHELSIO_CHIP_VERSION(adap->params.chip));
+ chip_ver);
return -EINVAL;
}
@@ -4958,7 +4984,7 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
if (!ret)
adap->flags |= CXGB4_SGE_DBQ_TIMER;
- if (is_bypass_device(adap->pdev->device))
+ if (is_bypass_device(cxgb4_pci_device_id(adap)))
adap->params.bypass = 1;
/*
@@ -5003,8 +5029,6 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
adap->rawf_cnt = val[1] - val[0] + 1;
}
- adap->tids.tid_base =
- t4_read_reg(adap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
}
/* qids (ingress/egress) returned from firmware can be anywhere
@@ -5021,14 +5045,21 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
- adap->sge.egr_map = kzalloc_objs(*adap->sge.egr_map, adap->sge.egr_sz);
+ adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
+ sizeof(*adap->sge.egr_map), GFP_KERNEL);
if (!adap->sge.egr_map) {
ret = -ENOMEM;
goto bye;
}
+ adap->sge.txq_maperr = bitmap_zalloc(adap->sge.egr_sz, GFP_KERNEL);
+ if (!adap->sge.txq_maperr) {
+ ret = -ENOMEM;
+ goto bye;
+ }
+
adap->sge.ingr_map = kzalloc_objs(*adap->sge.ingr_map,
- adap->sge.ingr_sz);
+ adap->sge.ingr_sz);
if (!adap->sge.ingr_map) {
ret = -ENOMEM;
goto bye;
@@ -5043,12 +5074,6 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
goto bye;
}
- adap->sge.txq_maperr = bitmap_zalloc(adap->sge.egr_sz, GFP_KERNEL);
- if (!adap->sge.txq_maperr) {
- ret = -ENOMEM;
- goto bye;
- }
-
#ifdef CONFIG_DEBUG_FS
adap->sge.blocked_fl = bitmap_zalloc(adap->sge.egr_sz, GFP_KERNEL);
if (!adap->sge.blocked_fl) {
@@ -5409,14 +5434,14 @@ static int adap_init0(struct adapter *adap, int vpd_skip)
bitmap_free(adap->sge.blocked_fl);
#endif
if (ret != -ETIMEDOUT && ret != -EIO)
- t4_fw_bye(adap, adap->mbox);
+ cxgb4_pci_fw_free(adap);
return ret;
}
/* EEH callbacks */
-static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
- pci_channel_state_t state)
+pci_ers_result_t cxgb4_pci_eeh_err_detected(struct pci_dev *pdev,
+ pci_channel_state_t state)
{
int i;
struct adapter *adap = pci_get_drvdata(pdev);
@@ -5448,7 +5473,7 @@ out: return state == pci_channel_io_perm_failure ?
PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
}
-static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
+pci_ers_result_t cxgb4_pci_eeh_slot_reset(struct pci_dev *pdev)
{
int i, ret;
struct fw_caps_config_cmd c;
@@ -5483,7 +5508,7 @@ static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
struct port_info *pi = adap2pinfo(adap, i);
u8 vivld = 0, vin = 0;
- ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
+ ret = t4_alloc_vi(adap, adap->mbox, pi->lport, adap->pf, 0, 1,
NULL, NULL, &vivld, &vin);
if (ret < 0)
return PCI_ERS_RESULT_DISCONNECT;
@@ -5504,13 +5529,13 @@ static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
adap->params.b_wnd);
- setup_memwin(adap);
+ cxgb4_pci_setup_memwin(adap);
if (cxgb_up(adap))
return PCI_ERS_RESULT_DISCONNECT;
return PCI_ERS_RESULT_RECOVERED;
}
-static void eeh_resume(struct pci_dev *pdev)
+void cxgb4_pci_eeh_resume(struct pci_dev *pdev)
{
int i;
struct adapter *adap = pci_get_drvdata(pdev);
@@ -5532,7 +5557,7 @@ static void eeh_resume(struct pci_dev *pdev)
rtnl_unlock();
}
-static void eeh_reset_prepare(struct pci_dev *pdev)
+void cxgb4_pci_eeh_reset_prepare(struct pci_dev *pdev)
{
struct adapter *adapter = pci_get_drvdata(pdev);
int i;
@@ -5557,7 +5582,7 @@ static void eeh_reset_prepare(struct pci_dev *pdev)
cxgb_down(adapter);
}
-static void eeh_reset_done(struct pci_dev *pdev)
+void cxgb4_pci_eeh_reset_done(struct pci_dev *pdev)
{
struct adapter *adapter = pci_get_drvdata(pdev);
int err, i;
@@ -5572,7 +5597,7 @@ static void eeh_reset_done(struct pci_dev *pdev)
return;
}
- setup_memwin(adapter);
+ cxgb4_pci_setup_memwin(adapter);
err = adap_init0(adapter, 1);
if (err) {
@@ -5581,7 +5606,7 @@ static void eeh_reset_done(struct pci_dev *pdev)
return;
}
- setup_memwin_rdma(adapter);
+ cxgb4_pci_setup_memwin_rdma(adapter);
if (adapter->flags & CXGB4_FW_OK) {
err = t4_port_init(adapter, adapter->pf, adapter->pf, 0);
@@ -5613,14 +5638,6 @@ static void eeh_reset_done(struct pci_dev *pdev)
cxgb_open(adapter->port[i]);
}
-static const struct pci_error_handlers cxgb4_eeh = {
- .error_detected = eeh_err_detected,
- .slot_reset = eeh_slot_reset,
- .resume = eeh_resume,
- .reset_prepare = eeh_reset_prepare,
- .reset_done = eeh_reset_done,
-};
-
/* Return true if the Link Configuration supports "High Speeds" (those greater
* than 1Gb/s).
*/
@@ -5751,6 +5768,17 @@ static int cfg_queues(struct adapter *adap)
s->ofldqsets = avail_uld_qsets;
}
+ /*
+ * 1. num_of_cores should not be less than one for tensilica
+ * 2. num of ofld queues per port should not be less than num cores
+ */
+
+ if (adap->params.tid_qid_sel_mask &&
+ s->ofldqsets <
+ adap->params.num_up_cores * adap->params.nports)
+ s->ofldqsets =
+ adap->params.num_up_cores * adap->params.nports;
+
avail_qsets -= num_ulds * s->ofldqsets;
}
@@ -5802,6 +5830,26 @@ static int cfg_queues(struct adapter *adap)
return 0;
}
+bool cxgb4_msix_enabled(struct adapter *adap)
+{
+ return cxgb4_pci_msix_enabled(adap);
+}
+
+bool cxgb4_msi_enabled(struct adapter *adap)
+{
+ return cxgb4_pci_msi_enabled(adap);
+}
+
+#ifdef CONFIG_CHELSIO_T4_OFFLOAD
+
+int cxgb4_filter_field_shift(const struct net_device *dev, int filter_sel)
+{
+ return t4_filter_field_shift(netdev2adap(dev), filter_sel);
+}
+EXPORT_SYMBOL(cxgb4_filter_field_shift);
+
+#endif /* CONFIG_CHELSIO_T4_OFFLOAD */
+
/*
* Reduce the number of Ethernet queues across all ports to at most n.
* n provides at least one queue per port.
@@ -5894,7 +5942,7 @@ static int enable_msix(struct adapter *adap)
{
u32 eth_need, uld_need = 0, ethofld_need = 0, mirror_need = 0;
u32 ethqsets = 0, ofldqsets = 0, eoqsets = 0, mirrorqsets = 0;
- u8 num_uld = 0, nchan = adap->params.nports;
+ u8 nchan = adap->params.nports;
u32 i, want, need, num_vec;
struct sge *s = &adap->sge;
struct msix_entry *entries;
@@ -5912,9 +5960,8 @@ static int enable_msix(struct adapter *adap)
#endif
eth_need = need;
if (is_uld(adap)) {
- num_uld = adap->num_ofld_uld + adap->num_uld;
- want += num_uld * s->ofldqsets;
- uld_need = num_uld * nchan;
+ want += s->ofldqsets;
+ uld_need = adap->params.num_up_cores * nchan;
need += uld_need;
}
@@ -5956,6 +6003,7 @@ static int enable_msix(struct adapter *adap)
goto out_free;
}
+ adap->flags |= CXGB4_USING_MSI;
dev_info(adap->pdev_dev,
"Disabling offload due to insufficient MSI-X vectors\n");
adap->params.offload = 0;
@@ -5967,6 +6015,8 @@ static int enable_msix(struct adapter *adap)
uld_need = 0;
ethofld_need = 0;
mirror_need = 0;
+ } else {
+ adap->flags |= CXGB4_USING_MSIX;
}
num_vec = allocated;
@@ -6066,16 +6116,24 @@ static int enable_msix(struct adapter *adap)
adap->msix_info[i].idx = i;
}
+ if (cxgb4_msix_enabled(adap))
+ dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, ",
+ allocated);
+ else if (cxgb4_msi_enabled(adap))
+ dev_info(adap->pdev_dev, "%d MSI vectors allocated, ",
+ allocated);
+ else
+ dev_info(adap->pdev_dev, "%d Legacy vectors allocated, ",
+ allocated);
+
dev_info(adap->pdev_dev,
- "%d MSI-X vectors allocated, nic %d eoqsets %d per uld %d mirrorqsets %d\n",
- allocated, s->max_ethqsets, s->eoqsets, s->nqs_per_uld,
- s->mirrorqsets);
+ "nic %d eoqsets %d per uld %d mirrorqsets %d\n",
+ s->max_ethqsets, s->eoqsets, s->nqs_per_uld, s->mirrorqsets);
- kfree(entries);
return 0;
out_disable_msix:
- pci_disable_msix(adap->pdev);
+ disable_msi(adap);
out_free:
kfree(entries);
@@ -6111,10 +6169,10 @@ static void print_adapter_info(struct adapter *adapter)
/* Software/Hardware configuration */
dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
- is_offload(adapter) ? "R" : "",
- ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
- (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
- is_offload(adapter) ? "Offload" : "non-Offload");
+ is_uld(adapter) ? "R" : "",
+ cxgb4_msix_enabled(adapter) ? "MSI-X" :
+ (cxgb4_msi_enabled(adapter) ? "MSI" : ""),
+ is_uld(adapter) ? "Offload" : "non-Offload");
}
static void print_port_info(const struct net_device *dev)
@@ -6190,7 +6248,7 @@ static void free_some_resources(struct adapter *adapter)
free_netdev(adapter->port[i]);
}
if (adapter->flags & CXGB4_FW_OK)
- t4_fw_bye(adapter, adapter->pf);
+ cxgb4_pci_fw_free(adapter);
}
#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN | \
@@ -6199,23 +6257,6 @@ static void free_some_resources(struct adapter *adapter)
NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
#define SEGMENT_SIZE 128
-static int t4_get_chip_type(struct adapter *adap, int ver)
-{
- u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
-
- switch (ver) {
- case CHELSIO_T4:
- return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
- case CHELSIO_T5:
- return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
- case CHELSIO_T6:
- return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
- default:
- break;
- }
- return -EINVAL;
-}
-
#ifdef CONFIG_PCI_IOV
static void cxgb4_mgmt_setup(struct net_device *dev)
{
@@ -6232,7 +6273,7 @@ static void cxgb4_mgmt_setup(struct net_device *dev)
dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
}
-static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
+int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
{
struct adapter *adap = pci_get_drvdata(pdev);
int err = 0;
@@ -6568,109 +6609,81 @@ static const struct xfrmdev_ops cxgb4_xfrmdev_ops = {
#endif /* CONFIG_CHELSIO_IPSEC_INLINE */
-static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+static int cxgb4_primary_pf(struct adapter *adapter)
+{
+ return adapter->primary_pf;
+}
+
+int cxgb4_is_primary_pf(struct adapter *adapter)
+{
+ return adapter->pf == cxgb4_primary_pf(adapter);
+}
+
+struct adapter *cxgb4_adap_alloc(struct device *dev)
+{
+ return devm_kzalloc(dev, sizeof(struct adapter), GFP_KERNEL);
+}
+
+int cxgb4_mbox_log_init(struct adapter *adap)
+{
+ adap->mbox_log =
+ kzalloc(sizeof(struct mbox_cmd_log) +
+ (sizeof(struct mbox_cmd) * T4_OS_LOG_MBOX_CMDS),
+ GFP_KERNEL);
+ if (!adap->mbox_log)
+ return -ENOMEM;
+
+ t4_os_lock_init(&adap->mbox_lock);
+ INIT_LIST_HEAD(&adap->mlist.list);
+ adap->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
+ return 0;
+}
+
+void cxgb4_mbox_log_free(struct adapter *adap)
+{
+ kfree(adap->mbox_log);
+}
+
+int cxgb4_adap_probe(struct adapter *adapter)
{
struct net_device *netdev;
- struct adapter *adapter;
static int adap_idx = 1;
- int s_qpp, qpp, num_seg;
struct port_info *pi;
- enum chip_type chip;
- void __iomem *regs;
- int func, chip_ver;
- u16 device_id;
+ int chip_ver;
int i, err;
- u32 whoami;
- err = pci_request_regions(pdev, KBUILD_MODNAME);
- if (err) {
- /* Just info, some other driver may have claimed the device. */
- dev_info(&pdev->dev, "cannot obtain PCI resources\n");
+ err = cxgb4_pci_resource_init(adapter);
+ if (err < 0)
return err;
- }
-
- err = pci_enable_device(pdev);
- if (err) {
- dev_err(&pdev->dev, "cannot enable PCI device\n");
- goto out_release_regions;
- }
-
- regs = pci_ioremap_bar(pdev, 0);
- if (!regs) {
- dev_err(&pdev->dev, "cannot map device registers\n");
- err = -ENOMEM;
- goto out_disable_device;
- }
- adapter = kzalloc_obj(*adapter);
- if (!adapter) {
- err = -ENOMEM;
- goto out_unmap_bar0;
- }
-
- adapter->regs = regs;
- err = t4_wait_dev_ready(regs);
+ err = t4_wait_dev_ready(adapter->regs);
if (err < 0)
- goto out_free_adapter;
-
- /* We control everything through one PF */
- whoami = t4_read_reg(adapter, PL_WHOAMI_A);
- pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
- chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
- if ((int)chip < 0) {
- dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
- err = chip;
- goto out_free_adapter;
- }
- chip_ver = CHELSIO_CHIP_VERSION(chip);
- func = chip_ver <= CHELSIO_T5 ?
- SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
+ goto out_free_resources;
- adapter->pdev = pdev;
- adapter->pdev_dev = &pdev->dev;
- adapter->name = pci_name(pdev);
- adapter->mbox = func;
- adapter->pf = func;
- adapter->params.chip = chip;
adapter->adap_idx = adap_idx;
- adapter->msg_enable = DFLT_MSG_ENABLE;
- adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
- (sizeof(struct mbox_cmd) *
- T4_OS_LOG_MBOX_CMDS),
- GFP_KERNEL);
- if (!adapter->mbox_log) {
- err = -ENOMEM;
- goto out_free_adapter;
- }
- spin_lock_init(&adapter->mbox_lock);
- INIT_LIST_HEAD(&adapter->mlist.list);
- adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
- pci_set_drvdata(pdev, adapter);
+ err = cxgb4_pci_chip_init(adapter);
+ if (err < 0)
+ goto out_free_resources;
- if (func != ent->driver_data) {
- pci_disable_device(pdev);
- pci_save_state(pdev); /* to restore SR-IOV later */
+ if (!cxgb4_is_primary_pf(adapter))
return 0;
- }
-
- err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
- if (err) {
- dev_err(&pdev->dev, "no usable DMA configuration\n");
- goto out_free_adapter;
- }
- pci_set_master(pdev);
- pci_save_state(pdev);
- adap_idx++;
- adapter->workq = create_singlethread_workqueue("cxgb4");
- if (!adapter->workq) {
- err = -ENOMEM;
- goto out_free_adapter;
- }
+ /* Everything from here down is now the Primary Physical Function!
+ */
+ chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
/* PCI device has been enabled */
adapter->flags |= CXGB4_DEV_ENABLED;
memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
+ adap_idx++;
+ /* Default message set for the interfaces. This can be changed later
+ * via "ethtool -s ethX msglvl N".
+ */
+ adapter->msg_enable = DFLT_MSG_ENABLE;
+
+ err = cxgb4_workqueues_create(adapter);
+ if (err < 0)
+ goto out_free_adapter;
/* If possible, we use PCIe Relaxed Ordering Attribute to deliver
* Ingress Packet Data to Free List Buffers in order to allow for
@@ -6686,7 +6699,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
* PCIe configuration space to see if it's flagged with advice against
* using Relaxed Ordering.
*/
- if (!pcie_relaxed_ordering_enabled(pdev))
+ if (!pcie_relaxed_ordering_enabled(adapter->pdev))
adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
spin_lock_init(&adapter->stats_lock);
@@ -6713,46 +6726,14 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
}
}
- if (!is_t4(adapter->params.chip)) {
- s_qpp = (QUEUESPERPAGEPF0_S +
- (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
- adapter->pf);
- qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
- SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
- num_seg = PAGE_SIZE / SEGMENT_SIZE;
-
- /* Each segment size is 128B. Write coalescing is enabled only
- * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
- * queue is less no of segments that can be accommodated in
- * a page size.
- */
- if (qpp > num_seg) {
- dev_err(&pdev->dev,
- "Incorrect number of egress queues per page\n");
- err = -EINVAL;
- goto out_free_adapter;
- }
- adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
- pci_resource_len(pdev, 2));
- if (!adapter->bar2) {
- dev_err(&pdev->dev, "cannot map device bar2 region\n");
- err = -ENOMEM;
- goto out_free_adapter;
- }
- }
-
- setup_memwin(adapter);
+ cxgb4_pci_setup_memwin(adapter);
err = adap_init0(adapter, 0);
if (err)
- goto out_unmap_bar;
-
- setup_memwin_rdma(adapter);
+ dev_err(adapter->pdev_dev,
+ "Adapter initialization failed, error %d. Continuing in debug mode\n",
+ -err);
- /* configure SGE_STAT_CFG_A to read WC stats */
- if (!is_t4(adapter->params.chip))
- t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
- (is_t5(adapter->params.chip) ? STATMODE_V(0) :
- T6_STATMODE_V(0)));
+ cxgb4_pci_setup_memwin_rdma(adapter);
/* Initialize hash mac addr list */
INIT_LIST_HEAD(&adapter->mac_hlist);
@@ -6765,20 +6746,20 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
* know the actual # of EOTIDs supported.
*/
netdev = alloc_etherdev_mq(sizeof(struct port_info),
- MAX_ETH_QSETS + MAX_ATIDS);
+ MAX_ETH_QSETS + CXGB4_MAX_ATIDS);
if (!netdev) {
err = -ENOMEM;
goto out_free_dev;
}
- SET_NETDEV_DEV(netdev, &pdev->dev);
+ SET_NETDEV_DEV(netdev, adapter->pdev_dev);
adapter->port[i] = netdev;
pi = netdev_priv(netdev);
pi->adapter = adapter;
pi->xact_addr_filt = -1;
pi->port_id = i;
- netdev->irq = pdev->irq;
+ netdev->irq = adapter->pdev->irq;
netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
@@ -6812,13 +6793,6 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
refcount_set(&pi->adapter->chcr_ktls.ktls_refcount, 0);
}
#endif /* CONFIG_CHELSIO_TLS_DEVICE */
-#if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE)
- if (pi->adapter->params.crypto & FW_CAPS_CONFIG_IPSEC_INLINE) {
- netdev->hw_enc_features |= NETIF_F_HW_ESP;
- netdev->features |= NETIF_F_HW_ESP;
- netdev->xfrmdev_ops = &cxgb4_xfrmdev_ops;
- }
-#endif /* CONFIG_CHELSIO_IPSEC_INLINE */
netdev->priv_flags |= IFF_UNICAST_FLT;
@@ -6837,10 +6811,8 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
cxgb4_init_ethtool_dump(adapter);
- pci_set_drvdata(pdev, adapter);
-
if (adapter->flags & CXGB4_FW_OK) {
- err = t4_port_init(adapter, func, func, 0);
+ err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
if (err)
goto out_free_dev;
} else if (adapter->params.nports == 1) {
@@ -6859,6 +6831,8 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
hex2val(na[2 * i + 1]));
t4_set_hw_addr(adapter, 0, hw_addr);
}
+
+ adapter->tids.tid_base = t4_read_reg(adapter, LE_DB_ACTIVE_TABLE_START_INDEX_A);
}
if (!(adapter->flags & CXGB4_FW_OK))
@@ -6874,13 +6848,13 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
adapter->smt = t4_init_smt();
if (!adapter->smt) {
/* We tolerate a lack of SMT, giving up some functionality */
- dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
+ dev_warn(adapter->pdev_dev, "could not allocate SMT, continuing\n");
}
adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
if (!adapter->l2t) {
/* We tolerate a lack of L2T, giving up some functionality */
- dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
+ dev_warn(adapter->pdev_dev, "could not allocate L2T, continuing\n");
adapter->params.offload = 0;
}
@@ -6890,9 +6864,8 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
/* CLIP functionality is not present in hardware,
* hence disable all offload features
*/
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"CLIP not enabled in hardware, continuing\n");
- adapter->params.offload = 0;
} else {
adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
adapter->clipt_end);
@@ -6900,9 +6873,8 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
/* We tolerate a lack of clip_table, giving up
* some functionality
*/
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not allocate Clip table, continuing\n");
- adapter->params.offload = 0;
}
}
#endif
@@ -6911,73 +6883,46 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
pi = adap2pinfo(adapter, i);
pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
if (!pi->sched_tbl)
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not activate scheduling on port %d\n",
i);
}
- if (is_offload(adapter) || is_hashfilter(adapter)) {
- if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
- u32 v;
-
- v = t4_read_reg(adapter, LE_DB_HASH_CONFIG_A);
- if (chip_ver <= CHELSIO_T5) {
- adapter->tids.nhash = 1 << HASHTIDSIZE_G(v);
- v = t4_read_reg(adapter, LE_DB_TID_HASHBASE_A);
- adapter->tids.hash_base = v / 4;
- } else {
- adapter->tids.nhash = HASHTBLSIZE_G(v) << 3;
- v = t4_read_reg(adapter,
- T6_LE_DB_HASH_TID_BASE_A);
- adapter->tids.hash_base = v;
- }
- }
- }
-
if (tid_init(&adapter->tids) < 0) {
- dev_warn(&pdev->dev, "could not allocate TID table, "
+ dev_warn(adapter->pdev_dev, "could not allocate TID table, "
"continuing\n");
adapter->params.offload = 0;
} else {
adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
if (!adapter->tc_u32)
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not offload tc u32, continuing\n");
if (cxgb4_init_tc_flower(adapter))
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not offload tc flower, continuing\n");
if (cxgb4_init_tc_mqprio(adapter))
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not offload tc mqprio, continuing\n");
if (cxgb4_init_tc_matchall(adapter))
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not offload tc matchall, continuing\n");
if (cxgb4_init_ethtool_filters(adapter))
- dev_warn(&pdev->dev,
+ dev_warn(adapter->pdev_dev,
"could not initialize ethtool filters, continuing\n");
}
- /* See what interrupts we'll be using */
- if (msi > 1 && enable_msix(adapter) == 0)
- adapter->flags |= CXGB4_USING_MSIX;
- else if (msi > 0 && pci_enable_msi(pdev) == 0) {
- adapter->flags |= CXGB4_USING_MSI;
- if (msi > 1)
- free_msix_info(adapter);
- }
-
- /* check for PCI Express bandwidth capabiltites */
- pcie_print_link_status(pdev);
-
- cxgb4_init_mps_ref_entries(adapter);
-
err = init_rss(adapter);
if (err)
goto out_free_dev;
+ /* See what interrupts we'll be using */
+ err = enable_msix(adapter);
+ if (err)
+ goto out_disable_interrupts;
+
err = setup_non_data_intr(adapter);
if (err) {
dev_err(adapter->pdev_dev,
@@ -6993,6 +6938,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
}
fw_attach_fail:
+ cxgb4_init_mps_ref_entries(adapter);
/*
* The card is now ready to go. If any errors occur during device
* registration we do not fail the whole card but rather proceed only
@@ -7010,26 +6956,40 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
err = register_netdev(adapter->port[i]);
if (err)
break;
- adapter->chan_map[pi->tx_chan] = i;
+
+ u8 idx, nchan;
+
+ switch (adapter->params.tp.lb_mode) {
+ case 1:
+ nchan = 4;
+ break;
+ case 2:
+ nchan = 2;
+ break;
+ default:
+ nchan = 1;
+ break;
+ }
+
+ for (idx = 0; idx < nchan; idx++)
+ adapter->chan_map[pi->lport * nchan + idx] = i;
print_port_info(adapter->port[i]);
}
if (i == 0) {
- dev_err(&pdev->dev, "could not register any net devices\n");
+ dev_err(adapter->pdev_dev, "could not register any net devices\n");
goto out_free_dev;
}
if (err) {
- dev_warn(&pdev->dev, "only %d net devices registered\n", i);
+ dev_warn(adapter->pdev_dev, "only %d net devices registered\n", i);
err = 0;
}
if (cxgb4_debugfs_root) {
- adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
- cxgb4_debugfs_root);
- setup_debugfs(adapter);
- }
+ const char *dir_name = pci_name(adapter->pdev);
- /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
- pdev->needs_freset = 1;
+ adapter->debugfs_root = debugfs_create_dir(dir_name, cxgb4_debugfs_root);
+ cxgb4_setup_debugfs(adapter);
+ }
if (is_uld(adapter))
cxgb4_uld_enable(adapter);
@@ -7044,40 +7004,31 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
print_adapter_info(adapter);
return 0;
- out_free_dev:
+out_disable_interrupts:
+ disable_msi(adapter);
+
+out_free_dev:
t4_free_sge_resources(adapter);
free_some_resources(adapter);
if (adapter->flags & CXGB4_USING_MSIX)
free_msix_info(adapter);
if (adapter->num_uld || adapter->num_ofld_uld)
t4_uld_mem_free(adapter);
- out_unmap_bar:
- if (!is_t4(adapter->params.chip))
- iounmap(adapter->bar2);
- out_free_adapter:
- if (adapter->workq)
- destroy_workqueue(adapter->workq);
-
- kfree(adapter->mbox_log);
- kfree(adapter);
- out_unmap_bar0:
- iounmap(regs);
- out_disable_device:
- pci_disable_device(pdev);
- out_release_regions:
- pci_release_regions(pdev);
+out_free_adapter:
+ cxgb4_workqueues_destroy(adapter);
+ cxgb4_pci_chip_free(adapter);
+
+out_free_resources:
+ cxgb4_pci_resource_free(adapter);
return err;
}
-static void remove_one(struct pci_dev *pdev)
+void cxgb4_adap_remove(struct adapter *adapter)
{
- struct adapter *adapter = pci_get_drvdata(pdev);
struct hash_mac_addr *entry, *tmp;
- if (!adapter) {
- pci_release_regions(pdev);
+ if (!adapter)
return;
- }
/* If we allocated filters, free up state associated with any
* valid filters ...
@@ -7086,26 +7037,26 @@ static void remove_one(struct pci_dev *pdev)
adapter->flags |= CXGB4_SHUTTING_DOWN;
- if (adapter->pf == 4) {
+ if (cxgb4_is_primary_pf(adapter)) {
int i;
/* Tear down per-adapter Work Queue first since it can contain
* references to our adapter data structure.
*/
- destroy_workqueue(adapter->workq);
+ cxgb4_workqueues_destroy(adapter);
- detach_ulds(adapter);
+ if (is_uld(adapter)) {
+ if (!list_empty(&adapter->list_node))
+ detach_ulds(adapter);
+ t4_uld_clean_up(adapter);
+ }
+ adap_free_hma_mem(adapter);
+ disable_interrupts(adapter);
for_each_port(adapter, i)
if (adapter->port[i]->reg_state == NETREG_REGISTERED)
unregister_netdev(adapter->port[i]);
- t4_uld_clean_up(adapter);
-
- adap_free_hma_mem(adapter);
-
- disable_interrupts(adapter);
-
cxgb4_free_mps_ref_entries(adapter);
debugfs_remove_recursive(adapter->debugfs_root);
@@ -7122,6 +7073,7 @@ static void remove_one(struct pci_dev *pdev)
free_msix_info(adapter);
if (adapter->num_uld || adapter->num_ofld_uld)
t4_uld_mem_free(adapter);
+
free_some_resources(adapter);
list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
list) {
@@ -7132,23 +7084,16 @@ static void remove_one(struct pci_dev *pdev)
#if IS_ENABLED(CONFIG_IPV6)
t4_cleanup_clip_tbl(adapter);
#endif
- if (!is_t4(adapter->params.chip))
- iounmap(adapter->bar2);
}
#ifdef CONFIG_PCI_IOV
else {
- cxgb4_iov_configure(adapter->pdev, 0);
+ cxgb4_pci_iov_configure(adapter, 0);
}
#endif
- iounmap(adapter->regs);
- if ((adapter->flags & CXGB4_DEV_ENABLED)) {
- pci_disable_device(pdev);
- adapter->flags &= ~CXGB4_DEV_ENABLED;
- }
- pci_release_regions(pdev);
- kfree(adapter->mbox_log);
+ cxgb4_pci_chip_free(adapter);
+ cxgb4_pci_resource_free(adapter);
+ adapter->flags &= ~CXGB4_DEV_ENABLED;
synchronize_rcu();
- kfree(adapter);
}
/* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
@@ -7156,22 +7101,18 @@ static void remove_one(struct pci_dev *pdev)
* function where we do the minimal amount of work necessary to shutdown any
* further activity.
*/
-static void shutdown_one(struct pci_dev *pdev)
+void cxgb4_adap_shutdown(struct adapter *adapter)
{
- struct adapter *adapter = pci_get_drvdata(pdev);
-
/* As with remove_one() above (see extended comment), we only want do
* do cleanup on PCI Devices which went all the way through init_one()
* ...
*/
- if (!adapter) {
- pci_release_regions(pdev);
+ if (!adapter)
return;
- }
adapter->flags |= CXGB4_SHUTTING_DOWN;
- if (adapter->pf == 4) {
+ if (cxgb4_is_primary_pf(adapter)) {
int i;
for_each_port(adapter, i)
@@ -7192,37 +7133,25 @@ static void shutdown_one(struct pci_dev *pdev)
t4_sge_stop(adapter);
if (adapter->flags & CXGB4_FW_OK)
- t4_fw_bye(adapter, adapter->mbox);
+ cxgb4_pci_fw_free(adapter);
}
}
-static struct pci_driver cxgb4_driver = {
- .name = KBUILD_MODNAME,
- .id_table = cxgb4_pci_tbl,
- .probe = init_one,
- .remove = remove_one,
- .shutdown = shutdown_one,
-#ifdef CONFIG_PCI_IOV
- .sriov_configure = cxgb4_iov_configure,
-#endif
- .err_handler = &cxgb4_eeh,
-};
-
static int __init cxgb4_init_module(void)
{
int ret;
cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
- ret = pci_register_driver(&cxgb4_driver);
+ ret = cxgb4_pci_driver_register();
if (ret < 0)
- goto err_pci;
+ goto out_err;
#if IS_ENABLED(CONFIG_IPV6)
if (!inet6addr_registered) {
ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
if (ret)
- pci_unregister_driver(&cxgb4_driver);
+ cxgb4_pci_driver_unregister();
else
inet6addr_registered = true;
}
@@ -7230,10 +7159,8 @@ static int __init cxgb4_init_module(void)
if (ret == 0)
return ret;
-
-err_pci:
+out_err:
debugfs_remove(cxgb4_debugfs_root);
-
return ret;
}
@@ -7245,7 +7172,7 @@ static void __exit cxgb4_cleanup_module(void)
inet6addr_registered = false;
}
#endif
- pci_unregister_driver(&cxgb4_driver);
+ cxgb4_pci_driver_unregister();
debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
}
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c
index 94c8ce39310b..ef514fe53b95 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c
@@ -28,6 +28,28 @@ static int cxgb4_mps_ref_dec_by_mac(struct adapter *adap,
return ret;
}
+static int cxgb4_mps_ref_dec(struct adapter *adap, u16 idx)
+{
+ struct mps_entries_ref *mps_entry, *tmp;
+ int ret = -EINVAL;
+
+ spin_lock(&adap->mps_ref_lock);
+ list_for_each_entry_safe(mps_entry, tmp, &adap->mps_ref, list) {
+ if (mps_entry->idx == idx) {
+ if (!refcount_dec_and_test(&mps_entry->refcnt)) {
+ spin_unlock(&adap->mps_ref_lock);
+ return -EBUSY;
+ }
+ list_del(&mps_entry->list);
+ kfree(mps_entry);
+ ret = 0;
+ break;
+ }
+ }
+ spin_unlock(&adap->mps_ref_lock);
+ return ret;
+}
+
static int cxgb4_mps_ref_inc(struct adapter *adap, const u8 *mac_addr,
u16 idx, const u8 *mask)
{
@@ -119,6 +141,36 @@ int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
return ret;
}
+int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
+ int idx, bool sleep_ok)
+{
+ int ret = 0;
+
+ if (!cxgb4_mps_ref_dec(adap, idx))
+ ret = t4_free_encap_mac_filt(adap, viid, idx, sleep_ok);
+
+ return ret;
+}
+
+int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
+ const u8 *addr, const u8 *mask,
+ unsigned int vni, unsigned int vni_mask,
+ u8 dip_hit, u8 lookup_type, bool sleep_ok)
+{
+ int ret;
+
+ ret = t4_alloc_encap_mac_filt(adap, viid, addr, mask, vni, vni_mask,
+ dip_hit, lookup_type, sleep_ok);
+ if (ret < 0)
+ return ret;
+
+ if (cxgb4_mps_ref_inc(adap, addr, ret, mask)) {
+ ret = -ENOMEM;
+ t4_free_encap_mac_filt(adap, viid, ret, sleep_ok);
+ }
+ return ret;
+}
+
int cxgb4_init_mps_ref_entries(struct adapter *adap)
{
spin_lock_init(&adap->mps_ref_lock);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
index cbd06d9b95d4..6b19b439ad92 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
@@ -103,12 +103,14 @@ void cxgb4_ptp_read_hwstamp(struct adapter *adapter, struct port_info *pi)
skb_ts = skb_hwtstamps(adapter->ptp_tx_skb);
- tx_ts = t4_read_reg(adapter,
- T5_PORT_REG(pi->port_id, MAC_PORT_TX_TS_VAL_LO));
-
- tx_ts |= (u64)t4_read_reg(adapter,
- T5_PORT_REG(pi->port_id,
- MAC_PORT_TX_TS_VAL_HI)) << 32;
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T7)
+ tx_ts = t4_read_reg64(adapter,
+ T7_PORT_REG(pi->port_id,
+ T7_MAC_PORT_TX_TS_VAL_LO));
+ else
+ tx_ts = t4_read_reg64(adapter,
+ T5_PORT_REG(pi->port_id,
+ MAC_PORT_TX_TS_VAL_LO));
skb_ts->hwtstamp = ns_to_ktime(tx_ts);
skb_tstamp_tx(adapter->ptp_tx_skb, skb_ts);
dev_kfree_skb_any(adapter->ptp_tx_skb);
@@ -319,9 +321,12 @@ static int cxgb4_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
ptp_clock_info);
u64 ns;
- ns = t4_read_reg(adapter, T5_PORT_REG(0, MAC_PORT_PTP_SUM_LO_A));
- ns |= (u64)t4_read_reg(adapter,
- T5_PORT_REG(0, MAC_PORT_PTP_SUM_HI_A)) << 32;
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T7)
+ ns = t4_read_reg64(adapter,
+ T7_PORT_REG(0, MAC_PORT_PTP_SUM_LO_A));
+ else
+ ns = t4_read_reg64(adapter,
+ T5_PORT_REG(0, MAC_PORT_PTP_SUM_LO_A));
/* convert to timespec*/
*ts = ns_to_timespec64(ns);
@@ -432,7 +437,7 @@ void cxgb4_ptp_init(struct adapter *adapter)
spin_lock_init(&adapter->ptp_lock);
adapter->ptp_clock = ptp_clock_register(&adapter->ptp_clock_info,
- &adapter->pdev->dev);
+ adapter->pdev_dev);
if (IS_ERR_OR_NULL(adapter->ptp_clock)) {
adapter->ptp_clock = NULL;
dev_err(adapter->pdev_dev,
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next v1 09/10] cxgb4: Update debugfs interface for T7 versioned structures
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
` (7 preceding siblings ...)
2026-06-07 3:52 ` [PATCH net-next v1 08/10] cxgb4: Update driver lifecycle and peripherals for T7 Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 10/10] cxgb4: Update SGE path and filtering logic for T7 Potnuri Bharat Teja
2026-06-08 21:13 ` [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Jakub Kicinski
10 siblings, 0 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Update the debugfs diagnostic interface to support the versioned layouts
and multi-core telemetry requirements of T7 adapters.
Integrate T7-specific data structures into the active debug parsers:
- Refactor the CIM LA display logic to correctly decode and format the
struct_cim_la_rev1 layout.
- Update the SGE context output routines to process the expanded
struct_sge_ctxt_rev1 definition.
- Upgrade the CIM QCFG interface to interpret the data blocks emitted
by the cim_qcfg_rev1 versioned specification.
- Add a debugfs_multicore tracking array to dynamically provision
isolated per-core debugfs subdirectories across the architecture.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../ethernet/chelsio/cxgb4/cxgb4_debugfs.c | 1048 ++++++++++++-----
.../ethernet/chelsio/cxgb4/cxgb4_debugfs.h | 16 +-
2 files changed, 783 insertions(+), 281 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
index f521737d1275..9ee986303e47 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
@@ -196,21 +196,22 @@ static int cim_la_show_pc_t6(struct seq_file *seq, void *v, int idx)
static int cim_la_open(struct inode *inode, struct file *file)
{
- int ret;
- unsigned int cfg;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
+ u8 coreid = d->coreid;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
+ unsigned int cfg;
+ int ret;
- ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
+ ret = t4_cim_read_core(adap, 1, coreid, UP_UP_DBG_LA_CFG_A, 1, &cfg);
if (ret)
return ret;
- if (is_t6(adap->params.chip)) {
- /* +1 to account for integer division of CIMLA_SIZE/10 */
- p = seq_open_tab(file, (adap->params.cim_la_size / 10) + 1,
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T6) {
+ p = seq_open_tab(file, adap->params.cim_la_size / 10,
10 * sizeof(u32), 1,
cfg & UPDBGLACAPTPCONLY_F ?
- cim_la_show_pc_t6 : cim_la_show_t6);
+ cim_la_show_pc_t6 : cim_la_show_t6);
} else {
p = seq_open_tab(file, adap->params.cim_la_size / 8,
8 * sizeof(u32), 1,
@@ -220,7 +221,7 @@ static int cim_la_open(struct inode *inode, struct file *file)
if (!p)
return -ENOMEM;
- ret = t4_cim_read_la(adap, (u32 *)p->data, NULL);
+ ret = t4_cim_read_la_core(adap, coreid, (u32 *)p->data, NULL);
if (ret)
seq_release_private(inode, file);
return ret;
@@ -256,8 +257,9 @@ static int cim_pif_la_show(struct seq_file *seq, void *v, int idx)
static int cim_pif_la_open(struct inode *inode, struct file *file)
{
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
p = seq_open_tab(file, 2 * CIM_PIFLA_SIZE, 6 * sizeof(u32), 1,
cim_pif_la_show);
@@ -302,8 +304,9 @@ static int cim_ma_la_show(struct seq_file *seq, void *v, int idx)
static int cim_ma_la_open(struct inode *inode, struct file *file)
{
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
p = seq_open_tab(file, 2 * CIM_MALA_SIZE, 5 * sizeof(u32), 1,
cim_ma_la_show);
@@ -323,8 +326,112 @@ static const struct file_operations cim_ma_la_fops = {
.release = seq_release_private
};
+static int cim_qcfg_show_t7(struct seq_file *seq, struct adapter *adap,
+ u8 coreid)
+{
+ static const char *const qname_t7[] = {
+ /* IBQ */
+ "TP0",
+ "TP1",
+ "TP2",
+ "TP3",
+ "ULP",
+ "SGE0",
+ "SGE1",
+ "NC-SI",
+ "RSVD",
+ "IPC1",
+ "IPC2",
+ "IPC3",
+ "IPC4",
+ "IPC5",
+ "IPC6",
+ "IPC7",
+ /* OBQ */
+ "ULP0",
+ "ULP1",
+ "ULP2",
+ "ULP3",
+ "SGE",
+ "NC-SI",
+ "SGE0-RX",
+ "RSVD",
+ "RSVD",
+ "IPC1",
+ "IPC2",
+ "IPC3",
+ "IPC4",
+ "IPC5",
+ "IPC6",
+ "IPC7",
+ };
+ u32 stat[(4 * (CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7))];
+ u16 base[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+ u16 size[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+ u32 obq_wr[2 * CIM_NUM_OBQ_T7];
+ u16 thres[CIM_NUM_IBQ_T7];
+ u32 *wr = obq_wr;
+ u32 *p = stat;
+ u32 addr;
+ int ret;
+ u8 i;
+
+ ret = t4_cim_read_core(adap, 1, coreid, T7_UP_IBQ_0_SHADOW_RDADDR_A,
+ 4 * CIM_NUM_IBQ_T7, stat);
+ if (ret < 0)
+ return ret;
+
+ ret = t4_cim_read_core(adap, 1, coreid, T7_UP_OBQ_0_SHADOW_RDADDR_A,
+ 4 * CIM_NUM_OBQ_T7, &stat[4 * CIM_NUM_IBQ_T7]);
+ if (ret < 0)
+ return ret;
+
+ addr = T7_UP_OBQ_0_SHADOW_REALADDR_A;
+ for (i = 0; i < CIM_NUM_OBQ_T7 * 2; i++, addr += 8) {
+ ret = t4_cim_read_core(adap, 1, coreid, addr, 1, &obq_wr[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ t4_read_cimq_cfg_core(adap, coreid, base, size, thres);
+
+ seq_printf(seq,
+ " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail\n");
+
+ for (i = 0; i < CIM_NUM_IBQ_T7; i++, p += 4) {
+ if (!size[i])
+ continue;
+
+ seq_printf(seq, "%7s %5x %5u %5u %6x %4x %4u %4u %5u\n",
+ qname_t7[i], base[i], size[i], thres[i],
+ IBQRDADDR_G(p[0]) & 0xfff, IBQWRADDR_G(p[1]) & 0xfff,
+ QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
+ T7_QUEREMFLITS_G(p[2]) * 16);
+ }
+
+ for ( ; i < CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7; i++, p += 4, wr += 2) {
+ if (!size[i])
+ continue;
+
+ seq_printf(seq, "%7s %5x %5u %12x %4x %4u %4u %5u\n",
+ qname_t7[i], base[i], size[i],
+ QUERDADDR_G(p[0]) & 0xfff, (wr[0] << 1),
+ QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
+ T7_QUEREMFLITS_G(p[2]) * 16);
+ }
+
+ return 0;
+}
+
static int cim_qcfg_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ u8 coreid = d->coreid;
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ return cim_qcfg_show_t7(seq, adap, coreid);
+
static const char * const qname[] = {
"TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",
"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",
@@ -332,7 +439,6 @@ static int cim_qcfg_show(struct seq_file *seq, void *v)
};
int i;
- struct adapter *adap = seq->private;
u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
u32 stat[(4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5))];
@@ -391,16 +497,19 @@ static int cimq_show(struct seq_file *seq, void *v, int idx)
static int cim_ibq_open(struct inode *inode, struct file *file)
{
- int ret;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
+ unsigned int qid = d->data;
+ u8 coreid = d->coreid;
struct seq_tab *p;
- unsigned int qid = (uintptr_t)inode->i_private & 7;
- struct adapter *adap = inode->i_private - qid;
+ int ret;
p = seq_open_tab(file, CIM_IBQ_SIZE, 4 * sizeof(u32), 0, cimq_show);
if (!p)
return -ENOMEM;
- ret = t4_read_cim_ibq(adap, qid, (u32 *)p->data, CIM_IBQ_SIZE * 4);
+ ret = t4_read_cim_ibq_core(adap, coreid, qid, (u32 *)p->data,
+ CIM_IBQ_SIZE * 4);
if (ret < 0)
seq_release_private(inode, file);
else
@@ -418,16 +527,19 @@ static const struct file_operations cim_ibq_fops = {
static int cim_obq_open(struct inode *inode, struct file *file)
{
- int ret;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
+ unsigned int qid = d->data;
+ u8 coreid = d->coreid;
struct seq_tab *p;
- unsigned int qid = (uintptr_t)inode->i_private & 7;
- struct adapter *adap = inode->i_private - qid;
+ int ret;
p = seq_open_tab(file, 6 * CIM_OBQ_SIZE, 4 * sizeof(u32), 0, cimq_show);
if (!p)
return -ENOMEM;
- ret = t4_read_cim_obq(adap, qid, (u32 *)p->data, 6 * CIM_OBQ_SIZE * 4);
+ ret = t4_read_cim_obq_core(adap, coreid, qid, (u32 *)p->data,
+ 6 * CIM_OBQ_SIZE * 4);
if (ret < 0) {
seq_release_private(inode, file);
} else {
@@ -638,8 +750,9 @@ static int tp_la_show3(struct seq_file *seq, void *v, int idx)
static int tp_la_open(struct inode *inode, struct file *file)
{
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
switch (DBGLAMODE_G(t4_read_reg(adap, TP_DBG_LA_CONFIG_A))) {
case 2:
@@ -663,11 +776,14 @@ static int tp_la_open(struct inode *inode, struct file *file)
static ssize_t tp_la_write(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- int err;
- char s[32];
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
unsigned long val;
- size_t size = min(sizeof(s) - 1, count);
- struct adapter *adap = file_inode(file)->i_private;
+ size_t size;
+ char s[32];
+ int err;
+
+ size = min(sizeof(s) - 1, count);
if (copy_from_user(s, buf, size))
return -EFAULT;
@@ -707,8 +823,9 @@ static int ulprx_la_show(struct seq_file *seq, void *v, int idx)
static int ulprx_la_open(struct inode *inode, struct file *file)
{
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
- struct adapter *adap = inode->i_private;
p = seq_open_tab(file, ULPRX_LA_SIZE, 8 * sizeof(u32), 1,
ulprx_la_show);
@@ -748,10 +865,11 @@ static int pm_stats_show(struct seq_file *seq, void *v)
"Read:", "Write bypass:", "Write mem:", "Flush:"
};
- int i;
u32 tx_cnt[T6_PM_NSTATS], rx_cnt[T6_PM_NSTATS];
u64 tx_cyc[T6_PM_NSTATS], rx_cyc[T6_PM_NSTATS];
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ int i;
t4_pmtx_get_stats(adap, tx_cnt, tx_cyc);
t4_pmrx_get_stats(adap, rx_cnt, rx_cyc);
@@ -771,12 +889,12 @@ static int pm_stats_show(struct seq_file *seq, void *v)
* It is not useful as it reaches the max value too fast.
* Hence display this Input FIFO wait for T6 onwards.
*/
- seq_printf(seq, "%13s %10s %20s\n",
- " ", "Total wait", "Total Occupancy");
+ seq_printf(seq, "%13s %10s %20s\n", " ", "Total wait",
+ "Total Occupancy");
seq_printf(seq, "Tx FIFO wait %10u %20llu\n",
tx_cnt[i], tx_cyc[i]);
- seq_printf(seq, "Rx FIFO wait %10u %20llu\n",
- rx_cnt[i], rx_cyc[i]);
+ seq_printf(seq, "Rx FIFO wait %10u %20llu\n", rx_cnt[i],
+ rx_cyc[i]);
/* Skip index 6 as there is nothing useful ihere */
i += 2;
@@ -784,12 +902,67 @@ static int pm_stats_show(struct seq_file *seq, void *v)
/* At index 7, a new stat for read latency (count, total wait)
* is added.
*/
- seq_printf(seq, "%13s %10s %20s\n",
- " ", "Reads", "Total wait");
- seq_printf(seq, "Tx latency %10u %20llu\n",
- tx_cnt[i], tx_cyc[i]);
- seq_printf(seq, "Rx latency %10u %20llu\n",
- rx_cnt[i], rx_cyc[i]);
+ seq_printf(seq, "%13s %10s %20s\n", " ", "Reads",
+ "Total wait");
+ seq_printf(seq, "Tx latency %10u %20llu\n", tx_cnt[i],
+ tx_cyc[i]);
+ seq_printf(seq, "Rx latency %10u %20llu\n", rx_cnt[i],
+ rx_cyc[i]);
+ }
+
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7) {
+ u32 stats[T7_PM_RX_CACHE_NSTATS];
+
+ t4_pmrx_cache_get_stats(adap, stats);
+
+ i = 0;
+ seq_puts(seq, "\n\nPM RX Cache Stats\n");
+ seq_printf(seq, "%-40s %u\n", "ReqWrite", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "ReqReadInv", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "ReqReadNoInv", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Split Request",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Normal Read Split (Read Invalidate)", stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Feedback Read Split (Read NoInvalidate)",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Hit", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Normal Read Hit", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Feedback Read Hit",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Normal Read Hit Full Avail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Normal Read Hit Full UnAvail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Normal Read Hit Partial Avail", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "FB Read Hit Full Avail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "FB Read Hit Full UnAvail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "FB Read Hit Partial Avail",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Normal Read Full Free",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Normal Read Part-avail Mul-Regions", stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "FB Read Part-avail Mul-Regions", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Miss FL Used",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Miss LRU Used",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Write Miss LRU-Multiple Evict", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Hit Increasing Islands",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n",
+ "Normal Read Island Read split", stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Write Overflow Eviction",
+ stats[i++]);
+ seq_printf(seq, "%-40s %u\n", "Read Overflow Eviction",
+ stats[i++]);
}
return 0;
}
@@ -802,7 +975,8 @@ static int pm_stats_open(struct inode *inode, struct file *file)
static ssize_t pm_stats_clear(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- struct adapter *adap = file_inode(file)->i_private;
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0);
t4_write_reg(adap, PM_TX_STAT_CONFIG_A, 0);
@@ -820,8 +994,9 @@ static const struct file_operations pm_stats_debugfs_fops = {
static int tx_rate_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
u64 nrate[NCHAN], orate[NCHAN];
- struct adapter *adap = seq->private;
t4_get_chan_txrate(adap, nrate, orate);
if (adap->params.arch.nchan == NCHAN) {
@@ -856,9 +1031,10 @@ static int cctrl_tbl_show(struct seq_file *seq, void *v)
"0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
"0.9375" };
- int i;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
u16 (*incr)[NCCTRL_WIN];
- struct adapter *adap = seq->private;
+ int i;
incr = kmalloc_objs(*incr, NMTUS);
if (!incr)
@@ -902,13 +1078,16 @@ static char *unit_conv(char *buf, size_t len, unsigned int val,
static int clk_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
+ unsigned int cclk_ps, tre, dack_re, res;
+ struct adapter *adap = d->adap;
+ unsigned long long tp_tick_us;
char buf[32];
- struct adapter *adap = seq->private;
- unsigned int cclk_ps = 1000000000 / adap->params.vpd.cclk; /* in ps */
- u32 res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
- unsigned int tre = TIMERRESOLUTION_G(res);
- unsigned int dack_re = DELAYEDACKRESOLUTION_G(res);
- unsigned long long tp_tick_us = (cclk_ps << tre) / 1000000; /* in us */
+ cclk_ps = 1000000000 / adap->params.vpd.cclk; /* in ps */
+ res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
+ tre = TIMERRESOLUTION_G(res);
+ dack_re = DELAYEDACKRESOLUTION_G(res);
+ tp_tick_us = (cclk_ps << tre) / 1000000; /* in us */
seq_printf(seq, "Core clock period: %s ns\n",
unit_conv(buf, sizeof(buf), cclk_ps, 1000));
@@ -1080,13 +1259,17 @@ static const struct seq_operations devlog_seq_ops = {
*/
static int devlog_open(struct inode *inode, struct file *file)
{
- struct adapter *adap = inode->i_private;
- struct devlog_params *dparams = &adap->params.devlog;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
+ struct devlog_params *dparams;
struct devlog_info *dinfo;
+ u8 coreid = d->coreid;
unsigned int index;
u32 fseqno;
int ret;
+ dparams = &adap->params.devlog[coreid];
+
/* If we don't know where the log is we can't do anything.
*/
if (dparams->start == 0)
@@ -1153,11 +1336,13 @@ static const struct file_operations devlog_fops = {
*/
static int mboxlog_show(struct seq_file *seq, void *v)
{
- struct adapter *adapter = seq->private;
- struct mbox_cmd_log *log = adapter->mbox_log;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ struct mbox_cmd_log *log;
struct mbox_cmd *entry;
int entry_idx, i;
+ log = adap->mbox_log;
if (v == SEQ_START_TOKEN) {
seq_printf(seq,
"%10s %15s %5s %5s %s\n",
@@ -1191,10 +1376,11 @@ static int mboxlog_show(struct seq_file *seq, void *v)
static inline void *mboxlog_get_idx(struct seq_file *seq, loff_t pos)
{
- struct adapter *adapter = seq->private;
- struct mbox_cmd_log *log = adapter->mbox_log;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
- return ((pos <= log->size) ? (void *)(uintptr_t)(pos + 1) : NULL);
+ return ((pos <= adap->mbox_log->size) ?
+ (void *)(uintptr_t)(pos + 1) : NULL);
}
static void *mboxlog_start(struct seq_file *seq, loff_t *pos)
@@ -1241,14 +1427,16 @@ static const struct file_operations mboxlog_fops = {
static int mbox_show(struct seq_file *seq, void *v)
{
- static const char * const owner[] = { "none", "FW", "driver",
- "unknown", "<unread>" };
-
+ static const char * const owner[] = {
+ "none", "FW", "driver", "FW Deferred", "<unread>"
+ };
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ unsigned int mbox = d->data;
+ void __iomem *addr;
int i;
- unsigned int mbox = (uintptr_t)seq->private & 7;
- struct adapter *adap = seq->private - mbox;
- void __iomem *addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
+ addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
/* For T4 we don't have a shadow copy of the Mailbox Control register.
* And since reading that real register causes a side effect of
* granting ownership, we're best of simply not reading it at all.
@@ -1278,14 +1466,14 @@ static int mbox_open(struct inode *inode, struct file *file)
static ssize_t mbox_write(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- int i;
- char c = '\n', s[256];
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
+ unsigned int mbox = d->data;
unsigned long long data[8];
- const struct inode *ino;
- unsigned int mbox;
- struct adapter *adap;
+ char s[256], c = '\n';
void __iomem *addr;
void __iomem *ctrl;
+ int i;
if (count > sizeof(s) - 1 || !count)
return -EINVAL;
@@ -1298,19 +1486,16 @@ static ssize_t mbox_write(struct file *file, const char __user *buf,
&data[7], &c) < 8 || c != '\n')
return -EINVAL;
- ino = file_inode(file);
- mbox = (uintptr_t)ino->i_private & 7;
- adap = ino->i_private - mbox;
addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
ctrl = addr + MBOX_LEN;
- if (MBOWNER_G(readl(ctrl)) != X_MBOWNER_PL)
+ if (MBOWNER_G(readl(ctrl)) != MBOWNER_PL_X)
return -EBUSY;
for (i = 0; i < 8; i++)
writeq(data[i], addr + 8 * i);
- writel(MBMSGVALID_F | MBOWNER_V(X_MBOWNER_FW), ctrl);
+ writel(MBMSGVALID_F | MBOWNER_V(MBOWNER_FW_X), ctrl);
return count;
}
@@ -1411,18 +1596,13 @@ static unsigned int xdigit2int(unsigned char c)
static ssize_t mps_trc_write(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- int i, enable, ret;
- u32 *data, *mask;
- struct trace_params tp;
- const struct inode *ino;
- unsigned int trcidx;
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
+ unsigned int trcidx = d->data;
char *s, *p, *word, *end;
- struct adapter *adap;
- u32 j;
-
- ino = file_inode(file);
- trcidx = (uintptr_t)ino->i_private & 3;
- adap = ino->i_private - trcidx;
+ struct trace_params tp;
+ int i, enable, ret;
+ u32 *data, *mask, j;
/* Don't accept input more than 1K, can't be anything valid except lots
* of whitespace. Well, use less.
@@ -1619,9 +1799,10 @@ static const struct file_operations mps_trc_debugfs_fops = {
static ssize_t flash_read(struct file *file, char __user *buf, size_t count,
loff_t *ppos)
{
- loff_t pos = *ppos;
+ struct t4_linux_debugfs_data *d = file->private_data;
loff_t avail = file_inode(file)->i_size;
- struct adapter *adap = file->private_data;
+ struct adapter *adap = d->adap;
+ loff_t pos = *ppos;
if (pos < 0)
return -EINVAL;
@@ -1671,8 +1852,11 @@ static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
static int mps_tcam_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
- unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ unsigned int chip_ver;
+
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
if (v == SEQ_START_TOKEN) {
if (chip_ver > CHELSIO_T5) {
seq_puts(seq, "Idx Ethernet address Mask "
@@ -1683,27 +1867,91 @@ static int mps_tcam_show(struct seq_file *seq, void *v)
" P0 P1 P2 P3 ML\n");
} else {
if (adap->params.arch.mps_rplc_size > 128)
- seq_puts(seq, "Idx Ethernet address Mask "
+ seq_puts(seq,
+ "Idx Ethernet address Mask "
"Vld Ports PF VF "
"Replication "
" P0 P1 P2 P3 ML\n");
else
- seq_puts(seq, "Idx Ethernet address Mask "
+ seq_puts(seq,
+ "Idx Ethernet address Mask "
"Vld Ports PF VF Replication"
" P0 P1 P2 P3 ML\n");
}
} else {
- u64 mask;
- u8 addr[ETH_ALEN];
+ u32 cls_lo, cls_hi, ctl, data2, vnix = 0, vniy = 0;
bool replicate, dip_hit = false, vlan_vld = false;
unsigned int idx = (uintptr_t)v - 2;
+ u8 lookup_type = 0, port_num = 0;
u64 tcamy, tcamx, val;
- u32 cls_lo, cls_hi, ctl, data2, vnix = 0, vniy = 0;
+ u8 addr[ETH_ALEN];
u32 rplc[8] = {0};
- u8 lookup_type = 0, port_num = 0;
u16 ivlan = 0;
+ u64 mask;
- if (chip_ver > CHELSIO_T5) {
+ if (chip_ver >= CHELSIO_T7) {
+ /* CtlReqID - 1: use Host Driver Requester ID
+ * CtlCmdType - 0: Read, 1: Write
+ * CtlXYBitSel- 0: Y bit, 1: X bit
+ ####### for T6 ######
+ * CtlTcamSel - 26:25 Control bit. 0: TCAM0, 1: TCAM1
+ * CtlTcamIndex - 24:17 Control bits. Index of TCAM location to be accessed
+ ####### for T7B ######
+ * CtlTcamSel - 27:26 Control bit. 0: TCAM0, 1: TCAM1, 2: TCAM2
+ * CtlTcamIndex - 25:17 Control bits. Index of TCAM location to be accessed
+ */
+
+ /* Read tcamy */
+ ctl = (CTLREQID_V(1) |
+ CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0));
+
+ if (idx < 512)
+ ctl |= T7_1_CTLTCAMINDEX_V(idx) | T7_CTLTCAMSEL_V(0);
+ else if (idx < 1024)
+ ctl |= T7_1_CTLTCAMINDEX_V(idx - 512) |
+ T7_CTLTCAMSEL_V(1);
+ else /* idx 1024 to 1535 */
+ ctl |= T7_1_CTLTCAMINDEX_V(idx - 1024) |
+ T7_CTLTCAMSEL_V(2);
+
+ t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
+ val = t4_read_reg(adap, MPS_CLS_TCAM0_RDATA1_REQ_ID1_A);
+ tcamy = DMACH_G(val) << 32;
+ tcamy |= t4_read_reg(adap,
+ MPS_CLS_TCAM0_RDATA0_REQ_ID1_A);
+ data2 = t4_read_reg(adap, MPS_CLS_TCAM0_RDATA2_REQ_ID1_A);
+ lookup_type = DATALKPTYPE_G(data2);
+ /* 0 - Outer header, 1 - Inner header
+ * [71:48] bit locations are overloaded for
+ * outer vs. inner lookup types.
+ */
+ if (lookup_type && lookup_type != DATALKPTYPE_M) {
+ /* Inner header VNI */
+ vniy = (((data2 & DATAVIDH2_F) |
+ DATAVIDH1_G(data2)) << 16) |
+ VIDL_G(val);
+ dip_hit = data2 & DATADIPHIT_F;
+ } else {
+ vlan_vld = data2 & DATAVIDH2_F;
+ ivlan = VIDL_G(val);
+ }
+ port_num = DATAPORTNUM_G(data2);
+
+ /* Read tcamx. Change the control param */
+ vnix = 0;
+ ctl |= CTLXYBITSEL_V(1);
+ t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
+ val = t4_read_reg(adap, MPS_CLS_TCAM0_RDATA1_REQ_ID1_A);
+ tcamx = DMACH_G(val) << 32;
+ tcamx |= t4_read_reg(adap, MPS_CLS_TCAM0_RDATA0_REQ_ID1_A);
+ data2 = t4_read_reg(adap, MPS_CLS_TCAM0_RDATA2_REQ_ID1_A);
+ if (lookup_type && lookup_type != DATALKPTYPE_M) {
+ /* Inner header VNI mask */
+ vnix = (((data2 & DATAVIDH2_F) |
+ DATAVIDH1_G(data2)) << 16) |
+ VIDL_G(val);
+ }
+ } else if (chip_ver > CHELSIO_T5) {
/* CtlCmdType - 0: Read, 1: Write
* CtlTcamSel - 0: TCAM0, 1: TCAM1
* CtlXYBitSel- 0: Y bit, 1: X bit
@@ -1755,8 +2003,19 @@ static int mps_tcam_show(struct seq_file *seq, void *v)
tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));
}
- cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
- cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));
+ /* t7b changes MPS_T5_CLS_SRAM_H_A to indirect register */
+ if (is_t7(adap->params.chip)) {
+ u32 tmp_ctl = 0;
+
+ tmp_ctl |= SRAMWRN_V(0) |
+ SRAMINDEX_V(idx & SRAMINDEX_M);
+ t4_write_reg(adap, MPS_T5_CLS_SRAM_H_A, tmp_ctl);
+ cls_lo = t4_read_reg(adap, MPS_T5_CLS_SRAM_L_A);
+ cls_hi = t4_read_reg(adap, MPS_T5_CLS_SRAM_H_A);
+ } else {
+ cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
+ cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));
+ }
if (tcamx & tcamy) {
seq_printf(seq, "%3u -\n", idx);
@@ -1886,11 +2145,11 @@ out: return 0;
static inline void *mps_tcam_get_idx(struct seq_file *seq, loff_t pos)
{
- struct adapter *adap = seq->private;
- int max_mac_addr = is_t4(adap->params.chip) ?
- NUM_MPS_CLS_SRAM_L_INSTANCES :
- NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
- return ((pos <= max_mac_addr) ? (void *)(uintptr_t)(pos + 1) : NULL);
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+
+ return ((pos <= adap->params.arch.mps_tcam_size) ?
+ (void *)(uintptr_t)(pos + 1) : NULL);
}
static void *mps_tcam_start(struct seq_file *seq, loff_t *pos)
@@ -1939,7 +2198,8 @@ static const struct file_operations mps_tcam_debugfs_fops = {
*/
static int sensors_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
u32 param[7], val[7];
int ret;
@@ -1988,9 +2248,10 @@ static int rss_show(struct seq_file *seq, void *v, int idx)
static int rss_open(struct inode *inode, struct file *file)
{
- struct adapter *adap = inode->i_private;
- int ret, nentries;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct seq_tab *p;
+ int ret, nentries;
nentries = t4_chip_rss_size(adap);
p = seq_open_tab(file, nentries / 8, 8 * sizeof(u16), 0, rss_show);
@@ -2028,7 +2289,8 @@ static const char *yesno(int x)
static int rss_config_show(struct seq_file *seq, void *v)
{
- struct adapter *adapter = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
static const char * const keymode[] = {
"global",
"global and per-VF scramble",
@@ -2037,7 +2299,7 @@ static int rss_config_show(struct seq_file *seq, void *v)
};
u32 rssconf;
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_A);
seq_printf(seq, "TP_RSS_CONFIG: %#x\n", rssconf);
seq_printf(seq, " Tnl4TupEnIpv6: %3s\n", yesno(rssconf &
TNL4TUPENIPV6_F));
@@ -2087,11 +2349,11 @@ static int rss_config_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_TNL_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_TNL_A);
seq_printf(seq, "TP_RSS_CONFIG_TNL: %#x\n", rssconf);
seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf));
seq_printf(seq, " MaskFilter: %3d\n", MASKFILTER_G(rssconf));
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) {
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
seq_printf(seq, " HashAll: %3s\n",
yesno(rssconf & HASHALL_F));
seq_printf(seq, " HashEth: %3s\n",
@@ -2101,7 +2363,7 @@ static int rss_config_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_OFD_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_OFD_A);
seq_printf(seq, "TP_RSS_CONFIG_OFD: %#x\n", rssconf);
seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf));
seq_printf(seq, " RRCplMapEn: %3s\n", yesno(rssconf &
@@ -2110,16 +2372,16 @@ static int rss_config_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_SYN_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_SYN_A);
seq_printf(seq, "TP_RSS_CONFIG_SYN: %#x\n", rssconf);
seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf));
seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F));
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
seq_printf(seq, "TP_RSS_CONFIG_VRT: %#x\n", rssconf);
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) {
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
seq_printf(seq, " KeyWrAddrX: %3d\n",
KEYWRADDRX_G(rssconf));
seq_printf(seq, " KeyExtend: %3s\n",
@@ -2133,7 +2395,7 @@ static int rss_config_show(struct seq_file *seq, void *v)
DISABLEVLAN_F));
seq_printf(seq, " EnUpSwt: %3s\n", yesno(rssconf & ENABLEUP0_F));
seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf));
- if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf));
else
seq_printf(seq, " VfWrAddr: %3d\n",
@@ -2145,7 +2407,7 @@ static int rss_config_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n");
- rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_CNG_A);
+ rssconf = t4_read_reg(adap, TP_RSS_CONFIG_CNG_A);
seq_printf(seq, "TP_RSS_CONFIG_CNG: %#x\n", rssconf);
seq_printf(seq, " ChnCount3: %3s\n", yesno(rssconf & CHNCOUNT3_F));
seq_printf(seq, " ChnCount2: %3s\n", yesno(rssconf & CHNCOUNT2_F));
@@ -2180,9 +2442,11 @@ DEFINE_SHOW_ATTRIBUTE(rss_config);
static int rss_key_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
u32 key[10];
- t4_read_rss_key(seq->private, key, true);
+ t4_read_rss_key(adap, key, true);
seq_printf(seq, "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n",
key[9], key[8], key[7], key[6], key[5], key[4], key[3],
key[2], key[1], key[0]);
@@ -2197,10 +2461,11 @@ static int rss_key_open(struct inode *inode, struct file *file)
static ssize_t rss_key_write(struct file *file, const char __user *buf,
size_t count, loff_t *pos)
{
- int i, j;
- u32 key[10];
+ struct t4_linux_debugfs_data *d = file_inode(file)->i_private;
+ struct adapter *adap = d->adap;
char s[100], *p;
- struct adapter *adap = file_inode(file)->i_private;
+ u32 key[10];
+ int i, j;
if (count > sizeof(s) - 1)
return -EINVAL;
@@ -2285,10 +2550,11 @@ static int rss_pf_config_show(struct seq_file *seq, void *v, int idx)
static int rss_pf_config_open(struct inode *inode, struct file *file)
{
- struct adapter *adapter = inode->i_private;
- struct seq_tab *p;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
u32 rss_pf_map, rss_pf_mask;
struct rss_pf_conf *pfconf;
+ struct seq_tab *p;
int pf;
p = seq_open_tab(file, 8, sizeof(*pfconf), 1, rss_pf_config_show);
@@ -2296,12 +2562,12 @@ static int rss_pf_config_open(struct inode *inode, struct file *file)
return -ENOMEM;
pfconf = (struct rss_pf_conf *)p->data;
- rss_pf_map = t4_read_rss_pf_map(adapter, true);
- rss_pf_mask = t4_read_rss_pf_mask(adapter, true);
+ rss_pf_map = t4_read_rss_pf_map(adap, true);
+ rss_pf_mask = t4_read_rss_pf_mask(adap, true);
for (pf = 0; pf < 8; pf++) {
pfconf[pf].rss_pf_map = rss_pf_map;
pfconf[pf].rss_pf_mask = rss_pf_mask;
- t4_read_rss_pf_config(adapter, pf, &pfconf[pf].rss_pf_config,
+ t4_read_rss_pf_config(adap, pf, &pfconf[pf].rss_pf_config,
true);
}
return 0;
@@ -2353,18 +2619,20 @@ static int rss_vf_config_show(struct seq_file *seq, void *v, int idx)
static int rss_vf_config_open(struct inode *inode, struct file *file)
{
- struct adapter *adapter = inode->i_private;
- struct seq_tab *p;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
struct rss_vf_conf *vfconf;
- int vf, vfcount = adapter->params.arch.vfcount;
+ struct seq_tab *p;
+ int vf, vfcount;
+ vfcount = adap->params.arch.vfcount;
p = seq_open_tab(file, vfcount, sizeof(*vfconf), 1, rss_vf_config_show);
if (!p)
return -ENOMEM;
vfconf = (struct rss_vf_conf *)p->data;
for (vf = 0; vf < vfcount; vf++) {
- t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl,
+ t4_read_rss_vf_config(adap, vf, &vfconf[vf].rss_vf_vfl,
&vfconf[vf].rss_vf_vfh, true);
}
return 0;
@@ -2384,7 +2652,8 @@ static const struct file_operations rss_vf_config_debugfs_fops = {
*/
static int dcb_info_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
if (v == SEQ_START_TOKEN) {
seq_puts(seq, "Data Center Bridging Information\n");
@@ -2405,7 +2674,6 @@ static int dcb_info_show(struct seq_file *seq, void *v)
if (dcb->msgs) {
int i;
-
seq_puts(seq, "\n Index\t\t\t :\t");
for (i = 0; i < 8; i++)
seq_printf(seq, " %3d", i);
@@ -2514,13 +2782,14 @@ static int dcb_info_show(struct seq_file *seq, void *v)
static inline void *dcb_info_get_idx(struct adapter *adap, loff_t pos)
{
return (pos <= adap->params.nports
- ? (void *)((uintptr_t)pos + 1)
- : NULL);
+ ? (void *)((uintptr_t)pos + 1)
+ : NULL);
}
static void *dcb_info_start(struct seq_file *seq, loff_t *pos)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
return (*pos
? dcb_info_get_idx(adap, *pos)
@@ -2533,7 +2802,8 @@ static void dcb_info_stop(struct seq_file *seq, void *v)
static void *dcb_info_next(struct seq_file *seq, void *v, loff_t *pos)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
(*pos)++;
return dcb_info_get_idx(adap, *pos);
@@ -2569,8 +2839,11 @@ static const struct file_operations dcb_info_debugfs_fops = {
static int resources_show(struct seq_file *seq, void *v)
{
- struct adapter *adapter = seq->private;
- struct pf_resources *pfres = &adapter->params.pfres;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ struct pf_resources *pfres;
+
+ pfres = &adap->params.pfres;
#define S(desc, fmt, var) \
seq_printf(seq, "%-60s " fmt "\n", \
@@ -2593,12 +2866,13 @@ static int resources_show(struct seq_file *seq, void *v)
}
DEFINE_SHOW_ATTRIBUTE(resources);
+#ifdef CONFIG_CXGB4_DCB
/**
* ethqset2pinfo - return port_info of an Ethernet Queue Set
* @adap: the adapter
* @qset: Ethernet Queue Set
*/
-static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset)
+static struct port_info *ethqset2pinfo(struct adapter *adap, int qset)
{
int pidx;
@@ -2614,6 +2888,7 @@ static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset)
BUG();
return NULL;
}
+#endif /* CONFIG_CXGB4_DCB */
static int sge_qinfo_uld_txq_entries(const struct adapter *adap, int uld)
{
@@ -2656,7 +2931,10 @@ static int sge_qinfo_show(struct seq_file *seq, void *v)
const struct sge_uld_txq_info *utxq_info;
const struct sge_uld_rxq_info *urxq_info;
struct cxgb4_tc_port_mqprio *port_mqprio;
- struct adapter *adap = seq->private;
+
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+
int i, j, n, r = (uintptr_t)v - 1;
struct sge *s = &adap->sge;
@@ -3101,7 +3379,6 @@ do { \
skip_uld:
if (r < ctrl_entries) {
const struct sge_ctrl_txq *tx = &s->ctrlq[r * 4];
-
n = min(4, adap->params.nports - 4 * r);
S("QType:", "Control");
@@ -3206,7 +3483,10 @@ static int sge_queue_entries(struct adapter *adap)
static void *sge_queue_start(struct seq_file *seq, loff_t *pos)
{
- int entries = sge_queue_entries(seq->private);
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+
+ int entries = sge_queue_entries(adap);
return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
}
@@ -3217,7 +3497,10 @@ static void sge_queue_stop(struct seq_file *seq, void *v)
static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos)
{
- int entries = sge_queue_entries(seq->private);
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+
+ int entries = sge_queue_entries(adap);
++*pos;
return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
@@ -3252,14 +3535,11 @@ static const struct file_operations sge_qinfo_debugfs_fops = {
int mem_open(struct inode *inode, struct file *file)
{
- unsigned int mem;
- struct adapter *adap;
+ struct t4_linux_debugfs_data *d = inode->i_private;
+ struct adapter *adap = d->adap;
file->private_data = inode->i_private;
- mem = (uintptr_t)file->private_data & 0x7;
- adap = file->private_data - mem;
-
(void)t4_fwcache(adap, FW_PARAM_DEV_FWCACHE_FLUSH);
return 0;
@@ -3268,10 +3548,11 @@ int mem_open(struct inode *inode, struct file *file)
static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
loff_t *ppos)
{
- loff_t pos = *ppos;
+ struct t4_linux_debugfs_data *d = file->private_data;
loff_t avail = file_inode(file)->i_size;
- unsigned int mem = (uintptr_t)file->private_data & 0x7;
- struct adapter *adap = file->private_data - mem;
+ struct adapter *adap = d->adap;
+ unsigned int mem = d->data;
+ loff_t pos = *ppos;
__be32 *data;
int ret;
@@ -3311,18 +3592,19 @@ static const struct file_operations mem_debugfs_fops = {
static int tid_info_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
const struct tid_info *t;
- enum chip_type chip;
+ unsigned int chip_ver;
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
t = &adap->tids;
- chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+
if (t4_read_reg(adap, LE_DB_CONFIG_A) & HASHEN_F) {
unsigned int sb;
seq_printf(seq, "Connections in use: %u\n",
atomic_read(&t->conns_in_use));
-
- if (chip <= CHELSIO_T5)
+ if (chip_ver <= CHELSIO_T5)
sb = t4_read_reg(adap, LE_DB_SERVER_INDEX_A) / 4;
else
sb = t4_read_reg(adap, LE_DB_SRVR_START_INDEX_A);
@@ -3330,13 +3612,12 @@ static int tid_info_show(struct seq_file *seq, void *v)
if (sb) {
seq_printf(seq, "TID range: %u..%u/%u..%u", t->tid_base,
sb - 1, adap->tids.hash_base,
- t->tid_base + t->ntids - 1);
+ t->ntids + t->tid_base - 1);
seq_printf(seq, ", in use: %u/%u\n",
atomic_read(&t->tids_in_use),
atomic_read(&t->hash_tids_in_use));
} else if (adap->flags & CXGB4_FW_OFLD_CONN) {
- seq_printf(seq, "TID range: %u..%u/%u..%u",
- t->aftid_base,
+ seq_printf(seq, "TID range: %u..%u/%u..%u", t->aftid_base,
t->aftid_end,
adap->tids.hash_base,
t->tid_base + t->ntids - 1);
@@ -3353,7 +3634,6 @@ static int tid_info_show(struct seq_file *seq, void *v)
} else if (t->ntids) {
seq_printf(seq, "Connections in use: %u\n",
atomic_read(&t->conns_in_use));
-
seq_printf(seq, "TID range: %u..%u", t->tid_base,
t->tid_base + t->ntids - 1);
seq_printf(seq, ", in use: %u\n",
@@ -3363,12 +3643,11 @@ static int tid_info_show(struct seq_file *seq, void *v)
if (t->nstids)
seq_printf(seq, "STID range: %u..%u, in use-IPv4/IPv6: %u/%u\n",
(!t->stid_base &&
- (chip <= CHELSIO_T5)) ?
+ (chip_ver <= CHELSIO_T5)) ?
t->stid_base + 1 : t->stid_base,
t->stid_base + t->nstids - 1,
t->stids_in_use - t->v6_stids_in_use,
t->v6_stids_in_use);
-
if (t->natids)
seq_printf(seq, "ATID range: 0..%u, in use: %u\n",
t->natids - 1, t->atids_in_use);
@@ -3378,11 +3657,11 @@ static int tid_info_show(struct seq_file *seq, void *v)
seq_printf(seq, "SFTID range: %u..%u in use: %u\n",
t->sftid_base, t->sftid_base + t->nsftids - 2,
t->sftids_in_use);
- if (t->nhpftids)
+ if (t->nhpftids && chip_ver > CHELSIO_T5)
seq_printf(seq, "HPFTID range: %u..%u\n", t->hpftid_base,
t->hpftid_base + t->nhpftids - 1);
if (t->neotids)
- seq_printf(seq, "EOTID range: %u..%u, in use: %u\n",
+ seq_printf(seq, "UOTID range: %u..%u, in use: %u\n",
t->eotid_base, t->eotid_base + t->neotids - 1,
atomic_read(&t->eotids_in_use));
if (t->ntids)
@@ -3393,22 +3672,17 @@ static int tid_info_show(struct seq_file *seq, void *v)
}
DEFINE_SHOW_ATTRIBUTE(tid_info);
-static void add_debugfs_mem(struct adapter *adap, const char *name,
- unsigned int idx, unsigned int size_mb)
-{
- debugfs_create_file_size(name, 0400, adap->debugfs_root,
- (void *)adap + idx, &mem_debugfs_fops,
- size_mb << 20);
-}
-
static ssize_t blocked_fl_read(struct file *filp, char __user *ubuf,
size_t count, loff_t *ppos)
{
- int len;
- const struct adapter *adap = filp->private_data;
+ struct t4_linux_debugfs_data *d = filp->private_data;
+ const struct adapter *adap = d->adap;
+ ssize_t size;
char *buf;
- ssize_t size = (adap->sge.egr_sz + 3) / 4 +
- adap->sge.egr_sz / 32 + 2; /* includes ,/\n/\0 */
+ int len;
+
+ size = (adap->sge.egr_sz + 3) / 4 + adap->sge.egr_sz / 32 +
+ 2; /* includes ,/\n/\0 */
buf = kzalloc(size, GFP_KERNEL);
if (!buf)
@@ -3425,9 +3699,10 @@ static ssize_t blocked_fl_read(struct file *filp, char __user *ubuf,
static ssize_t blocked_fl_write(struct file *filp, const char __user *ubuf,
size_t count, loff_t *ppos)
{
- int err;
+ struct t4_linux_debugfs_data *d = filp->private_data;
+ struct adapter *adap = d->adap;
unsigned long *t;
- struct adapter *adap = filp->private_data;
+ int err;
t = bitmap_zalloc(adap->sge.egr_sz, GFP_KERNEL);
if (!t)
@@ -3453,20 +3728,21 @@ static const struct file_operations blocked_fl_fops = {
};
static void mem_region_show(struct seq_file *seq, const char *name,
- unsigned int from, unsigned int to)
+ u64 from, u64 to)
{
char buf[40];
string_get_size((u64)to - from + 1, 1, STRING_UNITS_2, buf,
sizeof(buf));
- seq_printf(seq, "%-15s %#x-%#x [%s]\n", name, from, to, buf);
+ seq_printf(seq, "%-20s %#llx-%#llx [%s]\n", name, from, to, buf);
}
static int meminfo_show(struct seq_file *seq, void *v)
{
static const char * const memory[] = { "EDC0:", "EDC1:", "MC:",
"MC0:", "MC1:", "HMA:"};
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct cudbg_meminfo meminfo;
int i, rc;
@@ -3527,11 +3803,12 @@ DEFINE_SHOW_ATTRIBUTE(meminfo);
static int chcr_stats_show(struct seq_file *seq, void *v)
{
+ struct t4_linux_debugfs_data *d = seq->private;
#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
struct ch_ktls_port_stats_debug *ktls_port;
int i = 0;
#endif
- struct adapter *adap = seq->private;
+ struct adapter *adap = d->adap;
seq_puts(seq, "Chelsio Crypto Accelerator Stats \n");
seq_printf(seq, "Cipher Ops: %10u \n",
@@ -3615,7 +3892,8 @@ do { \
static void show_tcp_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_tcp_stats v4, v6;
spin_lock(&adap->stats_lock);
@@ -3634,7 +3912,8 @@ static void show_tcp_stats(struct seq_file *seq)
static void show_ddp_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_usm_stats stats;
spin_lock(&adap->stats_lock);
@@ -3648,8 +3927,9 @@ static void show_ddp_stats(struct seq_file *seq)
static void show_rdma_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
- struct tp_rdma_stats stats;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
+ struct tp_rdma_stats stats = {0};
spin_lock(&adap->stats_lock);
t4_tp_get_rdma_stats(adap, &stats, false);
@@ -3657,11 +3937,13 @@ static void show_rdma_stats(struct seq_file *seq)
PRINT_ADAP_STATS("rdma_no_rqe_mod_defer:", stats.rqe_dfr_mod);
PRINT_ADAP_STATS("rdma_no_rqe_pkt_defer:", stats.rqe_dfr_pkt);
+
}
static void show_tp_err_adapter_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_err_stats stats;
spin_lock(&adap->stats_lock);
@@ -3674,7 +3956,8 @@ static void show_tp_err_adapter_stats(struct seq_file *seq)
static void show_cpl_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_cpl_stats stats;
u8 i;
@@ -3688,7 +3971,8 @@ static void show_cpl_stats(struct seq_file *seq)
static void show_tp_err_channel_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_err_stats stats;
u8 i;
@@ -3708,7 +3992,8 @@ static void show_tp_err_channel_stats(struct seq_file *seq)
static void show_fcoe_stats(struct seq_file *seq)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
struct tp_fcoe_stats stats[NCHAN];
u8 i;
@@ -3728,7 +4013,8 @@ static void show_fcoe_stats(struct seq_file *seq)
static int tp_stats_show(struct seq_file *seq, void *v)
{
- struct adapter *adap = seq->private;
+ struct t4_linux_debugfs_data *d = seq->private;
+ struct adapter *adap = d->adap;
seq_puts(seq, "\n--------Adapter Stats--------\n");
show_tcp_stats(seq);
@@ -3738,9 +4024,8 @@ static int tp_stats_show(struct seq_file *seq, void *v)
seq_puts(seq, "\n-------- Channel Stats --------\n");
if (adap->params.arch.nchan == NCHAN)
- seq_printf(seq, "%-25s %-20s %-20s %-20s %-20s\n",
- " ", "channel 0", "channel 1",
- "channel 2", "channel 3");
+ seq_printf(seq, "%-25s %-20s %-20s %-20s %-20s\n", " ",
+ "channel 0", "channel 1", "channel 2", "channel 3");
else
seq_printf(seq, "%-25s %-20s %-20s\n",
" ", "channel 0", "channel 1");
@@ -3754,33 +4039,191 @@ DEFINE_SHOW_ATTRIBUTE(tp_stats);
/* Add an array of Debug FS files.
*/
-void add_debugfs_files(struct adapter *adap,
- struct t4_debugfs_entry *files,
- unsigned int nfiles)
+static void create_debugfs_file_entry(struct t4_linux_debugfs_entry *f,
+ const char *name,
+ const struct file_operations *ops,
+ umode_t mode, unsigned char data)
{
- int i;
+ f->name = name;
+ f->ops = ops;
+ f->mode = mode;
+ f->data = data;
+}
- /* debugfs support is best effort */
- for (i = 0; i < nfiles; i++)
- debugfs_create_file(files[i].name, files[i].mode,
- adap->debugfs_root,
- (void *)adap + files[i].data,
- files[i].ops);
+static void add_debugfs_file_size(struct adapter *adap, struct dentry *dentry,
+ struct t4_linux_debugfs_entry *f, u64 size)
+{
+ struct t4_linux_debugfs_data *data;
+
+ data = devm_kzalloc(adap->pdev_dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return;
+
+ data->adap = adap;
+ data->data = f->data;
+ data->coreid = 0;
+ debugfs_create_file_size(f->name, f->mode, dentry, data, f->ops, size);
}
-int t4_setup_debugfs(struct adapter *adap)
+static void add_debugfs_mem(struct adapter *adap, const char *name,
+ unsigned int i, unsigned int size_mb)
+{
+ struct t4_linux_debugfs_entry f;
+
+ create_debugfs_file_entry(&f, name, &mem_debugfs_fops, 0400, i);
+ add_debugfs_file_size(adap, adap->debugfs_root, &f, (u64)size_mb << 20);
+}
+
+void add_debugfs_files(struct adapter *adap, struct dentry *dentry,
+ unsigned char coreid, struct t4_linux_debugfs_entry *f,
+ unsigned int n)
{
+ struct t4_linux_debugfs_data *data;
int i;
- u32 size = 0;
- static struct t4_debugfs_entry t4_debugfs_files[] = {
+ for (i = 0; i < n; i++) {
+ data = devm_kzalloc(adap->pdev_dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ continue;
+
+ data->adap = adap;
+ data->data = f[i].data;
+ data->coreid = coreid;
+ debugfs_create_file(f[i].name, f[i].mode, dentry, data,
+ f[i].ops);
+ }
+}
+
+static void add_debugfs_files_multicore(struct adapter *adap)
+{
+ static struct t4_linux_debugfs_entry common_files[] = {
{ "cim_la", &cim_la_fops, 0400, 0 },
{ "cim_pif_la", &cim_pif_la_fops, 0400, 0 },
{ "cim_ma_la", &cim_ma_la_fops, 0400, 0 },
{ "cim_qcfg", &cim_qcfg_fops, 0400, 0 },
- { "clk", &clk_fops, 0400, 0 },
{ "devlog", &devlog_fops, 0400, 0 },
+ };
+ static struct t4_linux_debugfs_entry t4_files[] = {
+ { "ibq_tp0", &cim_ibq_fops, 0400, 0 },
+ { "ibq_tp1", &cim_ibq_fops, 0400, 1 },
+ { "ibq_ulp", &cim_ibq_fops, 0400, 2 },
+ { "ibq_sge0", &cim_ibq_fops, 0400, 3 },
+ { "ibq_sge1", &cim_ibq_fops, 0400, 4 },
+ { "ibq_ncsi", &cim_ibq_fops, 0400, 5 },
+ { "obq_ulp0", &cim_obq_fops, 0400, 0 },
+ { "obq_ulp1", &cim_obq_fops, 0400, 1 },
+ { "obq_ulp2", &cim_obq_fops, 0400, 2 },
+ { "obq_ulp3", &cim_obq_fops, 0400, 3 },
+ { "obq_sge", &cim_obq_fops, 0400, 4 },
+ { "obq_ncsi", &cim_obq_fops, 0400, 5 },
+ };
+ static struct t4_linux_debugfs_entry t5_files[] = {
+ { "ibq_tp0", &cim_ibq_fops, 0400, 0 },
+ { "ibq_tp1", &cim_ibq_fops, 0400, 1 },
+ { "ibq_ulp", &cim_ibq_fops, 0400, 2 },
+ { "ibq_sge0", &cim_ibq_fops, 0400, 3 },
+ { "ibq_sge1", &cim_ibq_fops, 0400, 4 },
+ { "ibq_ncsi", &cim_ibq_fops, 0400, 5 },
+ { "obq_ulp0", &cim_obq_fops, 0400, 0 },
+ { "obq_ulp1", &cim_obq_fops, 0400, 1 },
+ { "obq_ulp2", &cim_obq_fops, 0400, 2 },
+ { "obq_ulp3", &cim_obq_fops, 0400, 3 },
+ { "obq_sge", &cim_obq_fops, 0400, 4 },
+ { "obq_ncsi", &cim_obq_fops, 0400, 5 },
+ { "obq_sge_rx_q0", &cim_obq_fops, 0400, 6 },
+ { "obq_sge_rx_q1", &cim_obq_fops, 0400, 7 },
+ };
+ static struct t4_linux_debugfs_entry t7_files[] = {
+ { "ibq_tp0", &cim_ibq_fops, 0400, 0 },
+ { "ibq_tp1", &cim_ibq_fops, 0400, 1 },
+ { "ibq_tp2", &cim_ibq_fops, 0400, 2 },
+ { "ibq_tp3", &cim_ibq_fops, 0400, 3 },
+ { "ibq_ulp", &cim_ibq_fops, 0400, 4 },
+ { "ibq_sge0", &cim_ibq_fops, 0400, 5 },
+ { "ibq_sge1", &cim_ibq_fops, 0400, 6 },
+ { "ibq_ncsi", &cim_ibq_fops, 0400, 7 },
+ { "ibq_ipc1", &cim_ibq_fops, 0400, 9 },
+ { "ibq_ipc2", &cim_ibq_fops, 0400, 10 },
+ { "ibq_ipc3", &cim_ibq_fops, 0400, 11 },
+ { "ibq_ipc4", &cim_ibq_fops, 0400, 12 },
+ { "ibq_ipc5", &cim_ibq_fops, 0400, 13 },
+ { "ibq_ipc6", &cim_ibq_fops, 0400, 14 },
+ { "ibq_ipc7", &cim_ibq_fops, 0400, 15 },
+ { "obq_ulp0", &cim_obq_fops, 0400, 0 },
+ { "obq_ulp1", &cim_obq_fops, 0400, 1 },
+ { "obq_ulp2", &cim_obq_fops, 0400, 2 },
+ { "obq_ulp3", &cim_obq_fops, 0400, 3 },
+ { "obq_sge", &cim_obq_fops, 0400, 4 },
+ { "obq_ncsi", &cim_obq_fops, 0400, 5 },
+ { "obq_sge_rx_q0", &cim_obq_fops, 0400, 6 },
+ { "obq_ipc1", &cim_obq_fops, 0400, 9 },
+ { "obq_ipc2", &cim_obq_fops, 0400, 10 },
+ { "obq_ipc3", &cim_obq_fops, 0400, 11 },
+ { "obq_ipc4", &cim_obq_fops, 0400, 12 },
+ { "obq_ipc5", &cim_obq_fops, 0400, 13 },
+ { "obq_ipc6", &cim_obq_fops, 0400, 14 },
+ { "obq_ipc7", &cim_obq_fops, 0400, 15 },
+ };
+ static struct t4_linux_debugfs_entry t7_sec_files[] = {
+ { "ibq_tp0", &cim_ibq_fops, 0400, 0 },
+ { "ibq_tp1", &cim_ibq_fops, 0400, 1 },
+ { "ibq_tp2", &cim_ibq_fops, 0400, 2 },
+ { "ibq_tp3", &cim_ibq_fops, 0400, 3 },
+ { "ibq_ulp", &cim_ibq_fops, 0400, 4 },
+ { "ibq_sge0", &cim_ibq_fops, 0400, 5 },
+ { "ibq_ipc0", &cim_ibq_fops, 0400, 9 },
+ { "obq_ulp0", &cim_obq_fops, 0400, 0 },
+ { "obq_ulp1", &cim_obq_fops, 0400, 1 },
+ { "obq_ulp2", &cim_obq_fops, 0400, 2 },
+ { "obq_ulp3", &cim_obq_fops, 0400, 3 },
+ { "obq_sge", &cim_obq_fops, 0400, 4 },
+ { "obq_sge_rx_q0", &cim_obq_fops, 0400, 6 },
+ { "obq_ipc0", &cim_obq_fops, 0400, 9 },
+ };
+ u32 chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ char name[8];
+ u8 i;
+
+ /* Add primary core files */
+ add_debugfs_files(adap, adap->debugfs_root, 0, common_files,
+ ARRAY_SIZE(common_files));
+
+ switch (chip) {
+ case CHELSIO_T4:
+ add_debugfs_files(adap, adap->debugfs_root, 0, t4_files,
+ ARRAY_SIZE(t4_files));
+ break;
+ case CHELSIO_T5:
+ case CHELSIO_T6:
+ add_debugfs_files(adap, adap->debugfs_root, 0, t5_files,
+ ARRAY_SIZE(t5_files));
+ break;
+ default:
+ add_debugfs_files(adap, adap->debugfs_root, 0, t7_files,
+ ARRAY_SIZE(t7_files));
+ break;
+ }
+
+ /* Add secondary core files */
+ for (i = 1; i < adap->params.num_up_cores; i++) {
+ snprintf(name, sizeof(name), "core_%u", i);
+ adap->debugfs_multicore[i] =
+ debugfs_create_dir(name, adap->debugfs_root);
+
+ add_debugfs_files(adap, adap->debugfs_multicore[i], i,
+ common_files, ARRAY_SIZE(common_files));
+ add_debugfs_files(adap, adap->debugfs_multicore[i], i,
+ t7_sec_files, ARRAY_SIZE(t7_sec_files));
+ }
+}
+
+int t4_setup_debugfs(struct adapter *adap)
+{
+ static struct t4_linux_debugfs_entry t4_debugfs_files[] = {
+ { "clk", &clk_fops, 0400, 0 },
+#ifdef T4_OS_LOG_MBOX_CMDS
{ "mboxlog", &mboxlog_fops, 0400, 0 },
+#endif
{ "mbox0", &mbox_debugfs_fops, 0600, 0 },
{ "mbox1", &mbox_debugfs_fops, 0600, 1 },
{ "mbox2", &mbox_debugfs_fops, 0600, 2 },
@@ -3789,105 +4232,158 @@ int t4_setup_debugfs(struct adapter *adap)
{ "mbox5", &mbox_debugfs_fops, 0600, 5 },
{ "mbox6", &mbox_debugfs_fops, 0600, 6 },
{ "mbox7", &mbox_debugfs_fops, 0600, 7 },
- { "trace0", &mps_trc_debugfs_fops, 0600, 0 },
- { "trace1", &mps_trc_debugfs_fops, 0600, 1 },
- { "trace2", &mps_trc_debugfs_fops, 0600, 2 },
- { "trace3", &mps_trc_debugfs_fops, 0600, 3 },
- { "l2t", &t4_l2t_fops, 0400, 0},
{ "mps_tcam", &mps_tcam_debugfs_fops, 0400, 0 },
- { "rss", &rss_debugfs_fops, 0400, 0 },
- { "rss_config", &rss_config_fops, 0400, 0 },
- { "rss_key", &rss_key_debugfs_fops, 0400, 0 },
- { "rss_pf_config", &rss_pf_config_debugfs_fops, 0400, 0 },
- { "rss_vf_config", &rss_vf_config_debugfs_fops, 0400, 0 },
- { "resources", &resources_fops, 0400, 0 },
-#ifdef CONFIG_CHELSIO_T4_DCB
- { "dcb_info", &dcb_info_debugfs_fops, 0400, 0 },
-#endif
- { "sge_qinfo", &sge_qinfo_debugfs_fops, 0400, 0 },
- { "ibq_tp0", &cim_ibq_fops, 0400, 0 },
- { "ibq_tp1", &cim_ibq_fops, 0400, 1 },
- { "ibq_ulp", &cim_ibq_fops, 0400, 2 },
- { "ibq_sge0", &cim_ibq_fops, 0400, 3 },
- { "ibq_sge1", &cim_ibq_fops, 0400, 4 },
- { "ibq_ncsi", &cim_ibq_fops, 0400, 5 },
- { "obq_ulp0", &cim_obq_fops, 0400, 0 },
- { "obq_ulp1", &cim_obq_fops, 0400, 1 },
- { "obq_ulp2", &cim_obq_fops, 0400, 2 },
- { "obq_ulp3", &cim_obq_fops, 0400, 3 },
- { "obq_sge", &cim_obq_fops, 0400, 4 },
- { "obq_ncsi", &cim_obq_fops, 0400, 5 },
{ "tp_la", &tp_la_fops, 0400, 0 },
{ "ulprx_la", &ulprx_la_fops, 0400, 0 },
{ "sensors", &sensors_fops, 0400, 0 },
+ { "tp_stats", &tp_stats_fops, 0400, 0 },
{ "pm_stats", &pm_stats_debugfs_fops, 0400, 0 },
{ "tx_rate", &tx_rate_fops, 0400, 0 },
{ "cctrl", &cctrl_tbl_fops, 0400, 0 },
-#if IS_ENABLED(CONFIG_IPV6)
- { "clip_tbl", &clip_tbl_fops, 0400, 0 },
-#endif
- { "tids", &tid_info_fops, 0400, 0},
- { "blocked_fl", &blocked_fl_fops, 0600, 0 },
- { "meminfo", &meminfo_fops, 0400, 0 },
- { "crypto", &chcr_stats_fops, 0400, 0 },
- { "tp_stats", &tp_stats_fops, 0400, 0 },
- };
-
- /* Debug FS nodes common to all T5 and later adapters.
- */
- static struct t4_debugfs_entry t5_debugfs_files[] = {
- { "obq_sge_rx_q0", &cim_obq_fops, 0400, 6 },
- { "obq_sge_rx_q1", &cim_obq_fops, 0400, 7 },
+ { "rss", &rss_debugfs_fops, 0400, 0 },
+ { "rss_config", &rss_config_fops, 0400, 0 },
+ { "rss_key", &rss_key_debugfs_fops, 0400, 0 },
+ { "rss_pf_config", &rss_pf_config_debugfs_fops, 0400, 0 },
+ { "rss_vf_config", &rss_vf_config_debugfs_fops, 0400, 0 },
+ { "meminfo", &meminfo_fops, 0400, 0 }
};
+ u32 val, chip = CHELSIO_CHIP_VERSION(adap->params.chip);
+ struct t4_linux_debugfs_entry f;
+ int i;
- add_debugfs_files(adap,
- t4_debugfs_files,
+ add_debugfs_files(adap, adap->debugfs_root, 0, t4_debugfs_files,
ARRAY_SIZE(t4_debugfs_files));
- if (!is_t4(adap->params.chip))
- add_debugfs_files(adap,
- t5_debugfs_files,
- ARRAY_SIZE(t5_debugfs_files));
+
+ add_debugfs_files_multicore(adap);
i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
if (i & EDRAM0_ENABLE_F) {
- size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
- add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM0_SIZE_G(size));
+ val = t4_read_reg(adap, MA_EDRAM0_BAR_A);
+ add_debugfs_mem(adap, "edc0", MEM_EDC0, T7_EDRAM0_SIZE_G(val));
}
+
if (i & EDRAM1_ENABLE_F) {
- size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
- add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size));
+ val = t4_read_reg(adap, MA_EDRAM1_BAR_A);
+ add_debugfs_mem(adap, "edc1", MEM_EDC1,
+ T7_EDRAM1_SIZE_G(val));
}
- if (is_t5(adap->params.chip)) {
- if (i & EXT_MEM0_ENABLE_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
+
+ if (i & EXT_MEM_ENABLE_F) {
+ switch (chip) {
+ case CHELSIO_T4:
+ case CHELSIO_T6:
+ val = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
+ add_debugfs_mem(adap, "mc", MEM_MC,
+ EXT_MEM_SIZE_G(val));
+ break;
+ default:
+ val = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
add_debugfs_mem(adap, "mc0", MEM_MC0,
- EXT_MEM0_SIZE_G(size));
+ T7_EXT_MEM0_SIZE_G(val));
+ break;
}
- if (i & EXT_MEM1_ENABLE_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
+ }
+
+ if (i & EXT_MEM1_ENABLE_F) {
+ switch (chip) {
+ case CHELSIO_T4:
+ case CHELSIO_T6:
+ /* No support for mc1 */
+ break;
+ default:
+ /* No mc1 when split mode enabled */
+ if (i & MC_SPLIT_F)
+ break;
+
+ val = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
add_debugfs_mem(adap, "mc1", MEM_MC1,
- EXT_MEM1_SIZE_G(size));
- }
- } else {
- if (i & EXT_MEM_ENABLE_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
- add_debugfs_mem(adap, "mc", MEM_MC,
- EXT_MEM_SIZE_G(size));
+ T7_EXT_MEM1_SIZE_G(val));
+ break;
}
+ }
- if (i & HMA_MUX_F) {
- size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
+ if (i & HMA_MUX_F) {
+ switch (chip) {
+ case CHELSIO_T4:
+ case CHELSIO_T5:
+ /* No support for hma */
+ break;
+ case CHELSIO_T6:
+ val = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
+ add_debugfs_mem(adap, "hma", MEM_HMA,
+ EXT_MEM_SIZE_G(val));
+ break;
+ default:
+ val = t4_read_reg(adap, MA_HOST_MEMORY_BAR_A);
add_debugfs_mem(adap, "hma", MEM_HMA,
- EXT_MEM1_SIZE_G(size));
+ T7_HMA_SIZE_G(val));
+ break;
}
}
- debugfs_create_file_size("flash", 0400, adap->debugfs_root, adap,
- &flash_debugfs_fops, adap->params.sf_size);
+ create_debugfs_file_entry(&f, "flash", &flash_debugfs_fops, 0400, 0);
+ add_debugfs_file_size(adap, adap->debugfs_root, &f,
+ adap->params.sf_size);
+
debugfs_create_bool("use_backdoor", 0600,
- adap->debugfs_root, &adap->use_bd);
+ adap->debugfs_root, &adap->use_bd);
debugfs_create_bool("trace_rss", 0600,
- adap->debugfs_root, &adap->trace_rss);
+ adap->debugfs_root, &adap->trace_rss);
+ return 0;
+}
+
+/*
+ * Add an array of Debug FS files.
+ */
+static void cxgb4_add_debugfs_files(struct adapter *adap,
+ struct t4_linux_debugfs_entry *files,
+ unsigned int nfiles)
+{
+ int i;
+
+ /* debugfs support is best effort */
+ for (i = 0; i < nfiles; i++)
+ add_debugfs_files(adap, adap->debugfs_root, 0, &files[i], 1);
+}
+
+int cxgb4_setup_debugfs(struct adapter *adap)
+{
+ static struct t4_linux_debugfs_entry cxgb4_debugfs_files[] = {
+ { "blocked_fl", &blocked_fl_fops, 0600 },
+#ifdef CONFIG_CHELSIO_T4_DCB
+ { "dcb_info", &dcb_info_debugfs_fops, 0400, 0 },
+ #endif /* CONFIG_CHELSIO_T4_DCB */
+ { "resources", &resources_fops, 0400, 0 },
+ { "sge_qinfo", &sge_qinfo_debugfs_fops, 0400, 0 },
+ { "clip_tbl", &clip_tbl_fops, 0400, 0 },
+ { "tids", &tid_info_fops, 0400, 0 },
+ { "trace0", &mps_trc_debugfs_fops, 0600, 0 },
+ { "trace1", &mps_trc_debugfs_fops, 0600, 1 },
+ { "trace2", &mps_trc_debugfs_fops, 0600, 2 },
+ { "trace3", &mps_trc_debugfs_fops, 0600, 3 },
+ { "l2t", &t4_l2t_fops, 0400, 0 },
+ { "crypto", &chcr_stats_fops, 0400, 0 },
+ };
+
+ static struct t4_linux_debugfs_entry cxgb4_t7_debugfs_files[] = {
+ { "trace4", &mps_trc_debugfs_fops, 0600, 4 },
+ { "trace5", &mps_trc_debugfs_fops, 0600, 5 },
+ { "trace6", &mps_trc_debugfs_fops, 0600, 6 },
+ { "trace7", &mps_trc_debugfs_fops, 0600, 7 },
+ };
+
+ if (IS_ERR_OR_NULL(adap->debugfs_root))
+ return -1;
+
+#ifdef CONFIG_DEBUG_FS
+ t4_setup_debugfs(adap);
+#endif
+
+ cxgb4_add_debugfs_files(adap, cxgb4_debugfs_files,
+ ARRAY_SIZE(cxgb4_debugfs_files));
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ cxgb4_add_debugfs_files(adap, cxgb4_t7_debugfs_files,
+ ARRAY_SIZE(cxgb4_t7_debugfs_files));
return 0;
}
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
index 1471cf0deb58..52fba7f2027e 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
@@ -37,7 +37,13 @@
#include <linux/export.h>
-struct t4_debugfs_entry {
+struct t4_linux_debugfs_data {
+ struct adapter *adap;
+ unsigned int data;
+ unsigned char coreid;
+};
+
+struct t4_linux_debugfs_entry {
const char *name;
const struct file_operations *ops;
umode_t mode;
@@ -62,9 +68,9 @@ struct seq_tab *seq_open_tab(struct file *f, unsigned int rows,
int (*show)(struct seq_file *seq, void *v, int i));
int t4_setup_debugfs(struct adapter *adap);
-void add_debugfs_files(struct adapter *adap,
- struct t4_debugfs_entry *files,
- unsigned int nfiles);
+void add_debugfs_files(struct adapter *adap, struct dentry *dentry,
+ unsigned char coreid, struct t4_linux_debugfs_entry *f,
+ unsigned int n);
int mem_open(struct inode *inode, struct file *file);
-
+int cxgb4_setup_debugfs(struct adapter *adap);
#endif
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next v1 10/10] cxgb4: Update SGE path and filtering logic for T7
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
` (8 preceding siblings ...)
2026-06-07 3:52 ` [PATCH net-next v1 09/10] cxgb4: Update debugfs interface for T7 versioned structures Potnuri Bharat Teja
@ 2026-06-07 3:52 ` Potnuri Bharat Teja
2026-06-08 21:13 ` [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Jakub Kicinski
10 siblings, 0 replies; 13+ messages in thread
From: Potnuri Bharat Teja @ 2026-06-07 3:52 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, edumazet, pabeni, andrew+netdev, bharat
Optimize the SGE path and extend the hardware traffic filter engine to
support T7 active-open configurations.
Update the SGE ring management and transport paths to leverage T7 layout
features:
- Replace the runtime register calculations MYPF_REG for doorbells by
caching and reading physical tx_db_addr and rx_db_addr pointers.
- Fix sizing boundaries within is_eth_imm to account for the permanent
CPL header footprint.
- Transition transmit descriptors within the Ethernet paths to track
logical ports lport instead of transmit channels.
- Export encapsulated offload validation helper capabilities for use
by ULD modules.
- Refactor the filter programming logic inside cxgb4_filter.c to handle
T7 configuration flags, insert wide tuple structures like
cpl_t7_act_open_req, and expand hardware CLIP cleanup checks.
Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
.../net/ethernet/chelsio/cxgb4/cxgb4_filter.c | 212 +++++++++++-------
drivers/net/ethernet/chelsio/cxgb4/sge.c | 122 +++++-----
2 files changed, 209 insertions(+), 125 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c
index 657d96b9e2f6..38c08ffb8a0b 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c
@@ -66,9 +66,14 @@ static int set_tcb_field(struct adapter *adap, struct filter_entry *f,
req = (struct cpl_set_tcb_field *)__skb_put_zero(skb, sizeof(*req));
INIT_TP_WR_CPL(req, CPL_SET_TCB_FIELD, ftid);
- req->reply_ctrl = htons(REPLY_CHAN_V(0) |
- QUEUENO_V(adap->sge.fw_evtq.abs_id) |
- NO_REPLY_V(no_reply));
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T7)
+ req->reply_ctrl = htons(T7_REPLY_CHAN_V(0) |
+ T7_QUEUENO_V(adap->sge.fw_evtq.abs_id) |
+ NO_REPLY_V(no_reply));
+ else
+ req->reply_ctrl = htons(REPLY_CHAN_V(0) |
+ QUEUENO_V(adap->sge.fw_evtq.abs_id) |
+ NO_REPLY_V(no_reply));
req->word_cookie = htons(TCB_WORD_V(word) | TCB_COOKIE_V(ftid));
req->mask = cpu_to_be64(mask);
req->val = cpu_to_be64(val);
@@ -249,32 +254,54 @@ static int validate_filter(struct net_device *dev,
struct ch_filter_specification *fs)
{
struct adapter *adapter = netdev2adap(dev);
- u32 fconf, iconf;
+ u32 fconf, iconf, chip_ver;
+ chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
/* Check for unconfigured fields being used. */
iconf = adapter->params.tp.ingress_config;
fconf = fs->hash ? adapter->params.tp.filter_mask :
adapter->params.tp.vlan_pri_map;
- if (unsupported(fconf, FCOE_F, fs->val.fcoe, fs->mask.fcoe) ||
- unsupported(fconf, PORT_F, fs->val.iport, fs->mask.iport) ||
- unsupported(fconf, TOS_F, fs->val.tos, fs->mask.tos) ||
- unsupported(fconf, ETHERTYPE_F, fs->val.ethtype,
- fs->mask.ethtype) ||
- unsupported(fconf, MACMATCH_F, fs->val.macidx, fs->mask.macidx) ||
- unsupported(fconf, MPSHITTYPE_F, fs->val.matchtype,
- fs->mask.matchtype) ||
- unsupported(fconf, FRAGMENTATION_F, fs->val.frag, fs->mask.frag) ||
- unsupported(fconf, PROTOCOL_F, fs->val.proto, fs->mask.proto) ||
- unsupported(fconf, VNIC_ID_F, fs->val.pfvf_vld,
- fs->mask.pfvf_vld) ||
- unsupported(fconf, VNIC_ID_F, fs->val.ovlan_vld,
- fs->mask.ovlan_vld) ||
- unsupported(fconf, VNIC_ID_F, fs->val.encap_vld,
- fs->mask.encap_vld) ||
- unsupported(fconf, VLAN_F, fs->val.ivlan_vld, fs->mask.ivlan_vld))
- return -EOPNOTSUPP;
-
+ if (chip_ver >= CHELSIO_T7) {
+ if (unsupported(fconf, T7_FCOE_F, fs->val.fcoe, fs->mask.fcoe) ||
+ unsupported(fconf, T7_PORT_F, fs->val.iport, fs->mask.iport) ||
+ unsupported(fconf, T7_TOS_F, fs->val.tos, fs->mask.tos) ||
+ unsupported(fconf, T7_ETHERTYPE_F, fs->val.ethtype,
+ fs->mask.ethtype) ||
+ unsupported(fconf, T7_MACMATCH_F, fs->val.macidx, fs->mask.macidx) ||
+ unsupported(fconf, T7_MPSHITTYPE_F, fs->val.matchtype,
+ fs->mask.matchtype) ||
+ unsupported(fconf, T7_FRAGMENTATION_F, fs->val.frag, fs->mask.frag) ||
+ unsupported(fconf, T7_PROTOCOL_F, fs->val.proto, fs->mask.proto) ||
+ unsupported(fconf, T7_VNIC_ID_F, fs->val.pfvf_vld,
+ fs->mask.pfvf_vld) ||
+ unsupported(fconf, T7_VNIC_ID_F, fs->val.ovlan_vld,
+ fs->mask.ovlan_vld) ||
+ unsupported(fconf, T7_VNIC_ID_F, fs->val.encap_vld,
+ fs->mask.encap_vld) ||
+ unsupported(fconf, T7_VLAN_F, fs->val.ivlan_vld, fs->mask.ivlan_vld) ||
+ unsupported(fconf, SYNONLY_F, fs->val.synonly, fs->mask.synonly))
+ return -EOPNOTSUPP;
+ } else {
+ if (unsupported(fconf, FCOE_F, fs->val.fcoe, fs->mask.fcoe) ||
+ unsupported(fconf, PORT_F, fs->val.iport, fs->mask.iport) ||
+ unsupported(fconf, TOS_F, fs->val.tos, fs->mask.tos) ||
+ unsupported(fconf, ETHERTYPE_F, fs->val.ethtype,
+ fs->mask.ethtype) ||
+ unsupported(fconf, MACMATCH_F, fs->val.macidx, fs->mask.macidx) ||
+ unsupported(fconf, MPSHITTYPE_F, fs->val.matchtype,
+ fs->mask.matchtype) ||
+ unsupported(fconf, FRAGMENTATION_F, fs->val.frag, fs->mask.frag) ||
+ unsupported(fconf, PROTOCOL_F, fs->val.proto, fs->mask.proto) ||
+ unsupported(fconf, VNIC_ID_F, fs->val.pfvf_vld,
+ fs->mask.pfvf_vld) ||
+ unsupported(fconf, VNIC_ID_F, fs->val.ovlan_vld,
+ fs->mask.ovlan_vld) ||
+ unsupported(fconf, VNIC_ID_F, fs->val.encap_vld,
+ fs->mask.encap_vld) ||
+ unsupported(fconf, VLAN_F, fs->val.ivlan_vld, fs->mask.ivlan_vld))
+ return -EOPNOTSUPP;
+ }
/* T4 inconveniently uses the same FT_VNIC_ID_W bits for both the Outer
* VLAN Tag and PF/VF/VFvld fields based on VNIC_F being set
* in TP_INGRESS_CONFIG. Hense the somewhat crazy checks
@@ -293,6 +320,8 @@ static int validate_filter(struct net_device *dev,
(is_field_set(fs->val.ovlan_vld, fs->mask.ovlan_vld) &&
(iconf & VNIC_F)))
return -EOPNOTSUPP;
+ if (chip_ver <= CHELSIO_T6 && is_field_set(fs->val.synonly, fs->mask.synonly))
+ return -EOPNOTSUPP;
if (fs->val.pf > 0x7 || fs->val.vf > 0x7f)
return -ERANGE;
fs->mask.pf &= 0x7;
@@ -993,7 +1022,9 @@ void clear_filter(struct adapter *adap, struct filter_entry *f)
t4_free_encap_mac_filt(adap, pi->viid,
f->fs.val.ovlan & 0x1ff, 0);
- if ((f->fs.hash || is_t6(adap->params.chip)) && f->fs.type)
+ if ((f->fs.hash ||
+ (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T6)) &&
+ f->fs.type)
cxgb4_clip_release(f->dev, (const u32 *)&f->fs.val.lip, 1);
/* The zeroing of the filter rule below clears the filter valid,
@@ -1296,20 +1327,15 @@ static void mk_act_open_req6(struct filter_entry *f, struct sk_buff *skb,
unsigned int qid_filterid, struct adapter *adap)
{
struct cpl_t6_act_open_req6 *t6req = NULL;
+ struct cpl_t7_act_open_req6 *t7req = NULL;
struct cpl_act_open_req6 *req = NULL;
+ u32 chip_ver, opt2;
+ u64 opt0;
- t6req = (struct cpl_t6_act_open_req6 *)__skb_put(skb, sizeof(*t6req));
- INIT_TP_WR(t6req, 0);
- req = (struct cpl_act_open_req6 *)t6req;
- OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6, qid_filterid));
- req->local_port = cpu_to_be16(f->fs.val.lport);
- req->peer_port = cpu_to_be16(f->fs.val.fport);
- req->local_ip_hi = *(__be64 *)(&f->fs.val.lip);
- req->local_ip_lo = *(((__be64 *)&f->fs.val.lip) + 1);
- req->peer_ip_hi = *(__be64 *)(&f->fs.val.fip);
- req->peer_ip_lo = *(((__be64 *)&f->fs.val.fip) + 1);
- req->opt0 = cpu_to_be64(NAGLE_V(f->fs.newvlan == VLAN_REMOVE ||
- f->fs.newvlan == VLAN_REWRITE) |
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ opt0 = cpu_to_be64(NAGLE_V(f->fs.newvlan == VLAN_REMOVE ||
+ f->fs.newvlan == VLAN_REWRITE) |
DELACK_V(f->fs.hitcnts) |
L2T_IDX_V(f->l2t ? f->l2t->idx : 0) |
SMAC_SEL_V((cxgb4_port_viid(f->dev) &
@@ -1319,52 +1345,87 @@ static void mk_act_open_req6(struct filter_entry *f, struct sk_buff *skb,
ULP_MODE_V(f->fs.nat_mode ?
ULP_MODE_TCPDDP : ULP_MODE_NONE) |
TCAM_BYPASS_F | NON_OFFLOAD_F);
- t6req->params = cpu_to_be64(FILTER_TUPLE_V(hash_filter_ntuple(&f->fs,
- f->dev)));
- t6req->opt2 = htonl(RSS_QUEUE_VALID_F |
- RSS_QUEUE_V(f->fs.iq) |
- TX_QUEUE_V(f->fs.nat_mode) |
- T5_OPT_2_VALID_F |
- RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
- PACE_V((f->fs.maskhash) |
+ opt2 = cpu_to_be32(RSS_QUEUE_VALID_F |
+ RSS_QUEUE_V(f->fs.iq) |
+ TX_QUEUE_V(f->fs.nat_mode) |
+ T5_OPT_2_VALID_F |
+ RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
+ PACE_V((f->fs.maskhash) |
((f->fs.dirsteerhash) << 1)));
+
+ if (chip_ver >= CHELSIO_T7) {
+ t7req = (struct cpl_t7_act_open_req6 *)__skb_put(skb, sizeof(*t7req));
+ INIT_TP_WR(t7req, 0);
+ req = (struct cpl_act_open_req6 *)t7req;
+ t7req->opt0 = opt0;
+ t7req->opt2 = opt2;
+ t7req->params = cpu_to_be64(T7_FILTER_TUPLE_V(hash_filter_ntuple(&f->fs, f->dev)));
+ } else {
+ t6req = (struct cpl_t6_act_open_req6 *)__skb_put(skb, sizeof(*t6req));
+ INIT_TP_WR(t6req, 0);
+ req = (struct cpl_act_open_req6 *)t6req;
+ t6req->opt0 = opt0;
+ t6req->opt2 = opt2;
+ t6req->params = cpu_to_be64(FILTER_TUPLE_V(hash_filter_ntuple(&f->fs, f->dev)));
+ }
+
+ OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6, qid_filterid));
+ req->local_port = cpu_to_be16(f->fs.val.lport);
+ req->peer_port = cpu_to_be16(f->fs.val.fport);
+ req->local_ip_hi = *(__be64 *)(&f->fs.val.lip);
+ req->local_ip_lo = *(((__be64 *)&f->fs.val.lip) + 1);
+ req->peer_ip_hi = *(__be64 *)(&f->fs.val.fip);
+ req->peer_ip_lo = *(((__be64 *)&f->fs.val.fip) + 1);
}
static void mk_act_open_req(struct filter_entry *f, struct sk_buff *skb,
unsigned int qid_filterid, struct adapter *adap)
{
struct cpl_t6_act_open_req *t6req = NULL;
+ struct cpl_t7_act_open_req *t7req = NULL;
struct cpl_act_open_req *req = NULL;
+ u32 chip_ver, opt2;
+ u64 opt0;
+
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
+
+ opt0 = cpu_to_be64(NAGLE_V(f->fs.newvlan == VLAN_REMOVE ||
+ f->fs.newvlan == VLAN_REWRITE) |
+ DELACK_V(f->fs.hitcnts) |
+ L2T_IDX_V(f->l2t ? f->l2t->idx : 0) |
+ SMAC_SEL_V((cxgb4_port_viid(f->dev) &
+ 0x7F) << 1) |
+ TX_CHAN_V(f->fs.eport) |
+ NO_CONG_V(f->fs.rpttid) |
+ ULP_MODE_V(f->fs.nat_mode ?
+ ULP_MODE_TCPDDP : ULP_MODE_NONE) |
+ TCAM_BYPASS_F | NON_OFFLOAD_F);
+ opt2 = cpu_to_be32(RSS_QUEUE_VALID_F |
+ RSS_QUEUE_V(f->fs.iq) |
+ TX_QUEUE_V(f->fs.nat_mode) |
+ T5_OPT_2_VALID_F |
+ RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
+ PACE_V((f->fs.maskhash) |
+ ((f->fs.dirsteerhash) << 1)));
+ if (chip_ver >= CHELSIO_T7) {
+ t7req = (struct cpl_t7_act_open_req *)__skb_put(skb, sizeof(*t7req));
+ INIT_TP_WR(t7req, 0);
+ req = (struct cpl_act_open_req *)t7req;
+ t7req->opt0 = opt0;
+ t7req->opt2 = opt2;
+ t7req->params = cpu_to_be64(T7_FILTER_TUPLE_V(hash_filter_ntuple(&f->fs, f->dev)));
+ } else {
+ t6req = (struct cpl_t6_act_open_req *)__skb_put(skb, sizeof(*t6req));
+ INIT_TP_WR(t6req, 0);
+ req = (struct cpl_act_open_req *)t6req;
+ t6req->opt0 = opt0;
+ t6req->opt2 = opt2;
+ t6req->params = cpu_to_be64(FILTER_TUPLE_V(hash_filter_ntuple(&f->fs, f->dev)));
+ }
- t6req = (struct cpl_t6_act_open_req *)__skb_put(skb, sizeof(*t6req));
- INIT_TP_WR(t6req, 0);
- req = (struct cpl_act_open_req *)t6req;
- OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ACT_OPEN_REQ, qid_filterid));
+ OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6, qid_filterid));
req->local_port = cpu_to_be16(f->fs.val.lport);
req->peer_port = cpu_to_be16(f->fs.val.fport);
- memcpy(&req->local_ip, f->fs.val.lip, 4);
- memcpy(&req->peer_ip, f->fs.val.fip, 4);
- req->opt0 = cpu_to_be64(NAGLE_V(f->fs.newvlan == VLAN_REMOVE ||
- f->fs.newvlan == VLAN_REWRITE) |
- DELACK_V(f->fs.hitcnts) |
- L2T_IDX_V(f->l2t ? f->l2t->idx : 0) |
- SMAC_SEL_V((cxgb4_port_viid(f->dev) &
- 0x7F) << 1) |
- TX_CHAN_V(f->fs.eport) |
- NO_CONG_V(f->fs.rpttid) |
- ULP_MODE_V(f->fs.nat_mode ?
- ULP_MODE_TCPDDP : ULP_MODE_NONE) |
- TCAM_BYPASS_F | NON_OFFLOAD_F);
-
- t6req->params = cpu_to_be64(FILTER_TUPLE_V(hash_filter_ntuple(&f->fs,
- f->dev)));
- t6req->opt2 = htonl(RSS_QUEUE_VALID_F |
- RSS_QUEUE_V(f->fs.iq) |
- TX_QUEUE_V(f->fs.nat_mode) |
- T5_OPT_2_VALID_F |
- RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
- PACE_V((f->fs.maskhash) |
- ((f->fs.dirsteerhash) << 1)));
}
static int cxgb4_set_hash_filter(struct net_device *dev,
@@ -1663,9 +1724,9 @@ int __cxgb4_set_filter(struct net_device *dev, int ftid,
if (ret)
goto free_tid;
- if (is_t6(adapter->params.chip) && fs->type &&
+ if (chip_ver >= CHELSIO_T6 && fs->type &&
ipv6_addr_type((const struct in6_addr *)fs->val.lip) !=
- IPV6_ADDR_ANY) {
+ IPV6_ADDR_ANY) {
ret = cxgb4_clip_get(dev, (const u32 *)&fs->val.lip, 1);
if (ret)
goto free_tid;
@@ -2140,12 +2201,13 @@ void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
void init_hash_filter(struct adapter *adap)
{
- u32 reg;
+ u32 reg, chip_ver;
+ chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
/* On T6, verify the necessary register configs and warn the user in
* case of improper config
*/
- if (is_t6(adap->params.chip)) {
+ if (chip_ver >= CHELSIO_T6) {
if (is_offload(adap)) {
if (!(t4_read_reg(adap, TP_GLOBAL_CONFIG_A)
& ACTIVEFILTERCOUNTS_F)) {
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index 9fccb8ea9bcd..c0f3eb22ad8d 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -496,8 +496,8 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
* mechanism.
*/
if (unlikely(q->bar2_addr == NULL)) {
- t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
- val | QID_V(q->cntxt_id));
+ writel(val | QID_V(q->cntxt_id),
+ adap->sge.tx_db_addr);
} else {
writel(val | QID_V(q->bar2_qid),
q->bar2_addr + SGE_UDB_KDOORBELL);
@@ -660,12 +660,13 @@ static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size,
{
size_t len = nelem * elem_size + stat_size;
void *s = NULL;
- void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL);
+ void *p = dma_alloc_coherent(dev, len, phys, GFP_NOWAIT);
- if (!p)
+ if (!p) {
return NULL;
+ }
if (sw_size) {
- s = kcalloc_node(sw_size, nelem, GFP_KERNEL, node);
+ s = kcalloc_node(sw_size, nelem, GFP_NOWAIT, node);
if (!s) {
dma_free_coherent(dev, len, p, *phys);
@@ -734,14 +735,14 @@ static inline int is_eth_imm(const struct sk_buff *skb, unsigned int chip_ver)
if (skb->encapsulation && skb_shinfo(skb)->gso_size &&
chip_ver > CHELSIO_T5) {
hdrlen = sizeof(struct cpl_tx_tnl_lso);
- hdrlen += sizeof(struct cpl_tx_pkt_core);
} else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
return 0;
} else {
hdrlen = skb_shinfo(skb)->gso_size ?
sizeof(struct cpl_tx_pkt_lso_core) : 0;
- hdrlen += sizeof(struct cpl_tx_pkt);
}
+
+ hdrlen += sizeof(struct cpl_tx_pkt);
if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen)
return hdrlen;
return 0;
@@ -1027,8 +1028,8 @@ inline void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
*/
spin_lock_irqsave(&q->db_lock, flags);
if (!q->db_disabled)
- t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
- QID_V(q->cntxt_id) | val);
+ writel(val | QID_V(q->cntxt_id),
+ adap->sge.tx_db_addr);
else
q->db_pidx_inc += n;
q->db_pidx = q->pidx;
@@ -1299,6 +1300,7 @@ enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb)
return tnl_type;
}
+EXPORT_SYMBOL(cxgb_encap_offload_supported);
static inline void t6_fill_tnl_lso(struct sk_buff *skb,
struct cpl_tx_tnl_lso *tnl_lso,
@@ -1510,6 +1512,7 @@ static netdev_tx_t cxgb4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
pi = netdev_priv(dev);
adap = pi->adapter;
ssi = skb_shinfo(skb);
+
#if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE)
if (xfrm_offload(skb) && !ssi->gso_size)
return adap->uld[CXGB4_ULD_IPSEC].tx_handler(skb, dev);
@@ -1690,7 +1693,7 @@ static netdev_tx_t cxgb4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
#endif /* CONFIG_CHELSIO_T4_FCOE */
}
- ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) |
+ ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->lport) |
TXPKT_PF_V(adap->pf);
if (ptp_enabled)
ctrl0 |= TXPKT_TSTAMP_F;
@@ -1996,7 +1999,7 @@ static netdev_tx_t cxgb4_vf_eth_xmit(struct sk_buff *skb,
/* Fill in the TX Packet CPL message header. */
cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) |
- TXPKT_INTF_V(pi->port_id) |
+ TXPKT_INTF_V(pi->lport) |
TXPKT_PF_V(0));
cpl->pack = cpu_to_be16(0);
cpl->len = cpu_to_be16(skb->len);
@@ -3036,6 +3039,7 @@ static void service_ofldq(struct sge_uld_txq *q)
__skb_unlink(skb, &q->sendq);
if (is_ofld_imm(skb))
kfree_skb(skb);
+
}
if (likely(written))
cxgb4_ring_tx_db(q->adap, &q->q, written);
@@ -3662,17 +3666,17 @@ static int cxgb4_validate_lb_pkt(struct port_info *pi, const struct pkt_gl *si)
int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
const struct pkt_gl *si)
{
- bool csum_ok;
- struct sk_buff *skb;
- const struct cpl_rx_pkt *pkt;
struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
struct adapter *adapter = q->adap;
struct sge *s = &q->adap->sge;
int cpl_trace_pkt = is_t4(q->adap->params.chip) ?
CPL_TRACE_PKT : CPL_TRACE_PKT_T5;
u16 err_vec, tnl_hdr_len = 0;
+ const struct cpl_rx_pkt *pkt;
+ struct sk_buff *skb;
struct port_info *pi;
int ret = 0;
+ bool csum_ok;
pi = netdev_priv(q->netdev);
/* If we're looking at TX Queue CIDX Update, handle that separately
@@ -4011,8 +4015,8 @@ static int napi_rx_handler(struct napi_struct *napi, int budget)
* doorbell mechanism; otherwise use the new BAR2 mechanism.
*/
if (unlikely(q->bar2_addr == NULL)) {
- t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
- val | INGRESSQID_V((u32)q->cntxt_id));
+ writel(val | INGRESSQID_V((u32)q->cntxt_id),
+ q->adap->sge.rx_db_addr);
} else {
writel(val | INGRESSQID_V(q->bar2_qid),
q->bar2_addr + SGE_UDB_GTS);
@@ -4346,6 +4350,9 @@ static void __iomem *bar2_address(struct adapter *adapter,
u64 bar2_qoffset;
int ret;
+ if (!adapter->bar2)
+ return NULL;
+
ret = t4_bar2_sge_qregs(adapter, qid, qtype, 0,
&bar2_qoffset, pbar2_qid);
if (ret)
@@ -4389,7 +4396,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
FW_IQ_CMD_IQANUD_V(UPDATEDELIVERY_INTERRUPT_X) |
FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx :
-intr_idx - 1));
- c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) |
+ c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(cxgb4_port_chan(dev)) |
FW_IQ_CMD_IQGTSMODE_F |
FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) |
FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4));
@@ -4409,17 +4416,19 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
* descriptor ring. The free list size needs to be a multiple
* of the Egress Queue Unit and at least 2 Egress Units larger
* than the SGE's Egress Congrestion Threshold
- * (fl_starve_thres - 1).
+ * (fl_starve_thres).
*/
- if (fl->size < s->fl_starve_thres - 1 + 2 * 8)
- fl->size = s->fl_starve_thres - 1 + 2 * 8;
+ if (fl->size < s->fl_starve_thres + 2 * 8)
+ fl->size = s->fl_starve_thres + 2 * 8;
fl->size = roundup(fl->size, 8);
fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64),
sizeof(struct rx_sw_desc), &fl->addr,
&fl->sdesc, s->stat_len,
dev_to_node(adap->pdev_dev));
- if (!fl->desc)
- goto fl_nomem;
+ if (!fl->desc) {
+ ret = -ENOMEM;
+ goto err;
+ }
flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F |
@@ -4532,8 +4541,6 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
return 0;
-fl_nomem:
- ret = -ENOMEM;
err:
if (iq->desc) {
dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len,
@@ -4576,7 +4583,7 @@ static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
*/
int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
struct net_device *dev, struct netdev_queue *netdevq,
- unsigned int iqid, u8 dbqt)
+ unsigned int iqid, u8 dbqt, int index)
{
unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
struct port_info *pi = netdev_priv(dev);
@@ -4584,6 +4591,9 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
struct fw_eq_eth_cmd c;
int ret, nentries;
+ if (adap->params.num_up_cores > 1)
+ txq->group_id = index % adap->params.num_up_cores;
+
/* Add status entries */
nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
@@ -4600,7 +4610,9 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
FW_EQ_ETH_CMD_PFN_V(adap->pf) |
FW_EQ_ETH_CMD_VFN_V(0));
c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F |
- FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c));
+ FW_EQ_ETH_CMD_EQSTART_F |
+ FW_EQ_ETH_CMD_COREGROUP_V(txq->group_id) |
+ (sizeof(c) / 16));
/* For TX Ethernet Queues using the SGE Doorbell Queue Timer
* mechanism, we use Ingress Queue messages for Hardware Consumer
@@ -4617,7 +4629,7 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V((chip_ver <= CHELSIO_T5) ?
HOSTFCMODE_INGRESS_QUEUE_X :
HOSTFCMODE_STATUS_PAGE_X) |
- FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) |
+ FW_EQ_ETH_CMD_PCIECHN_V(cxgb4_port_chan(dev)) |
FW_EQ_ETH_CMD_FETCHRO_F | FW_EQ_ETH_CMD_IQID_V(iqid));
/* Note that the CIDX Flush Threshold should match MAX_TX_RECLAIM. */
@@ -4644,18 +4656,12 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
FW_EQ_ETH_CMD_TIMERIX_V(txq->dbqtimerix));
ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
- if (ret) {
- kfree(txq->q.sdesc);
- txq->q.sdesc = NULL;
- dma_free_coherent(adap->pdev_dev,
- nentries * sizeof(struct tx_desc),
- txq->q.desc, txq->q.phys_addr);
- txq->q.desc = NULL;
- return ret;
- }
+ if (ret < 0)
+ goto out_free_txq;
txq->q.q_type = CXGB4_TXQ_ETH;
init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd)));
+
txq->txq = netdevq;
txq->tso = 0;
txq->uso = 0;
@@ -4663,19 +4669,30 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
txq->vlan_ins = 0;
txq->mapping_err = 0;
txq->dbqt = dbqt;
-
return 0;
+
+out_free_txq:
+ kfree(txq->q.sdesc);
+ txq->q.sdesc = NULL;
+ dma_free_coherent(adap->pdev_dev, nentries * sizeof(struct tx_desc),
+ txq->q.desc, txq->q.phys_addr);
+ txq->q.desc = NULL;
+ return ret;
}
int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
struct net_device *dev, unsigned int iqid,
- unsigned int cmplqid)
+ unsigned int cmplqid, int index)
{
unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
- struct port_info *pi = netdev_priv(dev);
struct sge *s = &adap->sge;
struct fw_eq_ctrl_cmd c;
- int ret, nentries;
+ int ret, nentries, ngroups;
+
+ ngroups = (adap->params.tid_qid_sel_mask >>
+ adap->params.tid_qid_sel_shift) + 1;
+ if (adap->params.tid_qid_sel_mask)
+ txq->tid_qid_group_id = index % ngroups;
/* Add status entries */
nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
@@ -4691,12 +4708,14 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
FW_EQ_CTRL_CMD_PFN_V(adap->pf) |
FW_EQ_CTRL_CMD_VFN_V(0));
c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F |
- FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c));
+ FW_EQ_CTRL_CMD_EQSTART_F |
+ FW_EQ_CTRL_CMD_COREGROUP_V(txq->tid_qid_group_id) |
+ (sizeof(c) / 16));
c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid));
c.physeqid_pkd = htonl(0);
c.fetchszm_to_iqid =
htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) |
- FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) |
+ FW_EQ_CTRL_CMD_PCIECHN_V(cxgb4_port_chan(dev)) |
FW_EQ_CTRL_CMD_FETCHRO_F | FW_EQ_CTRL_CMD_IQID_V(iqid));
c.dcaen_to_eqsize =
htonl(FW_EQ_CTRL_CMD_FBMIN_V(chip_ver <= CHELSIO_T5
@@ -4708,21 +4727,23 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
c.eqaddr = cpu_to_be64(txq->q.phys_addr);
ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
- if (ret) {
- dma_free_coherent(adap->pdev_dev,
- nentries * sizeof(struct tx_desc),
- txq->q.desc, txq->q.phys_addr);
- txq->q.desc = NULL;
- return ret;
- }
+ if (ret < 0)
+ goto out_free_ctrlq;
- txq->q.q_type = CXGB4_TXQ_CTRL;
init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid)));
+
+ txq->q.q_type = CXGB4_TXQ_CTRL;
txq->adap = adap;
skb_queue_head_init(&txq->sendq);
tasklet_setup(&txq->qresume_tsk, restart_ctrlq);
txq->full = 0;
return 0;
+
+out_free_ctrlq:
+ dma_free_coherent(adap->pdev_dev, nentries * sizeof(struct tx_desc),
+ txq->q.desc, txq->q.phys_addr);
+ txq->q.desc = NULL;
+ return ret;
}
int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
@@ -5182,6 +5203,7 @@ int t4_sge_init(struct adapter *adap)
egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
break;
case CHELSIO_T6:
+ case CHELSIO_T7:
egress_threshold = T6_EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
break;
default:
--
2.39.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH net-next v1 01/10] cxgb4: Add T7 register definitions and core structures
2026-06-07 3:52 ` [PATCH net-next v1 01/10] cxgb4: Add T7 register definitions and core structures Potnuri Bharat Teja
@ 2026-06-07 7:02 ` Andrew Lunn
0 siblings, 0 replies; 13+ messages in thread
From: Andrew Lunn @ 2026-06-07 7:02 UTC (permalink / raw)
To: Potnuri Bharat Teja; +Cc: netdev, davem, kuba, edumazet, pabeni, andrew+netdev
> +/**
> + * t4_os_lock_init - initialize spinlock
> + * @lock: the spinlock
> + */
> +static inline void t4_os_lock_init(spinlock_t *lock)
> +{
> + spin_lock_init(lock);
> +}
What is the point of this wrapper function. It does nothing.
Andrew
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
` (9 preceding siblings ...)
2026-06-07 3:52 ` [PATCH net-next v1 10/10] cxgb4: Update SGE path and filtering logic for T7 Potnuri Bharat Teja
@ 2026-06-08 21:13 ` Jakub Kicinski
10 siblings, 0 replies; 13+ messages in thread
From: Jakub Kicinski @ 2026-06-08 21:13 UTC (permalink / raw)
To: Potnuri Bharat Teja; +Cc: netdev, davem, edumazet, pabeni, andrew+netdev
On Sat, 6 Jun 2026 23:52:10 -0400 Potnuri Bharat Teja wrote:
> This patch series introduces base support for the next-generation Chelsio
> T7 adapter family into the cxgb4 driver.
Oh wow! I thought y'all disappeared.
There have been >50 patches to cxgb4 driver over the last 3 years.
Quick grep suggests that Chelsio only bothered reviewing a single one.
You are not fulfilling your responsibilities:
https://docs.kernel.org/next/maintainer/feature-and-driver-maintainers.html
This is not right, don't you think?
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-06-08 21:13 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-06-07 3:52 [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 01/10] cxgb4: Add T7 register definitions and core structures Potnuri Bharat Teja
2026-06-07 7:02 ` Andrew Lunn
2026-06-07 3:52 ` [PATCH net-next v1 02/10] cxgb4: Add T7 chip type identification and HW constants Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 03/10] cxgb4: Add T7 CPL messages, FW constants, and PCI IDs Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 04/10] cxgb4: Add versioned structures and scratch buffs Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 05/10] cxgb4: Add T7 indirect regs and update library Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 06/10] cxgb4: Move PCI initialization logic to cxgb4_pci.c Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 07/10] cxgb4: Extend hardware abstraction layer for T7 logs Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 08/10] cxgb4: Update driver lifecycle and peripherals for T7 Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 09/10] cxgb4: Update debugfs interface for T7 versioned structures Potnuri Bharat Teja
2026-06-07 3:52 ` [PATCH net-next v1 10/10] cxgb4: Update SGE path and filtering logic for T7 Potnuri Bharat Teja
2026-06-08 21:13 ` [PATCH net-next v1 0/10] cxgb4: Add Chelsio T7 support Jakub Kicinski
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