[PATCH net] net: ag71xx: let both QCA9550 MACs use MII, RGMII and SGMII

[PATCH net] net: ag71xx: let both QCA9550 MACs use MII, RGMII and SGMII

[Rosen Penev]

The GE0_SGMII bit of the QCA955x ETH_CFG register selects which GMAC
gets the SerDes (QCA9558 datasheet, 10.8.1): when it is clear, GMAC0
connects as RGMII/MII and GMAC1 as SGMII, and when it is set, the other
way around. The driver only allows the second layout, with SGMII on
GMAC0 and RGMII/MII on GMAC1, but boards like the TP-Link Archer C7
use the first one, with GMAC0 on RGMII.

Allow MII, RGMII and SGMII on both MACs.

Tested on Archer C7 v2. RGMII on port 0 of the switch works.

Fixes: 0767ec042897 ("net: ag71xx: extend link validation to support other SoCs")
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
 drivers/net/ethernet/atheros/ag71xx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c
index 16434a7139bc..b2d78819a0a2 100644
--- a/drivers/net/ethernet/atheros/ag71xx.c
+++ b/drivers/net/ethernet/atheros/ag71xx.c
@@ -1079,7 +1079,7 @@ static int ag71xx_phylink_setup(struct ag71xx *ag)
 	if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) ||
 	    ag71xx_is(ag, AR9340) ||
 	    ag71xx_is(ag, QCA9530) ||
-	    (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1))
+	    ag71xx_is(ag, QCA9550))
 		__set_bit(PHY_INTERFACE_MODE_MII,
 			  ag->phylink_config.supported_interfaces);
 
@@ -1089,7 +1089,7 @@ static int ag71xx_phylink_setup(struct ag71xx *ag)
 		__set_bit(PHY_INTERFACE_MODE_GMII,
 			  ag->phylink_config.supported_interfaces);
 
-	if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0)
+	if (ag71xx_is(ag, QCA9550))
 		__set_bit(PHY_INTERFACE_MODE_SGMII,
 			  ag->phylink_config.supported_interfaces);
 
@@ -1098,7 +1098,7 @@ static int ag71xx_phylink_setup(struct ag71xx *ag)
 			  ag->phylink_config.supported_interfaces);
 
 	if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) ||
-	    (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1))
+	    ag71xx_is(ag, QCA9550))
 		__set_bit(PHY_INTERFACE_MODE_RGMII,
 			  ag->phylink_config.supported_interfaces);
 
-- 
2.56.0

Re: [PATCH net] net: ag71xx: let both QCA9550 MACs use MII, RGMII and SGMII

[Paolo Abeni]

On 11/6/26 23:16, Rosen Penev wrote:
> The GE0_SGMII bit of the QCA955x ETH_CFG register selects which GMAC
> gets the SerDes (QCA9558 datasheet, 10.8.1): when it is clear, GMAC0
> connects as RGMII/MII and GMAC1 as SGMII, and when it is set, the other
> way around. The driver only allows the second layout, with SGMII on
> GMAC0 and RGMII/MII on GMAC1, but boards like the TP-Link Archer C7
> use the first one, with GMAC0 on RGMII.
> 
> Allow MII, RGMII and SGMII on both MACs.
> 
> Tested on Archer C7 v2. RGMII on port 0 of the switch works.
> 
> Fixes: 0767ec042897 ("net: ag71xx: extend link validation to support other SoCs")
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
IMHO this is not net material.

Applying to net-next.

/P

Re: [PATCH net] net: ag71xx: let both QCA9550 MACs use MII, RGMII and SGMII

[patchwork-bot+netdevbpf]

Hello:

This patch was applied to netdev/net-next.git (main)
by Paolo Abeni <pabeni@redhat.com>:

On Fri,  6 Nov 2026 14:16:07 -0800 you wrote:
> The GE0_SGMII bit of the QCA955x ETH_CFG register selects which GMAC
> gets the SerDes (QCA9558 datasheet, 10.8.1): when it is clear, GMAC0
> connects as RGMII/MII and GMAC1 as SGMII, and when it is set, the other
> way around. The driver only allows the second layout, with SGMII on
> GMAC0 and RGMII/MII on GMAC1, but boards like the TP-Link Archer C7
> use the first one, with GMAC0 on RGMII.
> 
> [...]

Here is the summary with links:
  - [net] net: ag71xx: let both QCA9550 MACs use MII, RGMII and SGMII
    https://git.kernel.org/netdev/net-next/c/7cb4cf087038

You are awesome, thank you!
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