[PATCH 0/9] RK3588: Enable the PHP SMMU

[PATCH 0/9] RK3588: Enable the PHP SMMU

[Arun Iyengar via B4 Relay]

The RK3588 PHP SMMU (MMU600_PHP) is disabled because nothing programs
the StreamIDs of its masters (GMAC0/1, SATA0-2, USB3OTG_2) in the PHP
GRF. Program them, attach the masters and enable the SMMU.

Shawn Lin asked whether mmu600_php should be enabled too; Heiko asked
for the same handling as the PCIe SMMU [3].

Patch 7 needs [1]. Please hold the last patch until [2] is merged:
PD_PHP is off in deep suspend and the SMMU resumes in bypass (GBPA read
as 0).

Tested on an Orange Pi 5 (RK3588S), 7.3-based with [2] (my Tested-by
is [4]):
- SATA0 root, GMAC1 and a USB3 disk translated: 1 GiB sha256-checked
  on each; three reboots; no SMMU events or bus errors;
- deep suspend 3/3 with all three translated; s2idle 3/3 with USB3OTG_2
  and GMAC1. TF-A v2.15 kept the StreamIDs; patch 6 restored six zeroed
  for the test (pm_test=core).
Not tested: GMAC0, SATA1/2, the series without [2], the reset (no
driver uses it).

Developed with Claude (Anthropic), which wrote the code and the commit
messages. I reviewed every change.

[1] https://lore.kernel.org/r/20261113-smmu-v3-pcie-pd-v3-0-39eb4f919529@gmail.com
[2] https://lore.kernel.org/r/20260929034510.2023173-1-praan@google.com
[3] https://lore.kernel.org/r/9_7qTfdNSViwtNUGq9D13w@sntech.de
[4] https://lore.kernel.org/r/179455903885.2418534.14656921897583011972@gmail.com

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
Arun Iyengar (9):
      dt-bindings: net: rockchip-dwmac: Allow iommus
      dt-bindings: ata: rockchip,dwc-ahci: Allow iommus
      dt-bindings: soc: rockchip: grf: Allow a clock for the RK3588 PHP GRF
      soc: rockchip: grf: Assign the StreamIDs of the RK3588 PHP SMMU masters
      arm64: dts: rockchip: Add the PHP GRF clock on RK3588
      soc: rockchip: grf: Restore the RK3588 PHP StreamIDs after system suspend
      arm64: dts: rockchip: Add the clock and reset of the RK3588 PHP SMMU
      arm64: dts: rockchip: Attach the masters of the RK3588 PHP SMMU
      arm64: dts: rockchip: Enable the RK3588 PHP SMMU

 .../devicetree/bindings/ata/rockchip,dwc-ahci.yaml |   3 +
 .../devicetree/bindings/net/rockchip-dwmac.yaml    |   3 +
 .../devicetree/bindings/soc/rockchip/grf.yaml      |  12 ++-
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi      |   8 +-
 arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi     |   2 +
 drivers/soc/rockchip/grf.c                         | 103 +++++++++++++++++++++
 6 files changed, 128 insertions(+), 3 deletions(-)
---
base-commit: c3baae5f1a15645cddadcb2b9abddef5df291f59
change-id: 20261113-mmu600-php-0367fe7f1609
prerequisite-message-id: <20261113-smmu-v3-pcie-pd-v3-0-39eb4f919529@gmail.com>
prerequisite-patch-id: 51134fb38514fa92f20d3831e7905b02c7fbaae6
prerequisite-patch-id: c59ab0be12ec964dc1698dfa3e0d5bfae82d0c54
prerequisite-patch-id: 845e9980a7e0de45c746b7d8b6fd439033e08fdd

Best regards,
--  
Arun Iyengar <aiyengar1990@gmail.com>

[PATCH 1/9] dt-bindings: net: rockchip-dwmac: Allow iommus

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

The RK3588 GMACs are behind the PHP SMMU. Allow iommus.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 Documentation/devicetree/bindings/net/rockchip-dwmac.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
index e8dda1961ab3..2a0cd56fb4fe 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
@@ -87,6 +87,9 @@ properties:
 
   dma-coherent: true
 
+  iommus:
+    maxItems: 1
+
   clock_in_out:
     description:
       For RGMII, it must be "input", means main clock(125MHz)

-- 
2.55.0

[PATCH 2/9] dt-bindings: ata: rockchip,dwc-ahci: Allow iommus

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

The RK3588 SATA controllers are behind the PHP SMMU. Allow iommus, as
snps,dwc-ahci does.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
index b5ecaabfe2e2..e33e8b5591ee 100644
--- a/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
+++ b/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
@@ -34,6 +34,9 @@ properties:
           - rockchip,rk3588-dwc-ahci
       - const: snps,dwc-ahci
 
+  iommus:
+    maxItems: 1
+
   ports-implemented:
     const: 1
 

-- 
2.55.0

[PATCH 3/9] dt-bindings: soc: rockchip: grf: Allow a clock for the RK3588 PHP GRF

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

The RK3588 PHP GRF is clocked from pclk_php_root, which is gated when
no PHP peripheral holds it. Allow the clock, so the syscon regmap
enables it.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index e94c83d7c138..2525eb51f13b 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -321,8 +321,16 @@ allOf:
         - clocks
 
     else:
-      properties:
-        clocks: false
+      if:
+        not:
+          properties:
+            compatible:
+              contains:
+                const: rockchip,rk3588-php-grf
+
+      then:
+        properties:
+          clocks: false
 
 examples:
   - |

-- 
2.55.0

[PATCH 4/9] soc: rockchip: grf: Assign the StreamIDs of the RK3588 PHP SMMU masters

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

The StreamIDs of the six masters behind the RK3588 PHP SMMU come from
PHP GRF registers that reset to 0 and are never programmed, so the SMMU
can not tell the masters apart.

Assign StreamIDs 1-6 on both AXI channels. 0 stays unused, so a master
that loses its ID is aborted instead of using another device's tables.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 drivers/soc/rockchip/grf.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
index b459607c118a..3f0f82a2119f 100644
--- a/drivers/soc/rockchip/grf.c
+++ b/drivers/soc/rockchip/grf.c
@@ -168,6 +168,40 @@ static const struct rockchip_grf_info rk3588_sysgrf __initconst = {
 	.num_values = ARRAY_SIZE(rk3588_defaults),
 };
 
+/* PHP SMMU StreamIDs: bits 15:0, no write-enable mask */
+#define RK3588_PHP_GRF_GMAC0_SID_AW	0x0074
+#define RK3588_PHP_GRF_GMAC1_SID_AW	0x007c
+#define RK3588_PHP_GRF_SATA0_SID_AW	0x0084
+#define RK3588_PHP_GRF_SATA1_SID_AW	0x008c
+#define RK3588_PHP_GRF_SATA2_SID_AW	0x0094
+#define RK3588_PHP_GRF_GMAC0_SID_AR	0x009c
+#define RK3588_PHP_GRF_GMAC1_SID_AR	0x00a4
+#define RK3588_PHP_GRF_SATA0_SID_AR	0x00ac
+#define RK3588_PHP_GRF_SATA1_SID_AR	0x00b4
+#define RK3588_PHP_GRF_SATA2_SID_AR	0x00bc
+#define RK3588_PHP_GRF_USB3OTG2_SID_AR	0x00c4
+#define RK3588_PHP_GRF_USB3OTG2_SID_AW	0x00cc
+
+static const struct rockchip_grf_value rk3588_defaults_php_grf[] __initconst = {
+	{ "gmac0 write streamid", RK3588_PHP_GRF_GMAC0_SID_AW, 1 },
+	{ "gmac0 read streamid", RK3588_PHP_GRF_GMAC0_SID_AR, 1 },
+	{ "gmac1 write streamid", RK3588_PHP_GRF_GMAC1_SID_AW, 2 },
+	{ "gmac1 read streamid", RK3588_PHP_GRF_GMAC1_SID_AR, 2 },
+	{ "sata0 write streamid", RK3588_PHP_GRF_SATA0_SID_AW, 3 },
+	{ "sata0 read streamid", RK3588_PHP_GRF_SATA0_SID_AR, 3 },
+	{ "sata1 write streamid", RK3588_PHP_GRF_SATA1_SID_AW, 4 },
+	{ "sata1 read streamid", RK3588_PHP_GRF_SATA1_SID_AR, 4 },
+	{ "sata2 write streamid", RK3588_PHP_GRF_SATA2_SID_AW, 5 },
+	{ "sata2 read streamid", RK3588_PHP_GRF_SATA2_SID_AR, 5 },
+	{ "usb3otg2 write streamid", RK3588_PHP_GRF_USB3OTG2_SID_AW, 6 },
+	{ "usb3otg2 read streamid", RK3588_PHP_GRF_USB3OTG2_SID_AR, 6 },
+};
+
+static const struct rockchip_grf_info rk3588_phpgrf __initconst = {
+	.values = rk3588_defaults_php_grf,
+	.num_values = ARRAY_SIZE(rk3588_defaults_php_grf),
+};
+
 static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
 	{
 		.compatible = "rockchip,rk3036-grf",
@@ -202,6 +236,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
 	}, {
 		.compatible = "rockchip,rk3576-ioc-grf",
 		.data = (void *)&rk3576_iocgrf,
+	}, {
+		.compatible = "rockchip,rk3588-php-grf",
+		.data = (void *)&rk3588_phpgrf,
 	}, {
 		.compatible = "rockchip,rk3588-sys-grf",
 		.data = (void *)&rk3588_sysgrf,

-- 
2.55.0

[PATCH 5/9] arm64: dts: rockchip: Add the PHP GRF clock on RK3588

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

Once the PHP peripherals suspend, pclk_php_root is gated and a PHP GRF
access hangs; the syscore resume op of the next patch hung deep suspend
this way. Add the clock, so the syscon regmap enables it.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index d0f364547ae5..8807ce6193bf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -619,6 +619,7 @@ usb_grf: syscon@fd5ac000 {
 	php_grf: syscon@fd5b0000 {
 		compatible = "rockchip,rk3588-php-grf", "syscon";
 		reg = <0x0 0xfd5b0000 0x0 0x1000>;
+		clocks = <&cru PCLK_PHP_ROOT>;
 	};
 
 	csidphy0_grf: syscon@fd5b4000 {

-- 
2.55.0

[PATCH 6/9] soc: rockchip: grf: Restore the RK3588 PHP StreamIDs after system suspend

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

The PHP GRF is in PD_PHP, which firmware may power off in system
suspend. The SMMU aborts a master whose StreamID was lost.

Write the StreamIDs again from a syscore resume op, before devices
resume. Register it only when the node has a clock, as the access hangs
without it.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 drivers/soc/rockchip/grf.c | 70 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 68 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
index 3f0f82a2119f..8f318ebc14e9 100644
--- a/drivers/soc/rockchip/grf.c
+++ b/drivers/soc/rockchip/grf.c
@@ -11,6 +11,8 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/syscore_ops.h>
 
 
 struct rockchip_grf_value {
@@ -22,6 +24,14 @@ struct rockchip_grf_value {
 struct rockchip_grf_info {
 	const struct rockchip_grf_value *values;
 	int num_values;
+	/* Rewrite the values on resume; such tables must not be __initconst */
+	bool restore_on_resume;
+};
+
+struct rockchip_grf_restore {
+	struct syscore syscore;
+	struct regmap *grf;
+	const struct rockchip_grf_info *info;
 };
 
 #define RK3036_GRF_SOC_CON0		0x140
@@ -182,7 +192,7 @@ static const struct rockchip_grf_info rk3588_sysgrf __initconst = {
 #define RK3588_PHP_GRF_USB3OTG2_SID_AR	0x00c4
 #define RK3588_PHP_GRF_USB3OTG2_SID_AW	0x00cc
 
-static const struct rockchip_grf_value rk3588_defaults_php_grf[] __initconst = {
+static const struct rockchip_grf_value rk3588_defaults_php_grf[] = {
 	{ "gmac0 write streamid", RK3588_PHP_GRF_GMAC0_SID_AW, 1 },
 	{ "gmac0 read streamid", RK3588_PHP_GRF_GMAC0_SID_AR, 1 },
 	{ "gmac1 write streamid", RK3588_PHP_GRF_GMAC1_SID_AW, 2 },
@@ -197,9 +207,10 @@ static const struct rockchip_grf_value rk3588_defaults_php_grf[] __initconst = {
 	{ "usb3otg2 read streamid", RK3588_PHP_GRF_USB3OTG2_SID_AR, 6 },
 };
 
-static const struct rockchip_grf_info rk3588_phpgrf __initconst = {
+static const struct rockchip_grf_info rk3588_phpgrf = {
 	.values = rk3588_defaults_php_grf,
 	.num_values = ARRAY_SIZE(rk3588_defaults_php_grf),
+	.restore_on_resume = true,
 };
 
 static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
@@ -246,6 +257,59 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
 	{ /* sentinel */ },
 };
 
+/* Syscore op: runs before the SMMU and its masters resume */
+static void rockchip_grf_resume(void *data)
+{
+	struct rockchip_grf_restore *restore = data;
+	const struct rockchip_grf_info *info = restore->info;
+	unsigned int cur;
+	int i, lost = 0;
+
+	for (i = 0; i < info->num_values; i++) {
+		const struct rockchip_grf_value *val = &info->values[i];
+
+		if (!regmap_read(restore->grf, val->reg, &cur) && cur == val->val)
+			continue;
+
+		lost++;
+		if (regmap_write(restore->grf, val->reg, val->val))
+			pr_err("%s: restoring %s in %#6x failed\n", __func__,
+			       val->desc, val->reg);
+	}
+
+	if (lost)
+		pr_info("%s: restored %d of %d values lost in suspend\n",
+			__func__, lost, info->num_values);
+}
+
+static const struct syscore_ops rockchip_grf_syscore_ops = {
+	.resume = rockchip_grf_resume,
+};
+
+static void __init rockchip_grf_register_restore(struct device_node *np,
+						 struct regmap *grf,
+						 const struct rockchip_grf_info *info)
+{
+	struct rockchip_grf_restore *restore;
+
+	if (!IS_ENABLED(CONFIG_PM_SLEEP) || !info->restore_on_resume)
+		return;
+
+	/* Without its bus clock the GRF is not accessible in syscore resume */
+	if (!of_property_present(np, "clocks"))
+		return;
+
+	restore = kzalloc_obj(*restore);
+	if (!restore)
+		return;
+
+	restore->grf = grf;
+	restore->info = info;
+	restore->syscore.ops = &rockchip_grf_syscore_ops;
+	restore->syscore.data = restore;
+	register_syscore(&restore->syscore);
+}
+
 static int __init rockchip_grf_init(void)
 {
 	const struct rockchip_grf_info *grf_info;
@@ -282,6 +346,8 @@ static int __init rockchip_grf_init(void)
 				pr_err("%s: write to %#6x failed with %d\n",
 					__func__, val->reg, ret);
 		}
+
+		rockchip_grf_register_restore(np, grf, grf_info);
 	}
 
 	return 0;

-- 
2.55.0

[PATCH 7/9] arm64: dts: rockchip: Add the clock and reset of the RK3588 PHP SMMU

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

Describe ACLK_MMU_PHP, so the SMMU keeps its clock while its masters
are idle, and SRST_A_MMU_PHP, as for the PCIe SMMU.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 8807ce6193bf..3bf8d0e4ff33 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -570,6 +570,8 @@ mmu600_php: iommu@fcb00000 {
 			     <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>,
 			     <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>;
 		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+		clocks = <&cru ACLK_MMU_PHP>;
+		resets = <&cru SRST_A_MMU_PHP>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};

-- 
2.55.0

[PATCH 8/9] arm64: dts: rockchip: Attach the masters of the RK3588 PHP SMMU

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

GMAC0/1, SATA0-2 and USB3OTG_2 are behind MMU600_PHP with StreamIDs
1-6. No effect until the SMMU is enabled.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi  | 4 ++++
 arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 3bf8d0e4ff33..cb0a39f63788 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -534,6 +534,7 @@ usb_host2_xhci: usb@fcd00000 {
 		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
 		reg = <0x0 0xfcd00000 0x0 0x400000>;
 		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
+		iommus = <&mmu600_php 6>;
 		clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
 			 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
 			 <&cru CLK_PIPEPHY2_PIPE_U3_G>;
@@ -2310,6 +2311,7 @@ gmac1: ethernet@fe1c0000 {
 		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
 			     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
 		interrupt-names = "macirq", "eth_wake_irq";
+		iommus = <&mmu600_php 2>;
 		clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
 			 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
 			 <&cru CLK_GMAC1_PTP_REF>;
@@ -2357,6 +2359,7 @@ sata0: sata@fe210000 {
 		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
 		reg = <0 0xfe210000 0 0x1000>;
 		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
+		iommus = <&mmu600_php 3>;
 		clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
 			 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
 			 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
@@ -2380,6 +2383,7 @@ sata2: sata@fe230000 {
 		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
 		reg = <0 0xfe230000 0 0x1000>;
 		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
+		iommus = <&mmu600_php 5>;
 		clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
 			 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
 			 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
index 2bcf30d8a338..425770a8ff61 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -538,6 +538,7 @@ gmac0: ethernet@fe1b0000 {
 		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
 			     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
 		interrupt-names = "macirq", "eth_wake_irq";
+		iommus = <&mmu600_php 1>;
 		clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
 			 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
 			 <&cru CLK_GMAC0_PTP_REF>;
@@ -585,6 +586,7 @@ sata1: sata@fe220000 {
 		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
 		reg = <0 0xfe220000 0 0x1000>;
 		interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+		iommus = <&mmu600_php 4>;
 		clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
 			 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
 			 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;

-- 
2.55.0

[PATCH 9/9] arm64: dts: rockchip: Enable the RK3588 PHP SMMU

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

Its masters now have StreamIDs and iommus, and the SMMU has its clock.

PD_PHP is powered off in deep suspend and the SMMU resumes from reset
in bypass, so this needs arm-smmu-v3 system sleep support [1].

Link: https://lore.kernel.org/r/20260929034510.2023173-1-praan@google.com [1]
Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index cb0a39f63788..0c3d59a39182 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -574,7 +574,6 @@ mmu600_php: iommu@fcb00000 {
 		clocks = <&cru ACLK_MMU_PHP>;
 		resets = <&cru SRST_A_MMU_PHP>;
 		#iommu-cells = <1>;
-		status = "disabled";
 	};
 
 	pmu1grf: syscon@fd58a000 {

-- 
2.55.0