From: Vasilij Strassheim <v.strassheim@linutronix.de>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Simon Horman <horms@kernel.org>,
Russell King <linux@armlinux.org.uk>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org,
Martin Kaistra <martin.kaistra@linutronix.de>,
Benedikt Spranger <b.spranger@linutronix.de>
Subject: Re: [PATCH net-next v2 4/4] net: dsa: soce: Add basic support for SoC-e switch IP cores
Date: Fri, 11 Sep 2026 15:39:34 +0200 [thread overview]
Message-ID: <64630356f2313d95c2d4a249d52c97d90e1504ef.camel@linutronix.de> (raw)
In-Reply-To: <5bc95ef2-4e23-4c80-af17-07aa3643bebf@lunn.ch>
On Thu, 2026-09-10 at 17:07 +0200, Andrew Lunn wrote:
> Thanks for this list.
>
> > ---
> > Global register block at 0x0000 (three registers currently used)
> > 0x00 Core Version - Major and minor revision number (RO)
> > 0x04 Licensed Features (RO)
> > 0x08 Reserved
> > 0x0C GUI Configuration - Implemented Features 0 (RO)
> > 0x10 GUI Configuration - Implemented Features 1 (RO)
>
> GUI? I assume this is not Graphical User Interface, but something
> else?
>
It actually stands for Graphical User Interface. This refers to
configuration in a graphical IDE, where the bitstream is customised and
synthesized.
"Implemented Features" can be enabled/disabled and configured there by
clicking on the respective checkboxes or options within the graphical
interface.
> > Licensed Features Register (RO) (Bits specify if the given
> > feature is enabled by license):
> > [31:27] - Maximum Number of Ports: These bits specify the maximum
> > number of ports licensed
> > [26:15] - Reserved
> > - ACL: Access Control List (ACL) feature
> > - LLDP: LLDP feature
> > - IEEE 802.1X
> > - IEEE 802.1AX-2008 - Link Aggregation
> > - IEEE 802.3br/IEEE 802.1Qbu - Preemption
> > - IEC 61158-4-2 - DLR
> > - IEC 62439-2 - MRP
> > - IGMP Snooping
> > - Port mirroring
> > - IEEE 802.1s - MSTP
> > - IEEE 802.1w - RSTP
> > - IEEE 1588 - Transparent Clock
> > - Switch mode: managed or unmanaged
>
> This is probably something which should be tested in the probe
> method. No point loading the driver if it cannot be managed.
>
"DSA" functionality is already tested and according to the
documentation, this excludes unmanaged variants. Therefore, I wouldn't
add an additional test for this.
> > - Secure Chip
> > - Time Limitation
>
> What do these two mean?
>
Took me some time to find this info. These are license-protection
features. "Security Chip" authenticates the IP license using an external
1-Wire security device, while "Time Limitation" restricts evaluation
licenses to a configured operating period. Neither is relevant to the
driver.
> > MDIO - Control
> > [26:16] - Bus selection: These bits specify the port number over
> > which MDIO operation is performed.
>
> 10 bits, which allows more MDIO busses than ports!
Actually 11 bits. However, too much. This may be a documentation error,
since the original driver also used only bits 20:16. I will clarify
this and if it's true, somehow address it as part of the MDIO/mux
rework.
>
> > > I also wounder at the name. Does the data sheet really call it DSA?
> > >
> >
> > Yes, there is even a chapter describing Distributed Switch Architecture
> > (DSA) as "a subsystem that was primarily designed to support specific
> > vendor switches using Linux, ..." followed by information about "custom
> > DSA tagging".
>
> Does the switch support the D in DSA?
>
Not as far as I understand. The hardware provides custom frame tagging
between the CPU and a single switch. I found no indication that it
supports cascaded switch trees or encodes a target switch identity in
the tag.
>
Thanks,
Vasilij
next prev parent reply other threads:[~2026-09-11 13:39 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 18:10 [PATCH net-next v2 0/4] net: dsa: Add SoC-e DSA driver Vasilij Strassheim
2026-09-03 18:10 ` [PATCH net-next v2 1/4] dt-bindings: vendor-prefixes: Add soce Vasilij Strassheim
2026-09-07 9:14 ` Krzysztof Kozlowski
2026-09-03 18:10 ` [PATCH net-next v2 2/4] dt-bindings: net: dsa: Add SoC-e SWIP switch Vasilij Strassheim
2026-09-07 9:21 ` Krzysztof Kozlowski
2026-09-07 14:01 ` Vasilij Strassheim
2026-09-07 18:56 ` Andrew Lunn
2026-09-08 10:16 ` Vasilij Strassheim
2026-09-08 10:29 ` Kurt Kanzenbach
2026-09-08 9:14 ` Krzysztof Kozlowski
2026-09-08 10:09 ` Vasilij Strassheim
2026-09-07 19:04 ` Andrew Lunn
2026-09-07 19:09 ` Andrew Lunn
2026-09-08 18:15 ` Vasilij Strassheim
2026-09-08 19:10 ` Andrew Lunn
2026-09-09 18:46 ` Vasilij Strassheim
2026-09-10 12:12 ` Andrew Lunn
2026-09-03 18:11 ` [PATCH net-next v2 3/4] net: dsa: Add tag handling for SoC-e switches Vasilij Strassheim
2026-09-09 12:12 ` netdev-bot+sashiko
2026-09-03 18:11 ` [PATCH net-next v2 4/4] net: dsa: soce: Add basic support for SoC-e switch IP cores Vasilij Strassheim
2026-09-07 19:28 ` Andrew Lunn
2026-09-08 18:44 ` Vasilij Strassheim
2026-09-08 19:20 ` Andrew Lunn
2026-09-09 19:28 ` Vasilij Strassheim
2026-09-10 12:18 ` Andrew Lunn
2026-09-08 0:37 ` Andrew Lunn
2026-09-10 13:01 ` Vasilij Strassheim
2026-09-10 15:07 ` Andrew Lunn
2026-09-11 13:39 ` Vasilij Strassheim [this message]
2026-09-08 8:25 ` Kurt Kanzenbach
2026-09-08 10:12 ` Vasilij Strassheim
2026-09-09 12:12 ` netdev-bot+sashiko
2026-09-07 9:10 ` [PATCH net-next v2 0/4] net: dsa: Add SoC-e DSA driver Krzysztof Kozlowski
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