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From: Dan Williams <dan.j.williams@intel.com>
To: <alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
	<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
	<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
	<pabeni@redhat.com>, <edumazet@google.com>,
	<dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v9 04/27] cxl/pci: add check for validating capabilities
Date: Fri, 17 Jan 2025 17:40:50 -0800	[thread overview]
Message-ID: <678b06a26cddc_20fa29492@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20241230214445.27602-5-alejandro.lucero-palau@amd.com>

alejandro.lucero-palau@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 
> During CXL device initialization supported capabilities by the device
> are discovered. Type3 and Type2 devices have different mandatory
> capabilities and a Type2 expects a specific set including optional
> capabilities.
> 
> Add a function for checking expected capabilities against those found
> during initialization and allow those mandatory/expected capabilities to
> be a subset of the capabilities found.
> 
> Rely on this function for validating capabilities instead of when CXL
> regs are probed.
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Zhi Wang <zhiw@nvidia.com>
> ---
>  drivers/cxl/core/pci.c  | 16 ++++++++++++++++
>  drivers/cxl/core/regs.c |  9 ---------
>  drivers/cxl/pci.c       | 24 ++++++++++++++++++++++++
>  include/cxl/cxl.h       |  3 +++
>  4 files changed, 43 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index ec57caf5b2d7..57318cdc368a 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -8,6 +8,7 @@
>  #include <linux/pci.h>
>  #include <linux/pci-doe.h>
>  #include <linux/aer.h>
> +#include <cxl/cxl.h>
>  #include <cxlpci.h>
>  #include <cxlmem.h>
>  #include <cxl.h>
> @@ -1055,3 +1056,18 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c)
>  
>  	return 0;
>  }
> +
> +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps,
> +			unsigned long *current_caps)
> +{
> +
> +	if (current_caps)
> +		bitmap_copy(current_caps, cxlds->capabilities, CXL_MAX_CAPS);
> +
> +	dev_dbg(cxlds->dev, "Checking cxlds caps 0x%pb vs expected caps 0x%pb\n",
> +		cxlds->capabilities, expected_caps);
> +
> +	/* Checking a minimum of mandatory/expected capabilities */
> +	return bitmap_subset(expected_caps, cxlds->capabilities, CXL_MAX_CAPS);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_pci_check_caps, "CXL");

cxl_setup_regs() is already exported from the core. Just make the caller
of cxl_setup_regs() responsible for checking the valid bits per its
constraints rather a new mechanism.

  parent reply	other threads:[~2025-01-18  1:40 UTC|newest]

Thread overview: 89+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-30 21:44 [PATCH v9 00/27] cxl: add type2 device basic support alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 01/27] " alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 02/27] sfc: add cxl support using new CXL API alejandro.lucero-palau
2025-01-02 14:32   ` Jonathan Cameron
2025-01-03  7:21     ` Alejandro Lucero Palau
2025-01-18  1:30   ` Dan Williams
2025-01-20 14:35     ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port alejandro.lucero-palau
2025-01-02 14:36   ` Jonathan Cameron
2025-01-03  7:20     ` Alejandro Lucero Palau
2025-01-03 10:50       ` Jonathan Cameron
2025-01-03 11:50         ` Alejandro Lucero Palau
2025-01-18  1:37   ` Dan Williams
2025-01-20 14:58     ` Alejandro Lucero Palau
2025-01-21 22:39       ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 04/27] cxl/pci: add check for validating capabilities alejandro.lucero-palau
2025-01-02 14:38   ` Jonathan Cameron
2025-01-18  1:40   ` Dan Williams [this message]
2025-01-20 15:14     ` Alejandro Lucero Palau
2025-01-21 22:42       ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 05/27] cxl: move pci generic code alejandro.lucero-palau
2025-01-02 14:41   ` Jonathan Cameron
2025-01-18  1:43   ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 06/27] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-01-02 14:53   ` Jonathan Cameron
2025-01-03  7:23     ` Alejandro Lucero Palau
2025-01-18  1:51   ` Dan Williams
2025-01-20 15:40     ` Alejandro Lucero Palau
2025-01-21 22:51       ` Dan Williams
2025-01-22  9:05         ` Alejandro Lucero Palau
2025-01-22 23:34           ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 07/27] sfc: use cxl api for regs setup and checking alejandro.lucero-palau
2025-01-02 14:54   ` Jonathan Cameron
2025-01-18  1:53   ` Dan Williams
2025-01-20 15:44     ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 08/27] cxl: add functions for resource request/release by a driver alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 09/27] sfc: request cxl ram resource alejandro.lucero-palau
2025-01-18  1:58   ` Dan Williams
2025-01-20 16:00     ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 10/27] resource: harden resource_contains alejandro.lucero-palau
2025-01-18  2:03   ` Dan Williams
2025-01-20 16:10     ` Alejandro Lucero Palau
2025-01-20 16:16       ` Alejandro Lucero Palau
2025-01-20 16:26         ` Alejandro Lucero Palau
2025-01-21 20:38           ` Alison Schofield
2025-01-22  9:37             ` Alejandro Lucero Palau
2025-01-21 23:01       ` Dan Williams
2025-01-22  9:41         ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 11/27] cxl: add function for setting media ready by a driver alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 12/27] sfc: set cxl media ready alejandro.lucero-palau
2025-01-02 14:55   ` Jonathan Cameron
2024-12-30 21:44 ` [PATCH v9 13/27] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-01-02 15:01   ` Jonathan Cameron
2025-01-03  7:24     ` Alejandro Lucero Palau
2025-01-18  2:27   ` Dan Williams
2025-01-20 17:15     ` Alejandro Lucero Palau
2025-01-21 23:11       ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 14/27] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-01-18  2:41   ` Dan Williams
2025-01-20 17:27     ` Alejandro Lucero Palau
2025-01-21 23:22       ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 15/27] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-01-02 15:10   ` Jonathan Cameron
2025-01-03  7:55     ` Alejandro Lucero Palau
2025-01-18  3:02   ` Dan Williams
2025-01-20 18:16     ` Alejandro Lucero Palau
2025-01-21 14:00       ` Alejandro Lucero Palau
2025-01-21 23:44         ` Dan Williams
2025-01-22  9:26           ` Alejandro Lucero Palau
2025-01-21 23:35       ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 16/27] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 17/27] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-01-02 15:15   ` Jonathan Cameron
2025-01-03  7:58     ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 18/27] sfc: get endpoint decoder alejandro.lucero-palau
2025-01-02 15:17   ` Jonathan Cameron
2025-01-02 16:38   ` Edward Cree
2024-12-30 21:44 ` [PATCH v9 19/27] cxl: make region type based on endpoint type alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 20/27] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 21/27] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 22/27] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-01-02 15:22   ` Jonathan Cameron
2025-01-03  8:16     ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 23/27] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-01-02 15:24   ` Jonathan Cameron
2024-12-30 21:44 ` [PATCH v9 24/27] sfc: create cxl region alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 25/27] cxl: add function for obtaining region range alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 26/27] sfc: update MCDI protocol headers alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 27/27] sfc: support pio mapping based on cxl alejandro.lucero-palau

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