From: Dan Williams <dan.j.williams@intel.com>
To: <alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
<pabeni@redhat.com>, <edumazet@google.com>,
<dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v9 13/27] cxl: prepare memdev creation for type2
Date: Fri, 17 Jan 2025 18:27:57 -0800 [thread overview]
Message-ID: <678b11ada467d_20fa2949b@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20241230214445.27602-14-alejandro.lucero-palau@amd.com>
alejandro.lucero-palau@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Current cxl core is relying on a CXL_DEVTYPE_CLASSMEM type device when
> creating a memdev leading to problems when obtaining cxl_memdev_state
> references from a CXL_DEVTYPE_DEVMEM type. This last device type is
> managed by a specific vendor driver and does not need same sysfs files
> since not userspace intervention is expected.
>
> Create a new cxl_mem device type with no attributes for Type2.
>
> Avoid debugfs files relying on existence of cxl_memdev_state.
>
> Make devm_cxl_add_memdev accesible from a accel driver.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> ---
> drivers/cxl/core/cdat.c | 3 +++
> drivers/cxl/core/memdev.c | 14 ++++++++++++--
> drivers/cxl/core/region.c | 3 ++-
> drivers/cxl/cxlmem.h | 2 --
> drivers/cxl/mem.c | 25 +++++++++++++++++++------
> include/cxl/cxl.h | 2 ++
> 6 files changed, 38 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
> index 8153f8d83a16..c57bc83e79ee 100644
> --- a/drivers/cxl/core/cdat.c
> +++ b/drivers/cxl/core/cdat.c
> @@ -577,6 +577,9 @@ static struct cxl_dpa_perf *cxled_get_dpa_perf(struct cxl_endpoint_decoder *cxle
> struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
> struct cxl_dpa_perf *perf;
>
> + if (!mds)
> + return ERR_PTR(-EINVAL);
> +
The references to @mds in cxled_get_dpa_perf() are gone
after the DPA partition changes.
If an accelerator has a CDAT it will get qos_class information for free.
If it does not have a CDAT then I wonder how it is telling the BIOS the
memory type for its CXL.mem?
> switch (mode) {
> case CXL_DECODER_RAM:
> perf = &mds->ram_perf;
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index 836db4a462b3..f91feca586dd 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -547,9 +547,16 @@ static const struct device_type cxl_memdev_type = {
> .groups = cxl_memdev_attribute_groups,
> };
>
> +static const struct device_type cxl_accel_memdev_type = {
> + .name = "cxl_accel_memdev",
> + .release = cxl_memdev_release,
> + .devnode = cxl_memdev_devnode,
> +};
> +
> bool is_cxl_memdev(const struct device *dev)
> {
> - return dev->type == &cxl_memdev_type;
> + return (dev->type == &cxl_memdev_type ||
> + dev->type == &cxl_accel_memdev_type);
At this point the game is over in terms of future code that trips over
the assumption that all "is_cxl_memdev() == true" devices are created
equal.
> }
> EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CXL");
>
> @@ -660,7 +667,10 @@ static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds,
> dev->parent = cxlds->dev;
> dev->bus = &cxl_bus_type;
> dev->devt = MKDEV(cxl_mem_major, cxlmd->id);
> - dev->type = &cxl_memdev_type;
> + if (cxlds->type == CXL_DEVTYPE_DEVMEM)
> + dev->type = &cxl_accel_memdev_type;
> + else
> + dev->type = &cxl_memdev_type;
> device_set_pm_not_required(dev);
> INIT_WORK(&cxlmd->detach_work, detach_memdev);
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index d77899650798..967132b49832 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1948,7 +1948,8 @@ static int cxl_region_attach(struct cxl_region *cxlr,
> return -EINVAL;
> }
>
> - cxl_region_perf_data_calculate(cxlr, cxled);
> + if (cxlr->type == CXL_DECODER_HOSTONLYMEM)
> + cxl_region_perf_data_calculate(cxlr, cxled);
Per-above no need to worry about @mds reference in this path.
> if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) {
> int i;
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 4c1c53c29544..360d3728f492 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -87,8 +87,6 @@ static inline bool is_cxl_endpoint(struct cxl_port *port)
> return is_cxl_memdev(port->uport_dev);
> }
>
> -struct cxl_memdev *devm_cxl_add_memdev(struct device *host,
> - struct cxl_dev_state *cxlds);
> int devm_cxl_sanitize_setup_notifier(struct device *host,
> struct cxl_memdev *cxlmd);
> struct cxl_memdev_state;
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 2f03a4d5606e..93106a43990b 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -130,12 +130,18 @@ static int cxl_mem_probe(struct device *dev)
> dentry = cxl_debugfs_create_dir(dev_name(dev));
> debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show);
>
> - if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds))
> - debugfs_create_file("inject_poison", 0200, dentry, cxlmd,
> - &cxl_poison_inject_fops);
> - if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds))
> - debugfs_create_file("clear_poison", 0200, dentry, cxlmd,
> - &cxl_poison_clear_fops);
> + /*
> + * Avoid poison debugfs files for Type2 devices as they rely on
> + * cxl_memdev_state.
> + */
> + if (mds) {
> + if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds))
> + debugfs_create_file("inject_poison", 0200, dentry, cxlmd,
> + &cxl_poison_inject_fops);
> + if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds))
> + debugfs_create_file("clear_poison", 0200, dentry, cxlmd,
> + &cxl_poison_clear_fops);
> + }
>
> rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
> if (rc)
> @@ -219,6 +225,13 @@ static umode_t cxl_mem_visible(struct kobject *kobj, struct attribute *a, int n)
> struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
>
> + /*
> + * Avoid poison sysfs files for Type2 devices as they rely on
> + * cxl_memdev_state.
> + */
> + if (!mds)
> + return 0;
It turns out that nothing in the poison handling path requires 'struct
cxl_memdev_state'. So rather than key this rejection off of @mds ==
NULL, I would prefer to find a way to make this optional relative to
data read from 'struct cxl_mailbox', or 'struct cxl_dev_state'.
Conceptually there is nothing stopping a CXL accelertor from supporting
poison management commands on its mailbox, it's just unlikely.
next prev parent reply other threads:[~2025-01-18 2:28 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-30 21:44 [PATCH v9 00/27] cxl: add type2 device basic support alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 01/27] " alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 02/27] sfc: add cxl support using new CXL API alejandro.lucero-palau
2025-01-02 14:32 ` Jonathan Cameron
2025-01-03 7:21 ` Alejandro Lucero Palau
2025-01-18 1:30 ` Dan Williams
2025-01-20 14:35 ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port alejandro.lucero-palau
2025-01-02 14:36 ` Jonathan Cameron
2025-01-03 7:20 ` Alejandro Lucero Palau
2025-01-03 10:50 ` Jonathan Cameron
2025-01-03 11:50 ` Alejandro Lucero Palau
2025-01-18 1:37 ` Dan Williams
2025-01-20 14:58 ` Alejandro Lucero Palau
2025-01-21 22:39 ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 04/27] cxl/pci: add check for validating capabilities alejandro.lucero-palau
2025-01-02 14:38 ` Jonathan Cameron
2025-01-18 1:40 ` Dan Williams
2025-01-20 15:14 ` Alejandro Lucero Palau
2025-01-21 22:42 ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 05/27] cxl: move pci generic code alejandro.lucero-palau
2025-01-02 14:41 ` Jonathan Cameron
2025-01-18 1:43 ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 06/27] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-01-02 14:53 ` Jonathan Cameron
2025-01-03 7:23 ` Alejandro Lucero Palau
2025-01-18 1:51 ` Dan Williams
2025-01-20 15:40 ` Alejandro Lucero Palau
2025-01-21 22:51 ` Dan Williams
2025-01-22 9:05 ` Alejandro Lucero Palau
2025-01-22 23:34 ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 07/27] sfc: use cxl api for regs setup and checking alejandro.lucero-palau
2025-01-02 14:54 ` Jonathan Cameron
2025-01-18 1:53 ` Dan Williams
2025-01-20 15:44 ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 08/27] cxl: add functions for resource request/release by a driver alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 09/27] sfc: request cxl ram resource alejandro.lucero-palau
2025-01-18 1:58 ` Dan Williams
2025-01-20 16:00 ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 10/27] resource: harden resource_contains alejandro.lucero-palau
2025-01-18 2:03 ` Dan Williams
2025-01-20 16:10 ` Alejandro Lucero Palau
2025-01-20 16:16 ` Alejandro Lucero Palau
2025-01-20 16:26 ` Alejandro Lucero Palau
2025-01-21 20:38 ` Alison Schofield
2025-01-22 9:37 ` Alejandro Lucero Palau
2025-01-21 23:01 ` Dan Williams
2025-01-22 9:41 ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 11/27] cxl: add function for setting media ready by a driver alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 12/27] sfc: set cxl media ready alejandro.lucero-palau
2025-01-02 14:55 ` Jonathan Cameron
2024-12-30 21:44 ` [PATCH v9 13/27] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-01-02 15:01 ` Jonathan Cameron
2025-01-03 7:24 ` Alejandro Lucero Palau
2025-01-18 2:27 ` Dan Williams [this message]
2025-01-20 17:15 ` Alejandro Lucero Palau
2025-01-21 23:11 ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 14/27] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-01-18 2:41 ` Dan Williams
2025-01-20 17:27 ` Alejandro Lucero Palau
2025-01-21 23:22 ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 15/27] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-01-02 15:10 ` Jonathan Cameron
2025-01-03 7:55 ` Alejandro Lucero Palau
2025-01-18 3:02 ` Dan Williams
2025-01-20 18:16 ` Alejandro Lucero Palau
2025-01-21 14:00 ` Alejandro Lucero Palau
2025-01-21 23:44 ` Dan Williams
2025-01-22 9:26 ` Alejandro Lucero Palau
2025-01-21 23:35 ` Dan Williams
2024-12-30 21:44 ` [PATCH v9 16/27] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 17/27] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-01-02 15:15 ` Jonathan Cameron
2025-01-03 7:58 ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 18/27] sfc: get endpoint decoder alejandro.lucero-palau
2025-01-02 15:17 ` Jonathan Cameron
2025-01-02 16:38 ` Edward Cree
2024-12-30 21:44 ` [PATCH v9 19/27] cxl: make region type based on endpoint type alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 20/27] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 21/27] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 22/27] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-01-02 15:22 ` Jonathan Cameron
2025-01-03 8:16 ` Alejandro Lucero Palau
2024-12-30 21:44 ` [PATCH v9 23/27] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-01-02 15:24 ` Jonathan Cameron
2024-12-30 21:44 ` [PATCH v9 24/27] sfc: create cxl region alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 25/27] cxl: add function for obtaining region range alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 26/27] sfc: update MCDI protocol headers alejandro.lucero-palau
2024-12-30 21:44 ` [PATCH v9 27/27] sfc: support pio mapping based on cxl alejandro.lucero-palau
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