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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: George Moussalem <george.moussalem@outlook.com>,
	Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Andrew Lunn <andrew@lunn.ch>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Kathiravan Thirumoorthy
	<kathiravan.thirumoorthy@oss.qualcomm.com>
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH 2/5] clk: qcom: gcc-ipq5018: fix GE PHY reset
Date: Tue, 27 May 2025 13:19:26 +0200	[thread overview]
Message-ID: <99fd4103-97e0-486d-9e6c-66c8adb70b3b@oss.qualcomm.com> (raw)
In-Reply-To: <DS7PR19MB8883BE13166F7CD5DCA777DB9D64A@DS7PR19MB8883.namprd19.prod.outlook.com>

On 5/27/25 1:14 PM, George Moussalem wrote:
> Hi Konrad,
> 
> On 5/27/25 15:00, Konrad Dybcio wrote:
>> On 5/25/25 7:56 PM, George Moussalem via B4 Relay wrote:
>>> From: George Moussalem <george.moussalem@outlook.com>
>>>
>>> The MISC reset is supposed to trigger a resets across the MDC, DSP, and
>>> RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask
>>> of the reset definition accordingly in the GCC as per the downstream
>>> driver.
>>>
>>> Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932
>>>
>>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>>> ---
>>>   drivers/clk/qcom/gcc-ipq5018.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
>>> index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..02d6f08f389f24eccc961b9a4271288c6b635bbc 100644
>>> --- a/drivers/clk/qcom/gcc-ipq5018.c
>>> +++ b/drivers/clk/qcom/gcc-ipq5018.c
>>> @@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = {
>>>       [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
>>>       [GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
>>>       [GCC_WCSSAON_RESET] = { 0x59010, 0},
>>> -    [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
>>> +    [GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = 0xf },
>>
>> The computer tells me there aren't any bits beyond this mask..
>>
>> Does this actually fix anything?
> 
> The mask is documented in the referenced downstream driver and allows for consolidating:
> 
> resets = <&gcc GCC_GEPHY_MDC_SW_ARES>,
>      <&gcc GCC_GEPHY_DSP_HW_ARES>,
>      <&gcc GCC_GEPHY_RX_ARES>,
>      <&gcc GCC_GEPHY_TX_ARES>;
> to:
> 
> resets = <&gcc GCC_MISC_ARES>;
> 
> to conform to this bindings restriction in ethernet-phy.yaml
> 
>   resets:
>     maxItems: 1
> 
> Effectively, there's no functional change. So we can also list all the resets in the device tree, whatever is preferred.

+ Kathiravan

are there any recommendations from the hw team on which one to use?
As far as I can tell, the _MISC one simply pulls all the aforementioned
resets, like George described.. it seems weird that it would be designed
like this

Konrad

  reply	other threads:[~2025-05-27 11:19 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-25 17:56 [PATCH 0/5] Add support for the IPQ5018 Internal GE PHY George Moussalem via B4 Relay
2025-05-25 17:56 ` [PATCH 1/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support George Moussalem via B4 Relay
2025-05-25 19:35   ` Andrew Lunn
2025-05-26  4:27     ` George Moussalem
2025-05-26 13:34       ` Andrew Lunn
2025-05-26 13:43         ` George Moussalem
2025-05-26  4:17   ` Krzysztof Kozlowski
2025-05-26  6:43     ` George Moussalem
2025-05-26 12:55       ` Krzysztof Kozlowski
2025-05-27 10:59         ` Konrad Dybcio
2025-05-27 11:28           ` George Moussalem
2025-05-27 11:31             ` Konrad Dybcio
2025-05-27 12:13               ` George Moussalem
2025-05-27 13:00                 ` Konrad Dybcio
2025-05-27 13:03                   ` George Moussalem
2025-05-27 13:08                 ` Andrew Lunn
2025-05-27 13:15                   ` Konrad Dybcio
2025-05-27 15:12                     ` Andrew Lunn
2025-05-25 17:56 ` [PATCH 2/5] clk: qcom: gcc-ipq5018: fix GE PHY reset George Moussalem via B4 Relay
2025-05-27 11:00   ` Konrad Dybcio
2025-05-27 11:14     ` George Moussalem
2025-05-27 11:19       ` Konrad Dybcio [this message]
2025-05-25 17:56 ` [PATCH 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support George Moussalem via B4 Relay
2025-05-25 19:42   ` Andrew Lunn
2025-05-26  4:28     ` George Moussalem
2025-05-25 17:56 ` [PATCH 4/5] arm64: dts: qcom: ipq5018: add MDIO buses George Moussalem via B4 Relay
2025-05-27 11:07   ` Konrad Dybcio
2025-05-27 11:23     ` George Moussalem
2025-05-25 17:56 ` [PATCH 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus George Moussalem via B4 Relay
2025-05-27 13:34   ` Konrad Dybcio
2025-05-27 13:36     ` George Moussalem
2025-05-27 17:56 ` [PATCH 0/5] Add support for the IPQ5018 Internal GE PHY Rob Herring (Arm)
2025-05-28  4:57   ` George Moussalem
2025-05-28 12:00     ` Andrew Lunn

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