* Re: large packet loss take2 2.6.31.x
From: Jarek Poplawski @ 2009-11-12 21:47 UTC (permalink / raw)
To: Caleb Cushing; +Cc: Frans Pop, Andi Kleen, linux-kernel, netdev
In-Reply-To: <4AFC5C58.9030207@gmail.com>
Jarek Poplawski wrote, On 11/12/2009 08:04 PM:
> Caleb Cushing wrote, On 11/12/2009 02:46 PM:
...
>>> Btw, you didn't send the stats you compared, and your wireshark dump
>>> doesn't show anything wrong either.
...
>> I didn't see that sorry. I wasn't sure if the dump would or not (I'm
>> not a networking expert, just know more than the average joe).
Hmm... I didn't see that either, sorry! After re-checking I can see
unanswered requests in this dump. Anyway, the main thing to test now is
the first hop to 192.168.1.1 (some info about it?), as I wrote before.
Jarek P.
^ permalink raw reply
* Re: [Bugme-new] [Bug 14586] New: bridge on bonding interface: DHCP replies don't get through
From: Andrew Morton @ 2009-11-12 22:39 UTC (permalink / raw)
To: Stephen Hemminger, bridge
Cc: bugzilla-daemon, bugme-daemon, netdev, harald.dunkel
In-Reply-To: <bug-14586-10286@http.bugzilla.kernel.org/>
(switched to email. Please respond via emailed reply-to-all, not via the
bugzilla web interface).
On Wed, 11 Nov 2009 14:28:00 GMT
bugzilla-daemon@bugzilla.kernel.org wrote:
> http://bugzilla.kernel.org/show_bug.cgi?id=14586
>
> Summary: bridge on bonding interface: DHCP replies don't get
> through
> Product: Networking
> Version: 2.5
> Kernel Version: 2.6.31.5
> Platform: All
> OS/Version: Linux
> Tree: Mainline
> Status: NEW
> Severity: normal
> Priority: P1
> Component: Other
> AssignedTo: acme@ghostprotocols.net
> ReportedBy: harald.dunkel@t-online.de
> Regression: No
>
>
> I would like to run a bridge for kvm on a bonding interface (4 * 1Gbit, Intel
> e1000e). Problem: The DHCPDISCOVER packets sent by the guest show up on my dhcp
> server as expected, but the DHCPOFFER sent as a reply doesn't reach the guest
> behind the bridge.
>
> Using tcpdump on host and guest I can see the DHCPOFFER on the bond0 and br0
> interface, but it never shows up on vnet0 or on the guest's eth0.
>
> If I drop the bonding interface and use the host's eth2 for the bridge instead,
> then there is no such problem.
>
> Kernel on host and guest is 2.6.31.5. Attached you can find more information
> about my setup.
>
> I had sent this information to the linux kvm mailing list before, but consensus
> was that this is a bridging problem. See
>
> http://www.spinics.net/lists/kvm/msg25153.html
>
> There was no reply on the linux bridge mailing list, see
>
>
> https://lists.linux-foundation.org/pipermail/bridge/2009-November/006749.html
^ permalink raw reply
* Re: [Bugme-new] [Bug 14586] New: bridge on bonding interface: DHCP replies don't get through
From: Stephen Hemminger @ 2009-11-12 22:55 UTC (permalink / raw)
To: harald.dunkel
Cc: Andrew Morton, bridge, bugzilla-daemon, bugme-daemon, netdev
In-Reply-To: <20091112143913.3d89e4f4.akpm@linux-foundation.org>
>
> I would like to run a bridge for kvm on a bonding interface (4 * 1Gbit, Intel
> e1000e). Problem: The DHCPDISCOVER packets sent by the guest show up on my dhcp
> server as expected, but the DHCPOFFER sent as a reply doesn't reach the guest
> behind the bridge.
>
> Using tcpdump on host and guest I can see the DHCPOFFER on the bond0 and br0
> interface, but it never shows up on vnet0 or on the guest's eth0.
>
> If I drop the bonding interface and use the host's eth2 for the bridge instead,
> then there is no such problem.
>
> Kernel on host and guest is 2.6.31.5. Attached you can find more information
> about my setup.
>
What is the configuration?
# brctl showstp virbr0
# brctl showmacs virbr0
Is dhclient being run on the bridge interface?
# cat /proc/net/ptype
# cat /proc/net/bonding/bond0
How is bond and bridge configured? Are bonding bridges (wrong)
or bridging bonded interfaces?
Are all links up?
Since this is the initial packet it will have to be flood forwarded by
the bridge, is there any iptables/netfilter rule that might be blocking
packets?
^ permalink raw reply
* Re: [PATCH v2] Documentation: rw_lock lessons learned
From: Stephen Hemminger @ 2009-11-12 23:00 UTC (permalink / raw)
To: sclark46
Cc: William Allen Simpson, Paul E. McKenney, Linus Torvalds,
Linux Kernel Developers, Linux Kernel Network Developers,
Eric Dumazet
In-Reply-To: <4AFC5E3F.7070609@earthlink.net>
On Thu, 12 Nov 2009 14:13:03 -0500
Stephen Clark <sclark46@earthlink.net> wrote:
> William Allen Simpson wrote:
> > In recent weeks, two different network projects erroneously
> > strayed down the rw_lock path. Update the Documentation
> > based upon comments by Eric Dumazet and Paul E. McKenney in
> > those threads.
> >
> > Merged with editorial changes by Stephen Hemminger.
> >
> > Signed-off-by: William.Allen.Simpson@gmail.com
> > Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> > ---
> > Documentation/spinlocks.txt | 186
> > ++++++++++++++++++++-----------------------
> > 1 files changed, 86 insertions(+), 100 deletions(-)
> >
>
> How up to date is this doc?
>
> http://www.kernel.org/pub/linux/kernel/people/rusty/kernel-locking/index.html
>
Out of date.
1. Missing mutex's which have largely replaced semaphores.
2. Missing change to lock initialization in later kernels.
3. Missing description of lock dependency checker which should be in same guide.
^ permalink raw reply
* Re: [RACE] net: in process_backlog
From: Changli Gao @ 2009-11-12 23:54 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: David S. Miller, Patrick McHardy, netdev
In-Reply-To: <20091112085739.1137f690@nehalam>
On Fri, Nov 13, 2009 at 12:57 AM, Stephen Hemminger
<shemminger@vyatta.com> wrote:
> On Thu, 12 Nov 2009 16:50:53 +0800
> Changli Gao <xiaosuo@gmail.com> wrote:
>
>
> There is are a couple of issues here, but it is not what you thought
> you saw.
>
> The receive process is always done in soft IRQ context. The backlog queue's
> are per-cpu. When a device is deleted an IPI is sent to all cpu's to
> scan there backlog queue. What should protect the skb is the fact that
> the network device destruction process waits for an RCU grace period.
> So skb->dev points to valid data.
Yea, if the process waits for a RCU grace period, there will be no
race. But think about another case:
1. flush_backlog().
2. dev_hold(skb->dev); netif_rx(). dev_put(skb->dev);
3. wait_for_refs();
4. free(dev);
5. netif_receive_skb(); //skb->dev doesn't present.
flush_backlog() can't prevent new skbs are added to backlog. If we
swap the flush_backlog() and wait_for_refs(), this case will be OK
too.
>
> BUT the flush_backlog is run too late in the device destruction process.
> It should be moved out of netdev_run_todo, to right after dev_shutdown().
> Also adding a check for skb->dev->reg_state in netif_receive_skb would
> be wise to drop packets.
>
>
> --
>
--
Regards，
Changli Gao(xiaosuo@gmail.com)
^ permalink raw reply
* Re: [RACE] net: in process_backlog
From: Stephen Hemminger @ 2009-11-13 0:11 UTC (permalink / raw)
To: Changli Gao; +Cc: David S. Miller, Patrick McHardy, netdev
In-Reply-To: <412e6f7f0911121554n22a6f975h1fb5df59bd4b84a2@mail.gmail.com>
On Fri, 13 Nov 2009 07:54:14 +0800
Changli Gao <xiaosuo@gmail.com> wrote:
> On Fri, Nov 13, 2009 at 12:57 AM, Stephen Hemminger
> <shemminger@vyatta.com> wrote:
> > On Thu, 12 Nov 2009 16:50:53 +0800
> > Changli Gao <xiaosuo@gmail.com> wrote:
> >
> >
> > There is are a couple of issues here, but it is not what you thought
> > you saw.
> >
> > The receive process is always done in soft IRQ context. The backlog queue's
> > are per-cpu. When a device is deleted an IPI is sent to all cpu's to
> > scan there backlog queue. What should protect the skb is the fact that
> > the network device destruction process waits for an RCU grace period.
> > So skb->dev points to valid data.
>
> Yea, if the process waits for a RCU grace period, there will be no
> race. But think about another case:
> 1. flush_backlog().
After flush backlog there should be no more skb's with that device
in the queue, and if more are added, the device is buggy.
> 2. dev_hold(skb->dev); netif_rx(). dev_put(skb->dev);
There is no dev_hold in netif_rx path.
> 3. wait_for_refs();
> 4. free(dev);
> 5. netif_receive_skb(); //skb->dev doesn't present.
> flush_backlog() can't prevent new skbs are added to backlog. If we
> swap the flush_backlog() and wait_for_refs(), this case will be OK
> too.
It is still up to device driver not to add skb's to queue when stopped.
--
^ permalink raw reply
* Re: [RACE] net: in process_backlog
From: Changli Gao @ 2009-11-13 1:17 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: David S. Miller, Patrick McHardy, netdev
In-Reply-To: <20091112161123.561d87fe@nehalam>
On Fri, Nov 13, 2009 at 8:11 AM, Stephen Hemminger
<shemminger@vyatta.com> wrote:
> On Fri, 13 Nov 2009 07:54:14 +0800
> Changli Gao <xiaosuo@gmail.com> wrote:
>
>>
>> Yea, if the process waits for a RCU grace period, there will be no
>> race. But think about another case:
>> 1. flush_backlog().
> After flush backlog there should be no more skb's with that device
> in the queue, and if more are added, the device is buggy.
>
>> 2. dev_hold(skb->dev); netif_rx(). dev_put(skb->dev);
> There is no dev_hold in netif_rx path.
>
If the caller of netif_rx or netif_rx_ni isn't the device driver self,
it must find and hold the dev, then call netif_rx and put it.
>> 3. wait_for_refs();
>> 4. free(dev);
>> 5. netif_receive_skb(); //skb->dev doesn't present.
>> flush_backlog() can't prevent new skbs are added to backlog. If we
>> swap the flush_backlog() and wait_for_refs(), this case will be OK
>> too.
>
> It is still up to device driver not to add skb's to queue when stopped.
>
do you mean before calling netif_rx, the caller should check the dev
is alive or not? If so, why not add the check into netif_rx or
netif_rx_ni()? Could you explains why swapping the flush_backlog() and
wait_for_refs() can't work?
--
Regards，
Changli Gao(xiaosuo@gmail.com)
^ permalink raw reply
* Re: [PATCH] ifb: add multi-queue support
From: Changli Gao @ 2009-11-13 1:26 UTC (permalink / raw)
To: Eric Dumazet
Cc: David S. Miller, Stephen Hemminger, Patrick McHardy, Tom Herbert,
netdev
In-Reply-To: <4AFC0436.9090906@gmail.com>
2009/11/12 Eric Dumazet <eric.dumazet@gmail.com>:
>
> I believe this patch is fine, but maybe Jarek concern about workqueue
> vs tasklet should be addressed...
>
> We could use the previous handling in case numtxqs==1 , ie use a tasklet
> instead of a work queue ?
I don't think it is a good idea. If we do so, the code will be messy,
and lost the flexibility of process. In fact, latency isn't a problem
when system load isn't high, and when system load is high (due to too
many NIC IRQs), throughput and interaction is more important, and the
current linux networking subsystem just dose so through the softirqd
mechanism.
>
>
> Sorry for this late idea...
>
--
Regards，
Changli Gao(xiaosuo@gmail.com)
^ permalink raw reply
* Re: [PATCH] ifb: add multi-queue support
From: Changli Gao @ 2009-11-13 1:28 UTC (permalink / raw)
To: Patrick McHardy
Cc: David S. Miller, Stephen Hemminger, Eric Dumazet, Tom Herbert,
netdev
In-Reply-To: <4AFC2563.1020902@trash.net>
On Thu, Nov 12, 2009 at 11:10 PM, Patrick McHardy <kaber@trash.net> wrote:
> Changli Gao wrote:
>>>> + rcu_read_lock();
>>>> + skb->dev = dev_get_by_index_rcu(&init_net, skb->iif);
>>>> + if (!skb->dev) {
>>>> + rcu_read_unlock();
>>>> + dev_kfree_skb(skb);
>>>> + txq->tx_dropped++;
>>>> + break;
>>>> + }
>>>> + rcu_read_unlock();
>>>> + skb->iif = dev->ifindex;
>>> What protects the device from disappearing here and below during
>>> dev_queue_xmit() and netif_rx_ni()?
>>
>> For dev_queue_xmit(), dev is holded by skb->_dst, so there is no
>> problem. But for netif_rx_ni(), I don't know how to prevent the device
>> disappearing, and it seems that all the NIC drivers have this problem.
>> Maybe there was the assumption about the execution context of
>> netif_rx() before. Now softirq can't be executed by softirqd, so the
>> packet receiving path maybe interleaved. I don't know how to prevent
>> it happening.
>
> You can either take a reference of move the rcu_read_unlock()
> after the skb submission.
good idea!
>
>>>> + break;
>>>> + case __constant_htons(ETH_P_IPV6):
>>>> + ip_proto = ipv6_hdr(skb)->nexthdr;
>>>> + addr1 = ipv6_hdr(skb)->saddr.s6_addr32[3];
>>>> + addr2 = ipv6_hdr(skb)->daddr.s6_addr32[3];
>>>> + ihl = 10;
>>> Where does 10 come from?
>>
>> It should be 40, after reviewing IPV6, I found that I need to loop
>> until finding the right protocol value.
>
> There is a helper for this (ipv6_skip_exthdr).
>
It is a little late. Thanks all the same, and I'll use it.
>>>> +static int ifb_get_tx_queues(struct net *net, struct nlattr *tb[],
>>>> + unsigned int *num_tx_queues,
>>>> + unsigned int *real_num_tx_queues)
>>>> +{
>>>> + if (tb[IFLA_NTXQ]) {
>>>> + *num_tx_queues = nla_get_u16(tb[IFLA_NTXQ]);
>>> We currently use unsigned ints for the queue number, so please
>>> use an u32 for the attribute as well.
>>>
>>>> + *real_num_tx_queues = *num_tx_queues;
>>>> + } else {
>>>> + *num_tx_queues = numtxqs;
>>>> + *real_num_tx_queues = numtxqs;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>> u16 (*ndo_select_queue)(struct net_device *dev,
>> struct sk_buff *skb);
>> use u16 as the return value so ..., and I think u16 is big enough. If
>> you insist on this, I'll use u32 instead.
>
> Well, get_tx_queues() uses unsigned int, as does struct net_device.
> I agree that it probably won't ever be needed, but there's no harm
> in using the correct type, the attribute encoding doesn't even need
> more room.
>
So, in the last patch, I use it instead. :)
--
Regards，
Changli Gao(xiaosuo@gmail.com)
^ permalink raw reply
* Re: [PATCH] ifb: add multi-queue support
From: Changli Gao @ 2009-11-13 1:32 UTC (permalink / raw)
To: Patrick McHardy
Cc: David S. Miller, Stephen Hemminger, Eric Dumazet, Tom Herbert,
netdev
In-Reply-To: <4AFC25A7.10301@trash.net>
On Thu, Nov 12, 2009 at 11:11 PM, Patrick McHardy <kaber@trash.net> wrote:
> Changli Gao wrote:
>> The corresponding iprout2 patch is attached.
>
> Printing the value during dumps is missing from this patch.
>
I doesn't know the rules about adding more dumps. Can I add it in the
end of the corresponding line?
ifb0: <BROADCAST,NOARP> mtu 1500 qdisc noop state DOWN qlen 32 ntxqs 4
--
Regards，
Changli Gao(xiaosuo@gmail.com)
^ permalink raw reply
* Re: [Bugme-new] [Bug 14586] New: bridge on bonding interface: DHCP replies don't get through
From: Andy Gospodarek @ 2009-11-13 3:23 UTC (permalink / raw)
To: Stephen Hemminger
Cc: harald.dunkel, Andrew Morton, bridge, bugzilla-daemon,
bugme-daemon, netdev
In-Reply-To: <20091112145529.303c2659@nehalam>
On Thu, Nov 12, 2009 at 02:55:29PM -0800, Stephen Hemminger wrote:
> >
> > I would like to run a bridge for kvm on a bonding interface (4 * 1Gbit, Intel
> > e1000e). Problem: The DHCPDISCOVER packets sent by the guest show up on my dhcp
> > server as expected, but the DHCPOFFER sent as a reply doesn't reach the guest
> > behind the bridge.
> >
> > Using tcpdump on host and guest I can see the DHCPOFFER on the bond0 and br0
> > interface, but it never shows up on vnet0 or on the guest's eth0.
> >
> > If I drop the bonding interface and use the host's eth2 for the bridge instead,
> > then there is no such problem.
> >
> > Kernel on host and guest is 2.6.31.5. Attached you can find more information
> > about my setup.
> >
>
> What is the configuration?
> # brctl showstp virbr0
> # brctl showmacs virbr0
>
I'm quite sure this output will show us why this isn't working and it
won't be the first time I've seen this.
What happens with mode 0 is that the DHCPDISCOVER goes out and since the
MAC is unlearned by the switch connected to the host, the frame will
come back on all other members of the bond other than the one that sent
it.
Since the bond interface is receiving the frame, the bridge will relearn
the source address of the guest on the bonding interface and any
subsequent frames received on the bond interface that have the
destination MAC of the guest will be dropped by the bridge. This is as
expected since a bridge should drop frames when the destination MAC of
the incoming frame matches an entry in the forwarding database that
indicates those frames are destined for the receiving port.
I would suggest switching to mode 5 (balance-tlb) if your switch cannot
handle bonding or mode 2 or 4 (balance-xor or 802.3ad, respectively) if
it can. Both of those modes avoid this problem since mode 5 will drop
additional broadcast frames and modes 2 and 4 will not send broadcast
frames back to any of the bond member's interfaces.
There is a Red Hat kbase article that talks about this problem as well:
http://kbase.redhat.com/faq/docs/DOC-16051
When it was originally written mode 6 was thought to be a workaround
as well, but it has been recently proved to still be a problem and the
article needs to be updated.
^ permalink raw reply
* Problem with VLANs and via-velocity driver
From: Kevin Shanahan @ 2009-11-13 3:32 UTC (permalink / raw)
To: netdev
Hi,
I've had some problems with getting a fairly simple (I thought) VLAN
configuration working with the on board Via NICs on my Via M700
board. Looks like as soon as a tagged VLAN interface is added, the
underlying "raw" (untagged) interface stops responding.
E.g. this is my desired setup on eth1:
Untagged VLAN: 10.193.38.0/24
cubert (Linux 2.6.30.5) - 10.193.38.254
switch (HP ProCurve) - 10.193.38.1
Tagged VLAN (101): 10.193.39.192/26
cubert (Linux) - 10.193.39.254
switch (HP ProCurve) - 10.193.39.193
Starting with just eth1 configured, VLAN interfaces are down:
cubert:~# ifconfig eth1
eth1 Link encap:Ethernet HWaddr 00:40:63:fa:bb:80
inet addr:10.193.38.254 Bcast:10.193.38.255 Mask:255.255.255.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:4504 errors:0 dropped:0 overruns:0 frame:0
TX packets:453 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:49136 (47.9 KiB) TX bytes:21066 (20.5 KiB)
Interrupt:36 Base address:0xdc00
cubert:~# ping 10.193.38.1
PING 10.193.38.1 (10.193.38.1) 56(84) bytes of data.
64 bytes from 10.193.38.1: icmp_seq=1 ttl=64 time=0.885 ms
64 bytes from 10.193.38.1: icmp_seq=2 ttl=64 time=0.889 ms
^C
--- 10.193.38.1 ping statistics ---
2 packets transmitted, 2 received, 0% packet loss, time 1001ms
rtt min/avg/max/mdev = 0.885/0.887/0.889/0.002 ms
cubert:~#
So far so good...
cubert:~# ifup vlan101
Set name-type for VLAN subsystem. Should be visible in /proc/net/vlan/config
Added VLAN with VID == 101 to IF -:eth1:-
cubert:~# ifconfig vlan101
vlan101 Link encap:Ethernet HWaddr 00:40:63:fa:bb:80
inet addr:10.193.39.254 Bcast:10.193.39.255 Mask:255.255.255.192
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)
cubert:~# ping 10.193.39.193
PING 10.193.39.193 (10.193.39.193) 56(84) bytes of data.
64 bytes from 10.193.39.193: icmp_seq=1 ttl=64 time=4.24 ms
64 bytes from 10.193.39.193: icmp_seq=2 ttl=64 time=1.11 ms
^C
--- 10.193.39.193 ping statistics ---
2 packets transmitted, 2 received, 0% packet loss, time 1001ms
rtt min/avg/max/mdev = 1.116/2.681/4.247/1.566 ms
cubert:~#
Also looking good, however:
cubert:~# ping 10.193.38.1
PING 10.193.38.1 (10.193.38.1) 56(84) bytes of data.
^C
--- 10.193.38.1 ping statistics ---
2 packets transmitted, 0 received, 100% packet loss, time 1010ms
And eth1 won't respond again until I take down vlan101 and eth1 and
bring eth1 back up again.
cubert:~# ifdown vlan101
Removed VLAN -:vlan101:-
cubert:~# ping 10.193.38.1
PING 10.193.38.1 (10.193.38.1) 56(84) bytes of data.
^C
--- 10.193.38.1 ping statistics ---
2 packets transmitted, 0 received, 100% packet loss, time 1011ms
cubert:~# ifdown eth1
cubert:~# ifup eth1
cubert:~# ping 10.193.38.1
PING 10.193.38.1 (10.193.38.1) 56(84) bytes of data.
64 bytes from 10.193.38.1: icmp_seq=1 ttl=64 time=0.869 ms
64 bytes from 10.193.38.1: icmp_seq=2 ttl=64 time=0.947 ms
^C
--- 10.193.38.1 ping statistics ---
2 packets transmitted, 2 received, 0% packet loss, time 1003ms
rtt min/avg/max/mdev = 0.869/0.908/0.947/0.039 ms
Here is my configuration in /etc/network/interfaces (Debian/Lenny):
iface eth1 inet static
address 10.193.38.254
netmask 255.255.255.0
broadcast 10.193.38.255
network 10.193.38.0
iface vlan101 inet static
address 10.193.39.254
netmask 255.255.255.192
broadcast 10.193.39.255
network 10.193.39.192
vlan_raw_device eth1
A bit of searching found a few references to similar problems going
back a few years (2005, 2007). Sounded like there were some driver
issues, but it wasn't clear from the messages I found whether they
were believed to be fixed or not. I tried the same test using a
differnt NIC with the tg3 driver and there were no problems, so it
looks to me like it's still a via-velocity issue. Unfortunately I
don't have room to add NICs to this machine and need to use the on
board Via hardware.
This is the network hardware on the non-working Via board:
cubert:~# lspci -k
...
02:00.0 Ethernet controller: VIA Technologies, Inc. VT6120/VT6121/VT6122 Gigabit Ethernet Adapter (rev 82)
Kernel driver in use: via-velocity
03:00.0 Ethernet controller: VIA Technologies, Inc. VT6120/VT6121/VT6122 Gigabit Ethernet Adapter (rev 82)
Kernel driver in use: via-velocity
And on my laptop where this same config does work:
kulgan:~# lspci -k
...
09:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5752 Gigabit Ethernet PCI Express (rev 02)
Subsystem: Dell Device 01d6
Kernel driver in use: tg3
I understand that it's not best practice to combine tagged and
untagged frames on the same link (something to do with VLAN hopping
attacks), so perhaps this is not a priority to fix. However, I'm happy
to test patches if there are any.
Regards,
Kevin Shanahan.
^ permalink raw reply
* Subject: [PATCH 0/6] bna: Brocade 10Gb Ethernet device driver
From: Rasesh Mody @ 2009-11-13 3:46 UTC (permalink / raw)
To: netdev; +Cc: adapter_linux_open_src_team
From: Rasesh Mody <rmody@brocade.com>
This is patch 0/6 which contains the summary of changes we've
done in this perticular submission for Brocade's BR1010/BR1020
10Gb CEE capable ethernet adapter. Source is based against
net-next-2.6.
We wish this patch to be considered for inclusion in net-next-2.6.
Please NOTE we've updated patches to a newer code, based on Brocade
Release 2.1, that has enhancements for better control path
synchronization.
We have addressed the following is a list of review comments apart
from the required clean-up:
1. Removed all the module parameters except bnad_ioc_auto_recover
2. Removed all the proprietary implementation of a driver debug
logging facility.
3. Fixed bnad_netpoll() for MSIX
4. Removed macros e.g. NETIF_F_*, SKB_GSO_TCPV4, VMK*,
BNAD_RXBUF_HEADROOM etc.
5. Removed bnad_ioctl() function
6. Remove call to netif_stop_queue after netif_carrier_off()
7. Removed bnad_get_stats_count()
8. Change return type to netdev_tx_t for bnad_start_xmit()
9. Remove superfluous casting to irq_handler_t
10. Use setup_timer() for timer initialization, use msecs_to_jiffies()
in mod_timer()
11. Convert BNAD_RESET_Q to a function
12. Removed pci_saved_config from bnad structure
13. Used module_param() to validate module params
14. Removed OS abstraction
- All endian-ness conversion functions
- Changed bfa_boolean to bool
- Changed BFA_[TRUE|FALSE] to true/false
15. Changed naming style for structures : dropped ._s. suffix
16. Removed setting of netdev->trans_start & netdev->last_rx
Signed-off-by: Rasesh Mody <rmody@brocade.com>
---
0 files changed
^ permalink raw reply
* Subject: [PATCH 1/6] bna: Brocade 10Gb Ethernet device driver
From: Rasesh Mody @ 2009-11-13 3:46 UTC (permalink / raw)
To: netdev; +Cc: adapter_linux_open_src_team
From: Rasesh Mody <rmody@brocade.com>
This is patch 1/6 which contains linux driver source for
Brocade's BR1010/BR1020 10Gb CEE capable ethernet adapter.
Source is based against net-next-2.6.
We wish this patch to be considered for inclusion in net-next-2.6
Signed-off-by: Rasesh Mody <rmody@brocade.com>
---
bnad.c | 3710 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
bnad.h | 350 ++++++
2 files changed, 4060 insertions(+)
diff -ruP net-next-2.6-orig/drivers/net/bna/bnad.c net-next-2.6-mod/drivers/net/bna/bnad.c
--- net-next-2.6-orig/drivers/net/bna/bnad.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bnad.c 2009-11-12 19:03:38.439405000 -0800
@@ -0,0 +1,3710 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ */
+
+/**
+ * bnad.c Brocade 10G PCIe Ethernet driver.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/pci.h>
+#include <linux/bitops.h>
+#include <linux/etherdevice.h>
+#include <linux/in.h>
+#include <linux/ethtool.h>
+#include <linux/if_vlan.h>
+#include <linux/delay.h>
+#include <linux/rtnetlink.h>
+#include <linux/if_ether.h>
+#include <linux/workqueue.h>
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/tcp.h>
+#include <linux/udp.h>
+#include <linux/pm.h>
+#include <linux/random.h>
+
+#include <net/checksum.h>
+
+#include "bnad.h"
+#include <cna.h>
+#include "bna_iocll.h"
+#include "bna_intr.h"
+#include "bnad_defs.h"
+
+
+
+
+#define BNAD_TXQ_WI_NEEDED(_vectors) (((_vectors) + 3) >> 2)
+static uint bnad_msix = 1;
+static uint bnad_small_large_rxbufs = 1;
+static uint bnad_rxqsets_used;
+static uint bnad_ipid_mode;
+static uint bnad_vlan_strip = 1;
+static uint bnad_txq_depth = BNAD_ENTRIES_PER_TXQ;
+static uint bnad_rxq_depth = BNAD_ENTRIES_PER_RXQ;
+static uint bnad_log_level ;
+
+static uint bnad_ioc_auto_recover = 1;
+module_param(bnad_ioc_auto_recover, uint, 0444);
+MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable auto recovery");
+
+uint bnad_rxqs_per_cq = 2;
+
+const char *bnad_states[] = {
+ "START",
+ "INIT",
+ "INIT_DOWN",
+ "INIT_DISABLING",
+ "INIT_DISABLED",
+ "OPENING",
+ "OPEN",
+ "OPEN_DOWN",
+ "OPEN_DISABING",
+ "OPEN_DISABLED",
+ "CLOSING",
+ "UNLOADING"
+};
+
+
+static void bnad_disable_msix(struct bnad *bnad);
+static void bnad_free_ibs(struct bnad *bnad);
+static void bnad_set_rx_mode(struct net_device *netdev);
+static void bnad_set_rx_mode_locked(struct net_device *netdev);
+static void bnad_reconfig_vlans(struct bnad *bnad);
+static void bnad_q_num_init(struct bnad *bnad, uint rxqsets);
+static int bnad_set_mac_address(struct net_device *netdev, void *addr);
+static int bnad_set_mac_address_locked(struct net_device *netdev, void *addr);
+static int bnad_disable_locked(struct bnad *bnad);
+static int bnad_change_mtu(struct net_device *netdev, int new_mtu);
+static void
+bnad_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
+static void bnad_vlan_rx_add_vid(struct net_device *netdev, unsigned short vid);
+static void
+bnad_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid);
+static void bnad_netpoll(struct net_device *netdev);
+
+static const struct net_device_ops bnad_netdev_ops = {
+ .ndo_open = bnad_open,
+ .ndo_stop = bnad_stop,
+ .ndo_start_xmit = bnad_start_xmit,
+ .ndo_get_stats = bnad_get_stats,
+ .ndo_set_rx_mode = &bnad_set_rx_mode,
+ .ndo_set_multicast_list = bnad_set_rx_mode,
+ .ndo_set_mac_address = bnad_set_mac_address,
+ .ndo_change_mtu = bnad_change_mtu,
+
+ .ndo_vlan_rx_register = bnad_vlan_rx_register,
+ .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
+ .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = bnad_netpoll,
+#endif
+};
+
+
+u32
+bnad_get_msglevel(struct net_device *netdev)
+{
+ return bnad_log_level;
+}
+
+void
+bnad_set_msglevel(struct net_device *netdev, u32 msglevel)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ bnad_conf_lock();
+ bnad_log_level = msglevel;
+ bnad_conf_unlock();
+}
+
+static unsigned int
+bnad_free_txbufs(struct bnad_txq_info *txqinfo, u16 updated_txq_cons)
+{
+ struct bnad *bnad = txqinfo->bnad;
+ unsigned int sent_packets = 0, sent_bytes = 0;
+ u16 wis, unmap_cons;
+ struct bnad_skb_unmap *unmap_array;
+ struct sk_buff *skb;
+ int i;
+
+ wis = BNAD_Q_INDEX_CHANGE(txqinfo->txq.q.consumer_index,
+ updated_txq_cons, txqinfo->txq.q.q_depth);
+ BNA_ASSERT(wis <=
+ BNA_QE_IN_USE_CNT(&txqinfo->txq.q, txqinfo->txq.q.q_depth));
+ unmap_array = txqinfo->skb_unmap_q.unmap_array;
+ unmap_cons = txqinfo->skb_unmap_q.consumer_index;
+ prefetch(&unmap_array[unmap_cons + 1]);
+ while (wis) {
+ skb = unmap_array[unmap_cons].skb;
+ BNA_ASSERT(skb);
+ unmap_array[unmap_cons].skb = NULL;
+ BNA_ASSERT(wis >=
+ BNAD_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags));
+ BNA_ASSERT(((txqinfo->skb_unmap_q.producer_index -
+ unmap_cons) & (txqinfo->skb_unmap_q.q_depth -
+ 1)) >=
+ 1 + skb_shinfo(skb)->nr_frags);
+
+ sent_packets++;
+ sent_bytes += skb->len;
+ wis -= BNAD_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
+
+ pci_unmap_single(bnad->pcidev,
+ pci_unmap_addr(&unmap_array[unmap_cons],
+ dma_addr), skb_headlen(skb),
+ PCI_DMA_TODEVICE);
+ pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
+ BNA_QE_INDX_ADD(unmap_cons, 1, txqinfo->skb_unmap_q.q_depth);
+ prefetch(&unmap_array[unmap_cons + 1]);
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ pci_unmap_page(bnad->pcidev,
+ pci_unmap_addr(&unmap_array[unmap_cons],
+ dma_addr),
+ skb_shinfo(skb)->frags[i].size,
+ PCI_DMA_TODEVICE);
+ pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
+ 0);
+ BNA_QE_INDX_ADD(unmap_cons, 1,
+ txqinfo->skb_unmap_q.q_depth);
+ prefetch(&unmap_array[unmap_cons + 1]);
+ }
+ dev_kfree_skb_any(skb);
+ }
+
+ /* Update consumer pointers. */
+ txqinfo->txq.q.consumer_index = updated_txq_cons;
+ txqinfo->skb_unmap_q.consumer_index = unmap_cons;
+ txqinfo->tx_packets += sent_packets;
+ txqinfo->tx_bytes += sent_bytes;
+ return sent_packets;
+}
+
+static inline void
+bnad_disable_txrx_irqs(struct bnad *bnad)
+{
+ int i;
+
+ for (i = 0; i < bnad->txq_num; i++) {
+ bna_ib_coalescing_timer_set(bnad->priv, &bnad->txq_table[i].ib,
+ 0);
+ bna_ib_ack(bnad->priv, &bnad->txq_table[i].ib, 0);
+ }
+
+ for (i = 0; i < bnad->cq_num; i++) {
+ bna_ib_coalescing_timer_set(bnad->priv, &bnad->cq_table[i].ib,
+ 0);
+ bna_ib_ack(bnad->priv, &bnad->cq_table[i].ib, 0);
+ }
+}
+
+static inline void
+bnad_enable_txrx_irqs(struct bnad *bnad)
+{
+ int i;
+
+ spin_lock_irq(&bnad->priv_lock);
+ for (i = 0; i < bnad->txq_num; i++) {
+ bna_ib_coalescing_timer_set(bnad->priv, &bnad->txq_table[i].ib,
+ bnad->tx_coalescing_timeo);
+ bna_ib_ack(bnad->priv, &bnad->txq_table[i].ib, 0);
+ }
+
+ for (i = 0; i < bnad->cq_num; i++) {
+ bna_ib_coalescing_timer_set(bnad->priv, &bnad->cq_table[i].ib,
+ bnad->cq_table[i].
+ rx_coalescing_timeo);
+ bna_ib_ack(bnad->priv, &bnad->cq_table[i].ib, 0);
+ }
+ spin_unlock_irq(&bnad->priv_lock);
+}
+
+static inline void
+bnad_disable_rx_irq(struct bnad *bnad, struct bnad_cq_info *cqinfo)
+{
+ bna_ib_coalescing_timer_set(bnad->priv, &cqinfo->ib, 0);
+ bna_ib_ack(bnad->priv, &cqinfo->ib, 0);
+}
+static inline void
+bnad_enable_rx_irq(struct bnad *bnad, struct bnad_cq_info *cqinfo)
+{
+ spin_lock_irq(&bnad->priv_lock);
+
+ bna_ib_coalescing_timer_set(bnad->priv, &cqinfo->ib,
+ cqinfo->rx_coalescing_timeo);
+
+ bna_ib_ack(bnad->priv, &cqinfo->ib, 0);
+
+ spin_unlock_irq(&bnad->priv_lock);
+}
+
+static unsigned int
+bnad_tx(struct bnad *bnad, struct bnad_txq_info *txqinfo)
+{
+ struct net_device *netdev = bnad->netdev;
+ unsigned int sent;
+
+ if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &txqinfo->flags))
+ return 0;
+
+ sent = bnad_free_txbufs(txqinfo,
+ (u16) (*txqinfo->hw_consumer_index));
+ if (sent) {
+ if (netif_queue_stopped(netdev) &&
+ netif_carrier_ok(netdev) &&
+ BNA_Q_FREE_COUNT(&txqinfo->txq) >=
+ BNAD_NETIF_WAKE_THRESHOLD) {
+ netif_wake_queue(netdev);
+ bnad->stats.netif_queue_wakeup++;
+ }
+ bna_ib_ack(bnad->priv, &txqinfo->ib, sent);
+ } else {
+ bna_ib_ack(bnad->priv, &txqinfo->ib, 0);
+ }
+
+ smp_mb__before_clear_bit();
+ clear_bit(BNAD_TXQ_FREE_SENT, &txqinfo->flags);
+
+ return sent;
+}
+
+static irqreturn_t
+bnad_msix_tx(int irq, void *data)
+{
+ struct bnad_txq_info *txqinfo = (struct bnad_txq_info *)data;
+ struct bnad *bnad = txqinfo->bnad;
+
+ bnad_tx(bnad, txqinfo);
+
+ return IRQ_HANDLED;
+}
+
+static void
+bnad_alloc_rxbufs(struct bnad_rxq_info *rxqinfo)
+{
+ u16 to_alloc, alloced, unmap_prod, wi_range;
+ struct bnad_skb_unmap *unmap_array;
+ struct bna_rxq_entry *rxent;
+ struct sk_buff *skb;
+ dma_addr_t dma_addr;
+
+ alloced = 0;
+ to_alloc =
+ BNA_QE_FREE_CNT(&rxqinfo->skb_unmap_q,
+ rxqinfo->skb_unmap_q.q_depth);
+
+ unmap_array = rxqinfo->skb_unmap_q.unmap_array;
+ unmap_prod = rxqinfo->skb_unmap_q.producer_index;
+ BNA_RXQ_QPGE_PTR_GET(unmap_prod, &rxqinfo->rxq.q, rxent, wi_range);
+ BNA_ASSERT(wi_range && wi_range <= rxqinfo->rxq.q.q_depth);
+
+ while (to_alloc--) {
+ if (!wi_range) {
+ BNA_RXQ_QPGE_PTR_GET(unmap_prod, &rxqinfo->rxq.q, rxent,
+ wi_range);
+ BNA_ASSERT(wi_range &&
+ wi_range <= rxqinfo->rxq.q.q_depth);
+ }
+ skb = alloc_skb(rxqinfo->rxq_config.buffer_size + NET_IP_ALIGN,
+ GFP_ATOMIC);
+ if (unlikely(!skb)) {
+ rxqinfo->rxbuf_alloc_failed++;
+ goto finishing;
+ }
+ skb->dev = rxqinfo->bnad->netdev;
+ skb_reserve(skb, NET_IP_ALIGN);
+ unmap_array[unmap_prod].skb = skb;
+ dma_addr =
+ pci_map_single(rxqinfo->bnad->pcidev, skb->data,
+ rxqinfo->rxq_config.buffer_size,
+ PCI_DMA_FROMDEVICE);
+ pci_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
+ dma_addr);
+ BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
+ BNA_QE_INDX_ADD(unmap_prod, 1, rxqinfo->skb_unmap_q.q_depth);
+
+ rxent++;
+ wi_range--;
+ alloced++;
+ }
+
+finishing:
+ if (likely(alloced)) {
+ rxqinfo->skb_unmap_q.producer_index = unmap_prod;
+ rxqinfo->rxq.q.producer_index = unmap_prod;
+ smp_mb();
+ bna_rxq_prod_indx_doorbell(&rxqinfo->rxq);
+ }
+}
+
+static inline void
+bnad_refill_rxq(struct bnad_rxq_info *rxqinfo)
+{
+ if (!test_and_set_bit(BNAD_RXQ_REFILL, &rxqinfo->flags)) {
+ if (BNA_QE_FREE_CNT
+ (&rxqinfo->skb_unmap_q,
+ rxqinfo->skb_unmap_q.
+ q_depth) >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
+ bnad_alloc_rxbufs(rxqinfo);
+ smp_mb__before_clear_bit();
+ clear_bit(BNAD_RXQ_REFILL, &rxqinfo->flags);
+ }
+}
+
+static unsigned int
+bnad_poll_cq(struct bnad *bnad, struct bnad_cq_info *cqinfo, int budget)
+{
+ struct bna_cq_entry *cmpl, *next_cmpl;
+ unsigned int wi_range, packets = 0, wis = 0;
+ struct bnad_rxq_info *rxqinfo = NULL;
+ struct bnad_unmap_q *unmap_q;
+ struct sk_buff *skb;
+ u32 flags;
+ struct bna_pkt_rate *pkt_rt = &cqinfo->pkt_rate;
+
+ prefetch(bnad);
+ prefetch(bnad->netdev);
+ cmpl = bna_cq_pg_prod_ptr(&cqinfo->cq, &wi_range);
+ BNA_ASSERT(wi_range && wi_range <= cqinfo->cq.q.q_depth);
+ while (cmpl->valid && packets < budget) {
+ packets++;
+ BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
+
+ rxqinfo = &bnad->rxq_table[cmpl->rxq_id];
+ unmap_q = &rxqinfo->skb_unmap_q;
+
+ skb = unmap_q->unmap_array[unmap_q->consumer_index].skb;
+ BNA_ASSERT(skb);
+ prefetch(skb->data - NET_IP_ALIGN);
+ unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL;
+ pci_unmap_single(bnad->pcidev,
+ pci_unmap_addr(&unmap_q->
+ unmap_array[unmap_q->
+ consumer_index],
+ dma_addr),
+ rxqinfo->rxq_config.buffer_size,
+ PCI_DMA_FROMDEVICE);
+ BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
+ /* XXX May be bad for performance. */
+ /* CATAPULT_BRINGUP : Should we add all the packets ? */
+ BNA_Q_CI_ADD(&rxqinfo->rxq, 1);
+
+ wis++;
+ if (likely(--wi_range))
+ next_cmpl = cmpl + 1;
+ else {
+ BNA_Q_PI_ADD(&cqinfo->cq, wis);
+ wis = 0;
+ next_cmpl = bna_cq_pg_prod_ptr(&cqinfo->cq, &wi_range);
+ BNA_ASSERT(wi_range &&
+ wi_range <= cqinfo->cq.q.q_depth);
+ }
+ prefetch(next_cmpl);
+
+ flags = ntohl(cmpl->flags);
+ if (unlikely
+ (flags &
+ (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
+ BNA_CQ_EF_TOO_LONG))) {
+ dev_kfree_skb_any(skb);
+ rxqinfo->rx_packets_with_error++;
+ goto next;
+ }
+
+ skb_put(skb, ntohs(cmpl->length));
+ if (likely
+ (bnad->rx_csum &&
+ (((flags & BNA_CQ_EF_IPV4) &&
+ (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
+ (flags & BNA_CQ_EF_IPV6)) &&
+ (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
+ (flags & BNA_CQ_EF_L4_CKSUM_OK)))
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ else
+ skb->ip_summed = CHECKSUM_NONE;
+
+ rxqinfo->rx_packets++;
+ rxqinfo->rx_bytes += skb->len;
+ skb->protocol = eth_type_trans(skb, bnad->netdev);
+
+ if (bnad->vlangrp && (flags & BNA_CQ_EF_VLAN) &&
+ bnad_vlan_strip) {
+ BNA_ASSERT(cmpl->vlan_tag);
+ vlan_hwaccel_receive_skb(skb, bnad->vlangrp,
+ ntohs(cmpl->vlan_tag));
+ } else
+ netif_receive_skb(skb);
+next:
+ cmpl->valid = 0;
+ cmpl = next_cmpl;
+ }
+
+ BNA_Q_PI_ADD(&cqinfo->cq, wis);
+
+ if (likely(rxqinfo)) {
+ bna_ib_ack(bnad->priv, &cqinfo->ib, packets);
+ /* Check the current queue first. */
+ bnad_refill_rxq(rxqinfo);
+
+ /* XXX counters per queue for refill? */
+ if (likely(bnad_small_large_rxbufs)) {
+ /* There are 2 RxQs - small and large buffer queues */
+ unsigned int rxq_id = (rxqinfo->rxq_id ^ 1);
+ bnad_refill_rxq(&bnad->rxq_table[rxq_id]);
+ }
+ } else {
+ bna_ib_ack(bnad->priv, &cqinfo->ib, 0);
+ }
+
+ return packets;
+}
+
+static irqreturn_t
+bnad_msix_rx(int irq, void *data)
+{
+ struct bnad_cq_info *cqinfo = (struct bnad_cq_info *)data;
+ struct bnad *bnad = cqinfo->bnad;
+
+ if (likely(napi_schedule_prep(&cqinfo->napi))) {
+ bnad_disable_rx_irq(bnad, cqinfo);
+ __napi_schedule(&cqinfo->napi);
+ }
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t
+bnad_msix_err_mbox(int irq, void *data)
+{
+ struct net_device *netdev = data;
+ struct bnad *bnad = netdev_priv(netdev);
+ u32 intr_status;
+
+ spin_lock(&bnad->priv_lock);
+
+ bna_intr_status_get(bnad->priv, &intr_status);
+ if (BNA_IS_MBOX_ERR_INTR(intr_status))
+ bna_mbox_err_handler(bnad->priv, intr_status);
+
+ spin_unlock(&bnad->priv_lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t
+bnad_isr(int irq, void *data)
+{
+ struct net_device *netdev = data;
+ struct bnad *bnad = netdev_priv(netdev);
+ u32 intr_status;
+
+ spin_lock(&bnad->priv_lock);
+ bna_intr_status_get(bnad->priv, &intr_status);
+
+ if (!intr_status) {
+ spin_unlock(&bnad->priv_lock);
+ return IRQ_NONE;
+ }
+
+ if (BNA_IS_MBOX_ERR_INTR(intr_status)) {
+ bna_mbox_err_handler(bnad->priv, intr_status);
+ spin_unlock(&bnad->priv_lock);
+ if (BNA_IS_ERR_INTR(intr_status) ||
+ !BNA_IS_INTX_DATA_INTR(intr_status))
+ goto exit_isr;
+ } else
+ spin_unlock(&bnad->priv_lock);
+
+ if (likely(napi_schedule_prep(&bnad->cq_table[0].napi))) {
+ bnad_disable_txrx_irqs(bnad);
+ __napi_schedule(&bnad->cq_table[0].napi);
+ }
+
+exit_isr:
+ return IRQ_HANDLED;
+}
+
+static int
+bnad_request_mbox_irq(struct bnad *bnad)
+{
+ int err;
+
+ if (bnad->config & BNAD_CF_MSIX) {
+ err = request_irq(bnad->msix_table[bnad->msix_num - 1].vector,
+ &bnad_msix_err_mbox, 0,
+ bnad->netdev->name, bnad->netdev);
+ } else {
+ err = request_irq(bnad->pcidev->irq, &bnad_isr,
+ IRQF_SHARED, bnad->netdev->name,
+ bnad->netdev);
+ }
+
+ if (err) {
+ dev_err(&bnad->pcidev->dev,
+ "Request irq for mailbox failed: %d\n", err);
+ return err;
+ }
+
+ if (bnad->config & BNAD_CF_MSIX)
+ bna_mbox_msix_idx_set(bnad->priv, bnad->msix_num - 1);
+
+ bna_mbox_intr_enable(bnad->priv);
+ return 0;
+}
+
+static void
+bnad_sync_mbox_irq(struct bnad *bnad)
+{
+ uint irq;
+
+ if (bnad->config & BNAD_CF_MSIX)
+ irq = bnad->msix_table[bnad->msix_num - 1].vector;
+ else
+ irq = bnad->pcidev->irq;
+ synchronize_irq(irq);
+}
+
+static void
+bnad_free_mbox_irq(struct bnad *bnad)
+{
+ uint irq;
+
+ if (bnad->config & BNAD_CF_MSIX)
+ irq = bnad->msix_table[bnad->msix_num - 1].vector;
+ else
+ irq = bnad->pcidev->irq;
+
+
+ spin_lock_irq(&bnad->priv_lock);
+ bna_mbox_intr_disable(bnad->priv);
+ spin_unlock_irq(&bnad->priv_lock);
+
+ free_irq(irq, bnad->netdev);
+}
+
+static int
+bnad_request_txq_irq(struct bnad *bnad, uint txq_id)
+{
+ BNA_ASSERT(txq_id < bnad->txq_num);
+ if (!(bnad->config & BNAD_CF_MSIX))
+ return 0;
+ return request_irq(bnad->msix_table[txq_id].vector,
+ &bnad_msix_tx, 0,
+ bnad->txq_table[txq_id].name,
+ &bnad->txq_table[txq_id]);
+}
+
+int
+bnad_request_cq_irq(struct bnad *bnad, uint cq_id)
+{
+ BNA_ASSERT(cq_id < bnad->cq_num);
+ if (!(bnad->config & BNAD_CF_MSIX))
+ return 0;
+ return request_irq(bnad->msix_table[bnad->txq_num + cq_id].vector,
+ &bnad_msix_rx, 0,
+ bnad->cq_table[cq_id].name, &bnad->cq_table[cq_id]);
+}
+
+static int
+bnad_request_txrx_irqs(struct bnad *bnad)
+{
+ struct msix_entry *entries;
+ int i;
+ int err;
+ char message[BNA_MESSAGE_SIZE];
+
+ if (!(bnad->config & BNAD_CF_MSIX)) {
+ u32 mask;
+ bna_intx_disable(bnad->priv, &mask);
+ mask &= ~0xffff;
+ bna_intx_enable(bnad->priv, mask);
+ for (i = 0; i < bnad->ib_num; i++)
+ bna_ib_ack(bnad->priv, bnad->ib_table[i].ib, 0);
+ return 0;
+ }
+
+ entries = bnad->msix_table;
+ for (i = 0; i < bnad->txq_num; i++) {
+ err = bnad_request_txq_irq(bnad, i);
+ if (err) {
+ sprintf(message, "%s request irq for TxQ %d failed %d",
+ bnad->netdev->name, i, err);
+ while (--i >= 0) {
+ free_irq(entries[i].vector,
+ &bnad->txq_table[i]);
+ }
+ return err;
+ }
+ }
+
+ for (i = 0; i < bnad->cq_num; i++) {
+ err = bnad_request_cq_irq(bnad, i);
+ if (err) {
+ sprintf(message, "%s request irq for CQ %u failed %d",
+ bnad->netdev->name, i, err);
+ while (--i >= 0) {
+ free_irq(entries[bnad->txq_num + i].vector,
+ &bnad->cq_table[i]);
+ }
+ goto free_txq_irqs;
+ }
+ }
+
+ return 0;
+
+free_txq_irqs:
+ for (i = 0; i < bnad->txq_num; i++)
+ free_irq(entries[i].vector, &bnad->txq_table[i]);
+
+ bnad_disable_msix(bnad);
+
+ return err;
+}
+
+static void
+bnad_free_txrx_irqs(struct bnad *bnad)
+{
+ struct msix_entry *entries;
+ uint i;
+
+ if (bnad->config & BNAD_CF_MSIX) {
+ entries = bnad->msix_table;
+ for (i = 0; i < bnad->txq_num; i++)
+ free_irq(entries[i].vector, &bnad->txq_table[i]);
+
+ for (i = 0; i < bnad->cq_num; i++) {
+ free_irq(entries[bnad->txq_num + i].vector,
+ &bnad->cq_table[i]);
+ }
+ } else
+ synchronize_irq(bnad->pcidev->irq);
+}
+
+void
+bnad_setup_ib(struct bnad *bnad, uint ib_id)
+{
+ struct bnad_ib_entry *ib_entry;
+
+
+ BNA_ASSERT(ib_id < bnad->ib_num);
+ ib_entry = &bnad->ib_table[ib_id];
+ spin_lock_irq(&bnad->priv_lock);
+ bna_ib_config_set(bnad->priv, ib_entry->ib, ib_id,
+ &ib_entry->ib_config);
+ /* Start the IB */
+ bna_ib_ack(bnad->priv, ib_entry->ib, 0);
+ spin_unlock_irq(&bnad->priv_lock);
+}
+
+static void
+bnad_setup_ibs(struct bnad *bnad)
+{
+ int i;
+
+ for (i = 0; i < bnad->txq_num; i++)
+ bnad_setup_ib(bnad, bnad->txq_table[i].txq_config.ib_id);
+
+ for (i = 0; i < bnad->cq_num; i++)
+ bnad_setup_ib(bnad, bnad->cq_table[i].cq_config.ib_id);
+}
+
+/* These functions are called back with priv_lock held. */
+
+static void
+bnad_lldp_get_cfg_cb(void *arg, u8 status)
+{
+ struct bnad *bnad = arg;
+ bnad->lldp_comp_status = status;
+ complete(&bnad->lldp_comp);
+}
+
+static void
+bnad_cee_get_attr_cb(void *arg, bfa_status_t status)
+{
+ struct bnad *bnad = arg;
+ bnad->lldp_comp_status = status;
+ complete(&bnad->lldp_comp);
+}
+
+static void
+bnad_cee_get_stats_cb(void *arg, bfa_status_t status)
+{
+ struct bnad *bnad = arg;
+ bnad->cee_stats_comp_status = status;
+ complete(&bnad->cee_stats_comp);
+}
+
+static void
+bnad_cee_reset_stats_cb(void *arg, bfa_status_t status)
+{
+ struct bnad *bnad = arg;
+ bnad->cee_reset_stats_status = status;
+ complete(&bnad->cee_reset_stats_comp);
+}
+
+static void
+bnad_ucast_set_cb(void *arg, u8 status)
+{
+ struct bnad *bnad = (struct bnad *)arg;
+
+ bnad->ucast_comp_status = status;
+ complete(&bnad->ucast_comp);
+}
+
+static void
+bnad_q_stop_cb(void *arg, u8 status)
+{
+ struct bnad *bnad = arg;
+
+ bnad->qstop_comp_status = status;
+ complete(&bnad->qstop_comp);
+}
+
+static unsigned int
+bnad_get_priority(struct bnad *bnad, u8 prio_map)
+{
+ unsigned int i;
+
+ if (prio_map) {
+ for (i = 0; i < 8; i++) {
+ if ((prio_map >> i) & 0x1)
+ break;
+ }
+ return i;
+ }
+ return 0;
+}
+
+static void
+bnad_link_up_cb(void *arg, u8 status)
+{
+ struct bnad *bnad = (struct bnad *)arg;
+ struct bfi_ll_aen *up_aen = (struct bfi_ll_aen *)
+ (&bnad->priv->mb_msg);
+
+
+
+ bnad->cee_linkup = up_aen->cee_linkup;
+ bnad->priority = bnad_get_priority(bnad, up_aen->prio_map);
+
+ bnad->link_state = BNAD_LS_UP;
+ bnad->work_flags |= BNAD_WF_LS_NOTIFY;
+
+ schedule_work(&bnad->work);
+}
+
+static void
+bnad_link_down_cb(void *arg, u8 status)
+{
+ struct bnad *bnad = (struct bnad *)arg;
+
+
+ bnad->link_state = BNAD_LS_DOWN;
+ bnad->work_flags |= BNAD_WF_LS_NOTIFY;
+
+ schedule_work(&bnad->work);
+}
+
+static void
+bnad_stats_get_cb(void *arg, u8 status)
+{
+ struct bnad *bnad = (struct bnad *)arg;
+
+ bnad->stats.hw_stats_updates++;
+ if (bnad->state == BNAD_S_OPEN)
+ mod_timer(&bnad->stats_timer, jiffies + HZ);
+}
+
+
+/* Called with bnad priv_lock held. */
+static void
+bnad_hw_error(struct bnad *bnad, u8 status)
+{
+ unsigned int irq;
+ char message[BNA_MESSAGE_SIZE];
+
+ set_bit(BNAD_F_HWERROR, &bnad->flags);
+
+ bna_mbox_intr_disable(bnad->priv);
+ if (bnad->config & BNAD_CF_MSIX) {
+ if (!test_and_set_bit(BNAD_F_MBOX_IRQ_DISABLED, &bnad->flags)) {
+ irq = bnad->msix_table[bnad->msix_num - 1].vector;
+ sprintf(message, "Disabling Mbox IRQ %d for port %d",
+ irq, bnad->bna_id);
+ DPRINTK(INFO, "%s",
+ message);
+ disable_irq_nosync(irq);
+ }
+ }
+
+ bna_cleanup(bnad->priv);
+
+ bnad->work_flags = BNAD_WF_ERROR;
+ if (bnad->state != BNAD_S_UNLOADING)
+ schedule_work(&bnad->work);
+}
+
+static void
+bnad_hw_error_cb(void *arg, u8 status)
+{
+ struct bnad *bnad = (struct bnad *)arg;
+
+ bnad_hw_error(bnad, status);
+}
+
+int
+bnad_alloc_unmap_q(struct bnad_unmap_q *unmap_q, u32 q_depth)
+{
+ /* Q_depth must be power of 2 for macros to work. */
+ BNA_ASSERT(BNA_POWER_OF_2(q_depth));
+ unmap_q->q_depth = q_depth;
+ unmap_q->unmap_array = vmalloc(q_depth * sizeof(struct bnad_skb_unmap));
+ if (!unmap_q->unmap_array)
+ return -ENOMEM;
+ memset(unmap_q->unmap_array, 0,
+ q_depth * sizeof(struct bnad_skb_unmap));
+ return 0;
+}
+
+static int
+bnad_alloc_unmap_queues(struct bnad *bnad)
+{
+ int i, err = 0;
+ struct bnad_txq_info *txqinfo;
+ struct bnad_rxq_info *rxqinfo;
+ char message[BNA_MESSAGE_SIZE];
+
+ for (i = 0; i < bnad->txq_num; i++) {
+ txqinfo = &bnad->txq_table[i];
+ err = bnad_alloc_unmap_q(&txqinfo->skb_unmap_q,
+ txqinfo->txq.q.q_depth * 4);
+ if (err) {
+ sprintf(message,
+ "%s allocating Tx unmap Q %d failed: %d",
+ bnad->netdev->name, i, err);
+ return err;
+ }
+ }
+ for (i = 0; i < bnad->rxq_num; i++) {
+ rxqinfo = &bnad->rxq_table[i];
+ err = bnad_alloc_unmap_q(&rxqinfo->skb_unmap_q,
+ rxqinfo->rxq.q.q_depth);
+ if (err) {
+ sprintf(message,
+ "%s allocating Rx unmap Q %d failed: %d",
+ bnad->netdev->name, i, err);
+ return err;
+ }
+ }
+ return 0;
+}
+
+static void
+bnad_reset_q(struct bnad *bnad, struct bna_q *q, struct bnad_unmap_q *unmap_q)
+{
+ u32 _ui;
+
+ BNA_ASSERT(q->producer_index == q->consumer_index);
+ BNA_ASSERT(unmap_q->producer_index == unmap_q->consumer_index);
+
+ q->producer_index = 0;
+ q->consumer_index = 0;
+ unmap_q->producer_index = 0;
+ unmap_q->consumer_index = 0;
+
+ for (_ui = 0; _ui < unmap_q->q_depth; _ui++)
+ BNA_ASSERT(!unmap_q->unmap_array[_ui].skb);
+}
+
+static void
+bnad_flush_rxbufs(struct bnad_rxq_info *rxqinfo)
+{
+ struct bnad *bnad = rxqinfo->bnad;
+ struct bnad_unmap_q *unmap_q;
+ struct sk_buff *skb;
+ u32 cq_id;
+
+ unmap_q = &rxqinfo->skb_unmap_q;
+ while (BNA_QE_IN_USE_CNT(unmap_q, unmap_q->q_depth)) {
+ skb = unmap_q->unmap_array[unmap_q->consumer_index].skb;
+ BNA_ASSERT(skb);
+ unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL;
+ pci_unmap_single(bnad->pcidev,
+ pci_unmap_addr(&unmap_q->
+ unmap_array[unmap_q->
+ consumer_index],
+ dma_addr),
+ rxqinfo->rxq_config.buffer_size + NET_IP_ALIGN,
+ PCI_DMA_FROMDEVICE);
+ dev_kfree_skb(skb);
+ BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
+ BNA_Q_CI_ADD(&rxqinfo->rxq, 1);
+ }
+
+ bnad_reset_q(bnad, &rxqinfo->rxq.q, &rxqinfo->skb_unmap_q);
+ cq_id = rxqinfo->rxq_id / bnad_rxqs_per_cq;
+ *bnad->cq_table[cq_id].hw_producer_index = 0;
+}
+
+/* Should be called with conf_lock held. */
+static int
+bnad_disable_txq(struct bnad *bnad, u32 txq_id)
+{
+ int err;
+ char message[BNA_MESSAGE_SIZE];
+
+ WARN_ON(in_interrupt());
+
+ init_completion(&bnad->qstop_comp);
+ spin_lock_irq(&bnad->priv_lock);
+ err = bna_txq_stop(bnad->priv, txq_id);
+ spin_unlock_irq(&bnad->priv_lock);
+
+ if (err) {
+ if (err == BNA_AGAIN)
+ err = 0;
+ goto txq_stop_exit;
+ }
+
+ if (BNAD_NOT_READY(bnad)) {
+ err = BNA_FAIL;
+ goto txq_stop_exit;
+ }
+ wait_for_completion(&bnad->qstop_comp);
+ err = bnad->qstop_comp_status;
+
+ if (err == BFI_LL_CMD_NOT_EXEC) {
+ if (bnad->state == BNAD_S_CLOSING)
+ err = 0;
+ else
+ err = BNA_FAIL;
+ }
+
+txq_stop_exit:
+ if (err) {
+ sprintf(message, "%s stop TxQ %u failed %d", bnad->netdev->name,
+ txq_id, err);
+ DPRINTK(INFO, "%s", message);
+ }
+
+ return err;
+}
+
+/* Should be called with conf_lock held. */
+int
+bnad_disable_rxqs(struct bnad *bnad, u64 rxq_id_mask)
+{
+ int err;
+ char message[BNA_MESSAGE_SIZE];
+
+ WARN_ON(in_interrupt());
+
+ init_completion(&bnad->qstop_comp);
+
+ spin_lock_irq(&bnad->priv_lock);
+ err = bna_multi_rxq_stop(bnad->priv, rxq_id_mask);
+ spin_unlock_irq(&bnad->priv_lock);
+ if (err) {
+ if (err == BNA_AGAIN)
+ err = 0;
+ goto rxq_stop_exit;
+ }
+
+ if (BNAD_NOT_READY(bnad)) {
+ err = BNA_FAIL;
+ goto rxq_stop_exit;
+ }
+ wait_for_completion(&bnad->qstop_comp);
+
+ err = bnad->qstop_comp_status;
+
+ if (err == BFI_LL_CMD_NOT_EXEC) {
+ if (bnad->state == BNAD_S_CLOSING)
+ err = 0;
+ else
+ err = BNA_FAIL;
+ }
+
+rxq_stop_exit:
+ if (err) {
+ sprintf(message, "%s stop RxQs(0x%llu) failed %d",
+ bnad->netdev->name, rxq_id_mask, err);
+ DPRINTK(INFO, "%s", message);
+ }
+
+ return err;
+}
+
+static int
+bnad_poll_rx(struct napi_struct *napi, int budget)
+{
+ struct bnad_cq_info *cqinfo =
+ container_of(napi, struct bnad_cq_info, napi);
+ struct bnad *bnad = cqinfo->bnad;
+ unsigned int rcvd;
+
+ rcvd = bnad_poll_cq(bnad, cqinfo, budget);
+ if (rcvd == budget)
+ return rcvd;
+ napi_complete(napi);
+ bnad->stats.napi_complete++;
+ bnad_enable_rx_irq(bnad, cqinfo);
+ return rcvd;
+}
+
+static int
+bnad_poll_txrx(struct napi_struct *napi, int budget)
+{
+ struct bnad_cq_info *cqinfo =
+ container_of(napi, struct bnad_cq_info, napi);
+ struct bnad *bnad = cqinfo->bnad;
+ unsigned int rcvd;
+
+ bnad_tx(bnad, &bnad->txq_table[0]);
+ rcvd = bnad_poll_cq(bnad, cqinfo, budget);
+ if (rcvd == budget)
+ return rcvd;
+ napi_complete(napi);
+ bnad->stats.napi_complete++;
+ bnad_enable_txrx_irqs(bnad);
+ return rcvd;
+}
+
+static void
+bnad_napi_init(struct bnad *bnad)
+{
+ int (*napi_poll) (struct napi_struct *, int);
+ int i;
+
+ if (bnad->config & BNAD_CF_MSIX)
+ napi_poll = bnad_poll_rx;
+ else
+ napi_poll = bnad_poll_txrx;
+
+ for (i = 0; i < bnad->cq_num; i++)
+ netif_napi_add(bnad->netdev, &bnad->cq_table[i].napi, napi_poll,
+ 64);
+}
+
+static void
+bnad_napi_enable(struct bnad *bnad)
+{
+ int i;
+
+ for (i = 0; i < bnad->cq_num; i++)
+ napi_enable(&bnad->cq_table[i].napi);
+}
+
+static void
+bnad_napi_disable(struct bnad *bnad)
+{
+ int i;
+
+ for (i = 0; i < bnad->cq_num; i++)
+ napi_disable(&bnad->cq_table[i].napi);
+}
+
+static void
+bnad_napi_uninit(struct bnad *bnad)
+{
+ int i;
+
+ for (i = 0; i < bnad->cq_num; i++)
+ netif_napi_del(&bnad->cq_table[i].napi);
+}
+
+static void
+bnad_stop_data_path(struct bnad *bnad, int on_error)
+{
+ int i;
+
+ spin_lock_irq(&bnad->priv_lock);
+ if (!on_error && !BNAD_NOT_READY(bnad)) {
+ bna_txf_disable(bnad->priv, BNAD_TX_FUNC_ID);
+ bna_multi_rxf_disable(bnad->priv, (1 << bnad->rxf_num) - 1);
+ for (i = 0; i < bnad->txq_num; i++)
+ bna_ib_disable(bnad->priv, &bnad->txq_table[i].ib);
+ for (i = 0; i < bnad->cq_num; i++)
+ bna_ib_disable(bnad->priv, &bnad->cq_table[i].ib);
+ }
+ spin_unlock_irq(&bnad->priv_lock);
+
+ /* Wait to make sure Tx and Rx are stopped. */
+ msleep(1000);
+ bnad_free_txrx_irqs(bnad);
+ bnad_sync_mbox_irq(bnad);
+
+ bnad_napi_disable(bnad);
+ bnad_napi_uninit(bnad);
+ /* Delete the stats timer after synchronize with mbox irq. */
+ del_timer_sync(&bnad->stats_timer);
+
+ netif_tx_disable(bnad->netdev);
+ netif_carrier_off(bnad->netdev);
+
+ /*
+ * Remove tasklets if scheduled
+ */
+ tasklet_kill(&bnad->tx_free_tasklet);
+}
+
+static void
+bnad_port_admin_locked(struct bnad *bnad, u8 up)
+{
+
+ spin_lock_irq(&bnad->priv_lock);
+ if (!BNAD_NOT_READY(bnad)) {
+ bna_port_admin(bnad->priv, up);
+ if (up)
+ mod_timer(&bnad->stats_timer, jiffies + HZ);
+ else
+ bnad->link_state = BNAD_LS_DOWN;
+ }
+ spin_unlock_irq(&bnad->priv_lock);
+}
+
+/* Should be called with conf_lock held */
+static int
+bnad_stop_locked_internal(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ char message[BNA_MESSAGE_SIZE];
+
+ switch (bnad->state) {
+ case BNAD_S_OPEN:
+ bnad->state = BNAD_S_CLOSING;
+ bnad_disable_locked(bnad);
+ bnad->state = BNAD_S_INIT;
+ sprintf(message, "%s is stopped", bnad->netdev->name);
+ DPRINTK(INFO, "%s", message);
+ break;
+ case BNAD_S_OPEN_DOWN:
+ bnad->state = BNAD_S_INIT_DOWN;
+ break;
+ case BNAD_S_OPEN_DISABLED:
+ bnad->state = BNAD_S_INIT_DISABLED;
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+
+
+/* Should be called with conf_lock held */
+int
+bnad_ioc_disabling_locked(struct bnad *bnad)
+{
+ switch (bnad->state) {
+ case BNAD_S_INIT:
+ case BNAD_S_INIT_DOWN:
+ bnad->state = BNAD_S_INIT_DISABLING;
+ break;
+ case BNAD_S_OPEN:
+ bnad->state = BNAD_S_OPEN_DISABLING;
+ bnad_port_admin_locked(bnad, BNA_DISABLE);
+ bnad_disable_locked(bnad);
+ break;
+ case BNAD_S_OPEN_DOWN:
+ bnad->state = BNAD_S_OPEN_DISABLING;
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static int
+bnad_alloc_ib(struct bnad *bnad, uint ib_id)
+{
+ struct bnad_ib_entry *ib_entry;
+ dma_addr_t dma_addr;
+
+ BNA_ASSERT(bnad->ib_table && ib_id < bnad->ib_num);
+ ib_entry = &bnad->ib_table[ib_id];
+ ib_entry->ib_seg_addr =
+ pci_alloc_consistent(bnad->pcidev, L1_CACHE_BYTES, &dma_addr);
+ if (!ib_entry->ib_seg_addr)
+ return -ENOMEM;
+
+ BNA_SET_DMA_ADDR(dma_addr, &ib_entry->ib_config.ib_seg_addr);
+ return 0;
+}
+static int
+bnad_alloc_ibs(struct bnad *bnad)
+{
+ uint i;
+ int err;
+
+ bnad->ib_num = bnad->txq_num + bnad->cq_num;
+ bnad->ib_table =
+ kzalloc(bnad->ib_num * sizeof(struct bnad_ib_entry),
+ GFP_KERNEL);
+ if (!bnad->ib_table)
+ return -ENOMEM;
+
+ for (i = 0; i < bnad->ib_num; i++) {
+ err = bnad_alloc_ib(bnad, i);
+ if (err)
+ goto free_ibs;
+ }
+ return 0;
+
+free_ibs:
+ bnad_free_ibs(bnad);
+ return err;
+}
+
+void
+bnad_free_ib(struct bnad *bnad, uint ib_id)
+{
+ struct bnad_ib_entry *ib_entry;
+ dma_addr_t dma_addr;
+
+ BNA_ASSERT(bnad->ib_table && ib_id < bnad->ib_num);
+ ib_entry = &bnad->ib_table[ib_id];
+ if (ib_entry->ib_seg_addr) {
+ BNA_GET_DMA_ADDR(&ib_entry->ib_config.ib_seg_addr, dma_addr);
+ pci_free_consistent(bnad->pcidev, L1_CACHE_BYTES,
+ ib_entry->ib_seg_addr, dma_addr);
+ ib_entry->ib_seg_addr = NULL;
+ }
+}
+
+static void
+bnad_free_ibs(struct bnad *bnad)
+{
+ uint i;
+
+ if (!bnad->ib_table)
+ return;
+ for (i = 0; i < bnad->ib_num; i++)
+ bnad_free_ib(bnad, i);
+ kfree(bnad->ib_table);
+ bnad->ib_table = NULL;
+}
+
+/* Let the caller deal with error - free memory. */
+static int
+bnad_alloc_q(struct bnad *bnad, struct bna_qpt *qpt, struct bna_q *q,
+ size_t qsize)
+{
+ size_t i;
+ dma_addr_t dma_addr;
+
+ qsize = ALIGN(qsize, PAGE_SIZE);
+ qpt->page_count = qsize >> PAGE_SHIFT;
+ qpt->page_size = PAGE_SIZE;
+
+
+ qpt->kv_qpt_ptr =
+ pci_alloc_consistent(bnad->pcidev,
+ qpt->page_count *
+ sizeof(struct bna_dma_addr), &dma_addr);
+ if (!qpt->kv_qpt_ptr)
+ return -ENOMEM;
+ BNA_SET_DMA_ADDR(dma_addr, &qpt->hw_qpt_ptr);
+
+ q->qpt_ptr = kzalloc(qpt->page_count * sizeof(void *), GFP_KERNEL);
+ if (!q->qpt_ptr)
+ return -ENOMEM;
+ qpt->qpt_ptr = q->qpt_ptr;
+ for (i = 0; i < qpt->page_count; i++) {
+ q->qpt_ptr[i] =
+ pci_alloc_consistent(bnad->pcidev, PAGE_SIZE,
+ &dma_addr);
+ if (!q->qpt_ptr[i])
+ return -ENOMEM;
+ BNA_SET_DMA_ADDR(dma_addr,
+ &((struct bna_dma_addr *)qpt->kv_qpt_ptr)[i]);
+
+ }
+
+ return 0;
+}
+
+static void
+bnad_free_q(struct bnad *bnad, struct bna_qpt *qpt, struct bna_q *q)
+{
+ int i;
+ dma_addr_t dma_addr;
+
+ if (qpt->kv_qpt_ptr && q->qpt_ptr) {
+ for (i = 0; i < qpt->page_count; i++) {
+ if (q->qpt_ptr[i]) {
+ BNA_GET_DMA_ADDR(&
+ ((struct bna_dma_addr *)qpt->
+ kv_qpt_ptr)[i], dma_addr);
+ pci_free_consistent(bnad->pcidev, PAGE_SIZE,
+ q->qpt_ptr[i], dma_addr);
+ }
+ }
+ }
+
+ kfree(q->qpt_ptr);
+ qpt->qpt_ptr = q->qpt_ptr = NULL;
+
+ if (qpt->kv_qpt_ptr) {
+ BNA_GET_DMA_ADDR(&qpt->hw_qpt_ptr, dma_addr);
+ pci_free_consistent(bnad->pcidev,
+ qpt->page_count *
+ sizeof(struct bna_dma_addr),
+ qpt->kv_qpt_ptr, dma_addr);
+ qpt->kv_qpt_ptr = NULL;
+ }
+}
+
+static void
+bnad_free_txq(struct bnad *bnad, uint txq_id)
+{
+ struct bnad_txq_info *txqinfo;
+
+ BNA_ASSERT(bnad->txq_table && txq_id < bnad->txq_num);
+ txqinfo = &bnad->txq_table[txq_id];
+ bnad_free_q(bnad, &txqinfo->txq_config.qpt, &txqinfo->txq.q);
+ if (txqinfo->skb_unmap_q.unmap_array) {
+ bnad_free_txbufs(txqinfo, txqinfo->txq.q.producer_index);
+ vfree(txqinfo->skb_unmap_q.unmap_array);
+ txqinfo->skb_unmap_q.unmap_array = NULL;
+ }
+}
+
+void
+bnad_free_rxq(struct bnad *bnad, uint rxq_id)
+{
+ struct bnad_rxq_info *rxqinfo;
+
+ BNA_ASSERT(bnad->rxq_table && rxq_id < bnad->rxq_num);
+ rxqinfo = &bnad->rxq_table[rxq_id];
+ bnad_free_q(bnad, &rxqinfo->rxq_config.qpt, &rxqinfo->rxq.q);
+ if (rxqinfo->skb_unmap_q.unmap_array) {
+ bnad_flush_rxbufs(rxqinfo);
+ vfree(rxqinfo->skb_unmap_q.unmap_array);
+ rxqinfo->skb_unmap_q.unmap_array = NULL;
+ }
+}
+
+void
+bnad_free_cq(struct bnad *bnad, uint cq_id)
+{
+ struct bnad_cq_info *cqinfo = &bnad->cq_table[cq_id];
+
+ BNA_ASSERT(bnad->cq_table && cq_id < bnad->cq_num);
+ bnad_free_q(bnad, &cqinfo->cq_config.qpt, &cqinfo->cq.q);
+}
+
+static void
+bnad_free_queues(struct bnad *bnad)
+{
+ uint i;
+
+ if (bnad->txq_table) {
+ for (i = 0; i < bnad->txq_num; i++)
+ bnad_free_txq(bnad, i);
+ kfree(bnad->txq_table);
+ bnad->txq_table = NULL;
+ }
+
+ if (bnad->rxq_table) {
+ for (i = 0; i < bnad->rxq_num; i++)
+ bnad_free_rxq(bnad, i);
+ kfree(bnad->rxq_table);
+ bnad->rxq_table = NULL;
+ }
+
+ if (bnad->cq_table) {
+ for (i = 0; i < bnad->cq_num; i++)
+ bnad_free_cq(bnad, i);
+ kfree(bnad->cq_table);
+ bnad->cq_table = NULL;
+ }
+}
+
+static int
+bnad_txq_init(struct bnad *bnad, uint txq_id)
+{
+ struct bnad_txq_info *txqinfo;
+ int err;
+
+ BNA_ASSERT(bnad->txq_table && txq_id < bnad->txq_num);
+ txqinfo = &bnad->txq_table[txq_id];
+ err = bnad_alloc_q(bnad, &txqinfo->txq_config.qpt, &txqinfo->txq.q,
+ bnad->txq_depth * sizeof(struct bna_txq_entry));
+ if (err) {
+ bnad_free_q(bnad, &txqinfo->txq_config.qpt, &txqinfo->txq.q);
+ return err;
+ }
+ txqinfo->txq.q.q_depth = bnad->txq_depth;
+ txqinfo->bnad = bnad;
+ txqinfo->txq_config.txf_id = BNAD_TX_FUNC_ID;
+ snprintf(txqinfo->name, sizeof(txqinfo->name), "%s TxQ %d",
+ bnad->netdev->name, txq_id);
+ return 0;
+}
+
+static int
+bnad_txqs_init(struct bnad *bnad)
+{
+ int i, err = 0;
+
+ bnad->txq_table =
+ kzalloc(bnad->txq_num * sizeof(struct bnad_txq_info),
+ GFP_KERNEL);
+ if (!bnad->txq_table)
+ return -ENOMEM;
+
+ for (i = 0; i < bnad->txq_num; i++) {
+ err = bnad_txq_init(bnad, i);
+ if (err)
+ break;
+ }
+ return err;
+}
+
+int
+bnad_rxq_init(struct bnad *bnad, uint rxq_id)
+{
+ struct bnad_rxq_info *rxqinfo;
+ int err;
+
+ BNA_ASSERT(bnad->rxq_table && rxq_id < bnad->rxq_num);
+ rxqinfo = &bnad->rxq_table[rxq_id];
+ err = bnad_alloc_q(bnad, &rxqinfo->rxq_config.qpt, &rxqinfo->rxq.q,
+ bnad->rxq_depth * sizeof(struct bna_rxq_entry));
+ if (err) {
+ bnad_free_q(bnad, &rxqinfo->rxq_config.qpt, &rxqinfo->rxq.q);
+ return err;
+ }
+ rxqinfo->rxq.q.q_depth = bnad->rxq_depth;
+ rxqinfo->bnad = bnad;
+ rxqinfo->rxq_id = rxq_id;
+ rxqinfo->rxq_config.cq_id = rxq_id / bnad_rxqs_per_cq;
+
+ return 0;
+}
+
+static int
+bnad_rxqs_init(struct bnad *bnad)
+{
+ int i, err = 0;
+
+ bnad->rxq_table =
+ kzalloc(bnad->rxq_num * sizeof(struct bnad_rxq_info),
+ GFP_KERNEL);
+ if (!bnad->rxq_table)
+ return -EINVAL;
+
+ for (i = 0; i < bnad->rxq_num; i++) {
+ err = bnad_rxq_init(bnad, i);
+ if (err)
+ break;
+ }
+ return err;
+}
+
+int
+bnad_cq_init(struct bnad *bnad, uint cq_id)
+{
+ struct bnad_cq_info *cqinfo;
+ int err;
+
+ BNA_ASSERT(bnad->cq_table && cq_id < bnad->cq_num);
+ cqinfo = &bnad->cq_table[cq_id];
+ err = bnad_alloc_q(bnad, &cqinfo->cq_config.qpt, &cqinfo->cq.q,
+ bnad->rxq_depth * bnad_rxqs_per_cq *
+ sizeof(struct bna_cq_entry));
+ if (err) {
+ bnad_free_q(bnad, &cqinfo->cq_config.qpt, &cqinfo->cq.q);
+ return err;
+ }
+
+ cqinfo->cq.q.q_depth = bnad->rxq_depth * bnad_rxqs_per_cq;
+ cqinfo->bnad = bnad;
+
+ cqinfo->rx_coalescing_timeo = bnad->rx_coalescing_timeo;
+
+ cqinfo->cq_id = cq_id;
+ snprintf(cqinfo->name, sizeof(cqinfo->name), "%s CQ %d",
+ bnad->netdev->name, cq_id);
+
+ return 0;
+}
+
+static int
+bnad_cqs_init(struct bnad *bnad)
+{
+ int i, err = 0;
+
+ bnad->cq_table =
+ kzalloc(bnad->cq_num * sizeof(struct bnad_cq_info), GFP_KERNEL);
+ if (!bnad->cq_table)
+ return -ENOMEM;
+
+ for (i = 0; i < bnad->cq_num; i++) {
+ err = bnad_cq_init(bnad, i);
+ if (err)
+ break;
+ }
+ return err;
+}
+
+static uint
+bnad_get_qsize(uint qsize_conf, uint mtu)
+{
+ uint qsize;
+
+ if (mtu >= ETH_DATA_LEN) {
+ qsize = qsize_conf / (mtu / ETH_DATA_LEN);
+ if (!BNA_POWER_OF_2(qsize))
+ BNA_TO_POWER_OF_2_HIGH(qsize);
+ if (qsize < BNAD_MIN_Q_DEPTH)
+ qsize = BNAD_MIN_Q_DEPTH;
+ } else
+ qsize = bnad_txq_depth;
+
+ return qsize;
+}
+
+static int
+bnad_init_queues(struct bnad *bnad)
+{
+ int err;
+
+ if (!(bnad->config & BNAD_CF_TXQ_DEPTH))
+ bnad->txq_depth =
+ bnad_get_qsize(bnad_txq_depth, bnad->netdev->mtu);
+ if (!(bnad->config & BNAD_CF_RXQ_DEPTH))
+ bnad->rxq_depth =
+ bnad_get_qsize(bnad_rxq_depth, bnad->netdev->mtu);
+
+ err = bnad_txqs_init(bnad);
+ if (err)
+ return err;
+
+ err = bnad_rxqs_init(bnad);
+ if (err)
+ return err;
+
+ err = bnad_cqs_init(bnad);
+
+ return err;
+}
+
+void
+bnad_rxib_init(struct bnad *bnad, uint cq_id, uint ib_id)
+{
+ struct bnad_cq_info *cqinfo;
+ struct bnad_ib_entry *ib_entry;
+ struct bna_ib_config *ib_config;
+
+ BNA_ASSERT(cq_id < bnad->cq_num && ib_id < bnad->ib_num);
+ cqinfo = &bnad->cq_table[cq_id];
+ ib_entry = &bnad->ib_table[ib_id];
+
+ cqinfo->hw_producer_index = (u32 *) (ib_entry->ib_seg_addr);
+ cqinfo->cq_config.ib_id = ib_id;
+ cqinfo->cq_config.ib_seg_index = 0;
+
+ ib_entry->ib = &cqinfo->ib;
+ ib_config = &ib_entry->ib_config;
+ ib_config->coalescing_timer = bnad->rx_coalescing_timeo;
+ ib_config->control_flags =
+ BNA_IB_CF_INT_ENABLE | BNA_IB_CF_MASTER_ENABLE;
+ if (bnad->config & BNAD_CF_MSIX) {
+ ib_config->control_flags |= BNA_IB_CF_MSIX_MODE;
+ ib_config->msix_vector = ib_id;
+ } else
+ ib_config->msix_vector = 1 << ib_id;
+
+ /* Every CQ has its own IB. */
+ ib_config->seg_size = 1;
+ ib_config->index_table_offset = ib_id;
+}
+
+static void
+bnad_ibs_init(struct bnad *bnad)
+{
+ struct bnad_ib_entry *ib_entry;
+ struct bna_ib_config *ib_config;
+ struct bnad_txq_info *txqinfo;
+
+ int ib_id, i;
+
+ ib_id = 0;
+ for (i = 0; i < bnad->txq_num; i++) {
+ txqinfo = &bnad->txq_table[i];
+ ib_entry = &bnad->ib_table[ib_id];
+
+ txqinfo->hw_consumer_index = ib_entry->ib_seg_addr;
+ txqinfo->txq_config.ib_id = ib_id;
+ txqinfo->txq_config.ib_seg_index = 0;
+
+ ib_entry->ib = &txqinfo->ib;
+ ib_config = &ib_entry->ib_config;
+ ib_config->coalescing_timer = bnad->tx_coalescing_timeo;
+ ib_config->control_flags =
+ BNA_IB_CF_INTER_PKT_DMA | BNA_IB_CF_INT_ENABLE |
+ BNA_IB_CF_COALESCING_MODE | BNA_IB_CF_MASTER_ENABLE;
+ if (bnad->config & BNAD_CF_MSIX) {
+ ib_config->control_flags |= BNA_IB_CF_MSIX_MODE;
+ ib_config->msix_vector = ib_id;
+ } else
+ ib_config->msix_vector = 1 << ib_id;
+ ib_config->interpkt_count = bnad->tx_interpkt_count;
+
+ /* Every TxQ has its own IB. */
+ ib_config->seg_size = 1;
+ ib_config->index_table_offset = ib_id;
+ ib_id++;
+ }
+
+ for (i = 0; i < bnad->cq_num; i++, ib_id++)
+ bnad_rxib_init(bnad, i, ib_id);
+}
+
+static void
+bnad_txf_init(struct bnad *bnad, uint txf_id)
+{
+ struct bnad_txf_info *txf_info;
+
+ BNA_ASSERT(bnad->txf_table && txf_id < bnad->txf_num);
+ txf_info = &bnad->txf_table[txf_id];
+ txf_info->txf_id = txf_id;
+ txf_info->txf_config.flags =
+ BNA_TXF_CF_VLAN_WI_BASED | BNA_TXF_CF_ENABLE;
+}
+
+void
+bnad_rxf_init(struct bnad *bnad, uint rxf_id, u8 rit_offset, int rss)
+{
+ struct bnad_rxf_info *rxf_info;
+
+ BNA_ASSERT(bnad->rxf_table && rxf_id < bnad->rxf_num);
+ rxf_info = &bnad->rxf_table[rxf_id];
+ rxf_info->rxf_id = rxf_id;
+ rxf_info->rxf_config.rit_offset = rit_offset;
+ rxf_info->rxf_config.mcast_rxq_id = BNAD_MULTICAST_RXQ_ID;
+ if (bnad_small_large_rxbufs)
+ rxf_info->rxf_config.flags |= BNA_RXF_CF_SM_LG_RXQ;
+ if (bnad_vlan_strip)
+ rxf_info->rxf_config.flags |= BNA_RXF_CF_VLAN_STRIP;
+ if (rss) {
+ struct bna_rxf_rss *rxf_rss;
+
+ rxf_info->rxf_config.flags |= BNA_RXF_CF_RSS_ENABLE;
+ rxf_rss = &rxf_info->rxf_config.rss;
+ rxf_rss->type =
+ BNA_RSS_V4_TCP | BNA_RSS_V4_IP | BNA_RSS_V6_TCP |
+ BNA_RSS_V6_IP;
+ rxf_rss->hash_mask = bnad->cq_num - 1;
+ get_random_bytes(rxf_rss->toeplitz_hash_key,
+ sizeof(rxf_rss->toeplitz_hash_key));
+ }
+}
+
+static int
+bnad_init_funcs(struct bnad *bnad)
+{
+ bnad->txf_table =
+ kzalloc(sizeof(struct bnad_txf_info) * bnad->txf_num,
+ GFP_KERNEL);
+ if (!bnad->txf_table)
+ return -ENOMEM;
+ bnad_txf_init(bnad, BNAD_TX_FUNC_ID);
+
+ bnad->rxf_table =
+ kzalloc(sizeof(struct bnad_rxf_info) * bnad->rxf_num,
+ GFP_KERNEL);
+ if (!bnad->rxf_table)
+ return -ENOMEM;
+ bnad_rxf_init(bnad, BNAD_RX_FUNC_ID, BNAD_RIT_OFFSET,
+ (bnad->cq_num > 1) ? 1 : 0);
+ return 0;
+}
+
+static void
+bnad_setup_txq(struct bnad *bnad, uint txq_id)
+{
+ struct bnad_txq_info *txqinfo;
+
+ BNA_ASSERT(txq_id < bnad->txq_num);
+ txqinfo = &bnad->txq_table[txq_id];
+
+ /* CEE state should not change while we do this */
+ spin_lock_irq(&bnad->priv_lock);
+ if (!bnad->cee_linkup) {
+ txqinfo->txq_config.priority = bnad->curr_priority = txq_id;
+ clear_bit(BNAD_F_CEE_RUNNING, &bnad->flags);
+ } else {
+ txqinfo->txq_config.priority = bnad->curr_priority =
+ bnad->priority;
+ set_bit(BNAD_F_CEE_RUNNING, &bnad->flags);
+ }
+ /* Set wrr_quota properly if multiple priorities/TxQs are enabled. */
+ txqinfo->txq_config.wrr_quota = BNAD_TX_MAX_WRR_QUOTA;
+ bna_txq_config(bnad->priv, &txqinfo->txq, txq_id, &txqinfo->txq_config);
+ spin_unlock_irq(&bnad->priv_lock);
+}
+
+void
+bnad_setup_rxq(struct bnad *bnad, uint rxq_id)
+{
+ struct bnad_rxq_info *rxqinfo;
+
+ BNA_ASSERT(rxq_id < bnad->rxq_num);
+ rxqinfo = &bnad->rxq_table[rxq_id];
+
+ /*
+ * Every RxQ set has 2 RxQs: the first is large buffer RxQ,
+ * the second is small buffer RxQ.
+ */
+ if ((rxq_id % bnad_rxqs_per_cq) == 0)
+ rxqinfo->rxq_config.buffer_size =
+ (bnad_vlan_strip ? VLAN_ETH_HLEN : ETH_HLEN) +
+ bnad->netdev->mtu + ETH_FCS_LEN;
+ else
+ rxqinfo->rxq_config.buffer_size = BNAD_SMALL_RXBUF_SIZE;
+
+ spin_lock_irq(&bnad->priv_lock);
+ bna_rxq_config(bnad->priv, &rxqinfo->rxq, rxq_id, &rxqinfo->rxq_config);
+ spin_unlock_irq(&bnad->priv_lock);
+}
+
+void
+bnad_setup_cq(struct bnad *bnad, uint cq_id)
+{
+ struct bnad_cq_info *cqinfo;
+
+ BNA_ASSERT(cq_id < bnad->cq_num);
+ cqinfo = &bnad->cq_table[cq_id];
+ spin_lock_irq(&bnad->priv_lock);
+ bna_cq_config(bnad->priv, &cqinfo->cq, cq_id, &cqinfo->cq_config);
+ spin_unlock_irq(&bnad->priv_lock);
+}
+
+static void
+bnad_setup_queues(struct bnad *bnad)
+{
+ uint i;
+
+ for (i = 0; i < bnad->txq_num; i++)
+ bnad_setup_txq(bnad, i);
+
+ for (i = 0; i < bnad->rxq_num; i++)
+ bnad_setup_rxq(bnad, i);
+
+ for (i = 0; i < bnad->cq_num; i++)
+ bnad_setup_cq(bnad, i);
+}
+
+
+static void
+bnad_setup_rit(struct bnad *bnad)
+{
+ int i, size;
+
+ size = bnad->cq_num;
+ for (i = 0; i < size; i++) {
+ if (bnad_small_large_rxbufs) {
+ bnad->rit[i].large_rxq_id = (i << 1);
+ bnad->rit[i].small_rxq_id = (i << 1) + 1;
+ } else {
+ bnad->rit[i].large_rxq_id = i;
+ }
+ }
+ spin_lock_irq(&bnad->priv_lock);
+ bna_rit_config_set(bnad->priv, BNAD_RIT_OFFSET, bnad->rit, size);
+ spin_unlock_irq(&bnad->priv_lock);
+}
+
+void
+bnad_alloc_for_rxq(struct bnad *bnad, uint rxq_id)
+{
+ struct bnad_rxq_info *rxqinfo = &bnad->rxq_table[rxq_id];
+ u16 rxbufs;
+
+ BNA_ASSERT(bnad->rxq_table && rxq_id < bnad->rxq_num);
+ bnad_alloc_rxbufs(rxqinfo);
+ rxbufs = BNA_QE_IN_USE_CNT(&rxqinfo->skb_unmap_q,
+ rxqinfo->skb_unmap_q.q_depth);
+}
+
+static int
+bnad_config_hw(struct bnad *bnad)
+{
+ int i, err = 0;
+ u64 rxq_id_mask = 0;
+ struct sockaddr sa;
+ struct net_device *netdev = bnad->netdev;
+
+ spin_lock_irq(&bnad->priv_lock);
+ if (BNAD_NOT_READY(bnad))
+ goto unlock_and_return;
+
+ /* Disable the RxF until later bringing port up. */
+ bna_multi_rxf_disable(bnad->priv, (1 << bnad->rxf_num) - 1);
+ for (i = 0; i < bnad->txq_num; i++) {
+ spin_unlock_irq(&bnad->priv_lock);
+ err = bnad_disable_txq(bnad, i);
+ spin_lock_irq(&bnad->priv_lock);
+ if (err || BNAD_NOT_READY(bnad))
+ goto unlock_and_return;
+ }
+ for (i = 0; i < bnad->rxq_num; i++)
+ rxq_id_mask |= (1 << i);
+ if (rxq_id_mask) {
+ spin_unlock_irq(&bnad->priv_lock);
+ err = bnad_disable_rxqs(bnad, rxq_id_mask);
+ spin_lock_irq(&bnad->priv_lock);
+ if (err || BNAD_NOT_READY(bnad))
+ goto unlock_and_return;
+ }
+ spin_unlock_irq(&bnad->priv_lock);
+
+ bnad_setup_queues(bnad);
+
+ bnad_setup_rit(bnad);
+
+ spin_lock_irq(&bnad->priv_lock);
+ bna_txf_config_set(bnad->priv, BNAD_TX_FUNC_ID,
+ &bnad->txf_table->txf_config);
+ for (i = 0; i < bnad->rxf_num; i++) {
+ bna_rxf_config_set(bnad->priv, i,
+ &bnad->rxf_table[i].rxf_config);
+ bna_rxf_vlan_filter(bnad->priv, i, BNA_ENABLE);
+ }
+
+ spin_unlock_irq(&bnad->priv_lock);
+ /* Mailbox should be enabled before this! */
+ memcpy(sa.sa_data, netdev->dev_addr, netdev->addr_len);
+ err = bnad_set_mac_address_locked(netdev, &sa);
+ spin_lock_irq(&bnad->priv_lock);
+ if (err || BNAD_NOT_READY(bnad))
+ goto unlock_and_return;
+
+ /* Receive broadcasts */
+ bna_rxf_broadcast(bnad->priv, BNAD_RX_FUNC_ID, BNA_ENABLE);
+
+ bna_mtu_info(bnad->priv, netdev->mtu, bnad);
+ bna_set_pause_config(bnad->priv, &bnad->pause_config, bnad);
+
+ bna_rxf_mcast_del_all(bnad->priv, BNAD_RX_FUNC_ID);
+ bna_mcast_mac_reset_list(bnad->priv);
+
+ bnad_set_rx_mode_locked(bnad->netdev);
+
+ bnad_reconfig_vlans(bnad);
+ spin_unlock_irq(&bnad->priv_lock);
+
+ bnad_setup_ibs(bnad);
+ return 0;
+
+unlock_and_return:
+ if (BNAD_NOT_READY(bnad))
+ err = BNA_FAIL;
+ spin_unlock_irq(&bnad->priv_lock);
+ return err;
+}
+
+/* Note: bnad_cleanup doesn't free irqs */
+static void
+bnad_cleanup(struct bnad *bnad)
+{
+
+ kfree(bnad->rit);
+ bnad->rit = NULL;
+
+ kfree(bnad->txf_table);
+ bnad->txf_table = NULL;
+
+ kfree(bnad->rxf_table);
+ bnad->rxf_table = NULL;
+
+ bnad_free_ibs(bnad);
+ bnad_free_queues(bnad);
+}
+
+/* Should be called with rtnl_lock held. */
+static int
+bnad_init(struct bnad *bnad)
+{
+ int err;
+
+ err = bnad_alloc_ibs(bnad);
+ if (err)
+ goto finished;
+
+ err = bnad_init_queues(bnad);
+ if (err)
+ goto finished;
+
+ bnad_ibs_init(bnad);
+
+ err = bnad_init_funcs(bnad);
+ if (err)
+ goto finished;
+
+ err = bnad_alloc_unmap_queues(bnad);
+ if (err)
+ goto finished;
+
+ bnad->rit =
+ kzalloc(bnad->cq_num * sizeof(struct bna_rit_entry),
+ GFP_KERNEL);
+ if (!bnad->rit)
+ goto finished;
+
+ return 0;
+
+finished:
+ bnad_cleanup(bnad);
+ return err;
+}
+
+static int
+bnad_enable_locked(struct bnad *bnad)
+{
+ struct net_device *netdev = bnad->netdev;
+ int err = 0;
+ uint i;
+ char message[BNA_MESSAGE_SIZE];
+
+ bnad->state = BNAD_S_OPENING;
+
+ err = bnad_init(bnad);
+ if (err) {
+ sprintf(message, "%s init failed %d", netdev->name, err);
+ DPRINTK(INFO, "%s",
+ message);
+ bnad->state = BNAD_S_INIT;
+ return err;
+ }
+
+ err = bnad_config_hw(bnad);
+ if (err) {
+ sprintf(message, "%s config HW failed %d", netdev->name, err);
+ DPRINTK(INFO, "%s",
+ message);
+ goto init_failed;
+ }
+
+ err = bnad_request_txrx_irqs(bnad);
+ if (err) {
+ sprintf(message, "%s requests Tx/Rx irqs failed: %d",
+ bnad->netdev->name, err);
+ DPRINTK(INFO, "%s",
+ message);
+ goto init_failed;
+ }
+ bnad_napi_init(bnad);
+ bnad_napi_enable(bnad);
+ for (i = 0; i < bnad->rxq_num; i++)
+ bnad_alloc_for_rxq(bnad, i);
+
+ bnad->state = BNAD_S_OPEN;
+ sprintf(message, "%s is opened", bnad->netdev->name);
+ DPRINTK(INFO, "%s", message);
+
+ spin_lock_irq(&bnad->priv_lock);
+ if (BNAD_NOT_READY(bnad)) {
+ /* Let bnad_error take care of the error. */
+ spin_unlock_irq(&bnad->priv_lock);
+ return 0;
+ }
+
+ /* RxF was disabled earlier. */
+ bna_rxf_enable(bnad->priv, BNAD_RX_FUNC_ID);
+ spin_unlock_irq(&bnad->priv_lock);
+
+ return 0;
+
+init_failed:
+ bnad_cleanup(bnad);
+ bnad->state = BNAD_S_INIT;
+ return err;
+}
+
+
+/* Should be called with conf_lock held */
+static
+ int
+bnad_open_locked_internal(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int err = 0;
+ char message[BNA_MESSAGE_SIZE];
+
+
+ switch (bnad->state) {
+ case BNAD_S_INIT:
+ err = bnad_enable_locked(bnad);
+ break;
+ case BNAD_S_INIT_DOWN:
+ bnad->state = BNAD_S_OPEN_DOWN;
+ sprintf(message, "%s is not ready yet: IOC down", netdev->name);
+ DPRINTK(INFO, "%s", message);
+ break;
+ case BNAD_S_INIT_DISABLED:
+ bnad->state = BNAD_S_OPEN_DISABLED;
+ sprintf(message, "%s is not ready yet: IOC disabled",
+ netdev->name);
+ DPRINTK(INFO, "%s", message);
+ break;
+ default:
+ BNA_ASSERT(0);
+ break;
+ }
+ return err;
+}
+
+int
+bnad_open_locked(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int err;
+
+
+ err = bnad_open_locked_internal(netdev);
+
+ if (!err && (bnad->state == BNAD_S_OPEN))
+ bnad_port_admin_locked(bnad, BNA_ENABLE);
+
+ return err;
+}
+
+int
+bnad_open(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int err = 0;
+ char message[BNA_MESSAGE_SIZE];
+
+ sprintf(message, "%s open", netdev->name);
+ DPRINTK(INFO, "%s", message);
+
+ bnad_conf_lock();
+
+ if (test_bit(BNAD_F_BCU_DISABLED, &bnad->flags)) {
+ sprintf(message, "%s is disabled", netdev->name);
+ DPRINTK(INFO, "%s", message);
+ } else
+ err = bnad_open_locked(netdev);
+
+ bnad_conf_unlock();
+
+ return err;
+}
+
+static int
+bnad_disable_locked(struct bnad *bnad)
+{
+ int err = 0, i;
+ u64 rxq_id_mask = 0;
+
+
+ bnad_stop_data_path(bnad, 0);
+
+ for (i = 0; i < bnad->txq_num; i++) {
+ err = bnad_disable_txq(bnad, i);
+ if (err)
+ goto cleanup;
+ }
+
+ for (i = 0; i < bnad->rxq_num; i++)
+ rxq_id_mask |= (1 << i);
+ if (rxq_id_mask) {
+ err = bnad_disable_rxqs(bnad, rxq_id_mask);
+ if (err)
+ goto cleanup;
+ }
+
+cleanup:
+ bnad_cleanup(bnad);
+ return err;
+}
+
+
+
+int
+bnad_stop_locked(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ if (bnad->state == BNAD_S_OPEN)
+ bnad_port_admin_locked(bnad, BNA_DISABLE);
+
+ return bnad_stop_locked_internal(netdev);
+}
+
+int
+bnad_stop(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int err = 0;
+ char message[BNA_MESSAGE_SIZE];
+
+ sprintf(message, "%s stop", netdev->name);
+ DPRINTK(INFO, "%s", message);
+
+ bnad_conf_lock();
+
+ if (test_bit(BNAD_F_BCU_DISABLED, &bnad->flags)) {
+ sprintf(message, "%s port is disabled", netdev->name);
+ DPRINTK(INFO, "%s", message);
+ } else
+ err = bnad_stop_locked(netdev);
+
+ bnad_conf_unlock();
+
+ return err;
+}
+
+/* Should be called with conf_lock held. */
+int
+bnad_sw_reset_locked_internal(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int err;
+ char message[BNA_MESSAGE_SIZE];
+
+
+ err = bnad_stop_locked_internal(netdev);
+ if (err) {
+ sprintf(message, "%s sw reset internal: stop failed %d",
+ bnad->netdev->name, err);
+ goto done;
+ }
+
+ err = bnad_open_locked_internal(netdev);
+
+ if (err) {
+ sprintf(message, "%s sw reset internal: open failed %d",
+ bnad->netdev->name, err);
+ goto done;
+ }
+ return 0;
+done:
+ DPRINTK(INFO, "%s", message);
+ return err;
+}
+
+/* Should be called with conf_lock held. */
+int
+bnad_sw_reset_locked(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int err;
+ char message[BNA_MESSAGE_SIZE];
+
+
+ if (bnad->state != BNAD_S_OPEN)
+ return 0;
+
+ bnad_port_admin_locked(bnad, BNA_DISABLE);
+
+ err = bnad_sw_reset_locked_internal(netdev);
+
+ if (err) {
+ sprintf(message, "%s sw reset: failed %d", bnad->netdev->name,
+ err);
+ DPRINTK(INFO, "%s", message);
+ return err;
+ }
+
+ /* After the reset, make sure we are in the OPEN state) */
+ if (bnad->state == BNAD_S_OPEN)
+ bnad_port_admin_locked(bnad, BNA_ENABLE);
+
+ return 0;
+}
+
+
+static int
+bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
+{
+ int err;
+
+ BNA_ASSERT(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4 ||
+ skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6);
+ if (skb_header_cloned(skb)) {
+ err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
+ if (err) {
+ bnad->stats.tso_err++;
+ return err;
+ }
+ }
+
+ /*
+ * For TSO, the TCP checksum field is seeded with pseudo-header sum
+ * excluding the length field.
+ */
+ if (skb->protocol == htons(ETH_P_IP)) {
+ struct iphdr *iph = ip_hdr(skb);
+
+ /* Do we really need these? */
+ iph->tot_len = 0;
+ iph->check = 0;
+
+ tcp_hdr(skb)->check =
+ ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
+ IPPROTO_TCP, 0);
+ bnad->stats.tso4++;
+ } else {
+ struct ipv6hdr *ipv6h = ipv6_hdr(skb);
+
+ BNA_ASSERT(skb->protocol == htons(ETH_P_IPV6));
+ ipv6h->payload_len = 0;
+ tcp_hdr(skb)->check =
+ ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
+ IPPROTO_TCP, 0);
+ bnad->stats.tso6++;
+ }
+
+ return 0;
+}
+
+netdev_tx_t
+bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ struct bnad_txq_info *txqinfo;
+ struct bna_txq *txq;
+ struct bnad_unmap_q *unmap_q;
+ u16 txq_prod, vlan_tag = 0;
+ unsigned int unmap_prod, wis, wis_used, wi_range;
+ unsigned int vectors, vect_id, i, acked;
+ int err;
+ dma_addr_t dma_addr;
+ struct bna_txq_entry *txqent;
+ bna_txq_wi_ctrl_flag_t flags;
+
+ if (unlikely
+ (skb->len <= ETH_HLEN || skb->len > BNAD_TX_MAX_DATA_PER_WI)) {
+ dev_kfree_skb(skb);
+ return NETDEV_TX_OK;
+ }
+
+ txqinfo = &bnad->txq_table[0];
+ txq = &txqinfo->txq;
+ unmap_q = &txqinfo->skb_unmap_q;
+
+ vectors = 1 + skb_shinfo(skb)->nr_frags;
+ if (vectors > BNAD_TX_MAX_VECTORS) {
+ dev_kfree_skb(skb);
+ return NETDEV_TX_OK;
+ }
+ wis = BNAD_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
+ acked = 0;
+ if (unlikely
+ (wis > BNA_Q_FREE_COUNT(txq) ||
+ vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
+ if ((u16) (*txqinfo->hw_consumer_index) !=
+ txq->q.consumer_index &&
+ !test_and_set_bit(BNAD_TXQ_FREE_SENT, &txqinfo->flags)) {
+ acked = bnad_free_txbufs(txqinfo,
+ (u16)(*txqinfo->
+ hw_consumer_index));
+ bna_ib_ack(bnad->priv, &txqinfo->ib, acked);
+
+ smp_mb__before_clear_bit();
+ clear_bit(BNAD_TXQ_FREE_SENT, &txqinfo->flags);
+ } else
+ netif_stop_queue(netdev);
+
+ smp_mb();
+ /*
+ * Check again to deal with race condition between
+ * netif_stop_queue here, and netif_wake_queue in
+ * interrupt handler which is not inside netif tx lock.
+ */
+ if (likely
+ (wis > BNA_Q_FREE_COUNT(txq) ||
+ vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
+ bnad->stats.netif_queue_stop++;
+ return NETDEV_TX_BUSY;
+ } else
+ netif_wake_queue(netdev);
+ }
+
+ unmap_prod = unmap_q->producer_index;
+ wis_used = 1;
+ vect_id = 0;
+ flags = 0;
+
+ txq_prod = txq->q.producer_index;
+ BNA_TXQ_QPGE_PTR_GET(txq_prod, &txq->q, txqent, wi_range);
+ BNA_ASSERT(wi_range && wi_range <= txq->q.q_depth);
+ txqent->hdr.wi.reserved = 0;
+ txqent->hdr.wi.num_vectors = vectors;
+ txqent->hdr.wi.opcode =
+ htons((skb_is_gso(skb) ? BNA_TXQ_WI_SEND_LSO :
+ BNA_TXQ_WI_SEND));
+
+ if (bnad_ipid_mode)
+ flags |= BNA_TXQ_WI_CF_IPID_MODE;
+
+ if (bnad->vlangrp && vlan_tx_tag_present(skb)) {
+ vlan_tag = (u16) vlan_tx_tag_get(skb);
+ flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
+ }
+ if (test_bit(BNAD_F_CEE_RUNNING, &bnad->flags)) {
+ vlan_tag =
+ (bnad->curr_priority & 0x7) << 13 | (vlan_tag & 0x1fff);
+ flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
+ }
+
+ txqent->hdr.wi.vlan_tag = htons(vlan_tag);
+
+ if (skb_is_gso(skb)) {
+ err = bnad_tso_prepare(bnad, skb);
+ if (err) {
+ dev_kfree_skb(skb);
+ return NETDEV_TX_OK;
+ }
+ txqent->hdr.wi.lso_mss = htons(skb_is_gso(skb));
+ flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
+ txqent->hdr.wi.l4_hdr_size_n_offset =
+ htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
+ (tcp_hdrlen(skb) >> 2,
+ skb_transport_offset(skb)));
+
+ } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ u8 proto = 0;
+
+ txqent->hdr.wi.lso_mss = 0;
+
+ if (skb->protocol == htons(ETH_P_IP))
+ proto = ip_hdr(skb)->protocol;
+ else if (skb->protocol == htons(ETH_P_IPV6)) {
+ /* XXX the nexthdr may not be TCP immediately. */
+ proto = ipv6_hdr(skb)->nexthdr;
+ }
+ if (proto == IPPROTO_TCP) {
+ flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
+ txqent->hdr.wi.l4_hdr_size_n_offset =
+ htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
+ (0, skb_transport_offset(skb)));
+ bnad->stats.tcpcsum_offload++;
+ BNA_ASSERT(skb_headlen(skb) >=
+ skb_transport_offset(skb) + tcp_hdrlen(skb));
+ } else if (proto == IPPROTO_UDP) {
+ flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
+ txqent->hdr.wi.l4_hdr_size_n_offset =
+ htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
+ (0, skb_transport_offset(skb)));
+ bnad->stats.udpcsum_offload++;
+ BNA_ASSERT(skb_headlen(skb) >=
+ skb_transport_offset(skb) +
+ sizeof(struct udphdr));
+ } else {
+ err = skb_checksum_help(skb);
+ bnad->stats.csum_help++;
+ if (err) {
+ dev_kfree_skb(skb);
+ bnad->stats.csum_help_err++;
+ return NETDEV_TX_OK;
+ }
+ }
+ } else {
+ txqent->hdr.wi.lso_mss = 0;
+ txqent->hdr.wi.l4_hdr_size_n_offset = 0;
+ }
+
+ txqent->hdr.wi.flags = htons(flags);
+
+ txqent->hdr.wi.frame_length = htonl(skb->len);
+
+ unmap_q->unmap_array[unmap_prod].skb = skb;
+ BNA_ASSERT(skb_headlen(skb) <= BNAD_TX_MAX_DATA_PER_VECTOR);
+ txqent->vector[vect_id].length = htons(skb_headlen(skb));
+ dma_addr =
+ pci_map_single(bnad->pcidev, skb->data, skb_headlen(skb),
+ PCI_DMA_TODEVICE);
+ pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
+ dma_addr);
+
+ BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
+ BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
+
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
+
+ if (++vect_id == BNAD_TX_MAX_VECTORS_PER_WI) {
+ vect_id = 0;
+ if (--wi_range)
+ txqent++;
+ else {
+ BNA_QE_INDX_ADD(txq_prod, wis_used,
+ txq->q.q_depth);
+ wis_used = 0;
+ BNA_TXQ_QPGE_PTR_GET(txq_prod, &txq->q, txqent,
+ wi_range);
+ BNA_ASSERT(wi_range &&
+ wi_range <= txq->q.q_depth);
+ }
+ wis_used++;
+ txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
+ }
+
+ BNA_ASSERT(frag->size <= BNAD_TX_MAX_DATA_PER_VECTOR);
+ txqent->vector[vect_id].length = htons(frag->size);
+ BNA_ASSERT(unmap_q->unmap_array[unmap_prod].skb == NULL);
+ dma_addr =
+ pci_map_page(bnad->pcidev, frag->page,
+ frag->page_offset, frag->size,
+ PCI_DMA_TODEVICE);
+ pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
+ dma_addr);
+ BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
+ BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
+ }
+
+ unmap_q->producer_index = unmap_prod;
+ BNA_QE_INDX_ADD(txq_prod, wis_used, txq->q.q_depth);
+ txq->q.producer_index = txq_prod;
+
+ smp_mb();
+ bna_txq_prod_indx_doorbell(txq);
+
+ if ((u16) (*txqinfo->hw_consumer_index) != txq->q.consumer_index)
+ tasklet_schedule(&bnad->tx_free_tasklet);
+
+ return NETDEV_TX_OK;
+}
+
+struct net_device_stats *
+bnad_get_stats(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ struct net_device_stats *net_stats = &bnad->net_stats;
+ struct cna_stats_mac_rx *rxstats = &bnad->hw_stats->mac_rx_stats;
+ struct cna_stats_mac_tx *txstats = &bnad->hw_stats->mac_tx_stats;
+ int i;
+
+ memset(net_stats, 0, sizeof(*net_stats));
+ if (bnad->rxq_table) {
+ for (i = 0; i < bnad->rxq_num; i++) {
+ net_stats->rx_packets += bnad->rxq_table[i].rx_packets;
+ net_stats->rx_bytes += bnad->rxq_table[i].rx_bytes;
+ }
+ }
+ if (bnad->txq_table) {
+ for (i = 0; i < bnad->txq_num; i++) {
+ net_stats->tx_packets += bnad->txq_table[i].tx_packets;
+ net_stats->tx_bytes += bnad->txq_table[i].tx_bytes;
+ }
+ }
+ net_stats->rx_errors =
+ rxstats->rx_fcs_error + rxstats->rx_alignment_error +
+ rxstats->rx_frame_length_error + rxstats->rx_code_error +
+ rxstats->rx_undersize;
+ net_stats->tx_errors = txstats->tx_fcs_error + txstats->tx_undersize;
+ net_stats->rx_dropped = rxstats->rx_drop;
+ net_stats->tx_dropped = txstats->tx_drop;
+ net_stats->multicast = rxstats->rx_multicast;
+ net_stats->collisions = txstats->tx_total_collision;
+
+ net_stats->rx_length_errors = rxstats->rx_frame_length_error;
+ net_stats->rx_crc_errors = rxstats->rx_fcs_error;
+ net_stats->rx_frame_errors = rxstats->rx_alignment_error;
+ /* recv'r fifo overrun */
+ net_stats->rx_fifo_errors = bnad->hw_stats->rxf_stats[0].frame_drops;
+
+ return net_stats;
+}
+
+/* Should be called with priv_lock held. */
+static void
+bnad_set_rx_mode_locked(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int err;
+
+ if (netdev->flags & IFF_PROMISC) {
+ bna_rxf_promiscuous(bnad->priv, BNAD_RX_FUNC_ID, BNA_ENABLE);
+ bnad->config |= BNAD_CF_PROMISC;
+ } else {
+ bna_rxf_promiscuous(bnad->priv, BNAD_RX_FUNC_ID, BNA_DISABLE);
+ bnad->config &= ~BNAD_CF_PROMISC;
+ }
+
+ if (netdev->flags & IFF_ALLMULTI) {
+ if (!(bnad->config & BNAD_CF_ALLMULTI)) {
+ bna_rxf_mcast_filter(bnad->priv, BNAD_RX_FUNC_ID,
+ BNA_DISABLE);
+ bnad->config |= BNAD_CF_ALLMULTI;
+ }
+ } else {
+ if (bnad->config & BNAD_CF_ALLMULTI) {
+ bna_rxf_mcast_filter(bnad->priv, BNAD_RX_FUNC_ID,
+ BNA_ENABLE);
+ bnad->config &= ~BNAD_CF_ALLMULTI;
+ }
+ }
+
+ if (netdev->mc_count) {
+ struct mac *mcaddr_list;
+ struct dev_mc_list *mc;
+ int i;
+
+ mcaddr_list =
+ kzalloc((netdev->mc_count + 1) * sizeof(struct mac),
+ GFP_ATOMIC);
+ if (!mcaddr_list)
+ return;
+
+ mcaddr_list[0] = bna_bcast_addr;
+
+ mc = netdev->mc_list;
+ for (i = 1; mc && i < netdev->mc_count + 1; i++, mc = mc->next)
+ memcpy(&mcaddr_list[i], mc->dmi_addr,
+ sizeof(struct mac));
+
+ err = bna_rxf_mcast_mac_set_list(bnad->priv, BNAD_RX_FUNC_ID,
+ (const struct mac *)mcaddr_list,
+ netdev->mc_count + 1);
+
+ /* XXX Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
+
+ kfree(mcaddr_list);
+ }
+}
+
+static void
+bnad_set_rx_mode(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ spin_lock_irq(&bnad->priv_lock);
+ bnad_set_rx_mode_locked(netdev);
+ spin_unlock_irq(&bnad->priv_lock);
+}
+
+/* Should be called with conf_lock held. */
+int
+bnad_ucast_mac(struct bnad *bnad, unsigned int rxf_id, u8 * mac_ptr,
+ unsigned int cmd)
+{
+ int err = 0;
+ char message[BNA_MESSAGE_SIZE];
+ enum bna_status_e(*ucast_mac_func) (struct bna_dev *bna_dev,
+ unsigned int rxf_id, const struct mac *mac_addr_ptr) = NULL;
+
+ WARN_ON(in_interrupt());
+ if (!is_valid_ether_addr(mac_ptr))
+ return -EINVAL;
+
+ switch (cmd) {
+ case BNAD_UCAST_MAC_SET:
+ ucast_mac_func = bna_rxf_ucast_mac_set;
+ break;
+ case BNAD_UCAST_MAC_ADD:
+ ucast_mac_func = bna_rxf_ucast_mac_add;
+ break;
+ case BNAD_UCAST_MAC_DEL:
+ ucast_mac_func = bna_rxf_ucast_mac_del;
+ break;
+ }
+
+ init_completion(&bnad->ucast_comp);
+ spin_lock_irq(&bnad->priv_lock);
+ err = ucast_mac_func(bnad->priv, rxf_id, (const struct mac *)mac_ptr);
+ spin_unlock_irq(&bnad->priv_lock);
+ if (err) {
+ if (err == BNA_AGAIN)
+ err = 0;
+ goto ucast_mac_exit;
+ }
+ wait_for_completion(&bnad->ucast_comp);
+ err = bnad->ucast_comp_status;
+ if (err == BFI_LL_CMD_NOT_EXEC)
+ err = 0;
+
+ucast_mac_exit:
+ if (err) {
+ sprintf(message, "%s unicast MAC address command %d failed: %d",
+ bnad->netdev->name, cmd, err);
+ DPRINTK(INFO, "%s",
+ message);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/* Should be called with conf_lock held. */
+static int
+bnad_set_mac_address_locked(struct net_device *netdev, void *addr)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ struct sockaddr *sa = (struct sockaddr *)addr;
+ int err;
+
+ if (!is_valid_ether_addr(sa->sa_data))
+ return -EADDRNOTAVAIL;
+
+ err = bnad_ucast_mac(bnad, BNAD_RX_FUNC_ID, (u8 *) sa->sa_data,
+ BNAD_UCAST_MAC_SET);
+ if (err)
+ return err;
+
+ memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
+ return 0;
+}
+
+static int
+bnad_set_mac_address(struct net_device *netdev, void *addr)
+{
+ int err = 0;
+ struct bnad *bnad = netdev_priv(netdev);
+
+ bnad_conf_lock();
+ err = bnad_set_mac_address_locked(netdev, addr);
+ bnad_conf_unlock();
+ return err;
+
+}
+
+static int
+bnad_change_mtu(struct net_device *netdev, int new_mtu)
+{
+ int err = 0;
+ struct bnad *bnad = netdev_priv(netdev);
+
+ WARN_ON(in_interrupt());
+
+ if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
+ return -EINVAL;
+
+ bnad_conf_lock();
+ netdev->mtu = new_mtu;
+ err = bnad_sw_reset_locked(netdev);
+ bnad_conf_unlock();
+
+ return err;
+}
+
+static void
+bnad_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ bnad_conf_lock();
+ bnad->vlangrp = grp;
+ bnad_conf_unlock();
+}
+
+static void
+bnad_vlan_rx_add_vid(struct net_device *netdev, unsigned short vid)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+
+ bnad_conf_lock();
+ spin_lock_irq(&bnad->priv_lock);
+ if (bnad->state == BNAD_S_OPEN && !BNAD_NOT_READY(bnad))
+ bna_rxf_vlan_add(bnad->priv, BNAD_RX_FUNC_ID,
+ (unsigned int)vid);
+ spin_unlock_irq(&bnad->priv_lock);
+ bnad_conf_unlock();
+}
+
+static void
+bnad_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+
+ bnad_conf_lock();
+ spin_lock_irq(&bnad->priv_lock);
+ if (bnad->state == BNAD_S_OPEN && !BNAD_NOT_READY(bnad))
+ bna_rxf_vlan_del(bnad->priv, BNAD_RX_FUNC_ID,
+ (unsigned int)vid);
+ spin_unlock_irq(&bnad->priv_lock);
+ bnad_conf_unlock();
+}
+
+/* Should be called with priv_lock held. */
+static void
+bnad_reconfig_vlans(struct bnad *bnad)
+{
+ u16 vlan_id;
+
+ bna_rxf_vlan_del_all(bnad->priv, BNAD_RX_FUNC_ID);
+ if (bnad->vlangrp) {
+ for (vlan_id = 0; vlan_id < VLAN_GROUP_ARRAY_LEN; vlan_id++) {
+ if (vlan_group_get_device(bnad->vlangrp, vlan_id))
+ bna_rxf_vlan_add(bnad->priv, BNAD_RX_FUNC_ID,
+ (unsigned int)vlan_id);
+ }
+ }
+}
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void
+bnad_netpoll(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ struct bnad_cq_info *cqinfo;
+ int i;
+
+ if (!(bnad->config & BNAD_CF_MSIX)) {
+ disable_irq(bnad->pcidev->irq);
+ bnad_isr(bnad->pcidev->irq, netdev);
+ enable_irq(bnad->pcidev->irq);
+ } else {
+ for (i = 0; i < bnad->cq_num; i++) {
+ cqinfo = &bnad->cq_table[i];
+ bnad_disable_rx_irq(bnad, cqinfo);
+ bnad_poll_cq(bnad, cqinfo, BNAD_MAX_Q_DEPTH);
+ bnad_enable_rx_irq(bnad, cqinfo);
+ }
+ }
+}
+#endif
+
+static void
+bnad_q_num_init(struct bnad *bnad, uint rxqsets)
+{
+ bnad->txq_num = BNAD_TXQ_NUM;
+ bnad->txf_num = 1;
+
+ if (bnad->config & BNAD_CF_MSIX) {
+ if (rxqsets) {
+ bnad->cq_num = rxqsets;
+ if (bnad->cq_num > BNAD_MAX_CQS)
+ bnad->cq_num = BNAD_MAX_CQS;
+ } else
+ bnad->cq_num =
+ min((uint) num_online_cpus(),
+ (uint) BNAD_MAX_RXQSETS_USED);
+ /* VMware does not use RSS like Linux driver */
+ if (!BNA_POWER_OF_2(bnad->cq_num))
+ BNA_TO_POWER_OF_2(bnad->cq_num);
+ bnad->rxq_num = bnad->cq_num * bnad_rxqs_per_cq;
+
+ bnad->rxf_num = 1;
+ bnad->msix_num =
+ bnad->txq_num + bnad->cq_num +
+ BNAD_MSIX_ERR_MAILBOX_NUM;
+ } else {
+ bnad->cq_num = 1;
+ bnad->rxq_num = bnad->cq_num * bnad_rxqs_per_cq;
+ bnad->rxf_num = 1;
+ bnad->msix_num = 0;
+ }
+}
+
+static void
+bnad_enable_msix(struct bnad *bnad)
+{
+ int i, ret;
+
+ if (!(bnad->config & BNAD_CF_MSIX) || bnad->msix_table)
+ return;
+
+ bnad->msix_table =
+ kzalloc(bnad->msix_num * sizeof(struct msix_entry), GFP_KERNEL);
+ if (!bnad->msix_table)
+ goto intx_mode;
+
+ for (i = 0; i < bnad->msix_num; i++)
+ bnad->msix_table[i].entry = i;
+
+ ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
+ if (ret > 0) {
+ /* Not enough MSI-X vectors. */
+ int rxqsets = ret;
+
+ dev_err(&bnad->pcidev->dev,
+ "Tried to get %d MSI-X vectors, only got %d\n",
+ bnad->msix_num, ret);
+ BNA_TO_POWER_OF_2(rxqsets);
+ while (bnad->msix_num > ret && rxqsets) {
+ bnad_q_num_init(bnad, rxqsets);
+ rxqsets >>= 1;
+ }
+ if (bnad->msix_num <= ret) {
+ ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
+ bnad->msix_num);
+ if (ret) {
+ dev_err(&bnad->pcidev->dev,
+ "Enabling MSI-X failed: %d\n", ret);
+ goto intx_mode;
+ }
+ } else {
+ dev_err(&bnad->pcidev->dev,
+ "Enabling MSI-X failed: limited (%d) vectors\n",
+ ret);
+ goto intx_mode;
+ }
+ } else if (ret < 0) {
+ dev_err(&bnad->pcidev->dev, "Enabling MSI-X failed: %d\n", ret);
+ goto intx_mode;
+ }
+
+ dev_info(&bnad->pcidev->dev,
+ "Enabling MSI-X succeeded with %d vectors, %s\n",
+ bnad->msix_num,
+ (bnad->cq_num > 1) ? "RSS is enabled" : "RSS is not enabled");
+ return;
+
+intx_mode:
+ dev_warn(&bnad->pcidev->dev, "Switching to INTx mode with no RSS\n");
+
+ kfree(bnad->msix_table);
+ bnad->msix_table = NULL;
+
+ bnad->config &= ~BNAD_CF_MSIX;
+ bnad_q_num_init(bnad, 0);
+}
+
+static void
+bnad_disable_msix(struct bnad *bnad)
+{
+ if (bnad->config & BNAD_CF_MSIX) {
+ pci_disable_msix(bnad->pcidev);
+ kfree(bnad->msix_table);
+ bnad->msix_table = NULL;
+ bnad->config &= ~BNAD_CF_MSIX;
+ }
+}
+
+static void
+bnad_error(struct bnad *bnad)
+{
+
+ spin_lock_irq(&bnad->priv_lock);
+
+ if (!test_and_clear_bit(BNAD_F_HWERROR, &bnad->flags)) {
+ spin_unlock_irq(&bnad->priv_lock);
+ return;
+ }
+ spin_unlock_irq(&bnad->priv_lock);
+
+ switch (bnad->state) {
+ case BNAD_S_INIT:
+ bnad->state = BNAD_S_INIT_DOWN;
+ break;
+ case BNAD_S_OPEN:
+ bnad->state = BNAD_S_OPEN_DOWN;
+ bnad_stop_data_path(bnad, 1);
+ bnad_cleanup(bnad);
+ break;
+ case BNAD_S_START:
+ case BNAD_S_INIT_DISABLING:
+ case BNAD_S_OPENING:
+ case BNAD_S_OPEN_DISABLING:
+ case BNAD_S_CLOSING:
+ BNA_ASSERT(0);
+ /* fall through */
+ default:
+ break;
+ }
+}
+
+static void
+bnad_resume_after_reset(struct bnad *bnad)
+{
+ int err;
+ struct net_device *netdev = bnad->netdev;
+ char message[BNA_MESSAGE_SIZE];
+
+
+ switch (bnad->state) {
+ case BNAD_S_INIT_DOWN:
+ bnad->state = BNAD_S_INIT;
+
+ bna_port_mac_get(bnad->priv, (struct mac *)bnad->perm_addr);
+ BNA_ASSERT(netdev->addr_len == sizeof(bnad->perm_addr));
+ memcpy(netdev->perm_addr, bnad->perm_addr, netdev->addr_len);
+ if (is_zero_ether_addr(netdev->dev_addr))
+ memcpy(netdev->dev_addr, bnad->perm_addr,
+ netdev->addr_len);
+ break;
+ case BNAD_S_OPEN_DOWN:
+ err = bnad_enable_locked(bnad);
+ if (err) {
+ sprintf(message,
+ "%s bnad_enable failed after reset: %d",
+ bnad->netdev->name, err);
+ DPRINTK(INFO, "%s",
+ message);
+ } else {
+ bnad_port_admin_locked(bnad, BNA_ENABLE);
+ }
+ break;
+ case BNAD_S_START:
+ case BNAD_S_INIT_DISABLING:
+ case BNAD_S_OPENING:
+ case BNAD_S_OPEN:
+ case BNAD_S_OPEN_DISABLING:
+ case BNAD_S_CLOSING:
+ BNA_ASSERT(0);
+ /* fall through */
+ default:
+ break;
+ }
+
+}
+
+static void
+bnad_tx_free_tasklet(unsigned long bnad_ptr)
+{
+ struct bnad *bnad = (struct bnad *)bnad_ptr;
+ struct bnad_txq_info *txqinfo;
+ struct bna_txq *txq;
+ unsigned int acked;
+
+ txqinfo = &bnad->txq_table[0];
+ txq = &txqinfo->txq;
+
+ if ((u16) (*txqinfo->hw_consumer_index) != txq->q.consumer_index &&
+ !test_and_set_bit(BNAD_TXQ_FREE_SENT, &txqinfo->flags)) {
+ acked = bnad_free_txbufs(txqinfo,
+ (u16) (*txqinfo->
+ hw_consumer_index));
+ bna_ib_ack(bnad->priv, &txqinfo->ib, acked);
+ smp_mb__before_clear_bit();
+ clear_bit(BNAD_TXQ_FREE_SENT, &txqinfo->flags);
+ }
+}
+
+
+static void
+bnad_cee_reconfig_prio(struct bnad *bnad, u8 cee_linkup, unsigned int prio)
+{
+
+
+ if (prio != bnad->curr_priority) {
+ bnad_sw_reset_locked_internal(bnad->netdev);
+ } else {
+ spin_lock_irq(&bnad->priv_lock);
+ if (!cee_linkup)
+ clear_bit(BNAD_F_CEE_RUNNING, &bnad->flags);
+ else
+ set_bit(BNAD_F_CEE_RUNNING, &bnad->flags);
+ spin_unlock_irq(&bnad->priv_lock);
+ }
+}
+
+static void
+bnad_link_state_notify(struct bnad *bnad)
+{
+ struct net_device *netdev = bnad->netdev;
+ enum bnad_link_state link_state;
+ u8 cee_linkup;
+ unsigned int prio = 0;
+ char message[BNA_MESSAGE_SIZE];
+
+
+ if (bnad->state != BNAD_S_OPEN) {
+ sprintf(message, "%s link up in state %d", netdev->name,
+ bnad->state);
+ DPRINTK(INFO, "%s", message);
+ return;
+ }
+
+ spin_lock_irq(&bnad->priv_lock);
+ link_state = bnad->link_state;
+ cee_linkup = bnad->cee_linkup;
+ if (cee_linkup)
+ prio = bnad->priority;
+ spin_unlock_irq(&bnad->priv_lock);
+
+ if (link_state == BNAD_LS_UP) {
+ bnad_cee_reconfig_prio(bnad, cee_linkup, prio);
+ if (!netif_carrier_ok(netdev)) {
+ netif_carrier_on(netdev);
+ netif_wake_queue(netdev);
+ bnad->stats.netif_queue_wakeup++;
+ }
+ } else {
+ if (netif_carrier_ok(netdev)) {
+ netif_carrier_off(netdev);
+ bnad->stats.netif_queue_stop++;
+ }
+ }
+}
+
+static void
+bnad_work(struct work_struct *work)
+{
+ struct bnad *bnad = container_of(work, struct bnad, work);
+ unsigned long work_flags;
+
+
+ bnad_conf_lock();
+
+ spin_lock_irq(&bnad->priv_lock);
+ work_flags = bnad->work_flags;
+ bnad->work_flags = 0;
+ spin_unlock_irq(&bnad->priv_lock);
+
+ if (work_flags & BNAD_WF_ERROR)
+ bnad_error(bnad);
+ if (work_flags & BNAD_WF_RESETDONE)
+ bnad_resume_after_reset(bnad);
+
+ if (work_flags & BNAD_WF_LS_NOTIFY)
+ bnad_link_state_notify(bnad);
+
+ bnad_conf_unlock();
+}
+
+static void
+bnad_stats_timeo(unsigned long data)
+{
+ struct bnad *bnad = (struct bnad *)data;
+ int i;
+ struct bnad_rxq_info *rxqinfo;
+
+ spin_lock_irq(&bnad->priv_lock);
+ bna_stats_get(bnad->priv);
+ spin_unlock_irq(&bnad->priv_lock);
+
+ if (bnad->rx_dyn_coalesce_on) {
+ u8 cls_timer;
+ struct bnad_cq_info *cq;
+ for (i = 0; i < bnad->cq_num; i++) {
+ cq = &bnad->cq_table[i];
+
+ if ((cq->pkt_rate.small_pkt_cnt == 0) &&
+ (cq->pkt_rate.large_pkt_cnt == 0))
+ continue;
+
+ cls_timer =
+ bna_calc_coalescing_timer(bnad->priv,
+ &cq->pkt_rate);
+
+ /* For NAPI version, coalescing timer need to stored */
+ cq->rx_coalescing_timeo = cls_timer;
+
+ bna_ib_coalescing_timer_set(bnad->priv, &cq->ib,
+ cls_timer);
+ }
+ }
+
+ for (i = 0; i < bnad->rxq_num; i++) {
+ rxqinfo = &bnad->rxq_table[i];
+ if (!
+ (BNA_QE_IN_USE_CNT
+ (&rxqinfo->skb_unmap_q,
+ rxqinfo->skb_unmap_q.
+ q_depth) >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)) {
+ if (test_and_set_bit(BNAD_RXQ_REFILL, &rxqinfo->flags))
+ continue;
+ bnad_alloc_rxbufs(rxqinfo);
+ smp_mb__before_clear_bit();
+ clear_bit(BNAD_RXQ_REFILL, &rxqinfo->flags);
+ }
+ }
+}
+
+static void
+bnad_free_ioc_mem(struct bnad *bnad)
+{
+ enum bna_dma_mem_type i;
+
+ for (i = 0; i < BNA_MEM_T_MAX; i++) {
+ if (!bnad->ioc_meminfo[i].len)
+ continue;
+ if (bnad->ioc_meminfo[i].kva && bnad->ioc_meminfo[i].dma)
+ pci_free_consistent(bnad->pcidev,
+ bnad->ioc_meminfo[i].len,
+ bnad->ioc_meminfo[i].kva,
+ *(dma_addr_t *) &bnad->
+ ioc_meminfo[i].dma);
+ else if (bnad->ioc_meminfo[i].kva)
+ vfree(bnad->ioc_meminfo[i].kva);
+ bnad->ioc_meminfo[i].kva = NULL;
+ }
+}
+
+/* The following IOC callback functions are called with priv_lock held. */
+
+void
+bna_iocll_enable_cbfn(void *arg, enum bfa_status error)
+{
+ struct bnad *bnad = arg;
+
+
+ if (!error) {
+ bnad->work_flags &= ~BNAD_WF_LS_NOTIFY;
+ bnad->work_flags |= BNAD_WF_RESETDONE;
+
+ if (bnad->state != BNAD_S_UNLOADING)
+ schedule_work(&bnad->work);
+ }
+
+ bnad->ioc_comp_status = error;
+ complete(&bnad->ioc_comp);
+}
+
+void
+bna_iocll_disable_cbfn(void *arg)
+{
+ struct bnad *bnad = arg;
+
+ complete(&bnad->ioc_comp);
+}
+
+void
+bna_iocll_hbfail_cbfn(void *arg)
+{
+ struct bnad *bnad = arg;
+
+ bnad_hw_error(bnad, BFA_STATUS_IOC_FAILURE);
+}
+
+void
+bna_iocll_reset_cbfn(void *arg)
+{
+ struct bnad *bnad = arg;
+ u32 int_status, int_mask;
+ unsigned int irq;
+
+ /* Clear the status */
+ bna_intr_status_get(bnad->priv, &int_status);
+
+
+ if (bnad->config & BNAD_CF_MSIX) {
+ if (test_and_clear_bit(BNAD_F_MBOX_IRQ_DISABLED,
+ &bnad->flags)) {
+ irq = bnad->msix_table[bnad->msix_num - 1].vector;
+ enable_irq(irq);
+ }
+ }
+
+ int_mask = ~(__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS);
+ bna_intx_enable(bnad->priv, int_mask);
+}
+
+static void
+bnad_ioc_timeout(unsigned long data)
+{
+ struct bnad *bnad = (struct bnad *)data;
+
+ spin_lock_irq(&bnad->priv_lock);
+ bna_iocll_timer(bnad->priv);
+ spin_unlock_irq(&bnad->priv_lock);
+
+ if (bnad->state != BNAD_S_UNLOADING)
+ mod_timer(&bnad->ioc_timer,
+ jiffies + msecs_to_jiffies(BNA_IOC_TIMER_PERIOD));
+}
+
+s32
+bnad_cee_attach(struct bnad *bnad)
+{
+ u8 *dma_kva;
+ dma_addr_t dma_pa;
+ struct bfa_cee *cee = &bnad->cee;
+
+ memset(cee, 0, sizeof(struct bfa_cee));
+
+ /* Allocate memory for dma */
+ dma_kva =
+ pci_alloc_consistent(bnad->pcidev, bfa_cee_meminfo(), &dma_pa);
+ if (dma_kva == NULL)
+ return -ENOMEM;
+
+ /* Ugly... need to remove once CAL is fixed. */
+ ((struct bna_dev *) bnad->priv)->cee = cee;
+
+ bnad->cee_cbfn.get_attr_cbfn = bnad_cee_get_attr_cb;
+ bnad->cee_cbfn.get_stats_cbfn = bnad_cee_get_stats_cb;
+ bnad->cee_cbfn.reset_stats_cbfn = bnad_cee_reset_stats_cb;
+ bnad->cee_cbfn.reset_stats_cbfn = NULL;
+
+ /* Invoke cee attach function */
+ bfa_cee_attach(cee, &bnad->priv->ioc, bnad, bnad->trcmod, bnad->logmod);
+ bfa_cee_mem_claim(cee, dma_kva, dma_pa);
+ return 0;
+}
+
+static void
+bnad_cee_detach(struct bnad *bnad)
+{
+ struct bfa_cee *cee = &bnad->cee;
+
+ if (cee->attr_dma.kva) {
+ pci_free_consistent(bnad->pcidev, bfa_cee_meminfo(),
+ cee->attr_dma.kva, cee->attr_dma.pa);
+ }
+ bfa_cee_detach(&bnad->cee);
+}
+
+static int
+bnad_priv_init(struct bnad *bnad)
+{
+ dma_addr_t dma_addr;
+ struct bna_dma_addr bna_dma_addr;
+ int err = 0, i;
+ struct bfa_pcidev pcidev_info;
+ u32 intr_mask;
+
+ if (bnad_msix)
+ bnad->config |= BNAD_CF_MSIX;
+ bnad_q_num_init(bnad, bnad_rxqsets_used);
+
+ bnad->work_flags = 0;
+ INIT_WORK(&bnad->work, bnad_work);
+
+ tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
+ (unsigned long)bnad);
+
+ setup_timer(&bnad->stats_timer, bnad_stats_timeo,
+ (unsigned long)bnad);
+
+ bnad->tx_coalescing_timeo = BNAD_TX_COALESCING_TIMEO;
+ bnad->tx_interpkt_count = BNAD_TX_INTERPKT_COUNT;
+
+ bnad->rx_coalescing_timeo = BNAD_RX_COALESCING_TIMEO;
+ bnad->rx_interpkt_count = BNAD_RX_INTERPKT_COUNT;
+ bnad->rx_interpkt_timeo = BNAD_RX_INTERPKT_TIMEO;
+
+ bnad->rx_dyn_coalesce_on = BNA_TRUE;
+
+ bnad->rx_csum = 1;
+ bnad->pause_config.tx_pause = 0;
+ bnad->pause_config.rx_pause = 0;
+
+ /* XXX could be vmalloc? */
+ bnad->trcmod = kzalloc(sizeof(struct bfa_trc_mod), GFP_KERNEL);
+ if (!bnad->trcmod) {
+ printk(KERN_ERR "port %u failed allocating trace buffer!\n",
+ bnad->bna_id);
+ return -ENOMEM;
+ }
+
+ bfa_trc_init(bnad->trcmod);
+
+ bnad->logmod = NULL;
+
+
+ bnad->priv = kzalloc(bna_get_handle_size(), GFP_KERNEL);
+ if (!bnad->priv) {
+ printk(KERN_ERR "port %u failed allocating memory for bna\n",
+ bnad->bna_id);
+ err = -ENOMEM;
+ goto free_trcmod;
+ }
+ bnad->priv_stats =
+ pci_alloc_consistent(bnad->pcidev, BNA_HW_STATS_SIZE,
+ &dma_addr);
+ if (!bnad->priv_stats) {
+ printk(KERN_ERR
+ "port %u failed allocating memory for bna stats\n",
+ bnad->bna_id);
+ err = -ENOMEM;
+ goto free_priv_mem;
+ }
+ pci_unmap_addr_set(bnad, priv_stats_dma, dma_addr);
+
+ BNA_SET_DMA_ADDR(dma_addr, &bna_dma_addr);
+ bna_init(bnad->priv, (void *)bnad->bar0, bnad->priv_stats, bna_dma_addr,
+ bnad->trcmod, bnad->logmod);
+ bna_all_stats_get(bnad->priv, &bnad->hw_stats);
+
+ spin_lock_init(&bnad->priv_lock);
+ init_MUTEX(&bnad->conf_sem);
+ bnad->priv_cbfn.ucast_set_cb = bnad_ucast_set_cb;
+ bnad->priv_cbfn.txq_stop_cb = bnad_q_stop_cb;
+ bnad->priv_cbfn.rxq_stop_cb = bnad_q_stop_cb;
+ bnad->priv_cbfn.link_up_cb = bnad_link_up_cb;
+ bnad->priv_cbfn.link_down_cb = bnad_link_down_cb;
+ bnad->priv_cbfn.stats_get_cb = bnad_stats_get_cb;
+ bnad->priv_cbfn.hw_error_cb = bnad_hw_error_cb;
+ bnad->priv_cbfn.lldp_get_cfg_cb = bnad_lldp_get_cfg_cb;
+
+ bna_register_callback(bnad->priv, &bnad->priv_cbfn, bnad);
+
+ bna_iocll_meminfo(bnad->priv, bnad->ioc_meminfo);
+ for (i = 0; i < BNA_MEM_T_MAX; i++) {
+ if (!bnad->ioc_meminfo[i].len)
+ continue;
+ switch (i) {
+ case BNA_KVA_MEM_T_FWTRC:
+ bnad->ioc_meminfo[i].kva =
+ vmalloc(bnad->ioc_meminfo[i].len);
+ break;
+ default:
+ bnad->ioc_meminfo[i].kva =
+ pci_alloc_consistent(bnad->pcidev,
+ bnad->ioc_meminfo[i].len,
+ (dma_addr_t *) &bnad->
+ ioc_meminfo[i].dma);
+
+ break;
+ }
+ if (!bnad->ioc_meminfo[i].kva) {
+ printk(KERN_ERR
+ "port %u failed allocating %u "
+ "bytes memory for IOC\n",
+ bnad->bna_id, bnad->ioc_meminfo[i].len);
+ err = -ENOMEM;
+ goto free_ioc_mem;
+ } else
+ memset(bnad->ioc_meminfo[i].kva, 0,
+ bnad->ioc_meminfo[i].len);
+ }
+
+ pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
+ pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
+ pcidev_info.device_id = bnad->pcidev->device;
+ pcidev_info.pci_bar_kva = bnad->bar0;
+ bna_iocll_attach(bnad->priv, bnad, bnad->ioc_meminfo, &pcidev_info,
+ bnad->trcmod, NULL, bnad->logmod);
+
+ err = bnad_cee_attach(bnad);
+ if (err) {
+ printk(KERN_ERR "port %u cee_attach failed: %d\n", bnad->bna_id,
+ err);
+ goto iocll_detach;
+ }
+
+ if (bnad->config & BNAD_CF_MSIX)
+ bnad_enable_msix(bnad);
+ else
+ dev_info(&bnad->pcidev->dev, "Working in INTx mode, no RSS\n");
+ bna_intx_disable(bnad->priv, &intr_mask);
+ err = bnad_request_mbox_irq(bnad);
+ if (err)
+ goto disable_msix;
+
+ setup_timer(&bnad->ioc_timer, bnad_ioc_timeout,
+ (unsigned long)bnad);
+ mod_timer(&bnad->ioc_timer, jiffies +
+ msecs_to_jiffies(BNA_IOC_TIMER_PERIOD));
+
+ bnad_conf_lock();
+ bnad->state = BNAD_S_START;
+
+ init_completion(&bnad->ioc_comp);
+ spin_lock_irq(&bnad->priv_lock);
+ bna_iocll_enable(bnad->priv);
+ spin_unlock_irq(&bnad->priv_lock);
+
+ wait_for_completion(&bnad->ioc_comp);
+
+ if (!bnad->ioc_comp_status) {
+ bnad->state = BNAD_S_INIT;
+ bna_port_mac_get(bnad->priv, (struct mac *)bnad->perm_addr);
+ } else {
+ bnad->state = BNAD_S_INIT_DOWN;
+ }
+ bnad_conf_unlock();
+
+ return 0;
+
+disable_msix:
+ bnad_disable_msix(bnad);
+ bnad_cee_detach(bnad);
+iocll_detach:
+ bna_iocll_detach(bnad->priv);
+free_ioc_mem:
+ bnad_free_ioc_mem(bnad);
+ bna_uninit(bnad->priv);
+ pci_free_consistent(bnad->pcidev, BNA_HW_STATS_SIZE, bnad->priv_stats,
+ pci_unmap_addr(bnad, priv_stats_dma));
+ bnad->priv_stats = NULL;
+free_priv_mem:
+ kfree(bnad->priv);
+ bnad->priv = NULL;
+free_trcmod:
+ kfree(bnad->trcmod);
+ bnad->trcmod = NULL;
+
+ return err;
+}
+
+static void
+bnad_priv_uninit(struct bnad *bnad)
+{
+ int i;
+ enum bna_status_e err;
+ char message[BNA_MESSAGE_SIZE];
+
+ if (bnad->priv) {
+
+
+ init_completion(&bnad->ioc_comp);
+
+ for (i = 0; i < 10; i++) {
+ spin_lock_irq(&bnad->priv_lock);
+ err = bna_iocll_disable(bnad->priv);
+ spin_unlock_irq(&bnad->priv_lock);
+ BNA_ASSERT(!err || err == BNA_BUSY);
+ if (!err)
+ break;
+ msleep(1000);
+ }
+ if (err) {
+ /* Probably firmware crashed. */
+ sprintf(message,
+ "bna_iocll_disable failed, "
+ "clean up and try again");
+ DPRINTK(INFO, "%s", message);
+ spin_lock_irq(&bnad->priv_lock);
+ bna_cleanup(bnad->priv);
+ err = bna_iocll_disable(bnad->priv);
+ spin_unlock_irq(&bnad->priv_lock);
+ BNA_ASSERT(!err);
+ }
+ wait_for_completion(&bnad->ioc_comp);
+
+ sprintf(message, "port %u IOC is disabled", bnad->bna_id);
+ DPRINTK(INFO, "%s", message);
+
+ bnad->state = BNAD_S_UNLOADING;
+
+ /* Stop the timer after disabling IOC. */
+ del_timer_sync(&bnad->ioc_timer);
+ bnad_free_ioc_mem(bnad);
+ bna_iocll_detach(bnad->priv);
+
+ flush_scheduled_work();
+ bnad_free_mbox_irq(bnad);
+
+ bnad_disable_msix(bnad);
+
+ bnad_cee_detach(bnad);
+
+
+ bna_uninit(bnad->priv);
+ if (bnad->priv_stats) {
+ pci_free_consistent(bnad->pcidev, BNA_HW_STATS_SIZE,
+ bnad->priv_stats,
+ pci_unmap_addr(bnad,
+ priv_stats_dma));
+ bnad->priv_stats = NULL;
+ }
+ kfree(bnad->priv);
+ bnad->priv = NULL;
+ }
+ kfree(bnad->trcmod);
+ bnad->trcmod = NULL;
+}
+
+static struct pci_device_id bnad_pci_id_table[] = {
+ {
+ .vendor = PCI_VENDOR_ID_BROCADE,
+ .device = PCI_DEVICE_ID_BROCADE_CATAPULT,
+ .subvendor = PCI_ANY_ID,
+ .subdevice = PCI_ANY_ID,
+ .class = PCI_CLASS_NETWORK_ETHERNET << 8,
+ .class_mask = 0xffff00},
+ {0, 0}
+};
+
+MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
+
+static int __devinit
+bnad_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pcidev_id)
+{
+ int err, using_dac;
+ struct net_device *netdev;
+ struct bnad *bnad;
+ unsigned long mmio_start, mmio_len;
+ static u32 bna_id;
+
+ printk(KERN_INFO "bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
+ pdev, pcidev_id, PCI_FUNC(pdev->devfn));
+
+ if (!bfad_get_firmware_buf(pdev)) {
+ printk(KERN_WARNING "Failed to load Firmware Image!\n");
+ return -ENODEV;
+ }
+
+ err = pci_enable_device(pdev);
+ if (err) {
+ dev_err(&pdev->dev, "pci_enable_device failed: %d\n", err);
+ return err;
+ }
+
+ err = pci_request_regions(pdev, BNAD_NAME);
+ if (err) {
+ dev_err(&pdev->dev, "pci_request_regions failed: %d\n", err);
+ goto disable_device;
+ }
+
+ if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
+ !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
+ using_dac = 1;
+ } else {
+ err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+ if (err) {
+ err = pci_set_consistent_dma_mask(pdev,
+ DMA_BIT_MASK(32));
+ if (err) {
+ dev_err(&pdev->dev,
+ "set 32bit consistent DMA mask failed: "
+ "%d\n", err);
+ goto release_regions;
+ }
+ }
+ using_dac = 0;
+ }
+
+ pci_set_master(pdev);
+
+ netdev = alloc_etherdev(sizeof(struct bnad));
+ if (!netdev) {
+ dev_err(&pdev->dev, "alloc_etherdev failed\n");
+ err = -ENOMEM;
+ goto release_regions;
+ }
+ SET_MODULE_OWNER(netdev);
+ SET_NETDEV_DEV(netdev, &pdev->dev);
+ pci_set_drvdata(pdev, netdev);
+
+ bnad = netdev_priv(netdev);
+
+ memset(bnad, 0, sizeof(struct bnad));
+
+ bnad->netdev = netdev;
+ bnad->pcidev = pdev;
+ mmio_start = pci_resource_start(pdev, 0);
+ mmio_len = pci_resource_len(pdev, 0);
+ bnad->bar0 = ioremap_nocache(mmio_start, mmio_len);
+ if (!bnad->bar0) {
+ dev_err(&pdev->dev, "ioremap for bar0 failed\n");
+ err = -ENOMEM;
+ goto free_devices;
+ }
+ printk(KERN_INFO "bar0 mapped to %p, len %lu\n", bnad->bar0, mmio_len);
+
+ netdev->netdev_ops = &bnad_netdev_ops;
+
+ netdev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
+ netdev->features |= NETIF_F_IPV6_CSUM;
+ netdev->features |= NETIF_F_TSO;
+ netdev->features |= NETIF_F_TSO6;
+
+#ifdef BNAD_VLAN_FEATURES
+ netdev->vlan_features = netdev->features;
+#endif
+ if (using_dac)
+ netdev->features |= NETIF_F_HIGHDMA;
+ netdev->features |=
+ NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
+ NETIF_F_HW_VLAN_FILTER;
+
+
+ netdev->mem_start = mmio_start;
+ netdev->mem_end = mmio_start + mmio_len - 1;
+
+ bnad_set_ethtool_ops(netdev);
+
+ bnad->bna_id = bna_id;
+ err = bnad_priv_init(bnad);
+ if (err) {
+ printk(KERN_ERR "port %u init failed: %d\n", bnad->bna_id, err);
+ goto unmap_bar0;
+ }
+
+ BNA_ASSERT(netdev->addr_len == ETH_ALEN);
+ memcpy(netdev->perm_addr, bnad->perm_addr, netdev->addr_len);
+ memcpy(netdev->dev_addr, bnad->perm_addr, netdev->addr_len);
+
+ netif_carrier_off(netdev);
+ err = register_netdev(netdev);
+ if (err) {
+ printk(KERN_ERR "port %u register_netdev failed: %d\n",
+ bnad->bna_id, err);
+ goto bnad_device_uninit;
+ }
+ bna_id++;
+ return 0;
+
+bnad_device_uninit:
+ bnad_priv_uninit(bnad);
+unmap_bar0:
+ iounmap(bnad->bar0);
+free_devices:
+ pci_set_drvdata(pdev, NULL);
+ free_netdev(netdev);
+release_regions:
+ pci_release_regions(pdev);
+disable_device:
+ pci_disable_device(pdev);
+
+ return err;
+}
+
+static void __devexit
+bnad_pci_remove(struct pci_dev *pdev)
+{
+ struct net_device *netdev = pci_get_drvdata(pdev);
+ struct bnad *bnad;
+
+ if (!netdev)
+ return;
+
+ printk(KERN_INFO "%s bnad_pci_remove\n", netdev->name);
+ bnad = netdev_priv(netdev);
+
+
+ unregister_netdev(netdev);
+
+ bnad_priv_uninit(bnad);
+ iounmap(bnad->bar0);
+ pci_set_drvdata(pdev, NULL);
+ free_netdev(netdev);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+}
+
+static struct pci_driver bnad_pci_driver = {
+ .name = BNAD_NAME,
+ .id_table = bnad_pci_id_table,
+ .probe = bnad_pci_probe,
+ .remove = __devexit_p(bnad_pci_remove),
+};
+
+static int __init
+bnad_module_init(void)
+{
+
+ printk(KERN_INFO "Module bna is loaded at 0x%p\n",
+ __this_module.module_core);
+
+ bfa_ioc_auto_recover(bnad_ioc_auto_recover);
+
+ return pci_register_driver(&bnad_pci_driver);
+}
+
+static void __exit
+bnad_module_exit(void)
+{
+ pci_unregister_driver(&bnad_pci_driver);
+
+ if (bfi_image_ct_size && bfi_image_ct)
+ vfree(bfi_image_ct);
+}
+
+module_init(bnad_module_init);
+module_exit(bnad_module_exit);
+
+MODULE_AUTHOR("Brocade");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
+MODULE_VERSION(BNAD_VERSION);
diff -ruP net-next-2.6-orig/drivers/net/bna/bnad.h net-next-2.6-mod/drivers/net/bna/bnad.h
--- net-next-2.6-orig/drivers/net/bna/bnad.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bnad.h 2009-11-12 19:03:38.446395000 -0800
@@ -0,0 +1,350 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ */
+
+#ifndef _BNAD_H_
+#define _BNAD_H_
+
+#include <cee/bfa_cee.h>
+#include "bna.h"
+
+#include "bnad_compat.h"
+
+#define BNAD_MAX_Q_DEPTH 0x10000
+#define BNAD_MIN_Q_DEPTH 0x200
+
+#define BNAD_TXQ_NUM 1
+#define BNAD_TX_FUNC_ID 0
+#define BNAD_ENTRIES_PER_TXQ 2048
+
+#define BNAD_MAX_RXQS 64
+#define BNAD_MAX_RXQSETS_USED 16
+#define BNAD_RX_FUNC_ID 0
+#define BNAD_ENTRIES_PER_RXQ 2048
+
+#define BNAD_MAX_CQS 64
+#define BNAD_MAX_RXQS_PER_CQ 2
+
+#define BNAD_MSIX_ERR_MAILBOX_NUM 1
+
+#define BNAD_INTX_MAX_IB_NUM 16
+#define BNAD_INTX_IB_NUM 2 /* 1 for Tx, 1 for Rx */
+#define BNAD_INTX_TX_IB_ID 0
+#define BNAD_INTX_RX_IB_ID 1
+
+#define BNAD_QUEUE_NAME_SIZE 16
+
+#define BNAD_JUMBO_MTU 9000
+
+#define BNAD_COALESCING_TIMER_UNIT 5 /* 5us */
+#define BNAD_MAX_COALESCING_TIMEO 0xFF /* in 5us units */
+#define BNAD_MAX_INTERPKT_COUNT 0xFF
+#define BNAD_MAX_INTERPKT_TIMEO 0xF /* in 0.5us units */
+
+#define BNAD_TX_COALESCING_TIMEO 20 /* 20 * 5 = 100us */
+#define BNAD_TX_INTERPKT_COUNT 32
+
+#define BNAD_RX_COALESCING_TIMEO 12 /* 12 * 5 = 60us */
+#define BNAD_RX_INTERPKT_COUNT 6
+#define BNAD_RX_INTERPKT_TIMEO 3 /* 3 * 0.5 = 1.5us */
+
+#define BNAD_SMALL_RXBUF_SIZE 128
+
+#define BNAD_RIT_OFFSET 0
+#define BNAD_MULTICAST_RXQ_ID 0
+
+#define BNAD_NETIF_WAKE_THRESHOLD 8
+
+#define BNAD_TX_MAX_VECTORS 255
+#define BNAD_TX_MAX_VECTORS_PER_WI 4
+#define BNAD_TX_MAX_DATA_PER_WI 0xFFFFFF /* 24 bits */
+#define BNAD_TX_MAX_DATA_PER_VECTOR 0x3FFF /* 14 bits */
+#define BNAD_TX_MAX_WRR_QUOTA 0xFFF /* 12 bits */
+
+#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3
+
+#define BNAD_NOT_READY(_bnad) test_bit(BNAD_F_HWERROR, &(_bnad)->flags)
+#define BNAD_ADMIN_DOWN(_bnad) (!netif_running((_bnad)->netdev) || \
+ test_bit(BNAD_F_BCU_DISABLED, &(_bnad)->flags))
+
+#define BNAD_Q_INDEX_CHANGE(_old_idx, _updated_idx, _q_depth) \
+ (((_updated_idx) - (_old_idx)) & ((_q_depth) - 1))
+
+#define bnad_conf_lock() down(&bnad->conf_sem)
+#define bnad_conf_unlock() up(&bnad->conf_sem)
+
+extern u32 bfi_image_ct_size;
+extern u32 *bfi_image_ct;
+extern u32 *bfad_get_firmware_buf(struct pci_dev *pdev);
+
+struct bnad_skb_unmap {
+ struct sk_buff *skb;
+ DECLARE_PCI_UNMAP_ADDR(dma_addr)
+};
+
+struct bnad_unmap_q {
+ u32 producer_index;
+ u32 consumer_index;
+ struct bnad_skb_unmap *unmap_array;
+ u32 q_depth;
+};
+
+struct bnad_ib_entry {
+ struct bna_ib *ib;
+ void *ib_seg_addr;
+ struct bna_ib_config ib_config;
+};
+
+struct bnad_txq_info {
+ unsigned long flags;
+#define BNAD_TXQ_FREE_SENT 0
+ struct bna_txq txq;
+ struct bna_ib ib;
+ struct bnad_unmap_q skb_unmap_q;
+ u64 tx_packets;
+ u64 tx_bytes;
+ struct bnad *bnad;
+ volatile u32 *hw_consumer_index;
+ struct bna_txq_config txq_config;
+ char name[BNAD_QUEUE_NAME_SIZE];
+} ____cacheline_aligned;
+
+struct bnad_rxq_info {
+ unsigned long flags;
+#define BNAD_RXQ_REFILL 0
+ struct bna_rxq rxq;
+ struct bnad_unmap_q skb_unmap_q;
+ u64 rx_packets;
+ u64 rx_bytes;
+ u64 rx_packets_with_error;
+ u64 rxbuf_alloc_failed;
+ struct bnad *bnad;
+ u32 rxq_id;
+ struct bna_rxq_config rxq_config;
+} ____cacheline_aligned;
+
+struct bnad_cq_info {
+ struct bna_cq cq;
+ struct bna_ib ib;
+ struct bnad *bnad;
+ struct bna_pkt_rate pkt_rate;
+ u8 rx_coalescing_timeo; /* Unit is 5usec. */
+ volatile u32 *hw_producer_index;
+ struct napi_struct napi;
+ u32 cq_id;
+ struct bna_cq_config cq_config;
+ char name[BNAD_QUEUE_NAME_SIZE];
+} ____cacheline_aligned;
+
+struct bnad_txf_info {
+ u32 txf_id;
+ struct bna_txf_config txf_config;
+};
+
+struct bnad_rxf_info {
+ u32 rxf_id;
+ struct bna_rxf_config rxf_config;
+};
+
+enum bnad_ucast_cmd {
+ BNAD_UCAST_MAC_SET,
+ BNAD_UCAST_MAC_ADD,
+ BNAD_UCAST_MAC_DEL
+};
+
+
+enum bnad_state {
+ BNAD_S_START = 0,
+ BNAD_S_INIT = 1,
+ BNAD_S_INIT_DOWN = 2,
+ BNAD_S_INIT_DISABLING = 3,
+ BNAD_S_INIT_DISABLED = 4,
+ BNAD_S_OPENING = 5,
+ BNAD_S_OPEN = 6,
+ BNAD_S_OPEN_DOWN = 7,
+ BNAD_S_OPEN_DISABLING = 8,
+ BNAD_S_OPEN_DISABLED = 9,
+ BNAD_S_CLOSING = 10,
+ BNAD_S_UNLOADING = 11
+};
+
+enum bnad_link_state {
+ BNAD_LS_DOWN = 0,
+ BNAD_LS_UP = 1
+};
+struct bnad {
+ struct net_device *netdev;
+ struct pci_dev *pcidev;
+ struct bna_dev *priv;
+
+ enum bnad_state state;
+ unsigned long flags;
+#define BNAD_F_BCU_DISABLED 0
+#define BNAD_F_HWERROR 1
+#define BNAD_F_MBOX_IRQ_DISABLED 2
+#define BNAD_F_CEE_RUNNING 3
+
+ unsigned int config;
+#define BNAD_CF_MSIX 0x01
+#define BNAD_CF_PROMISC 0x02
+#define BNAD_CF_ALLMULTI 0x04
+#define BNAD_CF_TXQ_DEPTH 0x10
+#define BNAD_CF_RXQ_DEPTH 0x20
+
+ unsigned int priority;
+ unsigned int curr_priority; /* currently applied priority */
+
+ enum bnad_link_state link_state;
+ u8 cee_linkup;
+
+ uint txq_num;
+ uint txq_depth;
+ struct bnad_txq_info *txq_table;
+
+ struct tasklet_struct tx_free_tasklet; /* For Tx cleanup */
+
+ uint rxq_num;
+ uint rxq_depth;
+ struct bnad_rxq_info *rxq_table;
+ uint cq_num;
+ struct bnad_cq_info *cq_table;
+
+ struct vlan_group *vlangrp;
+
+ u32 rx_csum;
+
+ uint msix_num;
+ struct msix_entry *msix_table;
+
+ uint ib_num;
+ struct bnad_ib_entry *ib_table;
+
+ struct bna_rit_entry *rit; /* RxQ Indirection Table */
+
+ spinlock_t priv_lock ____cacheline_aligned;
+
+ uint txf_num;
+ struct bnad_txf_info *txf_table;
+ uint rxf_num;
+ struct bnad_rxf_info *rxf_table;
+
+ struct timer_list stats_timer;
+ struct net_device_stats net_stats;
+
+ u8 tx_coalescing_timeo; /* Unit is 5usec. */
+ u8 tx_interpkt_count;
+
+ u8 rx_coalescing_timeo; /* Unit is 5usec. */
+ u8 rx_interpkt_count;
+ u8 rx_interpkt_timeo; /* 4 bits, unit is 0.5usec. */
+
+ u8 rx_dyn_coalesce_on; /* Rx Dynamic Intr Moderation Flag */
+
+ u8 ref_count;
+
+ u8 lldp_comp_status;
+ u8 cee_stats_comp_status;
+ u8 cee_reset_stats_status;
+ u8 ucast_comp_status;
+ u8 qstop_comp_status;
+
+ int ioc_comp_status;
+
+ struct bna_pause_config pause_config;
+
+ struct bna_stats *hw_stats;
+ struct bnad_drv_stats stats;
+
+ struct work_struct work;
+ unsigned int work_flags;
+#define BNAD_WF_ERROR 0x1
+#define BNAD_WF_RESETDONE 0x2
+#define BNAD_WF_CEE_PRIO 0x4
+#define BNAD_WF_LS_NOTIFY 0x8
+
+ struct completion lldp_comp;
+ struct completion cee_stats_comp;
+ struct completion cee_reset_stats_comp;
+ struct completion ucast_comp;
+ struct completion qstop_comp;
+ struct completion ioc_comp;
+
+ u32 bna_id;
+ u8 __iomem *bar0; /* registers */
+ unsigned char perm_addr[ETH_ALEN];
+
+ void *priv_stats;
+ DECLARE_PCI_UNMAP_ADDR(priv_stats_dma)
+
+ struct bfa_trc_mod *trcmod;
+ struct bfa_log_mod *logmod;
+ struct bna_meminfo ioc_meminfo[BNA_MEM_T_MAX];
+ struct timer_list ioc_timer;
+ struct semaphore conf_sem;
+
+ struct bna_mbox_cbfn priv_cbfn;
+
+ char adapter_name[64];
+ char port_name[64];
+
+ /* CEE Stuff */
+ struct bfa_cee_cbfn cee_cbfn;
+ struct bfa_cee cee;
+
+ struct list_head list_entry;
+};
+
+extern uint bnad_rxqs_per_cq;
+
+extern struct semaphore bnad_list_sem;
+extern struct list_head bnad_list;
+
+int bnad_open(struct net_device *netdev);
+int bnad_stop(struct net_device *netdev);
+int bnad_stop_locked(struct net_device *netdev);
+int bnad_open_locked(struct net_device *netdev);
+int bnad_sw_reset_locked(struct net_device *netdev);
+int bnad_ioc_disabling_locked(struct bnad *bnad);
+void bnad_set_ethtool_ops(struct net_device *netdev);
+void bnad_ioctl_init(void);
+void bnad_ioctl_exit(void);
+struct net_device_stats *bnad_get_stats(struct net_device *netdev);
+
+int bnad_ucast_mac(struct bnad *bnad, unsigned int rxf_id, u8 * mac_ptr,
+ unsigned int cmd);
+void bnad_rxf_init(struct bnad *bnad, uint rxf_id, u8 rit_offset, int rss);
+int bnad_rxq_init(struct bnad *bnad, uint rxq_id);
+void bnad_setup_rxq(struct bnad *bnad, uint rxq_id);
+void bnad_alloc_for_rxq(struct bnad *bnad, uint rxq_id);
+int bnad_disable_rxqs(struct bnad *bnad, u64 rxq_id_mask);
+void bnad_free_rxq(struct bnad *bnad, uint rxq_id);
+int bnad_cq_init(struct bnad *bnad, uint cq_id);
+void bnad_setup_cq(struct bnad *bnad, uint cq_id);
+void bnad_setup_ib(struct bnad *bnad, uint ib_id);
+void bnad_rxib_init(struct bnad *bnad, uint cq_id, uint ib_id);
+void bnad_free_ib(struct bnad *bnad, uint ib_id);
+int bnad_request_cq_irq(struct bnad *bnad, uint cq_id);
+u32 bnad_get_msglevel(struct net_device *netdev);
+void bnad_set_msglevel(struct net_device *netdev, u32 msglevel);
+int bnad_alloc_unmap_q(struct bnad_unmap_q *unmap_q, u32 q_depth);
+void bnad_free_cq(struct bnad *bnad, uint cq_id);
+void bnad_add_to_list(struct bnad *bnad);
+void bnad_remove_from_list(struct bnad *bnad);
+struct bnad *get_bnadev(int bna_id);
+int bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev);
+
+#endif /* _BNAD_H_ */
^ permalink raw reply
* Subject: [PATCH 4/6] bna: Brocade 10Gb Ethernet device driver
From: Rasesh Mody @ 2009-11-13 3:46 UTC (permalink / raw)
To: netdev; +Cc: adapter_linux_open_src_team
From: Rasesh Mody <rmody@brocade.com>
This is patch 4/6 which contains linux driver source for
Brocade's BR1010/BR1020 10Gb CEE capable ethernet adapter.
Source is based against net-next-2.6.
We wish this patch to be considered for inclusion in net-next-2.6
Signed-off-by: Rasesh Mody <rmody@brocade.com>
---
bfa_ioc.h | 312 +++++++
bfa_timer.h | 56 +
bna.h | 2392 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
bna_hwreg.h | 1002 +++++++++++++++++++++++++
bna_intr.h | 90 ++
5 files changed, 3852 insertions(+)
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_ioc.h net-next-2.6-mod/drivers/net/bna/bfa_ioc.h
--- net-next-2.6-orig/drivers/net/bna/bfa_ioc.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_ioc.h 2009-11-12 19:03:38.911356000 -0800
@@ -0,0 +1,312 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __BFA_IOC_H__
+#define __BFA_IOC_H__
+
+#include <cs/bfa_sm.h>
+#include <cs/bfa_trc.h>
+#include <bfi/bfi.h>
+#include <bfi/bfi_ioc.h>
+#include <bfi/bfi_boot.h>
+#include <bfa_timer.h>
+
+/**
+ * PCI device information required by IOC
+ */
+struct bfa_pcidev {
+ int pci_slot;
+ u8 pci_func;
+ u16 device_id;
+ bfa_addr_t pci_bar_kva;
+};
+
+/**
+ * Structure used to remember the DMA-able memory block's KVA and Physical
+ * Address
+ */
+struct bfa_dma {
+ void *kva; /* ! Kernel virtual address */
+ u64 pa; /* ! Physical address */
+};
+
+#define BFA_DMA_ALIGN_SZ 256
+#define BFA_ROUNDUP(_l, _s) (((_l) + ((_s) - 1)) & ~((_s) - 1))
+
+
+
+#define bfa_dma_addr_set(dma_addr, pa) \
+ __bfa_dma_addr_set(&dma_addr, (u64)pa)
+
+static inline void
+__bfa_dma_addr_set(union bfi_addr_u *dma_addr, u64 pa)
+{
+ dma_addr->a32.addr_lo = (u32) pa;
+ dma_addr->a32.addr_hi = (u32) (bfa_u32(pa));
+}
+
+
+#define bfa_dma_be_addr_set(dma_addr, pa) \
+ __bfa_dma_be_addr_set(&dma_addr, (u64)pa)
+static inline void
+__bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
+{
+ dma_addr->a32.addr_lo = (u32) htonl(pa);
+ dma_addr->a32.addr_hi = (u32) htonl(bfa_u32(pa));
+}
+
+struct bfa_ioc_regs {
+ bfa_addr_t hfn_mbox_cmd;
+ bfa_addr_t hfn_mbox;
+ bfa_addr_t lpu_mbox_cmd;
+ bfa_addr_t lpu_mbox;
+ bfa_addr_t pss_ctl_reg;
+ bfa_addr_t pss_err_status_reg;
+ bfa_addr_t app_pll_fast_ctl_reg;
+ bfa_addr_t app_pll_slow_ctl_reg;
+ bfa_addr_t ioc_sem_reg;
+ bfa_addr_t ioc_usage_sem_reg;
+ bfa_addr_t ioc_init_sem_reg;
+ bfa_addr_t ioc_usage_reg;
+ bfa_addr_t host_page_num_fn;
+ bfa_addr_t heartbeat;
+ bfa_addr_t ioc_fwstate;
+ bfa_addr_t ll_halt;
+ bfa_addr_t err_set;
+ bfa_addr_t shirq_isr_next;
+ bfa_addr_t shirq_msk_next;
+ bfa_addr_t smem_page_start;
+ u32 smem_pg0;
+};
+
+/**
+ * IOC Mailbox structures
+ */
+struct bfa_mbox_cmd {
+ struct list_head qe;
+ u32 msg[BFI_IOC_MSGSZ];
+};
+
+/**
+ * IOC mailbox module
+ */
+typedef void (*bfa_ioc_mbox_mcfunc_t)(void *cbarg, struct bfi_mbmsg *m);
+struct bfa_ioc_mbox_mod {
+ struct list_head cmd_q; /* pending mbox queue */
+ int nmclass; /* number of handlers */
+ struct {
+ bfa_ioc_mbox_mcfunc_t cbfn; /* message handlers */
+ void *cbarg;
+ } mbhdlr[BFI_MC_MAX];
+};
+
+/**
+ * IOC callback function interfaces
+ */
+typedef void (*bfa_ioc_enable_cbfn_t)(void *bfa, enum bfa_status status);
+typedef void (*bfa_ioc_disable_cbfn_t)(void *bfa);
+typedef void (*bfa_ioc_hbfail_cbfn_t)(void *bfa);
+typedef void (*bfa_ioc_reset_cbfn_t)(void *bfa);
+struct bfa_ioc_cbfn {
+ bfa_ioc_enable_cbfn_t enable_cbfn;
+ bfa_ioc_disable_cbfn_t disable_cbfn;
+ bfa_ioc_hbfail_cbfn_t hbfail_cbfn;
+ bfa_ioc_reset_cbfn_t reset_cbfn;
+};
+
+/**
+ * Heartbeat failure notification queue element.
+ */
+struct bfa_ioc_hbfail_notify {
+ struct list_head qe;
+ bfa_ioc_hbfail_cbfn_t cbfn;
+ void *cbarg;
+};
+
+/**
+ * Initialize a heartbeat failure notification structure
+ */
+#define bfa_ioc_hbfail_init(__notify, __cbfn, __cbarg) do { \
+ (__notify)->cbfn = (__cbfn); \
+ (__notify)->cbarg = (__cbarg); \
+} while (0)
+
+struct bfa_ioc {
+ bfa_fsm_t fsm;
+ struct bfa *bfa;
+ struct bfa_pcidev pcidev;
+ struct bfa_timer_mod *timer_mod;
+ struct bfa_timer ioc_timer;
+ struct bfa_timer sem_timer;
+ u32 hb_count;
+ u32 retry_count;
+ struct list_head hb_notify_q;
+ void *dbg_fwsave;
+ int dbg_fwsave_len;
+ bool dbg_fwsave_once;
+ enum bfi_mclass ioc_mc;
+ struct bfa_ioc_regs ioc_regs;
+ struct bfa_trc_mod *trcmod;
+ struct bfa_aen *aen;
+ struct bfa_log_mod *logm;
+ struct bfa_ioc_drv_stats stats;
+ bool auto_recover;
+ bool fcmode;
+ bool ctdev;
+ bool cna;
+ bool pllinit;
+ u8 port_id;
+
+ struct bfa_dma attr_dma;
+ struct bfi_ioc_attr *attr;
+ struct bfa_ioc_cbfn *cbfn;
+ struct bfa_ioc_mbox_mod mbox_mod;
+ struct bfa_ioc_hwif *ioc_hwif;
+};
+
+struct bfa_ioc_hwif {
+ bfa_status_t (*ioc_pll_init) (struct bfa_ioc *ioc);
+ bool (*ioc_firmware_lock) (struct bfa_ioc *ioc);
+ void (*ioc_firmware_unlock) (struct bfa_ioc *ioc);
+ u32 * (*ioc_fwimg_get_chunk) (struct bfa_ioc *ioc,
+ u32 off);
+ u32 (*ioc_fwimg_get_size) (struct bfa_ioc *ioc);
+ void (*ioc_reg_init) (struct bfa_ioc *ioc);
+ void (*ioc_map_port) (struct bfa_ioc *ioc);
+ void (*ioc_isr_mode_set) (struct bfa_ioc *ioc,
+ bool msix);
+ void (*ioc_notify_hbfail) (struct bfa_ioc *ioc);
+ void (*ioc_ownership_reset) (struct bfa_ioc *ioc);
+};
+
+#define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func)
+#define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id)
+#define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva)
+#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
+#define bfa_ioc_fetch_stats(__ioc, __stats) \
+ (((__stats)->drv_stats) = (__ioc)->stats)
+#define bfa_ioc_clr_stats(__ioc) \
+ memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
+#define bfa_ioc_maxfrsize(__ioc) ((__ioc)->attr->maxfrsize)
+#define bfa_ioc_rx_bbcredit(__ioc) ((__ioc)->attr->rx_bbcredit)
+#define bfa_ioc_speed_sup(__ioc) \
+ BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
+#define bfa_ioc_get_nports(__ioc) \
+ BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)
+
+#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
+#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
+
+#define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS)
+#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS)
+#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
+
+/**
+ * IOC mailbox interface
+ */
+void bfa_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd);
+void bfa_ioc_mbox_register(struct bfa_ioc *ioc,
+ bfa_ioc_mbox_mcfunc_t *mcfuncs);
+void bfa_ioc_mbox_isr(struct bfa_ioc *ioc);
+void bfa_ioc_mbox_send(struct bfa_ioc *ioc, void *ioc_msg, int len);
+void bfa_ioc_msgget(struct bfa_ioc *ioc, void *mbmsg);
+void bfa_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
+ bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
+
+/**
+ * IOC interfaces
+ */
+
+#define bfa_ioc_pll_init(__ioc) ((__ioc)->ioc_hwif->ioc_pll_init(__ioc))
+#define bfa_ioc_isr_mode_set(__ioc, __msix) \
+ ((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix))
+#define bfa_ioc_ownership_reset(__ioc) \
+ ((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
+
+
+void bfa_ioc_set_ct_hwif(struct bfa_ioc *ioc);
+void bfa_ioc_set_cb_hwif(struct bfa_ioc *ioc);
+
+void bfa_ioc_attach(struct bfa_ioc *ioc, void *bfa,
+ struct bfa_ioc_cbfn *cbfn, struct bfa_timer_mod *timer_mod,
+ struct bfa_trc_mod *trcmod,
+ struct bfa_aen *aen, struct bfa_log_mod *logm);
+void bfa_ioc_detach(struct bfa_ioc *ioc);
+void bfa_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
+ enum bfi_mclass mc);
+u32 bfa_ioc_meminfo(void);
+void bfa_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa);
+void bfa_ioc_enable(struct bfa_ioc *ioc);
+void bfa_ioc_disable(struct bfa_ioc *ioc);
+bool bfa_ioc_intx_claim(struct bfa_ioc *ioc);
+
+void bfa_ioc_boot(struct bfa_ioc *ioc, u32 boot_type,
+ u32 boot_param);
+void bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *msg);
+void bfa_ioc_error_isr(struct bfa_ioc *ioc);
+bool bfa_ioc_is_operational(struct bfa_ioc *ioc);
+bool bfa_ioc_is_disabled(struct bfa_ioc *ioc);
+bool bfa_ioc_fw_mismatch(struct bfa_ioc *ioc);
+bool bfa_ioc_adapter_is_disabled(struct bfa_ioc *ioc);
+void bfa_ioc_cfg_complete(struct bfa_ioc *ioc);
+enum bfa_ioc_type_e bfa_ioc_get_type(struct bfa_ioc *ioc);
+void bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, char *serial_num);
+void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc, char *fw_ver);
+void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc, char *optrom_ver);
+void bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model);
+void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc,
+ char *manufacturer);
+void bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc, char *chip_rev);
+enum bfa_ioc_state bfa_ioc_get_state(struct bfa_ioc *ioc);
+
+void bfa_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr);
+void bfa_ioc_get_adapter_attr(struct bfa_ioc *ioc,
+ struct bfa_adapter_attr *ad_attr);
+int bfa_ioc_debug_trcsz(bool auto_recover);
+void bfa_ioc_debug_memclaim(struct bfa_ioc *ioc, void *dbg_fwsave);
+bfa_status_t bfa_ioc_debug_fwsave(struct bfa_ioc *ioc, void *trcdata,
+ int *trclen);
+void bfa_ioc_debug_fwsave_clear(struct bfa_ioc *ioc);
+bfa_status_t bfa_ioc_debug_fwtrc(struct bfa_ioc *ioc, void *trcdata,
+ int *trclen);
+u32 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr);
+u32 bfa_ioc_smem_pgoff(struct bfa_ioc *ioc, u32 fmaddr);
+void bfa_ioc_set_fcmode(struct bfa_ioc *ioc);
+bool bfa_ioc_get_fcmode(struct bfa_ioc *ioc);
+void bfa_ioc_hbfail_register(struct bfa_ioc *ioc,
+ struct bfa_ioc_hbfail_notify *notify);
+bool bfa_ioc_sem_get(bfa_addr_t sem_reg);
+void bfa_ioc_sem_release(bfa_addr_t sem_reg);
+void bfa_ioc_hw_sem_release(struct bfa_ioc *ioc);
+void bfa_ioc_fwver_get(struct bfa_ioc *ioc,
+ struct bfi_ioc_image_hdr *fwhdr);
+bool bfa_ioc_fwver_cmp(struct bfa_ioc *ioc,
+ struct bfi_ioc_image_hdr *fwhdr);
+
+/*
+ * bfa mfg wwn API functions
+ */
+wwn_t bfa_ioc_get_pwwn(struct bfa_ioc *ioc);
+wwn_t bfa_ioc_get_nwwn(struct bfa_ioc *ioc);
+wwn_t bfa_ioc_get_wwn_naa5(struct bfa_ioc *ioc, u16 inst);
+struct mac bfa_ioc_get_mac(struct bfa_ioc *ioc);
+u64 bfa_ioc_get_adid(struct bfa_ioc *ioc);
+
+#endif /* __BFA_IOC_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_timer.h net-next-2.6-mod/drivers/net/bna/bfa_timer.h
--- net-next-2.6-orig/drivers/net/bna/bfa_timer.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_timer.h 2009-11-12 19:03:38.919338000 -0800
@@ -0,0 +1,56 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+#ifndef __BFA_TIMER_H__
+#define __BFA_TIMER_H__
+
+#include <cna.h>
+#include <cs/bfa_q.h>
+
+struct bfa;
+
+typedef void (*bfa_timer_cbfn_t)(void *);
+
+/**
+ * BFA timer data structure
+ */
+struct bfa_timer {
+ struct list_head qe;
+ bfa_timer_cbfn_t timercb;
+ void *arg;
+ int timeout; /**< in millisecs. */
+};
+
+/**
+ * Timer module structure
+ */
+struct bfa_timer_mod {
+ struct list_head timer_q;
+};
+
+#define BFA_TIMER_FREQ 200 /**< specified in millisecs */
+
+void bfa_timer_beat(struct bfa_timer_mod *mod);
+void bfa_timer_init(struct bfa_timer_mod *mod);
+void bfa_timer_begin(struct bfa_timer_mod *mod, struct bfa_timer *timer,
+ bfa_timer_cbfn_t timercb, void *arg,
+ unsigned int timeout);
+void bfa_timer_stop(struct bfa_timer *timer);
+
+#endif /* __BFA_TIMER_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/bna.h net-next-2.6-mod/drivers/net/bna/bna.h
--- net-next-2.6-orig/drivers/net/bna/bna.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bna.h 2009-11-12 19:03:38.928337000 -0800
@@ -0,0 +1,2392 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * @file bna.h
+ * BNA Exported Definitions & Prototypes
+ */
+
+#ifndef __BNA_H__
+#define __BNA_H__
+
+#include <bfa_timer.h>
+#include <bfa_ioc.h>
+#include <cna.h>
+#include <cna.h>
+#include <cna/pstats/phyport_defs.h>
+#include <cna/pstats/ethport_defs.h>
+#include <cee/bfa_cee.h>
+
+#define BNA_VLAN_ID_MAX 4095
+
+#define BNA_TXQ_ID_MAX 64
+#define BNA_RXQ_ID_MAX 64
+#define BNA_CQ_ID_MAX 64
+
+#define BNA_IB_ID_MAX 128
+#define BNA_RIT_SIZE 256
+#define BNA_RIT_ID_MAX 64
+
+#define BNA_UCAST_TABLE_SIZE 256
+#define BNA_MCAST_TABLE_SIZE 256
+
+#define BNA_HW_STATS_SIZE 16384
+#define BNA_DEFAULT_RXF_ID 0
+#define BNA_DEFAULT_TXF_ID 0
+
+#define BNA_RXF_ID_NONE 255
+
+#define BNA_MESSAGE_SIZE 256
+
+
+struct bna_dma_addr {
+ u32 msb;
+ u32 lsb;
+};
+
+struct bna_dma_addr_le {
+ u32 le_lsb;
+ u32 le_msb;
+};
+
+#define BNA_MIN(x, y) (((x) < (y)) ? (x) : (y))
+
+#define BNA_MAC_IS_MULTICAST(_mac_ms_octet) \
+ ((_mac_ms_octet) & 0x01)
+#define BNA_MAC_IS_UNICAST(_mac_ms_octet) \
+ (!BNA_MAC_IS_MULTICAST((_mac_ms_octet)))
+
+extern const struct mac bna_bcast_addr;
+extern const struct mac bna_zero_addr;
+
+#define BNA_MAC_IS_EQUAL(_mac1, _mac2) \
+ (!memcmp((_mac1), (_mac2), sizeof(struct mac)))
+
+#define BNA_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
+#define BNA_TO_POWER_OF_2(x) \
+do { \
+ int _shift = 0; \
+ while ((x) && (x) != 1) { \
+ (x) >>= 1; \
+ _shift++; \
+ } \
+ (x) <<= _shift; \
+} while (0)
+
+#define BNA_TO_POWER_OF_2_HIGH(x) \
+do { \
+ int n = 1; \
+ while (n < (x)) \
+ n <<= 1; \
+ (x) = n; \
+} while (0)
+
+/**
+ * BNA_SET_DMA_ADDR()
+ *
+ * Converts a dma address _addr from the host
+ * endian format to the bna_dma_addr_t format.
+ *
+ * @param[in] _addr - DMA'able address in host endian format
+ * @param[in] _bna_dma_addr - Pointer to bna_dma_addr_t where address
+ * - will be stored.
+ */
+#define BNA_SET_DMA_ADDR(_addr, _bna_dma_addr) \
+do { \
+ u64 tmp_addr = \
+ bna_dma_addr64((u64)(_addr)); \
+ (_bna_dma_addr)->msb = ((struct bna_dma_addr *)&tmp_addr)->msb; \
+ (_bna_dma_addr)->lsb = ((struct bna_dma_addr *)&tmp_addr)->lsb; \
+} while (0)
+
+/**
+ * BNA_GET_DMA_ADDR()
+ *
+ * Converts a dma address _addr from the host
+ * endian format to the bna_dma_addr_t format.
+ *
+ * @parma[in] _bna_dma_addr - Pointer to bna_dma_addr_t where address will
+ * be stored.
+ * @param[in] _addr - DMA'able address in host endian format
+ */
+#define BNA_GET_DMA_ADDR(_bna_dma_addr, _addr) \
+do { \
+ (_addr) = ((u64)(ntohl((_bna_dma_addr)->msb)) << 32)\
+ | ((ntohl((_bna_dma_addr)->lsb) & 0xffffffff)); \
+} while (0)
+
+/**
+ * BNA_ALIGN()
+ *
+ * Aligns a size to a given value
+ *
+ * @param[in] _x - Actual size to align
+ * @param[in] _a - Value to which size should be aligned
+ *
+ */
+#define BNA_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
+
+enum bna_enable_e { BNA_DISABLE = 0, BNA_ENABLE = 1 };
+
+enum bna_status_e {
+ BNA_OK = 0,
+ BNA_FAIL = 1,
+ BNA_DUPLICATE = 2,
+ BNA_BUSY = 3,
+ BNA_AGAIN = 4
+};
+
+enum bna_bool_e {
+ BNA_FALSE = 0,
+ BNA_TRUE = 1
+};
+
+#define BNA_LARGE_PKT_SIZE 1000
+/**
+ * This structure is for dynamic interrupt moderation
+ * Should be part of the driver private structure.
+ */
+struct bna_pkt_rate {
+ u32 small_pkt_cnt;
+ u32 large_pkt_cnt;
+};
+#define BNA_UPDATE_PKT_CNT(_pkt, _len) \
+do { \
+ if ((_len) > BNA_LARGE_PKT_SIZE) { \
+ (_pkt)->large_pkt_cnt++; \
+ } else { \
+ (_pkt)->small_pkt_cnt++; \
+ } \
+} while (0)
+
+/**
+ * BNA callback function prototype The driver registers this
+ * callback with BNA. This is called from the mailbox/error
+ * handler routine of BNA, for further driver processing.
+ *
+ * @param[in] cbarg - Opaque cookie used by the driver to identify the callback.
+ * @param[in] cmd_code - Command code for the callback
+ * @param[in] status - Status as returned by the f/w
+ *
+ * @return void
+ */
+
+typedef void (*bna_cbfn_t) (void *cbarg, u8 status);
+typedef void (*bna_diag_cbfn_t) (void *cbarg, void *data, u8 status);
+
+/**
+ * Structure of callbacks implemented by the driver
+ */
+struct bna_mbox_cbfn {
+ bna_cbfn_t ucast_set_cb;
+ bna_cbfn_t ucast_add_cb;
+ bna_cbfn_t ucast_del_cb;
+
+ bna_cbfn_t mcast_add_cb;
+ bna_cbfn_t mcast_del_cb;
+ bna_cbfn_t mcast_filter_cb;
+ bna_cbfn_t mcast_del_all_cb;
+
+ bna_cbfn_t set_promisc_cb;
+ bna_cbfn_t set_default_cb;
+
+ bna_cbfn_t txq_stop_cb;
+ bna_cbfn_t rxq_stop_cb;
+
+ bna_cbfn_t port_admin_cb;
+ bna_cbfn_t link_up_cb;
+ bna_cbfn_t link_down_cb;
+
+ bna_cbfn_t stats_get_cb;
+ bna_cbfn_t stats_clr_cb;
+
+ bna_cbfn_t hw_error_cb;
+
+ bna_cbfn_t lldp_get_cfg_cb;
+ bna_cbfn_t cee_get_stats_cb;
+
+ bna_cbfn_t set_diag_lb_cb; /* Diagnostics */
+
+ bna_cbfn_t set_pause_cb;
+
+ bna_cbfn_t mtu_info_cb;
+
+ bna_cbfn_t rxf_cb;
+};
+
+struct bna_chip_regs_offset {
+ u32 page_addr;
+ u32 fn_int_status;
+ u32 fn_int_mask;
+ u32 msix_idx;
+};
+/**
+ * Memory mapped addresses of often used chip registers
+ */
+struct bna_chip_regs {
+ u8 *page_addr;
+ u8 *fn_int_status;
+ u8 *fn_int_mask;
+};
+
+#define BNA_MAX_MBOX_CMD_QUEUE 256
+#define BNA_MAX_MBOX_CMD_LEN (BFI_IOC_MSGSZ * 4) /* 32 bytes */
+
+struct bna_mbox_cmd_qe {
+ struct bfa_mbox_cmd cmd;
+ u32 cmd_len; /* Length of the message in bytes */
+ void *cbarg; /* non-default callback argument */
+};
+
+struct bna_mbox_q {
+ u32 producer_index;
+ u32 consumer_index;
+ void *posted; /* Pointer to the posted element */
+ struct bna_mbox_cmd_qe mb_qe[BNA_MAX_MBOX_CMD_QUEUE];
+};
+
+/**
+ * BNA device structure
+ */
+struct bna_dev {
+ u8 *bar0;
+
+ u8 pci_fn;
+ u8 port;
+
+ u8 rxf_promiscuous_id;
+ u8 rxf_default_id;
+ u8 rit_size[BNA_RIT_ID_MAX];
+ u32 vlan_table[BNA_RXF_ID_MAX][(BNA_VLAN_ID_MAX + 1) / 32];
+ enum bna_enable_e vlan_filter_enable[BNA_RXF_ID_MAX];
+ u64 rxf_active;
+ u64 txf_active;
+ u64 rxf_active_last;
+ u64 txf_active_last;
+
+ struct bfi_ll_stats *hw_stats;
+ struct bna_dma_addr hw_stats_dma;
+
+ struct bna_stats stats;
+
+ struct mac mcast_addr[BNA_MCAST_TABLE_SIZE];
+
+ u32 rxa_arb_pri; /* RxA Arbitration Priority */
+
+ struct bna_chip_regs regs; /* Pointer to oft used registers */
+
+ struct bna_mbox_q mbox_q;
+ struct bna_mbox_cbfn mb_cbfns;
+ void *cbarg; /* Argument to callback function */
+ struct bfi_mbmsg mb_msg; /* Mailbox msg from f/w to host */
+
+ /* IOC integration */
+ struct bfa_ioc ioc;
+ struct bfa_timer_mod timer_mod;
+ struct bfa_trc_mod *trcmod;
+ u8 ioc_disable_pending;
+
+
+ u16 msg_ctr; /* Counter for mailbox messages posted */
+ struct bfa_cee *cee;
+ struct bfa_log_mod *logmod;
+};
+
+#define bna_get_handle_size() (sizeof(struct bna_dev))
+
+u8 bna_calc_coalescing_timer(struct bna_dev *dev,
+ struct bna_pkt_rate *pkt);
+
+/**
+ * bna_reg_read()
+ *
+ * Function to read the value of a register.
+ * Returns value in little-endian format.
+ *
+ * @param[in] _raddr - Absolute address of the register to read
+ *
+ * @return u32 - Value of the register read
+ */
+#define bna_reg_read(_raddr) readl(_raddr)
+
+/**
+ * bna_reg_write()
+ *
+ * Function to write the value to a register.
+ * Writes in little-endian format.
+ *
+ * @param[in] _raddr - Absolute address of the register to write.
+ * @param[in] _val - Value to be written.
+ *
+ * @return void
+ */
+#define bna_reg_write(_raddr, _val) writel(_val, _raddr)
+
+/**
+ * bna_mem_readw()
+ *
+ * Function to read the value of a memory location word by word.
+ * Returns value in big-endian format.
+ *
+ * @param[in] _raddr - Absolute address of the memory location to read.
+ *
+ * @return u32 - Value (word) of the memory location read.
+ */
+/* #define bna_mem_readw(_raddr) bna_os_mem_readw(_raddr) */
+#define bna_mem_readw(_raddr) readl(_raddr)
+
+/**
+ * bna_mem_writew()
+ *
+ * Function to write a value to a given memory location.
+ * Writes in big-endian format.
+ *
+ * @param[in] _raddr - Absolute address of the memory location to write.
+ * @param[in] _val - Value to be written.
+ *
+ * @return void
+ */
+/* #define bna_mem_writew(_raddr, _val) bna_os_mem_writew(_raddr, _val) */
+#define bna_mem_writew(_raddr, _val) writel(_val, _raddr)
+
+/**
+ * Holds DMA physical and virtual memory addresses
+ * and length. This is used for making IOC calls.
+ */
+struct bna_meminfo {
+ u8 *kva; /* Kernel virtual address */
+ u64 dma; /* Actual physical address */
+ u32 len; /* Memory size in bytes */
+};
+
+enum bna_dma_mem_type {
+ BNA_DMA_MEM_T_DIAG = 0,
+ BNA_DMA_MEM_T_FLASH = 1,
+ BNA_DMA_MEM_T_ATTR = 2,
+ BNA_KVA_MEM_T_FWTRC = 3,
+ BNA_MEM_T_MAX,
+};
+
+
+
+
+/**
+ * bna_register_callback()
+ *
+ * Function called by the driver to register a callback with
+ * the BNA
+ *
+ * @param[in] dev - Opaque handle to BNA private device.
+ * @param[in] cbfns - Structure of callbacks from drivers.
+ * @param[in] cbarg - Argument to use with the callback.
+ *
+ * @return BNA_OK or BNA_FAIL
+ */
+void bna_register_callback(struct bna_dev *dev, struct bna_mbox_cbfn *cbfns,
+ void *cbarg);
+
+/**
+ * Ethernet / Ethernet & VLAN header used by diag loopback
+ */
+struct bna_ether_hdr {
+ struct mac dst; /* destination mac address */
+ struct mac src; /* source mac address */
+ u16 proto; /* ethernet protocol */
+};
+
+struct bna_ether_vlan_hdr {
+ struct mac dst; /* destination mac address */
+ struct mac src; /* source mac address */
+ u16 vlan_proto; /* vlan ethernet protocol */
+ u16 vlan_tci; /* vlan tag/priority */
+ u16 proto; /* ethernet protocol */
+};
+
+/**
+ * Structure used to create loopback packet
+ */
+struct bna_lb_pkt_info {
+ u8 *buf; /* allocated by driver */
+ u32 buflen; /* buffer length */
+ u32 pattern; /* pattern to be filled in */
+ u32 vlan_tag; /* 0 for no tag */
+ struct mac mac; /* SA & DA to be used for lb pkt */
+};
+
+struct bna_diag_lb_pkt_stats {
+ u64 pkts_to_send;
+ u64 pkts_sent;
+ volatile u64 pkts_rcvd;
+ u64 tx_drops;
+ u64 rx_drops;
+};
+
+/**
+ * API called to create a loopback packet */
+enum bna_status_e bna_create_lb_pkt(void *dev, struct bna_lb_pkt_info *pktinfo);
+
+/**
+ * bna_diag_ll_loopback()
+ *
+ * Send mailbox message to enable / disable LL diag loopback mode
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] port - port on which loopback is enabled/disabled
+ * @param[in] enable - enable/disable diag loopback mode
+ *
+ * @return BNA_OK or BNA_FAIL
+ */
+enum bna_status_e bna_diag_ll_loopback(void *dev, u8 mode, u8 enable,
+ void *cbarg);
+
+
+
+/* Port Management */
+
+struct bna_port_stats {
+ u64 rx_frame_64;
+ u64 rx_frame_65_127;
+ u64 rx_frame_128_255;
+ u64 rx_frame_256_511;
+ u64 rx_frame_512_1023;
+ u64 rx_frame_1024_1518;
+ u64 rx_frame_1518_1522;
+ u64 rx_bytes;
+ u64 rx_packets;
+ u64 rx_fcs_error;
+ u64 rx_multicast;
+ u64 rx_broadcast;
+ u64 rx_control_frames;
+ u64 rx_pause;
+ u64 rx_unknown_opcode;
+ u64 rx_alignment_error;
+ u64 rx_frame_length_error;
+ u64 rx_code_error;
+ u64 rx_carrier_sense_error;
+ u64 rx_undersize;
+ u64 rx_oversize;
+ u64 rx_fragments;
+ u64 rx_jabber;
+ u64 rx_drop;
+
+ u64 tx_bytes;
+ u64 tx_packets;
+ u64 tx_multicast;
+ u64 tx_broadcast;
+ u64 tx_pause;
+ u64 tx_deferral;
+ u64 tx_excessive_deferral;
+ u64 tx_single_collision;
+ u64 tx_muliple_collision;
+ u64 tx_late_collision;
+ u64 tx_excessive_collision;
+ u64 tx_total_collision;
+ u64 tx_pause_honored;
+ u64 tx_drop;
+ u64 tx_jabber;
+ u64 tx_fcs_error;
+ u64 tx_control_frame;
+ u64 tx_oversize;
+ u64 tx_undersize;
+ u64 tx_fragments;
+};
+
+
+#define BNA_LINK_SPEED_10Gbps 10000
+struct bna_port_param {
+ u32 supported; /* Speeds and Flow Control supported */
+ u32 advertising; /* speeds and Flow-Control advertised */
+ u32 speed;
+ u32 duplex;
+ u32 autoneg;
+ u32 port;
+};
+
+/**
+ * bna_port_param_get()
+ *
+ * Get the port parameters.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[out] param_ptr - pointer to where the parameters will be
+ * returned.
+ * @return void
+ */
+void bna_port_param_get(struct bna_dev *dev,
+ struct bna_port_param *param_ptr);
+
+
+/**
+ * bna_port_mac_get()
+ *
+ * Get the Burnt-in or permanent MAC address. This function does not return
+ * the MAC set thru bna_rxf_ucast_mac_set() but the one that is assigned to
+ * the port upon reset.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[out] mac_ptr - Burnt-in or permanent MAC address.
+ *
+ * @return void
+ */
+void bna_port_mac_get(struct bna_dev *dev, struct mac *mac_ptr);
+
+
+/**
+ * bna_port_admin()
+ *
+ * Enable (up) or disable (down) the interface administratively.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] enable - enable/disable the interface.
+ *
+ * @return void
+ */
+enum bna_status_e bna_port_admin(struct bna_dev *dev,
+ enum bna_enable_e enable);
+
+
+/**
+ * bna_port_stats_get()
+ *
+ * Get the port statistics.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[out] stats_ptr - pointer to where the statistics will be returned.
+ *
+ * @return void
+ */
+void bna_port_stats_get(void *dev, struct bna_port_stats *stats_ptr);
+
+/**
+ * Ethernet 802.3X PAUSE confiiguration
+ */
+struct bna_pause_config {
+ u8 tx_pause;
+ u8 rx_pause;
+};
+
+/**
+ * bna_set_pause_config()
+ *
+ * Enable/disable Tx/Rx pause through F/W
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] pause - pointer to struct bna_pause_config
+ * @param[in] cbarg - argument for the callback function
+ *
+ * @return BNA_OK in case of success BNA_FAIL otherwise.
+ */
+enum bna_status_e bna_set_pause_config(struct bna_dev *dev,
+ struct bna_pause_config *pause, void *cbarg);
+
+/**
+ * bna_mtu_info()
+ *
+ * Send MTU information to F/W.
+ * This is required to do PAUSE efficiently.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] mtu - current mtu size
+ * @param[in] cbarg - argument for the callback function
+ *
+ * @return BNA_OK in case of success BNA_FAIL otherwise.
+ */
+enum bna_status_e bna_mtu_info(struct bna_dev *dev,
+ u16 mtu, void *cbarg);
+
+/*
+ *
+ *
+ * D O O R B E L L D E F I N E S
+ *
+ *
+ */
+
+/**
+ * These macros build the data portion of the TxQ/RxQ doorbell.
+ */
+#define BNA_DOORBELL_Q_PRD_IDX(_producer_index) (0x80000000 | (_producer_index))
+#define BNA_DOORBELL_Q_STOP (0x40000000)
+
+/* These macros build the data portion of the IB doorbell. */
+#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \
+ (0x80000000 | ((_timeout) << 16) | (_events))
+#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
+
+
+/*
+ *
+ *
+ * I N T E R R U P T B L O C K D E F I N E S
+ *
+ *
+ */
+
+/* IB Structure */
+struct bna_ib {
+ void __iomem *doorbell_addr; /* PCI address for IB doorbell */
+ u32 doorbell_ack; /* ack data format except for */
+ /* of events */
+};
+
+
+/* IB Control Flags in IB Configuration */
+typedef u8 bna_ib_cf_t;
+
+#define BNA_IB_CF_RESERVED1 (1 << 7)
+#define BNA_IB_CF_ACK_PENDING (1 << 6) /* Read Only */
+#define BNA_IB_CF_INTER_PKT_DMA (1 << 5) /* DMA segment w/o */
+ /* issuing interrupt */
+#define BNA_IB_CF_INT_ENABLE (1 << 4) /* Interrupt enable */
+#define BNA_IB_CF_INTER_PKT_ENABLE (1 << 3) /* Inter Packet */
+ /* Mechanism enable */
+#define BNA_IB_CF_COALESCING_MODE (1 << 2) /* 1 = Continuous; */
+ /* 0 = One-shot */
+#define BNA_IB_CF_MSIX_MODE (1 << 1) /* 1 = MSIX mode; */
+ /* 0 = INTx mode */
+#define BNA_IB_CF_MASTER_ENABLE (1 << 0) /* Master Enable */
+
+
+/* IB Configuration Structure */
+struct bna_ib_config {
+ struct bna_dma_addr ib_seg_addr; /* Host Address of IB Segment */
+ u8 coalescing_timer;
+ bna_ib_cf_t control_flags;
+ u8 msix_vector;
+ u8 interpkt_count;
+ u8 interpkt_timer;
+ u8 seg_size; /* No. of entries */
+ u8 index_table_offset;
+};
+
+
+/*
+ * bna_ib_idx_reset()
+ *
+ * For the specified IB, it clears the IB index
+ *
+ * @param[in] cfg_ptr - pointer to IB Configuration Structure.
+ *
+ * @return none
+ */
+void
+bna_ib_idx_reset(struct bna_dev *dev, const struct bna_ib_config *cfg_ptr);
+
+/**
+ * bna_ib_config_set()
+ *
+ * For IB "ib_id", it configures the Interrupt Block specified by "cfg_ptr".
+ *
+ * @param[in] ib_ptr - pointer to IB Data Structure.
+ * @param[in] ib_id - interrupt-block ID
+ * @param[in] cfg_ptr - pointer to IB Configuration Structure.
+ *
+ * @return None
+ */
+void bna_ib_config_set(struct bna_dev *bna_dev, struct bna_ib *ib_ptr,
+ unsigned int ib_id, const struct bna_ib_config *cfg_ptr);
+
+
+/**
+ * bna_ib_ack()
+ *
+ * Acknowledges the number of events triggered by the current interrupt.
+ *
+ * @param[in] bna_dev - Opaque handle to bna device.
+ * @param[in] ib_ptr - pointer to IB Data Structure.
+ * @param[in] events - number of events to acknowledge.
+ *
+ * @return None
+ */
+static inline void bna_ib_ack(struct bna_dev *bna_dev,
+ const struct bna_ib *ib_ptr, u16 events)
+{
+ /*
+ * bna_reg_write is defined in a header
+ * included later
+ */
+ bna_reg_write(ib_ptr->doorbell_addr,
+ (ib_ptr->doorbell_ack | events));
+}
+
+
+/**
+ * bna_ib_coalescing_timer_set()
+ *
+ * Sets the timeout value in the coalescing timer
+ *
+ * @param[in] ib_ptr - pointer to IB Data Structure.
+ * @param[in] timeout - coalescing timer value.
+ *
+ * @return None
+ */
+static inline void
+bna_ib_coalescing_timer_set(struct bna_dev *dev, struct bna_ib *ib_ptr,
+ u8 cls_timer)
+{
+ ib_ptr->doorbell_ack = BNA_DOORBELL_IB_INT_ACK(cls_timer, 0);
+}
+
+
+
+/**
+ * bna_ib_disable()
+ *
+ * Disables the Interrupt Block "ib_id".
+ *
+ * @param[in] bna_dev - pointer to BNA private handle.
+ * @param[in] ib_ptr - pointer to IB Data Structure.
+ *
+ * @return None
+ */
+void bna_ib_disable(struct bna_dev *bna_dev, const struct bna_ib *ib_ptr);
+
+
+/**
+ * Interrupt status register, mailbox status bits
+ */
+#define __LPU02HOST_MBOX0_STATUS_BITS 0x00100000
+#define __LPU12HOST_MBOX0_STATUS_BITS 0x00200000
+#define __LPU02HOST_MBOX1_STATUS_BITS 0x00400000
+#define __LPU12HOST_MBOX1_STATUS_BITS 0x00800000
+
+#define __LPU02HOST_MBOX0_MASK_BITS 0x00100000
+#define __LPU12HOST_MBOX0_MASK_BITS 0x00200000
+#define __LPU02HOST_MBOX1_MASK_BITS 0x00400000
+#define __LPU12HOST_MBOX1_MASK_BITS 0x00800000
+
+#define __LPU2HOST_MBOX_MASK_BITS \
+ (__LPU02HOST_MBOX0_MASK_BITS | __LPU02HOST_MBOX1_MASK_BITS | \
+ __LPU12HOST_MBOX0_MASK_BITS | __LPU12HOST_MBOX1_MASK_BITS)
+
+#define __LPU2HOST_IB_STATUS_BITS 0x0000ffff
+
+#define BNA_IS_LPU0_MBOX_INTR(_intr_status) \
+ ((_intr_status) & (__LPU02HOST_MBOX0_STATUS_BITS | \
+ __LPU02HOST_MBOX1_STATUS_BITS))
+
+#define BNA_IS_LPU1_MBOX_INTR(_intr_status) \
+ ((_intr_status) & (__LPU12HOST_MBOX0_STATUS_BITS | \
+ __LPU12HOST_MBOX1_STATUS_BITS))
+
+/**
+ * BNA_IS_MBOX_INTR()
+ *
+ * Checks if the mailbox interrupt status bits
+ * are set
+ *
+ * @param[in] _intr_status - Interrupt Status Register
+ */
+#define BNA_IS_MBOX_INTR(_intr_status) \
+ ((_intr_status) & \
+ (__LPU02HOST_MBOX0_STATUS_BITS | \
+ __LPU02HOST_MBOX1_STATUS_BITS | \
+ __LPU12HOST_MBOX0_STATUS_BITS | \
+ __LPU12HOST_MBOX1_STATUS_BITS))
+
+#define __EMC_ERROR_STATUS_BITS 0x00010000
+#define __LPU0_ERROR_STATUS_BITS 0x00020000
+#define __LPU1_ERROR_STATUS_BITS 0x00040000
+#define __PSS_ERROR_STATUS_BITS 0x00080000
+
+#define __HALT_STATUS_BITS 0x01000000
+
+#define __EMC_ERROR_MASK_BITS 0x00010000
+#define __LPU0_ERROR_MASK_BITS 0x00020000
+#define __LPU1_ERROR_MASK_BITS 0x00040000
+#define __PSS_ERROR_MASK_BITS 0x00080000
+
+#define __HALT_MASK_BITS 0x01000000
+
+#define __ERROR_MASK_BITS \
+ (__EMC_ERROR_MASK_BITS | __LPU0_ERROR_MASK_BITS | \
+ __LPU1_ERROR_MASK_BITS | __PSS_ERROR_MASK_BITS | \
+ __HALT_MASK_BITS)
+
+/**
+ * BNA_IS_ERR_INTR()
+ *
+ * Checks if the error interrupt status bits
+ * are set
+ *
+ * @param[in] _intr_status - Interrupt Status Register
+ */
+#define BNA_IS_ERR_INTR(_intr_status) \
+ ((_intr_status) & \
+ (__EMC_ERROR_STATUS_BITS | \
+ __LPU0_ERROR_STATUS_BITS | \
+ __LPU1_ERROR_STATUS_BITS | \
+ __PSS_ERROR_STATUS_BITS | \
+ __HALT_STATUS_BITS))
+
+/**
+ * BNA_IS_MBOX_ERR_INTR()
+ *
+ * Checks if the mailbox and error interrupt status bits
+ * are set
+ *
+ * @param[in] _intr_status - Interrupt Status Register
+ */
+#define BNA_IS_MBOX_ERR_INTR(_intr_status) \
+ (BNA_IS_MBOX_INTR((_intr_status)) | \
+ BNA_IS_ERR_INTR((_intr_status)))
+
+/**
+ * BNA_IS_INTX_DATA_INTR()
+ *
+ * Checks if the data bits (low 16 bits)
+ * are set in case of INTx
+ *
+ * @param[in] _intr_status - Interrupt Status Register
+ */
+#define BNA_IS_INTX_DATA_INTR(_intr_status) \
+ ((_intr_status) & __LPU2HOST_IB_STATUS_BITS)
+
+/**
+ * BNA_INTR_STATUS_MBOX_CLR()
+ *
+ * Clears the mailbox bits in _intr_status
+ * Does not write to hardware
+ *
+ * @param[in] _intr_status - Interrupt Status Register
+ */
+#define BNA_INTR_STATUS_MBOX_CLR(_intr_status) \
+do { \
+ (_intr_status) &= ~(__LPU02HOST_MBOX0_STATUS_BITS | \
+ __LPU02HOST_MBOX1_STATUS_BITS | \
+ __LPU12HOST_MBOX0_STATUS_BITS | \
+ __LPU12HOST_MBOX1_STATUS_BITS); \
+} while (0)
+
+/**
+ * BNA_INTR_STATUS_ERR_CLR()
+ *
+ * Clears the error bits in _intr_status
+ * Does not write to hardware
+ *
+ * @param[in] _intr_status - Interrupt Status Register
+ */
+#define BNA_INTR_STATUS_ERR_CLR(_intr_status) \
+do { \
+ (_intr_status) &= ~(__EMC_ERROR_STATUS_BITS | \
+ __LPU0_ERROR_STATUS_BITS | \
+ __LPU1_ERROR_STATUS_BITS | \
+ __PSS_ERROR_STATUS_BITS | \
+ __HALT_STATUS_BITS); \
+} while (0)
+
+
+/**
+ * bna_mbox_err_handler()
+ *
+ * The driver calls this API back after processing the
+ * mailbox/error interrupt for MSIX and INTx types.
+ * Should be called with a lock held.
+ * This will do the following for mbox interrupt :
+ * 1) Read the contents of the mbox
+ * 2) Call a function registered by the OS driver to handle
+ * the mailbox command.
+ * 3) Queue the next mbox command
+ * This will do the following for error interrupt :
+ * 1) Interpret the type of error & call the
+ * right BNA handler.
+ * 2) Call the driver defined callback.
+ *
+ * @param[in] bna_dev - Pointer to BNA private handle.
+ * @param[in] status - Interrupt status register.
+ *
+ * @return void
+ */
+void bna_mbox_err_handler(struct bna_dev *bna_dev, u32 status);
+
+/**
+ * bna_mbox_send()
+ *
+ * The driver calls this API to send a command to the
+ * firmware
+ *
+ * @param[in] bna_dev - Pointer to BNA private handle.
+ * @param[in] cmd - pointer to the command structur
+ * @param[in] cmd_len - length of the command structure
+ *
+ * @return BNA_OK or BNA_FAIL
+ */
+enum bna_status_e bna_mbox_send(struct bna_dev *bna_dev, void *cmd,
+ u32 cmd_len, void *cbarg);
+
+/*
+ *
+ *
+ * Q U E U E D E F I N E S
+ *
+ *
+ */
+#define BNA_TXQ_ENTRY_SIZE 64 /* bytes */
+#define BNA_RXQ_ENTRY_SIZE 8 /* bytes */
+#define BNA_CQ_ENTRY_SIZE 16 /* bytes */
+/**
+ * Queue Page Table (QPT)
+ */
+struct bna_qpt { /* Queue Page Table */
+ struct bna_dma_addr hw_qpt_ptr; /* Pointer to QPT used by HW */
+ void *kv_qpt_ptr; /* Kernel virtual pointer to */
+ /* hw QPT */
+ void **qpt_ptr; /* Pointer to S/W QPT for page */
+ /* segmented Q's */
+ u16 page_count; /* Size of QPT (i.e., number of */
+ /* pages) */
+ u16 page_size; /* Size of each page */
+};
+
+#define BNA_QPT_SIZE(_queue_size, _page_size) \
+ (((_queue_size) + (_page_size) - 1)/(_page_size))
+
+struct bna_q {
+ u16 producer_index;
+ u16 consumer_index;
+ u32 q_depth; /* Depth of the q */
+ void **qpt_ptr; /* pointer to SW QPT for Page-segmented */
+ /* queue */
+};
+
+
+/**
+ * BNA_TXQ_QPGE_PTR_GET()
+ *
+ * Gets the pointer corresponding to an queue-entry index for a
+ * page-segmented queue.
+ *
+ * NOTE: _q_depth, sizeof(_cast) and BNA_PAGE_SIZE must be power of two.
+ * _q_depth * sizeof(_cast) must be multiple of a BNA_PAGE_SIZE.
+ *
+ * @param[in] _qe_idx - producer/consumer queue entry index
+ * @param[in] _q_ptr - pointer to page-segmented queue structure
+ * @param[out] _qe_ptr - producer/consumer queue-entry pointer
+ * @param[out] _qe_ptr_range - number of entries addressable by
+ * queue-entry pointer (warns going beyond the
+ * page-size)
+ */
+
+/* TxQ element is 64 bytes */
+#define BNA_TXQ_PAGE_INDEX_MAX (BNA_PAGE_SIZE >> 6)
+#define BNA_TXQ_PAGE_INDEX_MAX_SHIFT (BNA_PAGE_SHIFT - 6)
+
+#define BNA_TXQ_QPGE_PTR_GET(_qe_idx, _q_ptr, _qe_ptr, _qe_ptr_range) \
+{ \
+ unsigned int page_index; /* index within a page */ \
+ void *page_addr; \
+ \
+ page_index = (_qe_idx) & (BNA_TXQ_PAGE_INDEX_MAX - 1); \
+ (_qe_ptr_range) = (BNA_TXQ_PAGE_INDEX_MAX - page_index); \
+ page_addr = (_q_ptr)->qpt_ptr[((_qe_idx) >> \
+ BNA_TXQ_PAGE_INDEX_MAX_SHIFT)]; \
+ (_qe_ptr) = &((struct bna_txq_entry *)(page_addr))[page_index]; \
+}
+
+/**
+ * BNA_RXQ_QPGE_PTR_GET()
+ *
+ * Gets the pointer corresponding to an queue-entry index for a
+ * page-segmented queue.
+ *
+ * NOTE: _q_depth, sizeof(_cast) and BNA_PAGE_SIZE must be power of two.
+ * _q_depth * sizeof(_cast) must be multiple of a BNA_PAGE_SIZE.
+ *
+ * @param[in] _qe_idx - producer/consumer queue entry index
+ * @param[in] _q_ptr - pointer to page-segmented queue structure
+ * @param[out] _qe_ptr - producer/consumer queue-entry pointer
+ * @param[out] _qe_ptr_range - number of entries addressable by
+ * queue-entry pointer (warns going beyond the
+ * page-size)
+ */
+/* RxQ element is 8 bytes */
+#define BNA_RXQ_PAGE_INDEX_MAX (BNA_PAGE_SIZE >> 3)
+#define BNA_RXQ_PAGE_INDEX_MAX_SHIFT (BNA_PAGE_SHIFT - 3)
+
+#define BNA_RXQ_QPGE_PTR_GET(_qe_idx, _q_ptr, _qe_ptr, _qe_ptr_range) \
+{ \
+ unsigned int page_index; /* index within a page */ \
+ void *page_addr; \
+ \
+ page_index = (_qe_idx) & (BNA_RXQ_PAGE_INDEX_MAX - 1); \
+ (_qe_ptr_range) = (BNA_RXQ_PAGE_INDEX_MAX - page_index); \
+ page_addr = (_q_ptr)->qpt_ptr[((_qe_idx) >> \
+ BNA_RXQ_PAGE_INDEX_MAX_SHIFT)]; \
+ (_qe_ptr) = &((struct bna_rxq_entry *)(page_addr))[page_index]; \
+}
+
+/**
+ * BNA_CQ_QPGE_PTR_GET()
+ *
+ * Gets the pointer corresponding to an queue-entry index for a
+ * page-segmented queue.
+ *
+ * NOTE: _q_depth, sizeof(_cast) and BNA_PAGE_SIZE must be power of two.
+ * _q_depth * sizeof(_cast) must be multiple of a BNA_PAGE_SIZE.
+ *
+ * @param[in] _qe_idx - producer/consumer queue entry index
+ * @param[in] _q_ptr - pointer to page-segmented queue structure
+ * @param[out] _qe_ptr - producer/consumer queue-entry pointer
+ * @param[out] _qe_ptr_range - number of entries addressable by
+ * queue-entry pointer (warns going beyond the
+ * page-size)
+ */
+
+/* CQ element is 16 bytes */
+#define BNA_CQ_PAGE_INDEX_MAX (BNA_PAGE_SIZE >> 4)
+#define BNA_CQ_PAGE_INDEX_MAX_SHIFT (BNA_PAGE_SHIFT - 4)
+
+#define BNA_CQ_QPGE_PTR_GET(_qe_idx, _q_ptr, _qe_ptr, _qe_ptr_range) \
+{ \
+ unsigned int page_index; /* index within a page */ \
+ void *page_addr; \
+ \
+ page_index = (_qe_idx) & (BNA_CQ_PAGE_INDEX_MAX - 1); \
+ (_qe_ptr_range) = (BNA_CQ_PAGE_INDEX_MAX - page_index); \
+ page_addr = (_q_ptr)->qpt_ptr[((_qe_idx) >> \
+ BNA_CQ_PAGE_INDEX_MAX_SHIFT)]; \
+ (_qe_ptr) = &((struct bna_cq_entry *)(page_addr))[page_index]; \
+}
+
+/**
+ * BNA_QE_INDX_2_PTR()
+ *
+ * Gets the pointer corresponding to an queue-entry index for a virtually-
+ * contiguous queue.
+ *
+ * NOTE: _q_depth must be power of two.
+ *
+ * @param[in] _cast - type cast of the entry.
+ * @param[in] _qe_idx - producer/consumer queue entry index
+ * @param[in] _q_base - queue base address
+ */
+#define BNA_QE_INDX_2_PTR(_cast, _qe_idx, _q_base) \
+ (&((_cast *)(_q_base))[(_qe_idx)])
+
+
+/**
+ * BNA_QE_INDX_RANGE()
+ *
+ * Returns number of entries that can be consecutively addressed for the
+ * specified queue. This function indicates when BNA_QE_INDX_2_PTR() must
+ * be called again get a new pointer due to the effect of wrapping around
+ * the queue.
+ *
+ * NOTE: _q_depth must be power of two.
+ *
+ * @param[in] _qe_idx - producer/consumer queue entry index
+ * @param[in] _q_depth - queue size in number of entries
+ */
+#define BNA_QE_INDX_RANGE(_qe_idx, _q_depth) \
+ ((_q_depth) - (_qe_idx))
+
+
+/**
+ * BNA_QE_INDX_ADD()
+ *
+ * Adds to a producer or consumer queue-entry index for either
+ * virtually-contiguous or page-segmented queue.
+ *
+ * NOTE: _q_depth must power of two.
+ *
+ * @param[in] _qe_idx - producer/consumer queue entry index
+ * @param[out] _qe_idx - updated producer/consumer queue entry index
+ * @param[in] _q_depth - queue size in number of entries
+ */
+#define BNA_QE_INDX_ADD(_qe_idx, _qe_num, _q_depth) \
+ ((_qe_idx) = ((_qe_idx) + (_qe_num)) & ((_q_depth) - 1))
+
+
+/**
+ * BNA_QE_FREE_CNT
+ *
+ * Returns the number of entries that can be added into the queue.
+ *
+ * NOTE: Must reserved one entry to distinguish between an empty
+ * and a full queue.
+ *
+ * @param[in] _q_ptr - pointer to queue structure
+ * @param[in] _q_depth - queue size in number of entries
+ */
+#define BNA_QE_FREE_CNT(_q_ptr, _q_depth) \
+ (((_q_ptr)->consumer_index - (_q_ptr)->producer_index - 1) & \
+ ((_q_depth) - 1))
+
+/**
+ * BNA_QE_IN_USE_CNT
+ *
+ * Returns the number of entries in the queue.
+ *
+ * @param[in] _q_ptr - pointer to queue structure
+ * @param[in] _q_depth - queue size in number of entries
+ */
+#define BNA_QE_IN_USE_CNT(_q_ptr, _q_depth) \
+ ((((_q_ptr)->producer_index - (_q_ptr)->consumer_index)) & \
+ (_q_depth - 1))
+
+
+/**
+ * BNA_Q_GET_CI
+ *
+ * Returns the current consumer index for that queue.
+ *
+ * @param[in] _q_ptr - pointer to queue (Tx/Rx/C) structure
+ */
+#define BNA_Q_GET_CI(_q_ptr) \
+ ((_q_ptr)->q.consumer_index)
+
+/**
+ * BNA_Q_GET_PI
+ *
+ * Returns the current producer index for that queue.
+ *
+ * @param[in] _q_ptr - pointer to queue (Tx/Rx/C) structure
+ */
+#define BNA_Q_GET_PI(_q_ptr) \
+ ((_q_ptr)->q.producer_index)
+
+/**
+ * BNA_Q_PI_ADD
+ *
+ * Increments the producer index of the queue by a certain number
+ *
+ * @param[in] _q_ptr - pointer to queue (Tx/Rx/C) structure
+ * @param[in] _num - the number by which CI needs to be incremented
+ */
+#define BNA_Q_PI_ADD(_q_ptr, _num) \
+ (_q_ptr)->q.producer_index = \
+ (((_q_ptr)->q.producer_index + (_num)) \
+ & ((_q_ptr)->q.q_depth - 1))
+
+/**
+ * BNA_Q_CI_ADD
+ *
+ * Increments the consumer index of the queue by a certain number
+ *
+ * @param[in] _q_ptr - pointer to queue (Tx/Rx/C) structure
+ * @param[in] _num - the number by which CI needs to be incremented
+ */
+#define BNA_Q_CI_ADD(_q_ptr, _num) \
+ (_q_ptr)->q.consumer_index = \
+ (((_q_ptr)->q.consumer_index + (_num)) \
+ & ((_q_ptr)->q.q_depth - 1))
+
+/**
+ * BNA_Q_FREE_COUNT()
+ *
+ * Returns the number of free entries for TxQ/RxQ/CQ
+ *
+ * @param[in] _q_ptr - pointer to TxQ/RxQ/CQ
+ */
+#define BNA_Q_FREE_COUNT(_q_ptr) \
+ (BNA_QE_FREE_CNT(&((_q_ptr)->q), (_q_ptr)->q.q_depth))
+
+/**
+ * BNA_Q_FREE_COUNT()
+ *
+ * Returns the number of entries in use for the queue.
+ *
+ * @param[in] _q_ptr - pointer to TxQ/RxQ/CQ
+ */
+#define BNA_Q_IN_USE_COUNT(_q_ptr) \
+ (BNA_QE_IN_USE_CNT(&(_q_ptr)->q, (_q_ptr)->q.q_depth))
+/*
+ *
+ *
+ * T X Q U E U E D E F I N E S
+ *
+ *
+ */
+/* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */
+struct bna_txq_wi_vector { /* Tx Buffer Descriptor */
+ u16 reserved;
+ u16 length; /* Only 14 LSB are valid */
+ struct bna_dma_addr host_addr; /* Tx-Buffer DMA address */
+};
+
+
+/* TxQ Entry Opcodes */
+#define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */
+#define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */
+#define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */
+typedef u16 bna_txq_wi_opcode_t;
+
+
+/* TxQ Entry Control Flags */
+#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8)
+#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5)
+#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4)
+#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3)
+#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2)
+#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1)
+#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0)
+typedef u16 bna_txq_wi_ctrl_flag_t;
+
+
+/**
+ * TxQ Entry Structure
+ *
+ * BEWARE: Load values into this structure with correct endianess.
+ */
+struct bna_txq_entry {
+ union {
+ struct {
+ u8 reserved;
+ u8 num_vectors; /* number of vectors present */
+ bna_txq_wi_opcode_t opcode; /* Either */
+ /* BNA_TXQ_WI_SEND or */
+ /* BNA_TXQ_WI_SEND_LSO */
+ bna_txq_wi_ctrl_flag_t flags; /* OR of all the flags */
+ u16 l4_hdr_size_n_offset;
+ u16 vlan_tag;
+ u16 lso_mss; /* Only 14 LSB are valid */
+ u32 frame_length; /* Only 24 LSB are valid */
+ } wi;
+
+ struct {
+ u16 reserved;
+ bna_txq_wi_opcode_t opcode; /* Must be */
+ /* BNA_TXQ_WI_EXTENSION */
+ u32 reserved2[3]; /* Place holder for */
+ /* removed vector (12 bytes) */
+ } wi_ext;
+ } hdr;
+ struct bna_txq_wi_vector vector[4];
+};
+#define wi_hdr hdr.wi
+#define wi_ext_hdr hdr.wi_ext
+
+#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
+ (((_hdr_size) << 10) | ((_offset) & 0x3FF))
+
+/* TxQ Structure */
+struct bna_txq {
+ u32 *doorbell;
+ struct bna_q q;
+};
+
+
+/* TxQ Configuration */
+struct bna_txq_config {
+ struct bna_qpt qpt;
+ u16 ib_id;
+ u8 ib_seg_index; /* index into IB segment */
+ u8 txf_id; /* Tx-Function ID */
+ u8 priority; /* frame or scheduling priority? FIXME */
+ u16 wrr_quota; /* Weighted Round-Robin Quota */
+};
+
+
+/**
+ * bna_txq_config()
+ *
+ * For TxQ "txq_id", it configures the Tx-Queue as specified by "cfg_ptr".
+ */
+void bna_txq_config(struct bna_dev *dev, struct bna_txq *q_ptr,
+ unsigned int txq_id, const struct bna_txq_config *cfg_ptr);
+
+
+
+/**
+ * bna_txq_pg_prod_ptr()
+ *
+ * Returns the producer pointer and its range for the specified page-segmented
+ * queue.
+ */
+static inline struct bna_txq_entry
+ *
+bna_txq_pg_prod_ptr(const struct bna_txq *q_ptr, unsigned int *ptr_range)
+{
+ struct bna_txq_entry *qe_ptr;
+
+ BNA_TXQ_QPGE_PTR_GET(q_ptr->q.producer_index, &q_ptr->q, qe_ptr,
+ *ptr_range);
+ return qe_ptr;
+}
+
+/**
+ * bna_txq_prod_indx_doorbell()
+ *
+ * Informs Catapult ASIC about queued entries.
+ */
+static inline void
+bna_txq_prod_indx_doorbell(const struct bna_txq *q_ptr)
+{
+ bna_reg_write(q_ptr->doorbell,
+ BNA_DOORBELL_Q_PRD_IDX(q_ptr->q.producer_index));
+}
+
+
+/**
+ * bna_txq_pg_cons_ptr()
+ *
+ * Returns the consumer pointer and its range for the specified
+ * page-segmented
+ * queue.
+ */
+static inline struct bna_txq_entry
+ *
+bna_txq_pg_cons_ptr(const struct bna_txq *q_ptr, unsigned int *ptr_range)
+{
+ struct bna_txq_entry *qe_ptr;
+
+ BNA_TXQ_QPGE_PTR_GET(q_ptr->q.consumer_index, &q_ptr->q, qe_ptr,
+ *ptr_range);
+ return qe_ptr;
+}
+
+/**
+ * bna_txq_stop()
+ *
+ * Stops the RxQ identified by the RxQ Id.
+ * Should be called with a lock held
+ * The driver should wait for the response to
+ * know if the Q stop is successful or not.
+ *
+ * @param[in] q_id - Id of the TxQ
+ *
+ * @return BNA_OK in case of success, else BNA_FAIL
+ */
+enum bna_status_e bna_txq_stop(struct bna_dev *bna_dev, u32 txq_id);
+
+/*
+ *
+ *
+ * R X Q U E U E D E F I N E S
+ *
+ *
+ */
+/* RxQ Entry (Rx-Vector, Rx-Buffer Address) */
+struct bna_rxq_entry { /* Rx-Buffer */
+ struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */
+};
+
+
+/* RxQ Structure */
+struct bna_rxq {
+ u32 *doorbell;
+ struct bna_q q;
+};
+
+
+/* RxQ Configuration */
+struct bna_rxq_config {
+ struct bna_qpt qpt;
+ u8 cq_id; /* Completion Queue ID */
+ u16 buffer_size; /* Rx-Buffer Length */
+};
+
+/**
+ * bna_rxq_config()
+ *
+ * For RxQ "rxq_id", it configures the Rx-Queue as specified by "cfg_ptr".
+ */
+void bna_rxq_config(struct bna_dev *dev, struct bna_rxq *q_ptr,
+ unsigned int rxq_id, const struct bna_rxq_config *cfg_ptr);
+
+/**
+ * bna_rxq_pg_prod_ptr()
+ *
+ * Returns the producer pointer and its range for the specified
+ * page-segmented
+ * queue.
+ */
+static inline struct bna_rxq_entry
+ *
+bna_rxq_pg_prod_ptr(const struct bna_rxq *q_ptr, unsigned int *ptr_range)
+{
+ struct bna_rxq_entry *qe_ptr;
+
+ BNA_RXQ_QPGE_PTR_GET(q_ptr->q.producer_index, &q_ptr->q, qe_ptr,
+ *ptr_range);
+ return qe_ptr;
+}
+
+/**
+ * bna_rxq_pg_cons_ptr()
+ *
+ * Returns the consumer pointer and its range for the specified
+ * page-segmented
+ * queue.
+ */
+static inline struct bna_rxq_entry
+ *
+bna_rxq_pg_cons_ptr(const struct bna_rxq *q_ptr, unsigned int *ptr_range)
+{
+ struct bna_rxq_entry *qe_ptr;
+
+ BNA_RXQ_QPGE_PTR_GET(q_ptr->q.consumer_index, &q_ptr->q, qe_ptr,
+ *ptr_range);
+ return qe_ptr;
+}
+
+/**
+ * bna_rxq_prod_indx_doorbell()
+ *
+ * Informs Catapult ASIC about queued entries.
+ */
+static inline void
+bna_rxq_prod_indx_doorbell(const struct bna_rxq *q_ptr)
+{
+ bna_reg_write(q_ptr->doorbell,
+ BNA_DOORBELL_Q_PRD_IDX(q_ptr->q.producer_index));
+}
+
+
+/**
+ * bna_rxq_stop()
+ *
+ * Stops the RxQ identified by the RxQ Id.
+ * Should be called with a lock held
+ * The driver should wait for the response to
+ * know if the Q stop is successful or not.
+ *
+ * @param[in] q_id - Id of the RxQ
+ *
+ * @return BNA_OK in case of success, else BNA_FAIL
+ */
+enum bna_status_e bna_rxq_stop(struct bna_dev *bna_dev, u32 rxq_id);
+
+/**
+ * bna_multi_rxq_stop()
+ *
+ * Stops the set of RxQs identified by rxq_id_mask
+ * Should be called with a lock held
+ * The driver should wait for the response to
+ * know if the Q stop is successful or not.
+ *
+ * @param[in] q_id - Id of the RxQ
+ *
+ * @return BNA_OK in case of success, else BNA_FAIL
+ */
+enum bna_status_e bna_multi_rxq_stop(struct bna_dev *dev,
+ u64 rxq_id_mask);
+/*
+ *
+ *
+ * R X C O M P L E T I O N Q U E U E D E F I N E S
+ *
+ *
+ */
+/* CQ Entry Flags */
+#define BNA_CQ_EF_MAC_ERROR (1 << 0)
+#define BNA_CQ_EF_FCS_ERROR (1 << 1)
+#define BNA_CQ_EF_TOO_LONG (1 << 2)
+#define BNA_CQ_EF_FC_CRC_OK (1 << 3)
+
+#define BNA_CQ_EF_RSVD1 (1 << 4)
+#define BNA_CQ_EF_L4_CKSUM_OK (1 << 5)
+#define BNA_CQ_EF_L3_CKSUM_OK (1 << 6)
+#define BNA_CQ_EF_HDS_HEADER (1 << 7)
+
+#define BNA_CQ_EF_UDP (1 << 8)
+#define BNA_CQ_EF_TCP (1 << 9)
+#define BNA_CQ_EF_IP_OPTIONS (1 << 10)
+#define BNA_CQ_EF_IPV6 (1 << 11)
+
+#define BNA_CQ_EF_IPV4 (1 << 12)
+#define BNA_CQ_EF_VLAN (1 << 13)
+#define BNA_CQ_EF_RSS (1 << 14)
+#define BNA_CQ_EF_RSVD2 (1 << 15)
+
+#define BNA_CQ_EF_MCAST_MATCH (1 << 16)
+#define BNA_CQ_EF_MCAST (1 << 17)
+#define BNA_CQ_EF_BCAST (1 << 18)
+#define BNA_CQ_EF_REMOTE (1 << 19)
+
+#define BNA_CQ_EF_LOCAL (1 << 20)
+typedef u32 bna_cq_e_flag_t;
+
+
+/* CQ Entry Structure */
+struct bna_cq_entry {
+ bna_cq_e_flag_t flags;
+ u16 vlan_tag;
+ u16 length;
+ u32 rss_hash;
+ u8 valid;
+ u8 reserved1;
+ u8 reserved2;
+ u8 rxq_id;
+};
+
+
+/* CQ Structure */
+struct bna_cq {
+ struct bna_q q;
+};
+
+
+/* CQ Configuration */
+struct bna_cq_config {
+ struct bna_qpt qpt;
+ u16 ib_id;
+ u8 ib_seg_index; /* index into IB segment */
+};
+
+/**
+ * bna_cq_config()
+ *
+ * For CQ "cq_id", it configures the Rx-Completion Queue as specified by
+ * "cfg_ptr".
+ */
+void bna_cq_config(struct bna_dev *dev, struct bna_cq *q_ptr,
+ unsigned int cq_id, const struct bna_cq_config *cfg_ptr);
+
+
+/**
+ * bna_cq_pg_prod_ptr()
+ *
+ * Returns the producer pointer and its range for the specified
+ * page-segmented
+ * queue.
+ */
+static inline struct bna_cq_entry
+ *
+bna_cq_pg_prod_ptr(const struct bna_cq *q_ptr, unsigned int *ptr_range)
+{
+ struct bna_cq_entry *qe_ptr;
+
+ BNA_CQ_QPGE_PTR_GET(q_ptr->q.producer_index, &q_ptr->q, qe_ptr,
+ *ptr_range);
+ return qe_ptr;
+}
+
+/**
+ * bna_cq_pg_cons_ptr()
+ *
+ * Returns the consumer pointer and its range for the specified
+ * page-segmented
+ * queue.
+ */
+static inline struct bna_cq_entry
+ *
+bna_cq_pg_cons_ptr(const struct bna_cq *q_ptr, unsigned int *ptr_range)
+{
+ struct bna_cq_entry *qe_ptr;
+
+ BNA_CQ_QPGE_PTR_GET(q_ptr->q.consumer_index, &q_ptr->q, qe_ptr,
+ *ptr_range);
+ return qe_ptr;
+}
+
+/*
+ *
+ *
+ * T X F U N C T I O N D E F I N E S
+ *
+ *
+ */
+
+/**
+ * TxF Control Flags
+ *
+ * BNA_TXF_CF_VLAN_INSERT & BNA_TXF_CF_VLAN_ADMIT are only applicable when
+ * BNA_TXF_CF_VLAN_WI_BASED == 0 (i.e., VLAN MODE = By Tx-Function).
+ */
+#define BNA_TXF_CF_VSWITCH_UCAST (1 << 15)
+#define BNA_TXF_CF_VSWITCH_MCAST (1 << 14)
+#define BNA_TXF_CF_VLAN_WI_BASED (1 << 13) /* else Tx-Function Based */
+#define BNA_TXF_CF_MAC_SA_CHECK (1 << 12)
+#define BNA_TXF_CF_RSVD1 (1 << 11)
+#define BNA_TXF_CF_VLAN_INSERT (1 << 10) /* Insert fn's VLAN ID */
+#define BNA_TXF_CF_VLAN_ADMIT (1 << 9) /* process VLAN frames */
+ /* from Host */
+#define BNA_TXF_CF_VLAN_FILTER (1 << 8) /* check against Rx */
+ /* VLAN Table */
+#define BNA_TXF_CF_RSVD2 (0x7F << 1)
+#define BNA_TXF_CF_ENABLE (1 << 0)
+typedef u16 bna_txf_ctrl_flag_t;
+
+
+/* TxF Configuration */
+struct bna_txf_config {
+ bna_txf_ctrl_flag_t flags; /* OR of bna_txf_ctrl_flag_t */
+ u16 vlan; /* valid when BNA_TXF_CF_VLAN_WI_BASED == 0 */
+ u8 rxf_id; /* validate BNA_TXF_CF_VSWITCH_UCAST */
+};
+
+/**
+ * bna_txf_config_set()
+ *
+ * For TxF "txf_id", it configures the TxF specified by "cfg_ptr" and
+ * indicates to the statistics collector to collect statistics for this
+ * Tx-Function.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] txf_id - tx-function ID.
+ * @param[in] cfg_ptr - pointer to tx-function configuration.
+ *
+ * @return void
+ */
+void bna_txf_config_set(struct bna_dev *dev, unsigned int txf_id,
+ const struct bna_txf_config *cfg_ptr);
+
+
+/**
+ * bna_txf_config_clear()
+ *
+ * For TxF "txf_id", it clears its configuration and indicates to the
+ * statistics collector to stop collecting statistics for this
+ * Tx-Function.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] txf_id - tx-function ID.
+ *
+ * @return void
+ */
+void bna_txf_config_clear(struct bna_dev *dev, unsigned int txf_id);
+
+
+
+/**
+ * bna_txf_disable()
+ *
+ * Disables the Tx Function without clearing the configuration
+ * Also disables collection of statistics.
+ *
+ * @param[in] bna_dev - Pointer to BNA BNA device handle
+ * @param[in] txf_id - Id of the Tx Function to be disabled
+ *
+ * @return void
+ */
+void bna_txf_disable(struct bna_dev *bna_dev, unsigned int txf_id);
+
+/**
+ * bna_txf_enable()
+ *
+ * Enables the Tx Function
+ *
+ * @param[in] bna_dev - Pointer to BNA BNA device handle
+ * @param[in] txf_id - Id of the Tx Function to be disabled
+ *
+ * @return void
+ */
+void bna_txf_enable(struct bna_dev *bna_dev, unsigned int txf_id);
+
+/*
+ *
+ *
+ * R X I N D I R E C T I O N T A B L E D E F I N E S
+ *
+ *
+ */
+/**
+ * Receive-Function RIT (Receive Indirection Table)
+ *
+ * RIT is required by RSS. However, in Catapult-LL, RIT must still be
+ * present for non-RSS. For non-RSS it just defines the unicast RxQs
+ * associated to a function.
+ *
+ * Each entry in the RIT holds two RxQs which are either Small and Large
+ * Buffer RxQs or Header and Data Buffer RxQs. "large_rxq_id" is used when
+ * neither Small/Large or Header-Data Split is configured.
+ */
+struct bna_rit_entry {
+ u8 large_rxq_id; /* used for either large or data buffers */
+ u8 small_rxq_id; /* used for either small or header buffers */
+};
+
+
+/**
+ * bna_rit_config_set()
+ *
+ * Loads RIT entries "rit" into RIT starting from RIT index "rit_offset".
+ * Care must be taken not to overlap regions within the RIT.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rit_offset - receive-indirection-table index.
+ * @param[in] rit[] - receive-indirection-table segment.
+ * @param[in] rit_size - size of receive-indirection-table segment.
+ *
+ * @return void
+ */
+void bna_rit_config_set(struct bna_dev *dev, unsigned int rit_offset,
+ const struct bna_rit_entry rit[],
+ unsigned int rit_size);
+
+
+/*
+ *******************************************************************************
+ *
+ * R X F U N C T I O N D E F I N E S
+ *
+ *******************************************************************************
+ */
+
+/* RxF RSS (Receive Side Scaling) */
+#define BNA_RSS_V4_TCP (1 << 11)
+#define BNA_RSS_V4_IP (1 << 10)
+#define BNA_RSS_V6_TCP (1 << 9)
+#define BNA_RSS_V6_IP (1 << 8)
+typedef u16 bna_rxf_rss_type_t;
+
+#define BNA_RSS_HASH_KEY_LEN 10 /* in words */
+
+struct bna_rxf_rss {
+ bna_rxf_rss_type_t type;
+ u8 hash_mask;
+ u32 toeplitz_hash_key[BNA_RSS_HASH_KEY_LEN];
+};
+
+
+/* RxF HDS (Header Data Split) */
+#define BNA_HDS_V4_TCP (1 << 11)
+#define BNA_HDS_V4_UDP (1 << 10)
+#define BNA_HDS_V6_TCP (1 << 9)
+#define BNA_HDS_V6_UDP (1 << 8)
+#define BNA_HDS_FORCED (1 << 7)
+typedef u16 bna_rxf_hds_type_t;
+
+
+#define BNA_HDS_FORCE_OFFSET_MIN 24 /* bytes */
+#define BNA_HDS_FORCE_OFFSET_MAX 60 /* bytes */
+
+
+struct bna_rxf_hds {
+ bna_rxf_hds_type_t type; /* OR of bna_rxf_hds_type_t */
+ u8 header_size; /* max header size for split */
+ u8 forced_offset; /* HDS at a force offset */
+};
+
+
+/* RxF Control Flags */
+#define BNA_RXF_CF_SM_LG_RXQ (1 << 15)
+#define BNA_RXF_CF_DEFAULT_VLAN (1 << 14)
+#define BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE (1 << 13)
+#define BNA_RXF_CF_VLAN_STRIP (1 << 12)
+#define BNA_RXF_CF_RSS_ENABLE (1 << 8)
+typedef u16 bna_rxf_ctrl_flag_t;
+
+
+/* RxF Configuration Structure */
+struct bna_rxf_config {
+ u8 rit_offset; /* offset into RIT */
+ u8 mcast_rxq_id; /* multicast RxQ ID */
+ u16 default_vlan; /* default VLAN for untagged frames */
+ bna_rxf_ctrl_flag_t flags; /* OR of bna_rxf_ctrl_flag_t */
+ struct bna_rxf_hds hds; /* valid when BNA_RXF_SM_LG_RXQ == 0 */
+ struct bna_rxf_rss rss; /* valid when BNA_RXF_RSS_ENABLE == 1 */
+};
+
+
+/**
+ * bna_rxf_config_set()
+ *
+ * For RxF "rxf_id", it configures RxF based on "cfg_ptr", and indicates
+ * to the statistics collector to collect statistics for this Rx-Function.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] cfg_ptr - pointer to rx-function configuration.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_config_set(struct bna_dev *dev, unsigned int rxf_id,
+ const struct bna_rxf_config *cfg_ptr);
+
+
+/**
+ * bna_rxf_config_clear()
+ *
+ * For RxF "rxf_id", it clear its configuration and indicates to the
+ * statistics collector to stop collecting statistics for this
+ * Rx-Function.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ *
+ * @return void
+ */
+void bna_rxf_config_clear(struct bna_dev *dev, unsigned int rxf_id);
+
+/**
+ * bna_multi_rxf_active()
+ *
+ * Disables/Enables the Rx Function without clearing the configuration
+ * Also disables/enables collection of statistics.
+ *
+ * @param[in] bna_dev - Pointer to BNA BNA device handle
+ * @param[in] rxf_id - Id of the Rx Function to be disabled
+ * @param[in] enable - 1 = enable, 0 = disable
+ *
+ * @return BNA_OK if mbox command succeeded else BNA_FAIL
+ */
+enum bna_status_e bna_multi_rxf_active(struct bna_dev *dev,
+ u64 rxf_id_mask, u8 enable);
+/**
+ * bna_rxf_disable()
+ *
+ * Disables the Rx Function without clearing the configuration
+ * Also disables collection of statistics.
+ *
+ * @param[in] bna_dev - Pointer to BNA BNA device handle
+ * @param[in] rxf_id - Id of the Rx Function to be disabled
+ *
+ * @return BNA_OK if mbox command succeeded else BNA_FAIL
+ */
+enum bna_status_e bna_rxf_disable(struct bna_dev *bna_dev,
+ unsigned int rxf_id);
+
+/**
+ * bna_multi_rxf_disable()
+ *
+ * Disables multiple Rx Functions as per the mask
+ * Also disables collection of statistics.
+ *
+ * @param[in] dev - Pointer to BNA device handle
+ * @param[in] rxf_id_mask - Mask of the functions to be
+ disabled
+ *
+ * @return BNA_OK if mbox command succeeded, else BNA_FAIL
+ */
+#define bna_multi_rxf_disable(dev, rxf_id_mask) \
+ bna_multi_rxf_active((dev), (rxf_id_mask), 0)
+
+/**
+ * bna_rxf_enable()
+ *
+ * Enables the Rx Function
+ *
+ * @param[in] bna_dev - Pointer to BNA BNA device handle
+ * @param[in] rxf_id - Id of the Rx Function to be disabled
+ *
+ * @return BNA_OK if mbox command succeeded else BNA_FAIL
+ */
+enum bna_status_e bna_rxf_enable(struct bna_dev *bna_dev,
+ unsigned int rxf_id);
+
+/**
+ * bna_multi_rxf_enable()
+ *
+ * Enables multiple Rx Functions as per the mask
+ * Also enables collection of statistics.
+ *
+ * @param[in] dev - Pointer to BNA device handle
+ * @param[in] rxf_id_mask - Mask of the functions to be
+ * enabled
+ *
+ * @return BNA_OK if mbox command succeeded, else BNA_FAIL
+ */
+#define bna_multi_rxf_enable(dev, rxf_id_mask) \
+ bna_multi_rxf_active((dev), (rxf_id_mask), 1)
+
+
+/* TODO : Delete when windows migration is complete */
+void bna_rxf_disable_old(struct bna_dev *dev, unsigned int rxf_id);
+
+/**
+ * bna_rxf_ucast_mac_get()
+ *
+ * For RxF "rxf_id", it overwrites the burnt-in unicast MAC with
+ * the one specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID
+ * @param[in] entry - offset into UCAM to read
+ * @param[in] mac_addr_ptr - pointer to mac adddress to set
+ *
+ * @return void
+ */
+void
+bna_rxf_ucast_mac_get(struct bna_dev *bna_dev, unsigned int *rxf_id,
+ unsigned int entry, const struct mac *mac_addr_ptr);
+
+/**
+ * bna_rxf_ucast_mac_set()
+ *
+ * For RxF "rxf_id", it overwrites the burnt-in unicast MAC with
+ * the one specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_ptr - pointer to unicast MAC address.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_ucast_mac_set(struct bna_dev *dev,
+ unsigned int rxf_id, const struct mac *mac_ptr);
+
+
+/**
+ * bna_rxf_ucast_mac_add()
+ *
+ * For RxF "rxf_id", it adds the unicast MAC specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_ptr - pointer to unicast MAC address.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_ucast_mac_add(struct bna_dev *dev,
+ unsigned int rxf_id, const struct mac *mac_ptr);
+
+
+/**
+ * bna_rxf_ucast_mac_del()
+ *
+ * For RxF "rxf_id", it deletes the unicast MAC specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_ptr - pointer to unicast MAC address.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_ucast_mac_del(struct bna_dev *dev,
+ unsigned int rxf_id, const struct mac *mac_ptr);
+
+
+/**
+ * bna_rxf_mcast_mac_add()
+ *
+ * For RxF "rxf_id", it adds the multicast MAC specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_ptr - pointer to multicast MAC address.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_mcast_mac_add(struct bna_dev *dev,
+ unsigned int rxf_id, const struct mac *mac_ptr);
+
+
+/**
+ * bna_rxf_mcast_mac_del()
+ *
+ * For RxF "rxf_id", it deletes the multicast MAC specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_ptr - pointer to multicast MAC address.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_mcast_mac_del(struct bna_dev *dev,
+ unsigned int rxf_id, const struct mac *mac_ptr);
+
+/**
+ * bna_rxf_broadcast()
+ *
+ * For RxF "rxf_id", it enables/disables the broadcast address.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable broadcast address
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_broadcast(struct bna_dev *bna_dev,
+ unsigned int rxf_id, enum bna_enable_e enable);
+
+/**
+ * bna_rxf_mcast_mac_set_list()
+ *
+ * For RxF "rxf_id", it sets the multicast MAC addresses
+ * specified by "mac_addr_ptr". The function first deletes the
+ * MAC addresses in the existing list that is not found in the
+ * new list. It then adds the new addresses that ar ein the new
+ * list but not in the old list. It then replaces the old list
+ * with the new list in the bna_dev structure.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_addr_ptr - pointer to the list of mac
+ * adddresses to set
+ * @param[in] mac_addr_num - number of mac addresses in the
+ * list
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_mcast_mac_set_list(struct bna_dev *bna_dev,
+ unsigned int rxf_id,
+ const struct mac *mac_addr_ptr,
+ unsigned int mac_addr_num);
+
+/**
+ * bna_mcast_mac_reset_list()
+ *
+ * Resets the multicast MAC address list kept by driver.
+ * Called when the hw gets reset.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void
+bna_mcast_mac_reset_list(struct bna_dev *bna_dev);
+
+/**
+ * bna_rxf_mcast_filter()
+ *
+ * For RxF "rxf_id", it enables/disables the Multicast Filter.
+ * Disabling the Multicast Filter allows reception of any multicast frame.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable Multicast Filtering.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_mcast_filter(struct bna_dev *dev,
+ unsigned int rxf_id, enum bna_enable_e enable);
+
+/**
+ * bna_rxf_mcast_del_all()
+ *
+ * For RxF "rxf_id", it clears the MCAST cam and MVT.
+ * This functionality is required by some of the drivers.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_mcast_del_all(struct bna_dev *dev,
+ unsigned int rxf_id);
+
+
+/**
+ * bna_rxf_vlan_add()
+ *
+ * For RxF "rxf_id", it adds this function as a member of the
+ * specified "vlan_id".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] vlan_id - VLAN ID.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void bna_rxf_vlan_add(struct bna_dev *dev, unsigned int rxf_id,
+ unsigned int vlan_id);
+
+
+/**
+ * bna_rxf_vlan_del()
+ *
+ * For RxF "rxf_id", it removes this function as a member of the
+ * specified "vlan_id".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] vlan_id - VLAN ID.
+ *
+ * @return void
+ */
+void bna_rxf_vlan_del(struct bna_dev *dev, unsigned int rxf_id,
+ unsigned int vlan_id);
+
+
+/**
+ * bna_rxf_vlan_filter()
+ *
+ * For RxF "rxf_id", it enables/disables the VLAN filter.
+ * Disabling the VLAN Filter allows reception of any VLAN-tagged frame.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable VLAN Filtering.
+ *
+ * @return void
+ */
+void bna_rxf_vlan_filter(struct bna_dev *dev, unsigned int rxf_id,
+ enum bna_enable_e enable);
+
+/**
+ * bna_rxf_vlan_del_all()
+ *
+ * For RxF "rxf_id", it clears all the VLANs.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+
+ *
+ * @return void
+ */
+void bna_rxf_vlan_del_all(struct bna_dev *bna_dev, unsigned int rxf_id);
+
+/**
+ * bna_rxf_promiscuous_mode()
+ *
+ * For RxF "rxf_id", it enables/disables promiscuous-mode.
+ * Only one RxF is allowed to be in promiscuous-mode, and will only disable
+ * the promiscuous-mode if the RxF ID is the one in promiscuous-mode.
+ * Must be called after the RxF has been configured.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable promiscuous-mode..
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_promiscuous(struct bna_dev *dev,
+ unsigned int rxf_id, enum bna_enable_e enable);
+
+/**
+ * bna_rxf_default_mode()
+ *
+ * For RxF "rxf_id", it enables/disables default mode.
+ * Only one RxF is allowed to be in default-mode, and will only disable
+ * the default-mode if the RxF ID is the one in default-mode.
+ * Must be called after the RxF has been configured.
+ * Must remove all unicast MAC associated to this RxF.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable default mode..
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_default_mode(struct bna_dev *dev,
+ unsigned int rxf_id, enum bna_enable_e enable);
+
+
+
+/**
+ * bna_rxf_frame_stats_get()
+ *
+ * For RxF "rxf_id", it loads frame statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[out] stats_ptr - pointer to rx-function statistics structure
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void bna_rxf_frame_stats_get(struct bna_dev *dev, unsigned int rxf_id,
+ struct bna_stats_rxf **stats_ptr);
+
+/**
+ * bna_txf_frame_stats_get()
+ *
+ * For TxF "txf_id", it loads frame statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] txf_id - tx-function ID.
+ * @param[out] stats_ptr - pointer to tx-function statistics structure
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void bna_txf_frame_stats_get(struct bna_dev *dev, unsigned int txf_id,
+ struct bna_stats_txf **stats_ptr);
+
+/**
+ * bna_mac_rx_stats_get()
+ *
+ * Loads MAC Rx statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+
+ * @param[out] stats_ptr - pointer to stats structure
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void bna_mac_rx_stats_get(struct bna_dev *bna_dev,
+ struct cna_stats_mac_rx **stats_ptr);
+
+/**
+ * bna_mac_tx_stats_get()
+ *
+ * Loads MAC Tx statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+
+ * @param[out] stats_ptr - pointer to stats structure
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void bna_mac_tx_stats_get(struct bna_dev *bna_dev,
+ struct cna_stats_mac_tx **stats_ptr);
+
+/**
+ * bna_all_stats_get()
+ *
+ * Loads all statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+
+ * @param[out] stats_ptr - pointer to stats structure
+ *
+ * @return void
+ */
+void bna_all_stats_get(struct bna_dev *bna_dev, struct bna_stats **stats_ptr);
+/**
+ * bna_stats_get()
+ *
+ * Get the statistics from the device. This function needs to
+ * be scheduled every second to get periodic update of the
+ * statistics data from hardware.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ *
+ * @return void
+ */
+enum bna_status_e bna_stats_get(struct bna_dev *dev);
+
+/**
+ * bna_stats_clear()
+ *
+ * Clear the statistics in the device.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_stats_clear(struct bna_dev *bna_dev,
+ u64 txf_id_mask, u64 rxf_id_mask);
+
+/**
+ * bna_rxf_stats_clear()
+ *
+ * Clear the statistics for specified txf.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ * @param[in] rxf_id - rx-function ID.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_stats_clear(struct bna_dev *dev,
+ unsigned int rxf_id);
+
+/**
+ * bna_lldp_stats_clear()
+ *
+ * Clear the lldp-dcbcx statistics in the device.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_lldp_stats_clear(struct bna_dev *bna_dev);
+
+/**
+ * bna_get_cfg_req()
+ *
+ * Gets the LLDP-DCBCXP Config from the f/w.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ * @param[in] dma_addr_bna - dma address to return the config.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_get_cfg_req(struct bna_dev *bna_dev,
+ struct bna_dma_addr *dma_addr_bna);
+
+/**
+
+* bna_get_cee_stats_req()
+*
+* Gets the LLDP-DCBCXP stats from the f/w.
+*
+* @param[in] dev - pointer to BNA device structure.
+* @param[in] dma_addr_bna - dma address to return the config.
+*
+* @return BNA_OK - successful
+* @return BNA_FAIL - failed on sanity checks.
+*/
+enum bna_status_e bna_get_cee_stats_req(struct bna_dev *bna_dev,
+ struct bna_dma_addr *dma_addr_bna);
+
+/**
+ * bna_stats_process()
+ *
+ * Process the statistics data DMAed from the device. This
+ * function needs to be scheduled upon getting an asynchronous
+ * notification from the firmware.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ *
+ * @return void
+ */
+void bna_stats_process(struct bna_dev *bna_dev);
+
+/**
+ * bna_init()
+ *
+ * Called by the driver during initialization. The driver is
+ * expected to allocate struct bna_dev structure for the BNA layer.
+ * Should be called with the lock held.
+ *
+ * @param[in] bna_handle - pointer to BNA device structure
+ * allocated by the calling driver
+ * @param[in] bar0 - BAR0 value
+ * @param[in] stats - pointer to stats host buffer
+ * @param[in] stats_dma - pointer to DMA value for stats
+ * @param[in] trcmod - pointer to struct bfa_trc_mod
+ * (for Interrupt Moderation)
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void bna_init(struct bna_dev *bna_handle, void *bar0, void *stats,
+ struct bna_dma_addr stats_dma, struct bfa_trc_mod *trcmod,
+ struct bfa_log_mod *logmod);
+
+/**
+ * bna_uninit()
+ *
+ * Called by the driver during removal/unload.
+ *
+ * @param[in] bna_handle - pointer to BNA device structure
+ * allocated by the calling driver
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_uninit(void *bna_handle);
+
+/**
+ * bna_cleanup()
+ *
+ * Called by the driver from the hb_fail callback to
+ * to let bna do the cleanup.
+ * This should be called before driver frees memory.
+ * Should be called with the lock held.
+ *
+ * @param[in] bna_handle - pointer to BNA device structure
+ * allocated by the calling driver
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_cleanup(void *bna_handle);
+
+#endif /* __BNA_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/bna_hwreg.h net-next-2.6-mod/drivers/net/bna/bna_hwreg.h
--- net-next-2.6-orig/drivers/net/bna/bna_hwreg.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bna_hwreg.h 2009-11-12 19:03:38.936341000 -0800
@@ -0,0 +1,1002 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See <license_file> for copyright and licensing details.
+ */
+
+/*
+ * bna_hwreg.h Catapult host block register definitions
+ *
+ */
+
+#ifndef __BNA_HWREG_H__
+#define __BNA_HWREG_H__
+
+#include <bfi/bfi_ctreg.h>
+
+/*
+ * REGISTER ACCESS
+ */
+/**
+ * CPE Block Register Address Offset from BAR0
+ */
+ /* TODO */
+/**
+ * RME Block Register Address Offset from BAR0
+ */
+ /* TODO */
+/**
+ * SGM Block Register Address Offset from BAR0
+ */
+ /* TODO */
+
+/**
+ * DMA Block Register Host Window Start Address
+ */
+#define DMA_BLK_REG_ADDR 0x00013000
+/**
+ * DMA Block Internal Registers
+ */
+#define DMA_CTRL_REG0 (DMA_BLK_REG_ADDR + 0x000)
+#define DMA_CTRL_REG1 (DMA_BLK_REG_ADDR + 0x004)
+#define DMA_ERR_INT_STATUS (DMA_BLK_REG_ADDR + 0x008)
+#define DMA_ERR_INT_ENABLE (DMA_BLK_REG_ADDR + 0x00c)
+#define DMA_ERR_INT_STATUS_SET (DMA_BLK_REG_ADDR + 0x010)
+
+/**
+ * APP Block Register Address Offset from BAR0
+ */
+#define APP_BLK_REG_ADDR 0x00014000
+
+/**
+ * Host Function Interrupt Mask Registers
+ */
+#define HOSTFN0_INT_MASK (APP_BLK_REG_ADDR + 0x004)
+#define HOSTFN1_INT_MASK (APP_BLK_REG_ADDR + 0x104)
+#define HOSTFN2_INT_MASK (APP_BLK_REG_ADDR + 0x304)
+#define HOSTFN3_INT_MASK (APP_BLK_REG_ADDR + 0x404)
+
+/**
+ * Host Function PCIe Error Registers
+ * Duplicates "Correctable" & "Uncorrectable"
+ * registers in PCIe Config space.
+ */
+#define FN0_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x014)
+#define FN1_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x114)
+#define FN2_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x314)
+#define FN3_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x414)
+
+/**
+ * Host Function Error Type Status Registers
+ */
+#define FN0_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x018)
+#define FN1_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x118)
+#define FN2_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x318)
+#define FN3_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x418)
+/**
+ * Host Function Error Type Mask Registers
+ */
+#define FN0_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x01c)
+#define FN1_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x11c)
+#define FN2_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x31c)
+#define FN3_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x41c)
+
+/**
+ * Catapult Host Semaphore Status Registers (App block)
+ */
+#define HOST_SEM_STS0_REG (APP_BLK_REG_ADDR + 0x630)
+#define HOST_SEM_STS1_REG (APP_BLK_REG_ADDR + 0x634)
+#define HOST_SEM_STS2_REG (APP_BLK_REG_ADDR + 0x638)
+#define HOST_SEM_STS3_REG (APP_BLK_REG_ADDR + 0x63c)
+#define HOST_SEM_STS4_REG (APP_BLK_REG_ADDR + 0x640)
+#define HOST_SEM_STS5_REG (APP_BLK_REG_ADDR + 0x644)
+#define HOST_SEM_STS6_REG (APP_BLK_REG_ADDR + 0x648)
+#define HOST_SEM_STS7_REG (APP_BLK_REG_ADDR + 0x64c)
+
+/**
+ * PCIe Misc Register
+ * Check catapult_spec.pdf for details
+ */
+#define PCIE_MISC_REG (APP_BLK_REG_ADDR + 0x200)
+/**
+ * Temp Sensor Control Registers
+ */
+#define TEMPSENSE_CNTL_REG (APP_BLK_REG_ADDR + 0x250)
+#define TEMPSENSE_STAT_REG (APP_BLK_REG_ADDR + 0x254)
+
+/**
+ * APP Block local error registers
+ */
+#define APP_LOCAL_ERR_STAT (APP_BLK_REG_ADDR + 0x258)
+#define APP_LOCAL_ERR_MSK (APP_BLK_REG_ADDR + 0x25c)
+
+/**
+ * PCIe Link Error registers
+ */
+#define PCIE_LNK_ERR_STAT (APP_BLK_REG_ADDR + 0x260)
+#define PCIE_LNK_ERR_MSK (APP_BLK_REG_ADDR + 0x264)
+
+/**
+ * FCoE/FIP Ethertype Register
+ * 31:16 -- Chip wide value for FIP type
+ * 15:0 -- Chip wide value for FCoE type
+ */
+#define FCOE_FIP_ETH_TYPE (APP_BLK_REG_ADDR + 0x280)
+
+/**
+ * Reserved Ethertype Register
+ * 31:16 -- Reserved
+ * 15:0 -- Other ethertype
+ */
+#define RESV_ETH_TYPE (APP_BLK_REG_ADDR + 0x284)
+
+/**
+ * Host Command Status Registers
+ * Each set consists of 3 registers :
+ * clear, set, cmd
+ * 16 such register sets in all
+ * See catapult_spec.pdf for detailed functionality
+ * Put each type in a single macro accessed by _num ?
+ */
+#define HOST_CMDSTS0_CLR_REG (APP_BLK_REG_ADDR + 0x500)
+#define HOST_CMDSTS0_SET_REG (APP_BLK_REG_ADDR + 0x504)
+#define HOST_CMDSTS0_REG (APP_BLK_REG_ADDR + 0x508)
+#define HOST_CMDSTS1_CLR_REG (APP_BLK_REG_ADDR + 0x510)
+#define HOST_CMDSTS1_SET_REG (APP_BLK_REG_ADDR + 0x514)
+#define HOST_CMDSTS1_REG (APP_BLK_REG_ADDR + 0x518)
+#define HOST_CMDSTS2_CLR_REG (APP_BLK_REG_ADDR + 0x520)
+#define HOST_CMDSTS2_SET_REG (APP_BLK_REG_ADDR + 0x524)
+#define HOST_CMDSTS2_REG (APP_BLK_REG_ADDR + 0x528)
+#define HOST_CMDSTS3_CLR_REG (APP_BLK_REG_ADDR + 0x530)
+#define HOST_CMDSTS3_SET_REG (APP_BLK_REG_ADDR + 0x534)
+#define HOST_CMDSTS3_REG (APP_BLK_REG_ADDR + 0x538)
+#define HOST_CMDSTS4_CLR_REG (APP_BLK_REG_ADDR + 0x540)
+#define HOST_CMDSTS4_SET_REG (APP_BLK_REG_ADDR + 0x544)
+#define HOST_CMDSTS4_REG (APP_BLK_REG_ADDR + 0x548)
+#define HOST_CMDSTS5_CLR_REG (APP_BLK_REG_ADDR + 0x550)
+#define HOST_CMDSTS5_SET_REG (APP_BLK_REG_ADDR + 0x554)
+#define HOST_CMDSTS5_REG (APP_BLK_REG_ADDR + 0x558)
+#define HOST_CMDSTS6_CLR_REG (APP_BLK_REG_ADDR + 0x560)
+#define HOST_CMDSTS6_SET_REG (APP_BLK_REG_ADDR + 0x564)
+#define HOST_CMDSTS6_REG (APP_BLK_REG_ADDR + 0x568)
+#define HOST_CMDSTS7_CLR_REG (APP_BLK_REG_ADDR + 0x570)
+#define HOST_CMDSTS7_SET_REG (APP_BLK_REG_ADDR + 0x574)
+#define HOST_CMDSTS7_REG (APP_BLK_REG_ADDR + 0x578)
+#define HOST_CMDSTS8_CLR_REG (APP_BLK_REG_ADDR + 0x580)
+#define HOST_CMDSTS8_SET_REG (APP_BLK_REG_ADDR + 0x584)
+#define HOST_CMDSTS8_REG (APP_BLK_REG_ADDR + 0x588)
+#define HOST_CMDSTS9_CLR_REG (APP_BLK_REG_ADDR + 0x590)
+#define HOST_CMDSTS9_SET_REG (APP_BLK_REG_ADDR + 0x594)
+#define HOST_CMDSTS9_REG (APP_BLK_REG_ADDR + 0x598)
+#define HOST_CMDSTS10_CLR_REG (APP_BLK_REG_ADDR + 0x5A0)
+#define HOST_CMDSTS10_SET_REG (APP_BLK_REG_ADDR + 0x5A4)
+#define HOST_CMDSTS10_REG (APP_BLK_REG_ADDR + 0x5A8)
+#define HOST_CMDSTS11_CLR_REG (APP_BLK_REG_ADDR + 0x5B0)
+#define HOST_CMDSTS11_SET_REG (APP_BLK_REG_ADDR + 0x5B4)
+#define HOST_CMDSTS11_REG (APP_BLK_REG_ADDR + 0x5B8)
+#define HOST_CMDSTS12_CLR_REG (APP_BLK_REG_ADDR + 0x5C0)
+#define HOST_CMDSTS12_SET_REG (APP_BLK_REG_ADDR + 0x5C4)
+#define HOST_CMDSTS12_REG (APP_BLK_REG_ADDR + 0x5C8)
+#define HOST_CMDSTS13_CLR_REG (APP_BLK_REG_ADDR + 0x5D0)
+#define HOST_CMDSTS13_SET_REG (APP_BLK_REG_ADDR + 0x5D4)
+#define HOST_CMDSTS13_REG (APP_BLK_REG_ADDR + 0x5D8)
+#define HOST_CMDSTS14_CLR_REG (APP_BLK_REG_ADDR + 0x5E0)
+#define HOST_CMDSTS14_SET_REG (APP_BLK_REG_ADDR + 0x5E4)
+#define HOST_CMDSTS14_REG (APP_BLK_REG_ADDR + 0x5E8)
+#define HOST_CMDSTS15_CLR_REG (APP_BLK_REG_ADDR + 0x5F0)
+#define HOST_CMDSTS15_SET_REG (APP_BLK_REG_ADDR + 0x5F4)
+#define HOST_CMDSTS15_REG (APP_BLK_REG_ADDR + 0x5F8)
+
+/**
+ * IOQ Block Register Address Offset from BAR0
+ */
+ /* TODO ? */
+/**
+ * IOH Block Register Address Offset from BAR0
+ */
+ /* Required only in FC mode */
+/**
+ * DIP Block Register Address Offset from BAR0
+ */
+ /* Required only in FC mode */
+/**
+ * SIP Block Register Address Offset from BAR0
+ */
+ /* Required only in FC mode */
+
+/**
+ * LPU0 Block Register Address Offset from BAR0
+ * Range 0x18000 - 0x18033
+ */
+#define LPU0_BLK_REG_ADDR 0x00018000
+
+/**
+ * LPU0 Registers
+ * Should they be directly used from host,
+ * except for diagnostics ?
+ * CTL_REG : Control register
+ * CMD_REG : Triggers exec. of cmd. in
+ * Mailbox memory
+ */
+#define LPU0_MBOX_CTL_REG (LPU0_BLK_REG_ADDR + 0x000)
+#define LPU0_MBOX_CMD_REG (LPU0_BLK_REG_ADDR + 0x004)
+#define LPU0_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x008)
+#define LPU1_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x00c)
+#define LPU0_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x010)
+#define LPU1_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x014)
+#define LPU0_ERR_STATUS_REG (LPU0_BLK_REG_ADDR + 0x018)
+#define LPU0_ERR_SET_REG (LPU0_BLK_REG_ADDR + 0x020)
+
+/**
+ * LPU1 Block Register Address Offset from BAR0
+ * Range 0x18400 - 0x18433
+ */
+#define LPU1_BLK_REG_ADDR 0x00018400
+
+/**
+ * LPU1 Registers
+ * Same as LPU0 registers above
+ */
+#define LPU1_MBOX_CTL_REG (LPU1_BLK_REG_ADDR + 0x000)
+#define LPU1_MBOX_CMD_REG (LPU1_BLK_REG_ADDR + 0x004)
+#define LPU0_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x008)
+#define LPU1_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x00c)
+#define LPU0_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x010)
+#define LPU1_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x014)
+#define LPU1_ERR_STATUS_REG (LPU1_BLK_REG_ADDR + 0x018)
+#define LPU1_ERR_SET_REG (LPU1_BLK_REG_ADDR + 0x020)
+
+/**
+ * PSS Block Register Address Offset from BAR0
+ * Range 0x18800 - 0x188DB
+ */
+#define PSS_BLK_REG_ADDR 0x00018800
+
+/**
+ * PSS Registers
+ * For details, see catapult_spec.pdf
+ * ERR_STATUS_REG : Indicates error in PSS module
+ * RAM_ERR_STATUS_REG : Indicates RAM module that detected error
+ */
+#define ERR_STATUS_SET (PSS_BLK_REG_ADDR + 0x018)
+#define PSS_RAM_ERR_STATUS_REG (PSS_BLK_REG_ADDR + 0x01C)
+
+/**
+ * PSS Semaphore Lock Registers, total 16
+ * First read when unlocked returns 0,
+ * and is set to 1, atomically.
+ * Subsequent reads returns 1.
+ * To clear set the value to 0.
+ * Range : 0x20 to 0x5c
+ */
+#define PSS_SEM_LOCK_REG(_num) \
+ (PSS_BLK_REG_ADDR + 0x020 + ((_num) << 2))
+
+/**
+ * PSS Semaphore Status Registers,
+ * corresponding to the lock registers above
+ */
+#define PSS_SEM_STATUS_REG(_num) \
+ (PSS_BLK_REG_ADDR + 0x060 + ((_num) << 2))
+
+/**
+ * Catapult CPQ Registers
+ * Defines for Mailbox Registers
+ * Used to send mailbox commands to firmware from
+ * host. The data part is written to the MBox
+ * memory, registers are used to indicate that
+ * a commnad is resident in memory.
+ *
+ * Note : LPU0<->LPU1 mailboxes are not listed here
+ */
+#define CPQ_BLK_REG_ADDR 0x00019000
+
+#define HOSTFN0_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x130)
+#define HOSTFN0_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x134)
+#define LPU0_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x138)
+#define LPU1_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x13C)
+
+#define HOSTFN1_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x140)
+#define HOSTFN1_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x144)
+#define LPU0_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x148)
+#define LPU1_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x14C)
+
+#define HOSTFN2_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x170)
+#define HOSTFN2_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x174)
+#define LPU0_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x178)
+#define LPU1_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x17C)
+
+#define HOSTFN3_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x180)
+#define HOSTFN3_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x184)
+#define LPU0_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x188)
+#define LPU1_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x18C)
+
+/**
+ * Host Function Force Parity Error Registers
+ */
+#define HOSTFN0_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x120)
+#define HOSTFN1_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x124)
+#define HOSTFN2_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x128)
+#define HOSTFN3_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x12C)
+
+/**
+ * LL Port[0|1] Halt Mask Registers
+ */
+#define LL_HALT_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1A0)
+#define LL_HALT_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1B0)
+
+/**
+ * LL Port[0|1] Error Mask Registers
+ */
+#define LL_ERR_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1D0)
+#define LL_ERR_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1D4)
+
+/**
+ * TXQ Block Register Address Offset from BAR0
+ */
+ /*
+ * TODO :
+ * For per-port registers, offsets look
+ * skewed, need clarification
+ */
+/**
+ * RDS (Rx Frame Data Store) Block Register Address Offset from BAR0
+ */
+ /* Host does not need to access these */
+/**
+ * TDS (Tx Frame Data Store) Block Register Address Offset from BAR0
+ */
+ /* Host does not need to access these */
+/**
+ * BAL Block Register Address Offset from BAR0
+ */
+ /* TODO : Some of these may be needed */
+
+/**
+ * EMC FLI (Flash Controller) Block Register Address Offset from BAR0
+ */
+#define FLI_BLK_REG_ADDR 0x0001D000
+
+/**
+ * EMC FLI Registers
+ */
+#define FLI_CMD_REG (FLI_BLK_REG_ADDR + 0x000)
+#define FLI_ADDR_REG (FLI_BLK_REG_ADDR + 0x004)
+#define FLI_CTL_REG (FLI_BLK_REG_ADDR + 0x008)
+#define FLI_WRDATA_REG (FLI_BLK_REG_ADDR + 0x00C)
+#define FLI_RDDATA_REG (FLI_BLK_REG_ADDR + 0x010)
+#define FLI_DEV_STATUS_REG (FLI_BLK_REG_ADDR + 0x014)
+#define FLI_SIG_WD_REG (FLI_BLK_REG_ADDR + 0x018)
+/*
+ * H/W document lists the following vendor ID register as
+ * FLI_ERR_VENDOR_REG -- typo ?
+ * RO register
+ * 31:16 -- Vendor Id
+ * 15:0 -- Device Id
+ */
+#define FLI_DEV_VENDOR_REG (FLI_BLK_REG_ADDR + 0x01C)
+#define FLI_ERR_STATUS_REG (FLI_BLK_REG_ADDR + 0x020)
+
+/**
+ * FPG (FC Port Group) Block Register Address Offset from BAR0
+ */
+ /* FC driver specific */
+
+/**
+ * RAD (RxAdm) Block Register Address Offset from BAR0
+ * RAD0 Range : 0x20000 - 0x203FF
+ * RAD1 Range : 0x20400 - 0x207FF
+ */
+#define RAD0_BLK_REG_ADDR 0x00020000
+#define RAD1_BLK_REG_ADDR 0x00020400
+
+/**
+ * RAD0 Registers
+ */
+#define RAD0_CTL_REG (RAD0_BLK_REG_ADDR + 0x000)
+#define RAD0_PE_PARM_REG (RAD0_BLK_REG_ADDR + 0x004)
+#define RAD0_BCN_REG (RAD0_BLK_REG_ADDR + 0x008)
+/*
+ * Default function ID register
+ */
+#define RAD0_DEFAULT_REG (RAD0_BLK_REG_ADDR + 0x00C)
+/*
+ * Default promiscuous ID register
+ */
+#define RAD0_PROMISC_REG (RAD0_BLK_REG_ADDR + 0x010)
+
+#define RAD0_BCNQ_REG (RAD0_BLK_REG_ADDR + 0x014)
+/*
+ * This register selects 1 of 8 PM Q's using
+ * VLAN pri, for non-BCN packets without a VLAN tag
+ */
+#define RAD0_DEFAULTQ_REG (RAD0_BLK_REG_ADDR + 0x018)
+
+#define RAD0_ERR_STS (RAD0_BLK_REG_ADDR + 0x01C)
+#define RAD0_SET_ERR_STS (RAD0_BLK_REG_ADDR + 0x020)
+#define RAD0_ERR_INT_EN (RAD0_BLK_REG_ADDR + 0x024)
+#define RAD0_FIRST_ERR (RAD0_BLK_REG_ADDR + 0x028)
+#define RAD0_FORCE_ERR (RAD0_BLK_REG_ADDR + 0x02C)
+
+#define RAD0_IF_RCVD (RAD0_BLK_REG_ADDR + 0x030)
+#define RAD0_IF_RCVD_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x034)
+#define RAD0_IF_RCVD_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x038)
+#define RAD0_IF_RCVD_VLAN (RAD0_BLK_REG_ADDR + 0x03C)
+#define RAD0_IF_RCVD_UCAST (RAD0_BLK_REG_ADDR + 0x040)
+#define RAD0_IF_RCVD_UCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x044)
+#define RAD0_IF_RCVD_UCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x048)
+#define RAD0_IF_RCVD_UCAST_VLAN (RAD0_BLK_REG_ADDR + 0x04C)
+#define RAD0_IF_RCVD_MCAST (RAD0_BLK_REG_ADDR + 0x050)
+#define RAD0_IF_RCVD_MCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x054)
+#define RAD0_IF_RCVD_MCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x058)
+#define RAD0_IF_RCVD_MCAST_VLAN (RAD0_BLK_REG_ADDR + 0x05C)
+#define RAD0_IF_RCVD_BCAST (RAD0_BLK_REG_ADDR + 0x060)
+#define RAD0_IF_RCVD_BCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x064)
+#define RAD0_IF_RCVD_BCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x068)
+#define RAD0_IF_RCVD_BCAST_VLAN (RAD0_BLK_REG_ADDR + 0x06C)
+#define RAD0_DROPPED_FRAMES (RAD0_BLK_REG_ADDR + 0x070)
+
+#define RAD0_MAC_MAN_1H (RAD0_BLK_REG_ADDR + 0x080)
+#define RAD0_MAC_MAN_1L (RAD0_BLK_REG_ADDR + 0x084)
+#define RAD0_MAC_MAN_2H (RAD0_BLK_REG_ADDR + 0x088)
+#define RAD0_MAC_MAN_2L (RAD0_BLK_REG_ADDR + 0x08C)
+#define RAD0_MAC_MAN_3H (RAD0_BLK_REG_ADDR + 0x090)
+#define RAD0_MAC_MAN_3L (RAD0_BLK_REG_ADDR + 0x094)
+#define RAD0_MAC_MAN_4H (RAD0_BLK_REG_ADDR + 0x098)
+#define RAD0_MAC_MAN_4L (RAD0_BLK_REG_ADDR + 0x09C)
+
+
+#define RAD0_LAST4_IP (RAD0_BLK_REG_ADDR + 0x100)
+
+/**
+ * RAD1 Registers
+ */
+#define RAD1_CTL_REG (RAD1_BLK_REG_ADDR + 0x000)
+#define RAD1_PE_PARM_REG (RAD1_BLK_REG_ADDR + 0x004)
+#define RAD1_BCN_REG (RAD1_BLK_REG_ADDR + 0x008)
+/*
+ * Default function ID register
+ */
+#define RAD1_DEFAULT_REG (RAD1_BLK_REG_ADDR + 0x00C)
+/*
+ * Promiscuous function ID register
+ */
+#define RAD1_PROMISC_REG (RAD1_BLK_REG_ADDR + 0x010)
+
+#define RAD1_BCNQ_REG (RAD1_BLK_REG_ADDR + 0x014)
+/*
+ * This register selects 1 of 8 PM Q's using
+ * VLAN pri, for non-BCN packets without a VLAN tag
+ */
+#define RAD1_DEFAULTQ_REG (RAD1_BLK_REG_ADDR + 0x018)
+
+#define RAD1_ERR_STS (RAD1_BLK_REG_ADDR + 0x01C)
+#define RAD1_SET_ERR_STS (RAD1_BLK_REG_ADDR + 0x020)
+#define RAD1_ERR_INT_EN (RAD1_BLK_REG_ADDR + 0x024)
+/*
+ * RxAdm Statistics Registers:
+ * F/W will access these, not required immediately for host
+ */
+
+/**
+ * RLB (Rx Loop Back) Block Register Address Offset from BAR0
+ */
+ /* TODO : ?? */
+/**
+ * TXA Block Register Address Offset from BAR0
+ * TXA0 Range : 0x21000 - 0x213FF
+ * TXA1 Range : 0x21400 - 0x217FF
+ */
+#define TXA0_BLK_REG_ADDR 0x00021000
+#define TXA1_BLK_REG_ADDR 0x00021400
+
+/**
+ * TXA Registers
+ */
+#define TXA0_CTRL_REG (TXA0_BLK_REG_ADDR + 0x000)
+#define TXA1_CTRL_REG (TXA1_BLK_REG_ADDR + 0x000)
+
+/**
+ * TSO Sequence # Registers (RO)
+ * Total 8 (for 8 queues)
+ * Holds the last seq.# for TSO frames
+ * See catapult_spec.pdf for more details
+ */
+#define TXA0_TSO_TCP_SEQ_REG(_num) \
+ (TXA0_BLK_REG_ADDR + 0x020 + ((_num) << 2))
+
+#define TXA1_TSO_TCP_SEQ_REG(_num) \
+ (TXA1_BLK_REG_ADDR + 0x020 + ((_num) << 2))
+
+/**
+ * TSO IP ID # Registers (RO)
+ * Total 8 (for 8 queues)
+ * Holds the last IP ID for TSO frames
+ * See catapult_spec.pdf for more details
+ */
+#define TXA0_TSO_IP_INFO_REG(_num) \
+ (TXA0_BLK_REG_ADDR + 0x040 + ((_num) << 2))
+
+#define TXA1_TSO_IP_INFO_REG(_num) \
+ (TXA1_BLK_REG_ADDR + 0x040 + ((_num) << 2))
+
+/**
+ * RXA Block Register Address Offset from BAR0
+ * RXA0 Range : 0x21800 - 0x21BFF
+ * RXA1 Range : 0x21C00 - 0x21FFF
+ */
+#define RXA0_BLK_REG_ADDR 0x00021800
+#define RXA1_BLK_REG_ADDR 0x00021C00
+
+/**
+ * RXA Registers
+ */
+#define RXA0_CTL_REG (RXA0_BLK_REG_ADDR + 0x040)
+#define RXA1_CTL_REG (RXA1_BLK_REG_ADDR + 0x040)
+
+/**
+ * PPLB Block Register Address Offset from BAR0
+ * PPLB0 Range : 0x22000 - 0x223FF
+ * PPLB1 Range : 0x22400 - 0x227FF
+ */
+#define PLB0_BLK_REG_ADDR 0x00022000
+#define PLB1_BLK_REG_ADDR 0x00022400
+
+/**
+ * PLB Registers
+ */
+/**
+ * Holds RL timer used time stamps in RLT tagged frames
+ */
+#define PLB0_ECM_TIMER_REG (PLB0_BLK_REG_ADDR + 0x05C)
+#define PLB1_ECM_TIMER_REG (PLB1_BLK_REG_ADDR + 0x05C)
+/**
+ * Controls the rate-limiter on each of the priority class
+ */
+#define PLB0_RL_CTL (PLB0_BLK_REG_ADDR + 0x060)
+#define PLB1_RL_CTL (PLB1_BLK_REG_ADDR + 0x060)
+/**
+ * Max byte register, total 8, 0-7
+ * see catapult_spec.pdf for details
+ */
+#define PLB0_RL_MAX_BC(_num) \
+ (PLB0_BLK_REG_ADDR + 0x064 + ((_num) << 2))
+#define PLB1_RL_MAX_BC(_num) \
+ (PLB1_BLK_REG_ADDR + 0x064 + ((_num) << 2))
+/**
+ * RL Time Unit Register for priority 0-7
+ * 4 bits per priority
+ * (2^rl_unit)*1us is the actual time period
+ */
+#define PLB0_RL_TU_PRIO (PLB0_BLK_REG_ADDR + 0x084)
+#define PLB1_RL_TU_PRIO (PLB1_BLK_REG_ADDR + 0x084)
+/**
+ * RL byte count register,
+ * bytes transmitted in (rl_unit*1)us time period
+ * 1 per priority, 8 in all, 0-7.
+ */
+#define PLB0_RL_BYTE_CNT(_num) \
+ (PLB0_BLK_REG_ADDR + 0x088 + ((_num) << 2))
+#define PLB1_RL_BYTE_CNT(_num) \
+ (PLB1_BLK_REG_ADDR + 0x088 + ((_num) << 2))
+/**
+ * RL Min factor register
+ * 2 bits per priority,
+ * 4 factors possible: 1, 0.5, 0.25, 0
+ * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1
+ */
+#define PLB0_RL_MIN_REG (PLB0_BLK_REG_ADDR + 0x0A8)
+#define PLB1_RL_MIN_REG (PLB1_BLK_REG_ADDR + 0x0A8)
+/**
+ * RL Max factor register
+ * 2 bits per priority,
+ * 4 factors possible: 1, 0.5, 0.25, 0
+ * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1
+ */
+#define PLB0_RL_MAX_REG (PLB0_BLK_REG_ADDR + 0x0AC)
+#define PLB1_RL_MAX_REG (PLB1_BLK_REG_ADDR + 0x0AC)
+
+/**
+ * MAC SERDES Address Paging register
+ */
+#define PLB0_EMS_ADD_REG (PLB0_BLK_REG_ADDR + 0xD0)
+#define PLB1_EMS_ADD_REG (PLB1_BLK_REG_ADDR + 0xD0)
+
+/**
+ * LL EMS Registers
+ */
+#define LL_EMS0_BLK_REG_ADDR 0x00026800
+#define LL_EMS1_BLK_REG_ADDR 0x00026C00
+
+/**
+ * BPC Block Register Address Offset from BAR0
+ * BPC0 Range : 0x23000 - 0x233FF
+ * BPC1 Range : 0x23400 - 0x237FF
+ */
+#define BPC0_BLK_REG_ADDR 0x00023000
+#define BPC1_BLK_REG_ADDR 0x00023400
+
+/**
+ * BPC Registers
+ */
+ /* TODO */
+/**
+ * PMM Block Register Address Offset from BAR0
+ * PMM0 Range : 0x23800 - 0x23BFF
+ * PMM1 Range : 0x23C00 - 0x23FFF
+ */
+#define PMM0_BLK_REG_ADDR 0x00023800
+#define PMM1_BLK_REG_ADDR 0x00023C00
+/**
+ * PMM Registers
+ */
+ /* TODO */
+
+/**
+ * HQM Block Register Address Offset from BAR0
+ * HQM0 Range : 0x24000 - 0x243FF
+ * HQM1 Range : 0x24400 - 0x247FF
+ */
+#define HQM0_BLK_REG_ADDR 0x00024000
+#define HQM1_BLK_REG_ADDR 0x00024400
+/**
+ * HQM Control Register
+ * Controls some aspects of IB
+ * See catapult_spec.pdf for details
+ */
+#define HQM0_CTL_REG (HQM0_BLK_REG_ADDR + 0x000)
+#define HQM1_CTL_REG (HQM1_BLK_REG_ADDR + 0x000)
+/**
+ * HQM Stop Q Semaphore Registers.
+ * Only one Queue resource can be stopped at
+ * any given time. This register controls access
+ * to the single stop Q resource.
+ * See catapult_spec.pdf for details
+ */
+#define HQM0_RXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x028)
+#define HQM0_TXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x02C)
+#define HQM1_RXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x028)
+#define HQM1_TXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x02C)
+
+/**
+ * LUT Block Register Address Offset from BAR0
+ * LUT0 Range : 0x25800 - 0x25BFF
+ * LUT1 Range : 0x25C00 - 0x25FFF
+ */
+#define LUT0_BLK_REG_ADDR 0x00025800
+#define LUT1_BLK_REG_ADDR 0x00025C00
+/**
+ * LUT Registers
+ * See catapult_spec.pdf for details
+ */
+#define LUT0_ERR_STS (LUT0_BLK_REG_ADDR + 0x000)
+#define LUT1_ERR_STS (LUT1_BLK_REG_ADDR + 0x000)
+#define LUT0_SET_ERR_STS (LUT0_BLK_REG_ADDR + 0x004)
+#define LUT1_SET_ERR_STS (LUT1_BLK_REG_ADDR + 0x004)
+
+/**
+ * LDM (Link Layer DMA) Registers
+ */
+ /* TODO */
+
+/**
+ * SGD (Scatter/Gather Database) Registers
+ */
+ /* TODO */
+
+/**
+ * TRC (Debug/Trace) Register Offset from BAR0
+ * Range : 0x26000 -- 0x263FFF
+ */
+#define TRC_BLK_REG_ADDR 0x00026000
+/**
+ * TRC Registers
+ * See catapult_spec.pdf for details of each
+ */
+#define TRC_CTL_REG (TRC_BLK_REG_ADDR + 0x000)
+#define TRC_MODS_REG (TRC_BLK_REG_ADDR + 0x004)
+#define TRC_TRGC_REG (TRC_BLK_REG_ADDR + 0x008)
+#define TRC_CNT1_REG (TRC_BLK_REG_ADDR + 0x010)
+#define TRC_CNT2_REG (TRC_BLK_REG_ADDR + 0x014)
+#define TRC_NXTS_REG (TRC_BLK_REG_ADDR + 0x018)
+#define TRC_DIRR_REG (TRC_BLK_REG_ADDR + 0x01C)
+/**
+ * TRC Trigger match filters, total 10
+ * Determines the trigger condition
+ */
+#define TRC_TRGM_REG(_num) \
+ (TRC_BLK_REG_ADDR + 0x040 + ((_num) << 2))
+/**
+ * TRC Next State filters, total 10
+ * Determines the next state conditions
+ */
+#define TRC_NXTM_REG(_num) \
+ (TRC_BLK_REG_ADDR + 0x080 + ((_num) << 2))
+/**
+ * TRC Store Match filters, total 10
+ * Determines the store conditions
+ */
+#define TRC_STRM_REG(_num) \
+ (TRC_BLK_REG_ADDR + 0x0C0 + ((_num) << 2))
+
+
+
+/*
+ * DOORBELLS ACCESS
+ */
+
+/**
+ * Catapult doorbells
+ * Each doorbell-queue set has
+ * 1 RxQ, 1 TxQ, 2 IBs in that order
+ * Size of each entry in 32 bytes, even though only 1 word
+ * is used. For Non-VM case each doorbell-q set is
+ * separated by 128 bytes, for VM case it is separated
+ * by 4K bytes
+ * Non VM case Range : 0x38000 - 0x39FFF
+ * VM case Range : 0x100000 - 0x11FFFF
+ * The range applies to both HQMs
+ */
+#define HQM_DOORBELL_BLK_BASE_ADDR 0x00038000
+#define HQM_DOORBELL_VM_BLK_BASE_ADDR 0x00100000
+
+/*
+ * MEMORY ACCESS
+ */
+
+/**
+ * Catapult H/W Block Memory Access Address
+ * To the host a memory space of 32K (page) is visible
+ * at a time. The address range is from 0x08000 to 0x0FFFF
+ */
+#define HW_BLK_HOST_MEM_ADDR 0x08000
+
+/**
+ * Catapult LUT Memory Access Page Numbers
+ * Range : LUT0 0xa0-0xa1
+ * LUT1 0xa2-0xa3
+ */
+#define LUT0_MEM_BLK_BASE_PG_NUM 0x000000A0
+#define LUT1_MEM_BLK_BASE_PG_NUM 0x000000A2
+
+/**
+ * Catapult RxFn Database Memory Block Base Offset
+ *
+ * The Rx function database exists in LUT block.
+ * In PCIe space this is accessible as a 256x32
+ * bit block. Each entry in this database is 4
+ * (4 byte) words. Max. entries is 64.
+ * Address of an entry corresponding to a function
+ * = base_addr + (function_no. * 16)
+ */
+#define RX_FNDB_RAM_BASE_OFFSET 0x0000B400
+
+/**
+ * Catapult TxFn Database Memory Block Base Offset Address
+ *
+ * The Tx function database exists in LUT block.
+ * In PCIe space this is accessible as a 64x32
+ * bit block. Each entry in this database is 1
+ * (4 byte) word. Max. entries is 64.
+ * Address of an entry corresponding to a function
+ * = base_addr + (function_no. * 4)
+ */
+#define TX_FNDB_RAM_BASE_OFFSET 0x0000B800
+
+/**
+ * Catapult Unicast CAM Base Offset Address
+ *
+ * Exists in LUT memory space.
+ * Shared by both the LL & FCoE driver.
+ * Size is 256x48 bits; mapped to PCIe space
+ * 512x32 bit blocks. For each address, bits
+ * are written in the order : [47:32] and then
+ * [31:0].
+ */
+#define UCAST_CAM_BASE_OFFSET 0x0000A800
+
+/**
+ * Catapult Unicast RAM Base Offset Address
+ *
+ * Exists in LUT memory space.
+ * Shared by both the LL & FCoE driver.
+ * Size is 256x9 bits.
+ */
+#define UCAST_RAM_BASE_OFFSET 0x0000B000
+
+/**
+ * Catapult Mulicast CAM Base Offset Address
+ *
+ * Exists in LUT memory space.
+ * Shared by both the LL & FCoE driver.
+ * Size is 256x48 bits; mapped to PCIe space
+ * 512x32 bit blocks. For each address, bits
+ * are written in the order : [47:32] and then
+ * [31:0].
+ */
+#define MCAST_CAM_BASE_OFFSET 0x0000A000
+
+/**
+ * Catapult VLAN RAM Base Offset Address
+ *
+ * Exists in LUT memory space.
+ * Size is 4096x66 bits; mapped to PCIe space as
+ * 8192x32 bit blocks.
+ * All the 4K entries are within the address range
+ * 0x0000 to 0x8000, so in the first LUT page.
+ */
+#define VLAN_RAM_BASE_OFFSET 0x00000000
+
+/**
+ * Catapult Tx Stats RAM Base Offset Address
+ *
+ * Exists in LUT memory space.
+ * Size is 1024x33 bits;
+ * Each Tx function has 64 bytes of space
+ */
+#define TX_STATS_RAM_BASE_OFFSET 0x00009000
+
+/**
+ * Catapult Rx Stats RAM Base Offset Address
+ *
+ * Exists in LUT memory space.
+ * Size is 1024x33 bits;
+ * Each Rx function has 64 bytes of space
+ */
+#define RX_STATS_RAM_BASE_OFFSET 0x00008000
+/**
+ * Catapult RXA Memory Access Page Numbers
+ */
+#define RXA0_MEM_BLK_BASE_PG_NUM 0x0000008C
+#define RXA1_MEM_BLK_BASE_PG_NUM 0x0000008D
+
+/**
+ * Catapult Multicast Vector Table Base Offset Address
+ *
+ * Exists in RxA memory space.
+ * Organized as 512x65 bit block.
+ * However for each entry 16 bytes allocated (power of 2)
+ * Total size 512*16 bytes.
+ * There are two logical divisions, 256 entries each :
+ * a) Entries 0x00 to 0xff (256) -- Approx. MVT
+ * Offset 0x000 to 0xFFF
+ * b) Entries 0x100 to 0x1ff (256) -- Exact MVT
+ * Offsets 0x1000 to 0x1FFF
+ */
+#define MCAST_APPROX_MVT_BASE_OFFSET 0x00000000
+#define MCAST_EXACT_MVT_BASE_OFFSET 0x00001000
+/**
+ * Catapult RxQ Translate Table (RIT) Base Offset Address
+ *
+ * Exists in RxA memory space
+ * Total no. of entries 64
+ * Each entry is 1 (4 byte) word.
+ * 31:12 -- Reserved
+ * 11:0 -- Two 6 bit RxQ Ids
+ */
+#define FUNCTION_TO_RXQ_TRANSLATE 0x00002000
+
+/**
+ * Catapult RxAdm (RAD) Memory Access Page Numbers
+ */
+#define RAD0_MEM_BLK_BASE_PG_NUM 0x00000086
+#define RAD1_MEM_BLK_BASE_PG_NUM 0x00000087
+
+/**
+ * Catapult RSS Table Base Offset Address
+ *
+ * Exists in RAD memory space.
+ * Each entry is 352 bits, but alligned on
+ * 64 byte (512 bit) boundary. Accessed
+ * 4 byte words, the whole entry can be
+ * broken into 11 word accesses.
+ */
+#define RSS_TABLE_BASE_OFFSET 0x00000800
+
+/**
+ * Catapult CPQ Block Page Number
+ * This value is written to the page number registers
+ * to access the memory associated with the mailboxes.
+ */
+#define CPQ_BLK_PG_NUM 0x00000005
+
+/**
+ * Clarification :
+ * LL functions are 2 & 3; can HostFn0/HostFn1
+ * <-> LPU0/LPU1 memories be used ?
+ */
+/**
+ * Catapult HostFn0/HostFn1 to LPU0/LPU1 Mbox memory
+ * Per catapult_spec.pdf, the offset of the mbox
+ * memory is in the register space at an offset of 0x200
+ */
+#define CPQ_BLK_REG_MBOX_ADDR (CPQ_BLK_REG_ADDR + 0x200)
+
+#define HOSTFN_LPU_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x000)
+/**
+ * Catapult LPU0/LPU1 to HostFn0/HostFn1 Mbox memory
+ */
+#define LPU_HOSTFN_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x080)
+
+/**
+ * Catapult HQM Block Page Number
+ * This is written to the page number register for
+ * the appropriate function to access the memory
+ * associated with HQM
+ */
+#define HQM0_BLK_PG_NUM 0x00000096
+#define HQM1_BLK_PG_NUM 0x00000097
+
+/**
+ * Note that TxQ and RxQ entries are interlaced
+ * the HQM memory, i.e RXQ0, TXQ0, RXQ1, TXQ1.. etc.
+ */
+
+#define HQM_RXTX_Q_RAM_BASE_OFFSET 0x00004000
+
+/**
+ * CQ Memory
+ * Exists in HQM Memory space
+ * Each entry is 16 (4 byte) words of which
+ * only 12 words are used for configuration
+ * Total 64 entries per HQM memory space
+ */
+#define HQM_CQ_RAM_BASE_OFFSET 0x00006000
+
+/**
+ * Interrupt Block (IB) Memory
+ * Exists in HQM Memory space
+ * Each entry is 8 (4 byte) words of which
+ * only 5 words are used for configuration
+ * Total 128 entries per HQM memory space
+ */
+#define HQM_IB_RAM_BASE_OFFSET 0x00001000
+
+/**
+ * Index Table (IT) Memory
+ * Exists in HQM Memory space
+ * Each entry is 1 (4 byte) word which
+ * is used for configuration
+ * Total 128 entries per HQM memory space
+ */
+#define HQM_INDX_TBL_RAM_BASE_OFFSET 0x00002000
+
+/**
+ * PSS Block Memory Page Number
+ * This is written to the appropriate page number
+ * register to access the CPU memory.
+ * Also known as the PSS secondary memory (SMEM).
+ * Range : 0x180 to 0x1CF
+ * See catapult_spec.pdf for details
+ */
+#define PSS_BLK_PG_NUM 0x00000180
+
+/**
+ * Offsets of different instances of PSS SMEM
+ * 2.5M of continuous 1T memory space : 2 blocks
+ * of 1M each (32 pages each, page=32KB) and 4 smaller
+ * blocks of 128K each (4 pages each, page=32KB)
+ * PSS_LMEM_INST0 is used for firmware download
+ */
+#define PSS_LMEM_INST0 0x00000000
+#define PSS_LMEM_INST1 0x00100000
+#define PSS_LMEM_INST2 0x00200000
+#define PSS_LMEM_INST3 0x00220000
+#define PSS_LMEM_INST4 0x00240000
+#define PSS_LMEM_INST5 0x00260000
+
+#endif /* __BNA_HWREG_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/bna_intr.h net-next-2.6-mod/drivers/net/bna/bna_intr.h
--- net-next-2.6-orig/drivers/net/bna/bna_intr.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bna_intr.h 2009-11-12 19:03:38.944355000 -0800
@@ -0,0 +1,90 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ *
+ * File for interrupt macros and functions
+ */
+
+#ifndef __BNA_INTR_H__
+#define __BNA_INTR_H__
+
+static inline void
+bna_intx_disable(struct bna_dev *dev, u32 * cur_mask)
+{
+ /* Store the original mask */
+ *cur_mask = bna_reg_read(dev->regs.fn_int_mask);
+ bna_reg_write(dev->regs.fn_int_mask, 0xffffffff);
+}
+
+#define bna_intx_enable(dev, new_mask) \
+ bna_reg_write((dev)->regs.fn_int_mask, (new_mask))
+
+#define bna_mbox_intr_disable(dev) \
+ bna_reg_write((dev)->regs.fn_int_mask, \
+ (bna_reg_read((dev)->regs.fn_int_mask) | \
+ (__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)))
+
+#define bna_mbox_intr_enable(dev) \
+ bna_reg_write((dev)->regs.fn_int_mask, \
+ (bna_reg_read((dev)->regs.fn_int_mask) & \
+ ~(__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)))
+
+static inline void
+bna_intr_status_get(struct bna_dev *dev, u32 * status)
+{
+ *status = bna_reg_read(dev->regs.fn_int_status);
+ /*
+ * Clear the status bits before returning
+ * But do not touch the mailbox bits as yet
+ */
+ /* Write a '1' to clear the required bits */
+ if (*status) {
+ bna_reg_write(dev->regs.fn_int_status,
+ *status & ~(__LPU02HOST_MBOX0_STATUS_BITS |
+ __LPU02HOST_MBOX1_STATUS_BITS |
+ __LPU12HOST_MBOX0_STATUS_BITS |
+ __LPU12HOST_MBOX1_STATUS_BITS));
+ }
+}
+
+#define bna_intr_status_get_no_clr(dev, status) \
+ (*(status) = bna_reg_read((dev)->regs.fn_int_status))
+
+#define bna_intr_mask_get(dev, mask) \
+ (*mask) = bna_reg_read((dev)->regs.fn_int_mask)
+
+#define bna_intr_ack(dev, intr_bmap) \
+ bna_reg_write((dev)->regs.fn_int_status, (intr_bmap))
+
+#define bna_ib_intx_disable(dev, ib_id) \
+ bna_reg_write((dev)->regs.fn_int_mask, \
+ bna_reg_read((dev)->regs.fn_int_mask) | \
+ (1 << (ib_id)))
+
+#define bna_ib_intx_enable(dev, ib_id) \
+ bna_reg_write((dev)->regs.fn_int_mask, \
+ bna_reg_read((dev)->regs.fn_int_mask) & \
+ ~(1 << (ib_id)))
+
+extern const struct bna_chip_regs_offset reg_offset[];
+#define bna_mbox_msix_idx_set(dev, msix_vector) \
+ bna_reg_write((dev)->bar0 + reg_offset[(dev)->pci_fn].msix_idx, \
+ ((msix_vector) & 0x000001ff))
+
+
+#endif /* __BNA_INTR_H__ */
^ permalink raw reply
* Subject: [PATCH 2/6] bna: Brocade 10Gb Ethernet device driver
From: Rasesh Mody @ 2009-11-13 3:46 UTC (permalink / raw)
To: netdev; +Cc: adapter_linux_open_src_team
From: Rasesh Mody <rmody@brocade.com>
This is patch 2/6 which contains linux driver source for
Brocade's BR1010/BR1020 10Gb CEE capable ethernet adapter.
Source is based against net-next-2.6.
We wish this patch to be considered for inclusion in net-next-2.6
Signed-off-by: Rasesh Mody <rmody@brocade.com>
---
bfa_timer.c | 93 ++
bfad_fwimg.c | 96 ++
bna_fn.c | 1967 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
bna_queue.c | 451 +++++++++++++
bnad_ethtool.c | 1117 ++++++++++++++++++++++++++++++++
5 files changed, 3724 insertions(+)
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_timer.c net-next-2.6-mod/drivers/net/bna/bfa_timer.c
--- net-next-2.6-orig/drivers/net/bna/bfa_timer.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_timer.c 2009-11-12 19:03:38.497343000 -0800
@@ -0,0 +1,93 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#include <bfa_timer.h>
+#include <cs/bfa_debug.h>
+
+void
+bfa_timer_init(struct bfa_timer_mod *mod)
+{
+ INIT_LIST_HEAD(&mod->timer_q);
+}
+
+void
+bfa_timer_beat(struct bfa_timer_mod *mod)
+{
+ struct list_head *qh = &mod->timer_q;
+ struct list_head *qe, *qe_next;
+ struct bfa_timer *elem;
+ struct list_head timedout_q;
+
+ INIT_LIST_HEAD(&timedout_q);
+
+ qe = bfa_q_next(qh);
+
+ while (qe != qh) {
+ qe_next = bfa_q_next(qe);
+
+ elem = (struct bfa_timer *) qe;
+ if (elem->timeout <= BFA_TIMER_FREQ) {
+ elem->timeout = 0;
+ list_del(&elem->qe);
+ list_add_tail(&elem->qe, &timedout_q);
+ } else {
+ elem->timeout -= BFA_TIMER_FREQ;
+ }
+
+ qe = qe_next; /* go to next elem */
+ }
+
+ /*
+ * Pop all the timeout entries
+ */
+ while (!list_empty(&timedout_q)) {
+ bfa_q_deq(&timedout_q, &elem);
+ elem->timercb(elem->arg);
+ }
+}
+
+/**
+ * Should be called with lock protection
+ */
+void
+bfa_timer_begin(struct bfa_timer_mod *mod, struct bfa_timer *timer,
+ void (*timercb) (void *), void *arg, unsigned int timeout)
+{
+
+ bfa_assert(timercb != NULL);
+ bfa_assert(!bfa_q_is_on_q(&mod->timer_q, timer));
+
+ timer->timeout = timeout;
+ timer->timercb = timercb;
+ timer->arg = arg;
+
+ list_add_tail(&timer->qe, &mod->timer_q);
+}
+
+/**
+ * Should be called with lock protection
+ */
+void
+bfa_timer_stop(struct bfa_timer *timer)
+{
+ bfa_assert(!list_empty(&timer->qe));
+
+ list_del(&timer->qe);
+}
diff -ruP net-next-2.6-orig/drivers/net/bna/bfad_fwimg.c net-next-2.6-mod/drivers/net/bna/bfad_fwimg.c
--- net-next-2.6-orig/drivers/net/bna/bfad_fwimg.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfad_fwimg.c 2009-11-12 19:03:38.507342000 -0800
@@ -0,0 +1,96 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+/**
+ * bfad_fwimg.c Linux driver PCI interface module.
+ */
+#include <cna.h>
+#include <defs/bfa_defs_version.h>
+#include <defs/bfa_defs_pci.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <asm/fcntl.h>
+#include <linux/pci.h>
+#include <linux/firmware.h>
+#include <bfa_fwimg_priv.h>
+
+u32 bfi_image_ct_size;
+u32 bfi_image_cb_size;
+u32 *bfi_image_ct;
+u32 *bfi_image_cb;
+
+
+#define BFAD_FW_FILE_CT "ctfw.bin"
+#define BFAD_FW_FILE_CB "cbfw.bin"
+
+u32 *
+bfad_read_firmware(struct pci_dev *pdev, u32 **bfi_image,
+ u32 *bfi_image_size, char *fw_name)
+{
+ const struct firmware *fw;
+
+ if (request_firmware(&fw, fw_name, &pdev->dev)) {
+ printk(KERN_ALERT "Can't locate firmware %s\n", fw_name);
+ goto error;
+ }
+
+ *bfi_image = vmalloc(fw->size);
+ if (NULL == *bfi_image) {
+ printk(KERN_ALERT "Fail to allocate buffer for fw image "
+ "size=%x!\n", (u32) fw->size);
+ goto error;
+ }
+
+ memcpy(*bfi_image, fw->data, fw->size);
+ *bfi_image_size = fw->size/sizeof(u32);
+
+ return *bfi_image;
+
+error:
+ return NULL;
+}
+
+u32 *
+bfad_get_firmware_buf(struct pci_dev *pdev)
+{
+ if (pdev->device == BFA_PCI_DEVICE_ID_CT) {
+ if (bfi_image_ct_size == 0)
+ bfad_read_firmware(pdev, &bfi_image_ct,
+ &bfi_image_ct_size, BFAD_FW_FILE_CT);
+ return bfi_image_ct;
+ } else {
+ if (bfi_image_cb_size == 0)
+ bfad_read_firmware(pdev, &bfi_image_cb,
+ &bfi_image_cb_size, BFAD_FW_FILE_CB);
+ return bfi_image_cb;
+ }
+}
+
+u32 *
+bfi_image_ct_get_chunk(u32 off)
+{ return (u32 *)(bfi_image_ct + off); }
+
+u32 *
+bfi_image_cb_get_chunk(u32 off)
+{ return (u32 *)(bfi_image_cb + off); }
+
diff -ruP net-next-2.6-orig/drivers/net/bna/bna_fn.c net-next-2.6-mod/drivers/net/bna/bna_fn.c
--- net-next-2.6-orig/drivers/net/bna/bna_fn.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bna_fn.c 2009-11-12 19:03:38.546340000 -0800
@@ -0,0 +1,1967 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * @file bna_fn.c BNA Rx and Tx Function Management
+ */
+
+#include <cna.h>
+#include "bna.h"
+#include "bna_hwreg.h"
+#include "bna_priv.h"
+#include <bfi/bfi_ll.h>
+#include <bfi/bfi_cee.h>
+
+
+/*
+ * 12 bit Max VLAN Id mask used to
+ * wrap overflowing VLANs wraps around the
+ * max value of 4095
+ */
+#define BNA_MAX_VLAN_ID_MASK 0x00000fff
+
+const struct bna_chip_regs_offset reg_offset[] =
+ { {HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS,
+ HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0},
+{HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS,
+ HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1},
+{HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS,
+ HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2},
+{HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS,
+ HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3},
+};
+const struct mac bna_bcast_addr = { {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
+const struct mac bna_zero_addr = { {0x0, 0x0, 0x0, 0x0, 0x0, 0x0} };
+
+/**
+ * bna_init()
+ *
+ * Called by the driver during initialization. The driver is
+ * expected to allocate struct bna_dev structure for the BNA layer.
+ *
+ * @param[in] bar0 - BAR0 value
+ * @param[in] bna_handle - pointer to BNA device structure
+ * allocated by the calling driver
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void
+bna_init(struct bna_dev *dev, void *bar0, void *stats,
+ struct bna_dma_addr stats_dma, struct bfa_trc_mod *trcmod,
+ struct bfa_log_mod *logmod)
+{
+ u32 pcifn;
+
+ memset(dev, 0, sizeof(struct bna_dev));
+
+ dev->trcmod = trcmod;
+ dev->logmod = logmod;
+
+ dev->bar0 = (u8 *) bar0;
+ dev->hw_stats = (struct bfi_ll_stats *)stats;
+ dev->hw_stats_dma.msb = stats_dma.msb;
+ dev->hw_stats_dma.lsb = stats_dma.lsb;
+
+ dev->rxf_promiscuous_id = BNA_RXF_ID_NONE;
+ dev->rxf_default_id = BNA_RXF_ID_NONE;
+
+ pcifn = bna_reg_read(dev->bar0 + FNC_ID_REG);
+ pcifn = bna_reg_read(dev->bar0 + FNC_ID_REG);
+ BNA_ASSERT(pcifn <= 3);
+
+ dev->regs.page_addr = dev->bar0 + reg_offset[pcifn].page_addr;
+ dev->regs.fn_int_status = dev->bar0 + reg_offset[pcifn].fn_int_status;
+ dev->regs.fn_int_mask = dev->bar0 + reg_offset[pcifn].fn_int_mask;
+
+ if (pcifn < 3)
+ dev->port = 0;
+ else
+ dev->port = 1;
+
+ dev->pci_fn = pcifn;
+
+ dev->ioc_disable_pending = 0;
+}
+
+/**
+ * bna_uninit()
+ *
+ * Called by the driver during removal/unload.
+ *
+ * @param[in] bna_handle - pointer to BNA device structure
+ * allocated by the calling driver
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_uninit(void *bna_handle)
+{
+ return BNA_OK;
+}
+
+/**
+ * bna_rit_config_set()
+ *
+ * Loads RIT entries "rit" into RIT starting from RIT index "rit_id".
+ * Care must be taken not to overlap regions within the RIT.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rit_offset - offset into the RIT
+ * @param[in] rit - RIT entry
+ * @param[in] rit_size - size of RIT entry
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void
+bna_rit_config_set(struct bna_dev *dev, unsigned int rit_offset,
+ const struct bna_rit_entry rit[], unsigned int rit_size)
+{
+ int i;
+
+ struct bna_rit_mem *rit_mem;
+
+
+ BNA_ASSERT(BNA_POWER_OF_2(rit_size));
+ BNA_ASSERT((rit_offset + rit_size) < BNA_RIT_SIZE);
+
+ rit_mem = (struct bna_rit_mem *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, FUNCTION_TO_RXQ_TRANSLATE);
+
+ dev->rit_size[rit_offset] = rit_size;
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(RXA0_MEM_BLK_BASE_PG_NUM + dev->port,
+ FUNCTION_TO_RXQ_TRANSLATE));
+
+ for (i = 0; i < rit_size; i++) {
+ bna_mem_writew(&rit_mem[i + rit_offset],
+ rit[i].large_rxq_id << 6 | rit[i].small_rxq_id);
+ }
+}
+
+/**
+ * bna_rxf_config_set()
+ *
+ * For RxF "rxf_id", it configures RxF based on "cfg_ptr", and indicates
+ * to the statistics collector to collect statistics for this Rx-Function.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] cfg_ptr - pointer to rx-function configuration.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_rxf_config_set(struct bna_dev *dev, unsigned int rxf_id,
+ const struct bna_rxf_config *cfg_ptr)
+{
+ u32 i;
+
+ struct bna_rss_mem *rss_mem;
+ struct bna_rx_fndb_ram *rx_fndb_ram;
+
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ rss_mem = (struct bna_rss_mem *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, RSS_TABLE_BASE_OFFSET);
+ rx_fndb_ram = (struct bna_rx_fndb_ram *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, RX_FNDB_RAM_BASE_OFFSET);
+
+ /* Need to revisit, don't do this check */
+ if (((cfg_ptr->flags & BNA_RXF_CF_SM_LG_RXQ)) &&
+ (cfg_ptr->hds.type == 1)) {
+ /* HDS and small-large RxQs are mutually exclusive */
+ return BNA_FAIL;
+ }
+
+ if (cfg_ptr->flags & BNA_RXF_CF_RSS_ENABLE) {
+ BNA_ASSERT(cfg_ptr->rss.hash_mask ==
+ dev->rit_size[cfg_ptr->rit_offset] - 1);
+
+ /* configure RSS Table */
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(RAD0_MEM_BLK_BASE_PG_NUM +
+ dev->port,
+ RSS_TABLE_BASE_OFFSET));
+
+ /* temporarily disable RSS, while hash value is being written */
+ bna_mem_writew(&rss_mem[0].type_n_hash, 0);
+
+ for (i = 0; i < BNA_RSS_HASH_KEY_LEN; i++) {
+ bna_mem_writew(&rss_mem[0].
+ hash_key[(BNA_RSS_HASH_KEY_LEN - 1) - i],
+ htonl(cfg_ptr->rss.
+ toeplitz_hash_key[i]));
+ }
+
+ bna_mem_writew(&rss_mem[0].type_n_hash,
+ cfg_ptr->rss.type | cfg_ptr->rss.hash_mask);
+
+ }
+ /* configure RxF based on "cfg_ptr" */
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2),
+ RX_FNDB_RAM_BASE_OFFSET));
+
+ /* we always use RSS table 0 */
+ bna_mem_writew(&rx_fndb_ram[rxf_id].rss_prop,
+ cfg_ptr->flags & BNA_RXF_CF_RSS_ENABLE);
+
+ /* small large buffer enable/disable */
+ bna_mem_writew(&rx_fndb_ram[rxf_id].size_routing_props,
+ (cfg_ptr->flags & BNA_RXF_CF_SM_LG_RXQ) | 0x80);
+
+ /* RIT offset, HDS forced offset, multicast RxQ Id */
+ bna_mem_writew(&rx_fndb_ram[rxf_id].rit_hds_mcastq,
+ (cfg_ptr->rit_offset << 16) | (cfg_ptr->hds.
+ forced_offset << 8) |
+ (cfg_ptr->hds.type & BNA_HDS_FORCED) | cfg_ptr->
+ mcast_rxq_id);
+
+ /*
+ * Default vlan tag, default function enable, strip vlan bytes,
+ * HDS type, header size
+ */
+ bna_mem_writew(&rx_fndb_ram[rxf_id].control_flags,
+ (cfg_ptr->default_vlan << 16) |
+ (cfg_ptr->flags &
+ (BNA_RXF_CF_DEFAULT_VLAN |
+ BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE |
+ BNA_RXF_CF_VLAN_STRIP)) |
+ (cfg_ptr->hds.type & ~BNA_HDS_FORCED) | cfg_ptr->hds.
+ header_size);
+
+ /* turn on statistics collection for this RxF */
+ dev->rxf_active |= ((u64) 1 << rxf_id);
+ return BNA_OK;
+}
+
+/**
+ * bna_rxf_config_clear()
+ *
+ * For RxF "rxf_id", it clear its configuration and indicates to the
+ * statistics collector to stop collecting statistics for this
+ * Rx-Function.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ *
+ * @return void
+ */
+void
+bna_rxf_config_clear(struct bna_dev *dev, unsigned int rxf_id)
+{
+ struct bna_rx_fndb_ram *rx_fndb_ram;
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ rx_fndb_ram = (struct bna_rx_fndb_ram *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, RX_FNDB_RAM_BASE_OFFSET);
+
+ /* clear configuration of RxF base */
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2),
+ RX_FNDB_RAM_BASE_OFFSET));
+
+ /* we always use RSS table 0 */
+ bna_mem_writew(&rx_fndb_ram[rxf_id].rss_prop, 0);
+
+ /* small large buffer enable/disable */
+ bna_mem_writew(&rx_fndb_ram[rxf_id].size_routing_props, 0x80);
+
+ /* RIT offset, HDS forced offset, multicast RxQ Id */
+ bna_mem_writew(&rx_fndb_ram[rxf_id].rit_hds_mcastq, 0);
+
+ /*
+ * default vlan tag, default function enable, strip vlan bytes,
+ * HDS type, header size
+ */
+ bna_mem_writew(&rx_fndb_ram[rxf_id].control_flags, 0);
+
+ /* turn off statistics collection for this RxF */
+ dev->rxf_active &= ~((u64) 1 << rxf_id);
+}
+
+/**
+ * bna_rxf_disable()
+ *
+ * Disables the Rx Function without clearing the configuration
+ * Also disables collection of statistics.
+ *
+ * @param[in] dev - Pointer to BNA device handle
+ * @param[in] rxf_id - Id of the Rx Function to be disabled
+ *
+ * @return BNA_OK if mbox command succeeded, else BNA_FAIL
+ */
+enum bna_status_e
+bna_rxf_disable(struct bna_dev *dev, unsigned int rxf_id)
+{
+ struct bfi_ll_rxf_multi_req ll_req;
+ u64 bit_mask = 1 << rxf_id;
+ enum bna_status_e status;
+
+ bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
+ ll_req.rxf_id_mask[0] = htonl((u32) bit_mask);
+ ll_req.rxf_id_mask[1] = htonl((u32) (bit_mask >> 32));
+ ll_req.enable = 0;
+
+ status = bna_mbox_send(dev, &ll_req, sizeof(ll_req), dev->cbarg);
+ if (!status)
+ dev->rxf_active &= ~bit_mask;
+ return status;
+}
+
+
+/* TODO : Delete when Windows migration is complete */
+void
+bna_rxf_disable_old(struct bna_dev *dev, unsigned int rxf_id)
+{
+ struct bna_rx_fndb_ram *rx_fndb_ram;
+ u32 ctl_flags;
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ /* Clear the vlan table first, before writing to the Rx Fn DB */
+ bna_rxf_vlan_del_all(dev, rxf_id);
+
+ rx_fndb_ram = (struct bna_rx_fndb_ram *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, RX_FNDB_RAM_BASE_OFFSET);
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2),
+ RX_FNDB_RAM_BASE_OFFSET));
+
+ ctl_flags = bna_mem_readw(&rx_fndb_ram[rxf_id].control_flags);
+
+ /* Enable setting of the default vlan tag for untagged packets */
+ /* Don't need to store these already there in the BNA config */
+ ctl_flags |= BNA_RXF_CF_DEFAULT_VLAN;
+
+ bna_mem_writew(&rx_fndb_ram[rxf_id].control_flags, ctl_flags);
+
+ /* turn off statistics collection for this RxF */
+ dev->rxf_active &= ~((u64) 1 << rxf_id);
+}
+
+/**
+ * bna_rxf_enable()
+ *
+ * Enables the Rx Function
+ *
+ * @param[in] dev - Pointer to BNA device handle
+ * @param[in] rxf_id - Id of the Rx Function to be disabled
+ *
+ * @return BNA_OK if mbox command succeeded, else BNA_FAIL
+ */
+enum bna_status_e
+bna_rxf_enable(struct bna_dev *dev, unsigned int rxf_id)
+{
+ struct bfi_ll_rxf_multi_req ll_req;
+ u64 bit_mask = 1 << rxf_id;
+ enum bna_status_e status;
+
+ bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
+ ll_req.rxf_id_mask[0] = htonl((u32) bit_mask);
+ ll_req.rxf_id_mask[1] = htonl((u32) (bit_mask >> 32));
+ ll_req.enable = 1;
+
+ status = bna_mbox_send(dev, &ll_req, sizeof(ll_req), dev->cbarg);
+ if (!status)
+ dev->rxf_active |= bit_mask;
+ return status;
+}
+
+
+enum bna_status_e bna_multi_rxf_active(struct bna_dev *dev,
+ u64 rxf_id_mask, u8 enable)
+{
+ struct bfi_ll_rxf_multi_req ll_req;
+ enum bna_status_e status;
+
+ bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
+ ll_req.rxf_id_mask[0] = htonl((u32) rxf_id_mask);
+ ll_req.rxf_id_mask[1] = htonl((u32) (rxf_id_mask >> 32));
+ ll_req.enable = enable;
+
+ status = bna_mbox_send(dev, &ll_req, sizeof(ll_req), dev->cbarg);
+ if (!status) {
+ if (enable)
+ dev->rxf_active |= rxf_id_mask;
+ else
+ dev->rxf_active &= ~rxf_id_mask;
+
+ }
+ return status;
+}
+
+/**
+ * bna_rxf_ucast_mac_get()
+ *
+ * For RxF "rxf_id", it overwrites the burnt-in unicast MAC with
+ * the one specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID
+ * @param[in] entry - offset into UCAM to read
+ * @param[in] mac_addr_ptr - pointer to mac adddress to set
+ *
+ * @return void
+ */
+void bna_rxf_ucast_mac_get(struct bna_dev *dev, unsigned int *rxf_id,
+ unsigned int entry, const struct mac *mac_addr_ptr)
+{
+ u32 mac_47_32, mac_31_0;
+ u8 *mac_ptr = (u8 *) mac_addr_ptr;
+ struct bna_cam *ucam;
+ struct bna_ucast_mem *ucam_ram;
+
+ ucam = (struct bna_cam *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, UCAST_CAM_BASE_OFFSET);
+ ucam_ram = (struct bna_ucast_mem *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, UCAST_RAM_BASE_OFFSET);
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2), UCAST_RAM_BASE_OFFSET));
+
+ /* turn on the bit corresponding to the given RxF */
+ *rxf_id = (bna_mem_readw(&ucam_ram[entry]) & 0x3f);
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2), UCAST_CAM_BASE_OFFSET));
+
+ /* add unicast MAC */
+ mac_47_32 = (bna_mem_readw(&ucam[entry].cam_mac_addr_47_32) & 0xffff);
+ mac_31_0 = bna_mem_readw(&ucam[entry].cam_mac_addr_31_0);
+
+
+ mac_ptr[0] = mac_47_32 >> 8;
+ mac_ptr[1] = mac_47_32 & 0xff;
+
+ mac_ptr[2] = mac_31_0 >> 24;
+ mac_ptr[3] = (mac_31_0 >> 16) & 0xff;
+ mac_ptr[4] = (mac_31_0 >> 8) & 0xff;
+ mac_ptr[5] = mac_31_0 & 0xff;
+}
+
+static enum bna_status_e
+bna_rxf_mac_mbox_cmd(struct bna_dev *dev, unsigned int rxf_id, u8 cmd,
+ const struct mac *mac_addr)
+{
+ struct bfi_ll_mac_addr_req req;
+
+
+ bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
+
+ req.rxf_id = rxf_id;
+ req.mac_addr = *mac_addr;
+
+ /* send command to firmware */
+ return bna_mbox_send(dev, &req, sizeof(req), dev->cbarg);
+}
+
+/**
+ * bna_rxf_ucast_mac_set()
+ *
+ * For RxF "rxf_id", it overwrites the burnt-in unicast MAC with
+ * the one specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_addr_ptr - pointer to mac adddress to set
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_rxf_ucast_mac_set(struct bna_dev *dev, unsigned int rxf_id,
+ const struct mac *mac_addr_ptr)
+{
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ /* we are supposed to set MAC adresses for default RxF only */
+ if (dev->rxf_default_id == BNA_RXF_ID_NONE) {
+ if (rxf_id != BNA_DEFAULT_RXF_ID)
+ return BNA_FAIL;
+ } else {
+ if (rxf_id != dev->rxf_default_id)
+ return BNA_FAIL;
+ }
+
+ return bna_rxf_mac_mbox_cmd(dev, rxf_id, BFI_LL_H2I_MAC_UCAST_SET_REQ,
+ mac_addr_ptr);
+}
+
+/**
+ * bna_rxf_ucast_mac_add()
+ *
+ * For RxF "rxf_id", it adds the unicast MAC specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_addr_ptr - pointer to mac adddress to add
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_rxf_ucast_mac_add(struct bna_dev *dev, unsigned int rxf_id,
+ const struct mac *mac_addr_ptr)
+{
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+ /* we are not supposed to add MAC adresses to default RxF */
+ if (rxf_id == dev->rxf_default_id)
+ return BNA_FAIL;
+
+ return bna_rxf_mac_mbox_cmd(dev, rxf_id, BFI_LL_H2I_MAC_UCAST_ADD_REQ,
+ mac_addr_ptr);
+}
+
+/**
+ * bna_rxf_ucast_mac_del()
+ *
+ * For RxF "rxf_id", it deletes the unicast MAC specified by "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_addr_ptr - pointer to mac adddress to add
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_rxf_ucast_mac_del(struct bna_dev *dev, unsigned int rxf_id,
+ const struct mac *mac_addr_ptr)
+{
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ /* we are not supposed to delete MAC adresses from default RxF */
+ if (rxf_id == dev->rxf_default_id)
+ return BNA_FAIL;
+
+ return bna_rxf_mac_mbox_cmd(dev, rxf_id, BFI_LL_H2I_MAC_UCAST_DEL_REQ,
+ mac_addr_ptr);
+}
+
+
+/**
+ * bna_rxf_mcast_mac_add()
+ *
+ * For RxF "rxf_id", it adds the multicast MAC specified by
+ * "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_addr_ptr - pointer to mac adddress to add
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_rxf_mcast_mac_add(struct bna_dev *dev, unsigned int rxf_id,
+ const struct mac *mac_addr_ptr)
+{
+ u32 i;
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ for (i = 0; i < BNA_MCAST_TABLE_SIZE; i++) {
+ if (BNA_MAC_IS_EQUAL(&dev->mcast_addr[i], mac_addr_ptr))
+ break;
+ }
+
+ if (i == BNA_MCAST_TABLE_SIZE) {
+ /*
+ * no existing entry found we need to find the
+ * first unused entry
+ */
+ for (i = 0; i < BNA_MCAST_TABLE_SIZE; i++) {
+ /* unused entry found, stop and use it */
+ if (BNA_MAC_IS_EQUAL
+ (&dev->mcast_addr[i], &bna_zero_addr))
+ break;
+ }
+ }
+
+ if (i == BNA_MCAST_TABLE_SIZE) {
+ /* no entry available, table full */
+ return BNA_FAIL;
+ }
+
+ dev->mcast_addr[i] = *mac_addr_ptr;
+
+
+ return bna_rxf_mac_mbox_cmd(dev, rxf_id, BFI_LL_H2I_MAC_MCAST_ADD_REQ,
+ mac_addr_ptr);
+}
+
+/**
+ * bna_rxf_mcast_mac_del()
+ *
+ * For RxF "rxf_id", it deletes the multicast MAC specified by
+ * "mac_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_addr_ptr - pointer to mac adddress to add
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_rxf_mcast_mac_del(struct bna_dev *dev, unsigned int rxf_id,
+ const struct mac *mac_addr_ptr)
+{
+ u32 i;
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+
+ for (i = 0; i < BNA_MCAST_TABLE_SIZE; i++) {
+ if (BNA_MAC_IS_EQUAL(&dev->mcast_addr[i], mac_addr_ptr))
+ break;
+ }
+
+ if (i == BNA_MCAST_TABLE_SIZE) {
+ /* no existing entry found */
+ return BNA_FAIL;
+ }
+ dev->mcast_addr[i] = bna_zero_addr;
+
+ return bna_rxf_mac_mbox_cmd(dev, rxf_id, BFI_LL_H2I_MAC_MCAST_DEL_REQ,
+ mac_addr_ptr);
+}
+
+/**
+ * bna_rxf_mcast_mac_set_list()
+ *
+ * For RxF "rxf_id", it sets the multicast MAC addresses
+ * specified by "mac_addr_ptr". The function first deletes the MAC addresses in
+ * the existing list that is not found in the new list. It then adds the new
+ * addresses that are in the new list but not in the old list. It then replaces
+ * the old list with the new list in the bna_dev structure.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] mac_addr_ptr - pointer to the list of mac
+ * adddresses to set
+ * @param[in] mac_addr_num - number of mac addresses in the
+ * list
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_rxf_mcast_mac_set_list(struct bna_dev *dev, unsigned int rxf_id,
+ const struct mac *mac_addr_ptr,
+ unsigned int mac_addr_num)
+{
+ u32 i, j;
+ int found;
+ char message[BNA_MESSAGE_SIZE];
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ if (mac_addr_num > BNA_MCAST_TABLE_SIZE) {
+ sprintf(message, "Too many Multicast Addresses [%d]",
+ mac_addr_num);
+ DPRINTK(INFO, "%s", message);
+ return BNA_FAIL;
+ }
+
+ /* find MAC addresses to delete */
+ for (i = 0; i < BNA_MCAST_TABLE_SIZE; i++) {
+ if (BNA_MAC_IS_EQUAL(&dev->mcast_addr[i], &bna_zero_addr))
+ continue;
+ found = 0;
+ for (j = 0; j < mac_addr_num; j++) {
+ if (BNA_MAC_IS_EQUAL
+ (&mac_addr_ptr[j], &dev->mcast_addr[i])) {
+ found = 1;
+ break;
+ }
+ }
+ if (!found) {
+ if (BNA_FAIL ==
+ bna_rxf_mac_mbox_cmd(dev, rxf_id,
+ BFI_LL_H2I_MAC_MCAST_DEL_REQ,
+ &dev->mcast_addr[i])) {
+ return BNA_FAIL;
+ }
+ }
+ }
+
+ /* find MAC addresses to add */
+ for (i = 0; i < mac_addr_num; i++) {
+ found = 0;
+ for (j = 0; j < BNA_MCAST_TABLE_SIZE; j++) {
+ if (BNA_MAC_IS_EQUAL
+ (&mac_addr_ptr[i], &dev->mcast_addr[j])) {
+ found = 1;
+ break;
+ }
+ }
+ if (!found) {
+ if (BNA_FAIL ==
+ bna_rxf_mac_mbox_cmd(dev, rxf_id,
+ BFI_LL_H2I_MAC_MCAST_ADD_REQ,
+ &mac_addr_ptr[i])) {
+ return BNA_FAIL;
+ }
+ }
+ }
+
+ memset(&dev->mcast_addr[0], 0, sizeof(dev->mcast_addr));
+ memcpy(&dev->mcast_addr[0], mac_addr_ptr,
+ mac_addr_num * sizeof(struct mac));
+
+ return BNA_OK;
+}
+
+/**
+ * bna_mcast_mac_reset_list()
+ *
+ * Resets the multicast MAC address list kept by driver.
+ * Called when the hw gets reset.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void
+bna_mcast_mac_reset_list(struct bna_dev *dev)
+{
+ memset(&dev->mcast_addr[0], 0, sizeof(dev->mcast_addr));
+}
+
+/**
+ * bna_rxf_broadcast()
+ *
+ * For RxF "rxf_id", it enables/disables the broadcast address.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable broadcast address
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_broadcast(struct bna_dev *dev,
+ unsigned int rxf_id, enum bna_enable_e enable)
+{
+ if (enable)
+ return bna_rxf_mcast_mac_add(dev, rxf_id, &bna_bcast_addr);
+
+ return bna_rxf_mcast_mac_del(dev, rxf_id, &bna_bcast_addr);
+}
+
+/**
+ * bna_rxf_vlan_add()
+ *
+ * For RxF "rxf_id", it adds this function as a member of the
+ * specified "vlan_id".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] vlan_id - VLAN id to be added
+ *
+ * @return void
+ */
+void bna_rxf_vlan_add(struct bna_dev *dev, unsigned int rxf_id,
+ unsigned int vlan_id)
+{
+
+ u32 new_vlan_id;
+
+ BNA_ASSERT((rxf_id <= BNA_RXF_ID_MAX));
+
+ /*
+ * wrap the vlan_id around in case it
+ * overflows the max limit
+ */
+ new_vlan_id = vlan_id & BNA_VLAN_ID_MAX;
+ BNA_BIT_TABLE_SET(dev->vlan_table[rxf_id], new_vlan_id);
+
+ if (dev->vlan_filter_enable[rxf_id] &&
+ (dev->rxf_active & ((u64) 1 << rxf_id))) {
+ /* add VLAN ID on this function */
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2),
+ VLAN_RAM_BASE_OFFSET));
+ bna_mem_writew(BNA_GET_VLAN_MEM_ENTRY_ADDR
+ (dev->bar0, rxf_id, new_vlan_id),
+ dev->vlan_table[rxf_id][new_vlan_id / 32]);
+ }
+}
+
+/**
+ * bna_rxf_vlan_del()
+ *
+ * For RxF "rxf_id", it removes this function as a member of the
+ * specified "vlan_id".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] vlan_id - VLAN id to be removed
+ *
+ * @return void
+ */
+void bna_rxf_vlan_del(struct bna_dev *dev, unsigned int rxf_id,
+ unsigned int vlan_id)
+{
+
+ u32 new_vlan_id;
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ new_vlan_id = vlan_id & BNA_VLAN_ID_MAX;
+ BNA_BIT_TABLE_CLEAR(dev->vlan_table[rxf_id], new_vlan_id);
+
+ if (dev->vlan_filter_enable[rxf_id] &&
+ (dev->rxf_active & ((u64) 1 << rxf_id))) {
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2),
+ VLAN_RAM_BASE_OFFSET));
+ bna_mem_writew(BNA_GET_VLAN_MEM_ENTRY_ADDR
+ (dev->bar0, rxf_id, new_vlan_id),
+ dev->vlan_table[rxf_id][new_vlan_id / 32]);
+ }
+}
+
+/**
+ * bna_rxf_vlan_filter()
+ *
+ * For RxF "rxf_id", it enables/disables the VLAN filter.
+ * Disabling the VLAN Filter allows reception of any VLAN-tagged frame.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable VLAN Filtering.
+ *
+ * @return void
+ */
+void bna_rxf_vlan_filter(struct bna_dev *dev, unsigned int rxf_id,
+ enum bna_enable_e enable)
+{
+ u32 i;
+
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ dev->vlan_filter_enable[rxf_id] = enable;
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2), VLAN_RAM_BASE_OFFSET));
+
+ if (enable) {
+ /* enable VLAN filtering on this function */
+ for (i = 0; i <= BNA_VLAN_ID_MAX / 32; i++) {
+ bna_mem_writew(BNA_GET_VLAN_MEM_ENTRY_ADDR
+ (dev->bar0, rxf_id, i * 32),
+ dev->vlan_table[rxf_id][i]);
+ }
+ } else {
+ /* disable VLAN filtering on this function */
+ for (i = 0; i <= BNA_VLAN_ID_MAX / 32; i++) {
+ bna_mem_writew(BNA_GET_VLAN_MEM_ENTRY_ADDR
+ (dev->bar0, rxf_id, i * 32), 0xffffffff);
+ }
+ }
+}
+
+/**
+ * bna_rxf_vlan_del_all()
+ *
+ * For RxF "rxf_id", it clears all the VLANs.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ *
+ * @return void
+ */
+void
+bna_rxf_vlan_del_all(struct bna_dev *dev, unsigned int rxf_id)
+{
+ u32 i;
+
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2), VLAN_RAM_BASE_OFFSET));
+
+ /* clear all VLANs for this function */
+ for (i = 0; i <= BNA_VLAN_ID_MAX / 32; i++) {
+ bna_mem_writew(BNA_GET_VLAN_MEM_ENTRY_ADDR
+ (dev->bar0, rxf_id, i * 32), 0);
+ }
+}
+
+
+/**
+ * bna_rxf_mcast_filter()
+ *
+ * For RxF "rxf_id", it enables/disables the multicast filter.
+ * Disabling the multicast filter allows reception of any
+ * multicast frame.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable multicast Filtering.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_mcast_filter(struct bna_dev *dev,
+ unsigned int rxf_id, enum bna_enable_e enable)
+{
+
+ struct bfi_ll_mcast_filter_req cmd;
+
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ bfi_h2i_set(cmd.mh, BFI_MC_LL, BFI_LL_H2I_MAC_MCAST_FILTER_REQ, 0);
+
+ cmd.rxf_id = rxf_id;
+ cmd.enable = enable;
+
+ /* send command to firmware */
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+}
+
+/**
+ * bna_rxf_mcast_del_all()
+ *
+ * For RxF "rxf_id", it clears the MCAST cam and MVT.
+ * This functionality is required by some of the drivers.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_rxf_mcast_del_all(struct bna_dev *dev, unsigned int rxf_id)
+{
+ struct bfi_ll_mcast_del_all_req cmd;
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ bfi_h2i_set(cmd.mh, BFI_MC_LL, BFI_LL_H2I_MAC_MCAST_DEL_ALL_REQ, 0);
+
+ cmd.rxf_id = rxf_id;
+
+ /* send command to firmware */
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+}
+
+/**
+ * bna_rxf_promiscuous()
+ *
+ * For RxF "rxf_id", it enables/disables promiscuous mode.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable promiscious mode
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_promiscuous(struct bna_dev *dev,
+ unsigned int rxf_id, enum bna_enable_e enable)
+{
+ struct bfi_ll_rxf_req cmd;
+
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ bfi_h2i_set(cmd.mh, BFI_MC_LL, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ, 0);
+
+ cmd.rxf_id = rxf_id;
+ cmd.enable = enable;
+
+
+ /*
+ * Need to revisit.
+ * Can the second check be an ASSERT ?
+ */
+ if (enable &&
+ ((dev->rxf_promiscuous_id == BNA_RXF_ID_NONE) ||
+ (dev->rxf_promiscuous_id == rxf_id))) {
+ dev->rxf_promiscuous_id = rxf_id;
+
+ /* allow all VLANs */
+ bna_rxf_vlan_filter(dev, rxf_id, BNA_DISABLE);
+
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+ } else if (!enable && (dev->rxf_promiscuous_id == rxf_id)) {
+ dev->rxf_promiscuous_id = BNA_RXF_ID_NONE;
+
+ /* Revert VLAN filtering */
+ bna_rxf_vlan_filter(dev, rxf_id, BNA_ENABLE);
+
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+ }
+
+ return BNA_FAIL;
+}
+
+/**
+ * bna_rxf_default_mode()
+ *
+ * For RxF "rxf_id", it enables/disables default mode.
+ * Must be called after the RxF has been configured.
+ * Must remove all unicast MAC associated to this RxF.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[in] enable - enable/disable default mode
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_rxf_default_mode(struct bna_dev *dev,
+ unsigned int rxf_id, enum bna_enable_e enable)
+{
+ struct bna_rx_fndb_ram *rx_fndb_ram;
+ u32 i, ctl_flags;
+ struct bfi_ll_rxf_req cmd;
+
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ rx_fndb_ram = (struct bna_rx_fndb_ram *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, RX_FNDB_RAM_BASE_OFFSET);
+
+ bfi_h2i_set(cmd.mh, BFI_MC_LL, BFI_LL_H2I_RXF_DEFAULT_SET_REQ, 0);
+
+ cmd.rxf_id = rxf_id;
+ cmd.enable = enable;
+
+ /*
+ * Need to revisit.
+ * Can the second check be an ASSERT ?
+ */
+ if (enable &&
+ ((dev->rxf_default_id == BNA_RXF_ID_NONE) ||
+ (dev->rxf_default_id == rxf_id))) {
+ dev->rxf_default_id = rxf_id;
+
+ /* allow all VLANs */
+ bna_rxf_vlan_filter(dev, rxf_id, BNA_DISABLE);
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2),
+ RX_FNDB_RAM_BASE_OFFSET));
+
+ for (i = 0; i < BNA_RXF_ID_MAX; i++) {
+ if (i == rxf_id)
+ continue;
+
+ ctl_flags =
+ bna_mem_readw(&rx_fndb_ram[i].control_flags);
+ ctl_flags |= BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
+ bna_mem_writew(&rx_fndb_ram[i].control_flags,
+ ctl_flags);
+ }
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+ } else if (!enable && (dev->rxf_default_id == rxf_id)) {
+ dev->rxf_default_id = BNA_RXF_ID_NONE;
+
+ /* Revert VLAN filtering */
+ bna_rxf_vlan_filter(dev, rxf_id,
+ dev->vlan_filter_enable[rxf_id]);
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2),
+ RX_FNDB_RAM_BASE_OFFSET));
+
+ for (i = 0; i < BNA_RXF_ID_MAX; i++) {
+ ctl_flags =
+ bna_mem_readw(&rx_fndb_ram[i].control_flags);
+ ctl_flags &= ~BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
+ bna_mem_writew(&rx_fndb_ram[i].control_flags,
+ ctl_flags);
+ }
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+ }
+ return BNA_FAIL;
+}
+
+/**
+ * bna_rxf_frame_stats_get()
+ *
+ * For RxF "rxf_id", it loads frame statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] rxf_id - rx-function ID.
+ * @param[out] stats_ptr - pointer to stats structure to fill
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void
+bna_rxf_frame_stats_get(struct bna_dev *dev, unsigned int rxf_id,
+ struct bna_stats_rxf **stats_ptr)
+{
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ *stats_ptr = &dev->stats.rxf_stats[rxf_id];
+}
+
+/**
+ * bna_txf_frame_stats_get()
+ *
+ * For TxF "txf_id", it loads frame statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] txf_id - tx-function ID.
+ * @param[out] stats_ptr - pointer to tx-function statistics.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void
+bna_txf_frame_stats_get(struct bna_dev *dev, unsigned int txf_id,
+ struct bna_stats_txf **stats_ptr)
+{
+
+ BNA_ASSERT(txf_id < BNA_TXF_ID_MAX);
+
+ *stats_ptr = &dev->stats.txf_stats[txf_id];
+}
+
+/**
+ * bna_mac_rx_stats_get()
+ *
+ * Loads MAC Rx statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+
+ * @param[out] stats_ptr - pointer to stats structure to fill
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void
+bna_mac_rx_stats_get(struct bna_dev *dev, struct cna_stats_mac_rx **stats_ptr)
+{
+ *stats_ptr = &dev->stats.mac_rx_stats;
+}
+
+/**
+ * bna_mac_tx_stats_get()
+ *
+ * Loads MAC Tx statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+
+ * @param[out] stats_ptr - pointer to stats structure to fill
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+void
+bna_mac_tx_stats_get(struct bna_dev *dev, struct cna_stats_mac_tx **stats_ptr)
+{
+ *stats_ptr = &dev->stats.mac_tx_stats;
+}
+
+/**
+ * bna_all_stats_get()
+ *
+ * Loads all statistics into "stats_ptr".
+ *
+ * @param[in] dev - pointer to BNA device structure
+
+ * @param[out] stats_ptr - pointer to stats structure
+ *
+ * @return void
+ */
+void
+bna_all_stats_get(struct bna_dev *dev, struct bna_stats **stats_ptr)
+{
+ *stats_ptr = &dev->stats;
+}
+
+/**
+ * bna_stats_get()
+ *
+ * Get the statistics from the device. This function needs to
+ * be scheduled every second to get periodic update of the
+ * statistics data from hardware.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_stats_get(struct bna_dev *dev)
+{
+ struct bfi_ll_stats_req cmd;
+
+ bfi_h2i_set(cmd.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0);
+
+ cmd.stats_mask = htons(BFI_LL_STATS_ALL);
+ cmd.rxf_id_mask[0] =
+ htonl((u32) (dev->rxf_active & 0xffffffff));
+ cmd.rxf_id_mask[1] = htonl((u32) (dev->rxf_active >> 32));
+
+ cmd.txf_id_mask[0] =
+ htonl((u32) (dev->txf_active & 0xffffffff));
+ cmd.txf_id_mask[1] = htonl((u32) (dev->txf_active >> 32));
+
+ cmd.host_buffer.a32.addr_hi = dev->hw_stats_dma.msb;
+ cmd.host_buffer.a32.addr_lo = dev->hw_stats_dma.lsb;
+
+ dev->rxf_active_last = dev->rxf_active;
+ dev->txf_active_last = dev->txf_active;
+
+ /* send command to firmware */
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+}
+
+/**
+ * bna_stats_clear()
+ *
+ * Clear the statistics in the device.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e bna_stats_clear(struct bna_dev *dev,
+ u64 txf_id_mask, u64 rxf_id_mask)
+{
+ struct bfi_ll_stats_req cmd;
+
+ bfi_h2i_set(cmd.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
+
+ cmd.stats_mask = htons(BFI_LL_STATS_ALL);
+ cmd.rxf_id_mask[0] = htonl((u32) rxf_id_mask);
+ cmd.rxf_id_mask[1] = htonl((u32) (rxf_id_mask >> 32));
+
+ cmd.txf_id_mask[0] = htonl((u32) txf_id_mask);
+ cmd.txf_id_mask[1] = htonl((u32) (txf_id_mask >> 32));
+
+ /* send command to firmware */
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+}
+
+/**
+ * bna_rxf_stats_clear()
+ *
+ * Clear the statistics for specified txf.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ * @param[in] rxf_id - rx-function ID.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_rxf_stats_clear(struct bna_dev *dev, unsigned int rxf_id)
+{
+ struct bfi_ll_stats_req cmd;
+
+ BNA_ASSERT(rxf_id < BNA_RXF_ID_MAX);
+
+ bfi_h2i_set(cmd.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
+
+ cmd.stats_mask = 0;
+
+ if (rxf_id < 32) {
+ cmd.rxf_id_mask[0] = htonl((u32) (1 << rxf_id));
+ cmd.rxf_id_mask[1] = 0;
+ } else {
+ cmd.rxf_id_mask[0] = 0;
+ cmd.rxf_id_mask[1] =
+ htonl((u32) (1 << (rxf_id - 32)));
+ }
+
+ cmd.txf_id_mask[0] = 0;
+ cmd.txf_id_mask[1] = 0;
+
+ /* send command to firmware */
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+}
+
+/**
+ * bna_lldp_stats_clear()
+ *
+ * Clear the DCBCX-LLDP statistics in the f/w.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_lldp_stats_clear(struct bna_dev *dev)
+{
+ struct bfi_lldp_reset_stats cmd;
+
+ bfi_h2i_set(cmd.mh, BFI_MC_CEE, BFI_CEE_H2I_RESET_STATS, 0);
+
+ /* send command to firmware */
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+}
+
+/**
+ * bna_get_cfg_req()
+ *
+ * Request to get the LLDP-DCBCX Config.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ * @param[in] dma_ddr - dma address in "bna_dma_addr_t" format.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_get_cfg_req(struct bna_dev *dev, struct bna_dma_addr *dma_addr)
+{
+ struct bfi_cee_get_req cmd;
+
+ bfi_h2i_set(cmd.mh, BFI_MC_CEE, BFI_CEE_H2I_GET_CFG_REQ, 0);
+ cmd.dma_addr.a32.addr_lo = dma_addr->lsb;
+ cmd.dma_addr.a32.addr_hi = dma_addr->msb;
+ /* send command to firmware */
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+}
+
+/**
+ * bna_get_cee_stats_req()
+ *
+ * Request to get the LLDP-DCBCX stats.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ * @param[in] dma_ddr - dma address in "bna_dma_addr_t" format.
+ *
+ * @return BNA_OK - successful
+ * @return BNA_FAIL - failed on sanity checks.
+ */
+enum bna_status_e
+bna_get_cee_stats_req(struct bna_dev *dev, struct bna_dma_addr *dma_addr)
+{
+ struct bfi_cee_get_req cmd;
+
+ bfi_h2i_set(cmd.mh, BFI_MC_CEE, BFI_CEE_H2I_GET_STATS_REQ, 0);
+ cmd.dma_addr.a32.addr_lo = dma_addr->lsb;
+ cmd.dma_addr.a32.addr_hi = dma_addr->msb;
+ /* send command to firmware */
+ return bna_mbox_send(dev, &cmd, sizeof(cmd), dev->cbarg);
+}
+
+/**
+ * bna_stats_process()
+ *
+ * Process the statistics data DMAed from the device. This
+ * function needs to be scheduled upon getting an asynchronous
+ * notification from the firmware.
+ *
+ * @param[in] dev - pointer to BNA device structure.
+ *
+ * @return void
+ */
+void
+bna_stats_process(struct bna_dev *dev)
+{
+ u32 i, j;
+ struct bna_stats_rxf *rxf_hw_stats;
+ struct bna_stats_txf *txf_hw_stats;
+
+ dev->stats.fc_tx_stats.txf_ucast_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.
+ txf_ucast_octets);
+ dev->stats.fc_tx_stats.txf_ucast =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.txf_ucast);
+ dev->stats.fc_tx_stats.txf_ucast_vlan =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.
+ txf_ucast_vlan);
+
+ dev->stats.fc_tx_stats.txf_mcast_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.
+ txf_mcast_octets);
+ dev->stats.fc_tx_stats.txf_mcast =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.txf_mcast);
+ dev->stats.fc_tx_stats.txf_mcast_vlan =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.
+ txf_mcast_vlan);
+
+ dev->stats.fc_tx_stats.txf_bcast_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.
+ txf_bcast_octets);
+ dev->stats.fc_tx_stats.txf_bcast =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.txf_bcast);
+ dev->stats.fc_tx_stats.txf_bcast_vlan =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.
+ txf_bcast_vlan);
+
+ dev->stats.fc_tx_stats.txf_parity_errors =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.
+ txf_parity_errors);
+ dev->stats.fc_tx_stats.txf_timeout =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.txf_timeout);
+ dev->stats.fc_tx_stats.txf_fid_parity_errors =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_tx_stats.
+ txf_fid_parity_errors);
+
+ for (i = 0; i < 8; i++) {
+ dev->stats.bpc_tx_stats.tx_pause[i] =
+ bna_hw_stats_to_stats(dev->hw_stats->bpc_stats.
+ tx_pause[i]);
+ dev->stats.bpc_tx_stats.tx_zero_pause[i] =
+ bna_hw_stats_to_stats(dev->hw_stats->bpc_stats.
+ tx_zero_pause[i]);
+ dev->stats.bpc_tx_stats.tx_first_pause[i] =
+ bna_hw_stats_to_stats(dev->hw_stats->bpc_stats.
+ tx_first_pause[i]);
+ }
+
+ dev->stats.mac_tx_stats.tx_bytes =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_bytes);
+ dev->stats.mac_tx_stats.tx_packets =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_packets);
+ dev->stats.mac_tx_stats.tx_multicast =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_multicast);
+ dev->stats.mac_tx_stats.tx_broadcast =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_broadcast);
+ dev->stats.mac_tx_stats.tx_pause =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_pause);
+ dev->stats.mac_tx_stats.tx_deferral =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_deferral);
+ dev->stats.mac_tx_stats.tx_excessive_deferral =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ tx_excessive_deferral);
+ dev->stats.mac_tx_stats.tx_single_collision =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ tx_single_collision);
+ dev->stats.mac_tx_stats.tx_muliple_collision =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ tx_muliple_collision);
+ dev->stats.mac_tx_stats.tx_late_collision =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ tx_late_collision);
+ dev->stats.mac_tx_stats.tx_excessive_collision =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ tx_excessive_collision);
+ dev->stats.mac_tx_stats.tx_total_collision =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ tx_total_collision);
+ dev->stats.mac_tx_stats.tx_pause_honored =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ tx_pause_honored);
+ dev->stats.mac_tx_stats.tx_drop =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_drop);
+ dev->stats.mac_tx_stats.tx_jabber =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_jabber);
+ dev->stats.mac_tx_stats.tx_fcs_error =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_fcs_error);
+ dev->stats.mac_tx_stats.tx_control_frame =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ tx_control_frame);
+ dev->stats.mac_tx_stats.tx_oversize =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_oversize);
+ dev->stats.mac_tx_stats.tx_undersize =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_undersize);
+ dev->stats.mac_tx_stats.tx_fragments =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.tx_fragments);
+
+ dev->stats.fc_rx_stats.rxf_ucast_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_rx_stats.
+ rxf_ucast_octets);
+ dev->stats.fc_rx_stats.rxf_ucast =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_rx_stats.rxf_ucast);
+ dev->stats.fc_rx_stats.rxf_ucast_vlan =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_rx_stats.
+ rxf_ucast_vlan);
+
+ dev->stats.fc_rx_stats.rxf_mcast_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_rx_stats.
+ rxf_mcast_octets);
+ dev->stats.fc_rx_stats.rxf_mcast =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_rx_stats.rxf_mcast);
+ dev->stats.fc_rx_stats.rxf_mcast_vlan =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_rx_stats.
+ rxf_mcast_vlan);
+
+ dev->stats.fc_rx_stats.rxf_bcast_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_rx_stats.
+ rxf_bcast_octets);
+ dev->stats.fc_rx_stats.rxf_bcast =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_rx_stats.rxf_bcast);
+ dev->stats.fc_rx_stats.rxf_bcast_vlan =
+ bna_hw_stats_to_stats(dev->hw_stats->fc_rx_stats.
+ rxf_bcast_vlan);
+
+ for (i = 0; i < 8; i++) {
+ dev->stats.bpc_rx_stats.rx_pause[i] =
+ bna_hw_stats_to_stats(dev->hw_stats->bpc_stats.
+ rx_pause[i]);
+ dev->stats.bpc_rx_stats.rx_zero_pause[i] =
+ bna_hw_stats_to_stats(dev->hw_stats->bpc_stats.
+ rx_zero_pause[i]);
+ dev->stats.bpc_rx_stats.rx_first_pause[i] =
+ bna_hw_stats_to_stats(dev->hw_stats->bpc_stats.
+ rx_first_pause[i]);
+ }
+
+ dev->stats.rad_stats.rx_frames =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_frames);
+ dev->stats.rad_stats.rx_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_octets);
+ dev->stats.rad_stats.rx_vlan_frames =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_vlan_frames);
+
+ dev->stats.rad_stats.rx_ucast =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_ucast);
+ dev->stats.rad_stats.rx_ucast_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_ucast_octets);
+ dev->stats.rad_stats.rx_ucast_vlan =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_ucast_vlan);
+
+ dev->stats.rad_stats.rx_mcast =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_mcast);
+ dev->stats.rad_stats.rx_mcast_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_mcast_octets);
+ dev->stats.rad_stats.rx_mcast_vlan =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_mcast_vlan);
+
+ dev->stats.rad_stats.rx_bcast =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_bcast);
+ dev->stats.rad_stats.rx_bcast_octets =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_bcast_octets);
+ dev->stats.rad_stats.rx_bcast_vlan =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_bcast_vlan);
+
+ dev->stats.rad_stats.rx_drops =
+ bna_hw_stats_to_stats(dev->hw_stats->rad_stats.rx_drops);
+
+ dev->stats.mac_rx_stats.frame_64 =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.frame_64);
+ dev->stats.mac_rx_stats.frame_65_127 =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.frame_65_127);
+ dev->stats.mac_rx_stats.frame_128_255 =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.frame_128_255);
+ dev->stats.mac_rx_stats.frame_256_511 =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.frame_256_511);
+ dev->stats.mac_rx_stats.frame_512_1023 =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.frame_512_1023);
+ dev->stats.mac_rx_stats.frame_1024_1518 =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.frame_1024_1518);
+ dev->stats.mac_rx_stats.frame_1518_1522 =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.frame_1519_1522);
+ dev->stats.mac_rx_stats.rx_bytes =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_bytes);
+ dev->stats.mac_rx_stats.rx_packets =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_packets);
+ dev->stats.mac_rx_stats.rx_fcs_error =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_fcs_error);
+ dev->stats.mac_rx_stats.rx_multicast =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_multicast);
+ dev->stats.mac_rx_stats.rx_broadcast =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_broadcast);
+ dev->stats.mac_rx_stats.rx_control_frames =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ rx_control_frames);
+ dev->stats.mac_rx_stats.rx_pause =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_pause);
+ dev->stats.mac_rx_stats.rx_unknown_opcode =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ rx_unknown_opcode);
+ dev->stats.mac_rx_stats.rx_alignment_error =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ rx_alignment_error);
+ dev->stats.mac_rx_stats.rx_frame_length_error =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ rx_frame_length_error);
+ dev->stats.mac_rx_stats.rx_code_error =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_code_error);
+ dev->stats.mac_rx_stats.rx_carrier_sense_error =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.
+ rx_carrier_sense_error);
+ dev->stats.mac_rx_stats.rx_undersize =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_undersize);
+ dev->stats.mac_rx_stats.rx_oversize =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_oversize);
+ dev->stats.mac_rx_stats.rx_fragments =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_jabber);
+ dev->stats.mac_rx_stats.rx_jabber =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_jabber);
+ dev->stats.mac_rx_stats.rx_drop =
+ bna_hw_stats_to_stats(dev->hw_stats->mac_stats.rx_drop);
+
+ rxf_hw_stats = (struct bna_stats_rxf *)&dev->hw_stats->rxf_stats[0];
+ j = 0;
+
+ for (i = 0; i < BNA_RXF_ID_MAX; i++) {
+ if (dev->rxf_active_last & ((u64) 1 << i)) {
+ dev->stats.rxf_stats[i].ucast_octets =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].
+ ucast_octets);
+ dev->stats.rxf_stats[i].ucast =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].ucast);
+ dev->stats.rxf_stats[i].ucast_vlan =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].
+ ucast_vlan);
+
+ dev->stats.rxf_stats[i].mcast_octets =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].
+ mcast_octets);
+ dev->stats.rxf_stats[i].mcast =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].mcast);
+ dev->stats.rxf_stats[i].mcast_vlan =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].
+ mcast_vlan);
+
+ dev->stats.rxf_stats[i].bcast_octets =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].
+ bcast_octets);
+ dev->stats.rxf_stats[i].bcast =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].bcast);
+ dev->stats.rxf_stats[i].bcast_vlan =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].
+ bcast_vlan);
+
+ dev->stats.rxf_stats[i].frame_drops =
+ bna_hw_stats_to_stats(rxf_hw_stats[j].
+ frame_drops);
+
+ j++;
+ }
+ }
+
+ txf_hw_stats = (struct bna_stats_txf *)&rxf_hw_stats[j];
+ j = 0;
+
+ for (i = 0; i < BNA_TXF_ID_MAX; i++) {
+ if (dev->txf_active_last & ((u64) 1 << i)) {
+ dev->stats.txf_stats[i].ucast_octets =
+ bna_hw_stats_to_stats(txf_hw_stats[j].
+ ucast_octets);
+ dev->stats.txf_stats[i].ucast =
+ bna_hw_stats_to_stats(txf_hw_stats[j].ucast);
+ dev->stats.txf_stats[i].ucast_vlan =
+ bna_hw_stats_to_stats(txf_hw_stats[j].
+ ucast_vlan);
+
+ dev->stats.txf_stats[i].mcast_octets =
+ bna_hw_stats_to_stats(txf_hw_stats[j].
+ mcast_octets);
+ dev->stats.txf_stats[i].mcast =
+ bna_hw_stats_to_stats(txf_hw_stats[j].mcast);
+ dev->stats.txf_stats[i].mcast_vlan =
+ bna_hw_stats_to_stats(txf_hw_stats[j].
+ mcast_vlan);
+
+ dev->stats.txf_stats[i].bcast_octets =
+ bna_hw_stats_to_stats(txf_hw_stats[j].
+ bcast_octets);
+ dev->stats.txf_stats[i].bcast =
+ bna_hw_stats_to_stats(txf_hw_stats[j].bcast);
+ dev->stats.txf_stats[i].bcast_vlan =
+ bna_hw_stats_to_stats(txf_hw_stats[j].
+ bcast_vlan);
+
+ dev->stats.txf_stats[i].errors =
+ bna_hw_stats_to_stats(txf_hw_stats[j].errors);
+ dev->stats.txf_stats[i].filter_vlan =
+ bna_hw_stats_to_stats(txf_hw_stats[j].
+ filter_vlan);
+ dev->stats.txf_stats[i].filter_mac_sa =
+ bna_hw_stats_to_stats(txf_hw_stats[j].
+ filter_mac_sa);
+
+ j++;
+ }
+ }
+}
+
+/**
+ * bna_txf_config_set()
+ *
+ * For TxF "txf_id", it configures the TxF specified by "cfg_ptr" and
+ * indicates to the statistics collector to collect statistics for this
+ * Tx-Function.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] txf_id - tx-function ID.
+ * @param[in] cfg_ptr - pointer to tx-function configuration.
+ *
+ * @return void
+ */
+void
+bna_txf_config_set(struct bna_dev *dev, unsigned int txf_id,
+ const struct bna_txf_config *cfg_ptr)
+{
+
+ struct bna_tx_fndb_ram *tx_fndb;
+
+
+ BNA_ASSERT(txf_id < BNA_TXF_ID_MAX);
+
+ tx_fndb = (struct bna_tx_fndb_ram *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, TX_FNDB_RAM_BASE_OFFSET);
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2),
+ TX_FNDB_RAM_BASE_OFFSET));
+
+ bna_mem_writew(&tx_fndb[txf_id],
+ (cfg_ptr->vlan << 16) | cfg_ptr->flags);
+
+ /* turn on statistics collection */
+ dev->txf_active |= ((u64) 1 << txf_id);
+}
+
+/**
+ * bna_txf_config_clear()
+ *
+ * For TxF "txf_id", it clears its configuration and indicates to the
+ * statistics collector to stop collecting statistics for this
+ * Tx-Function.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] txf_id - tx-function ID.
+ *
+ * @return void
+ */
+void
+bna_txf_config_clear(struct bna_dev *dev, unsigned int txf_id)
+{
+
+ struct bna_tx_fndb_ram *tx_fndb;
+
+ BNA_ASSERT(txf_id < BNA_TXF_ID_MAX);
+
+ tx_fndb = (struct bna_tx_fndb_ram *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, TX_FNDB_RAM_BASE_OFFSET);
+
+ bna_reg_write(dev->regs.page_addr,
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
+ (dev->port * 2),
+ TX_FNDB_RAM_BASE_OFFSET));
+
+ bna_mem_writew(&tx_fndb[txf_id], 0);
+
+ /* turn off statistics collection */
+ dev->txf_active &= ~((u64) 1 << txf_id);
+}
+
+/**
+ * bna_txf_disable()
+ *
+ * Disables the Tx Function without clearing the configuration
+ * Also disables collection of statistics.
+ *
+ * @param[in] bna_dev - Pointer to BNA device handle
+ * @param[in] txf_id - Id of the Tx Function to be disabled
+ *
+ * @return void
+ */
+void
+bna_txf_disable(struct bna_dev *dev, unsigned int txf_id)
+{
+ struct bna_tx_fndb_ram *tx_fndb;
+ u32 page_num, ctl_flags;
+
+ BNA_ASSERT(txf_id < BNA_TXF_ID_MAX);
+
+ tx_fndb = (struct bna_tx_fndb_ram *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, TX_FNDB_RAM_BASE_OFFSET);
+
+ /* Write the page number register */
+ page_num =
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM + (dev->port * 2),
+ TX_FNDB_RAM_BASE_OFFSET);
+ bna_reg_write(dev->regs.page_addr, page_num);
+
+ ctl_flags = bna_mem_readw(&tx_fndb[txf_id].vlan_n_ctrl_flags);
+
+ ctl_flags &= ~BNA_TXF_CF_ENABLE;
+
+ bna_mem_writew(&tx_fndb[txf_id].vlan_n_ctrl_flags, ctl_flags);
+
+ /* turn off statistics collection */
+ dev->txf_active &= ~((u64) 1 << txf_id);
+}
+
+/**
+ * bna_txf_enable()
+ *
+ * Enables the Tx Function without reconfiguring.
+ * Also disables collection of statistics.
+ *
+ * @param[in] bna_dev - Pointer to BNA device handle
+ * @param[in] txf_id - Id of the Tx Function to be disabled
+ *
+ * @return void
+ */
+void
+bna_txf_enable(struct bna_dev *dev, unsigned int txf_id)
+{
+ struct bna_tx_fndb_ram *tx_fndb;
+ u32 page_num, ctl_flags;
+
+ BNA_ASSERT(txf_id < BNA_TXF_ID_MAX);
+
+ tx_fndb = (struct bna_tx_fndb_ram *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, TX_FNDB_RAM_BASE_OFFSET);
+
+ /* Write the page number register */
+ page_num =
+ BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM + (dev->port * 2),
+ TX_FNDB_RAM_BASE_OFFSET);
+ bna_reg_write(dev->regs.page_addr, page_num);
+
+ ctl_flags = bna_mem_readw(&tx_fndb[txf_id].vlan_n_ctrl_flags);
+
+ ctl_flags |= BNA_TXF_CF_ENABLE;
+
+ bna_mem_writew(&tx_fndb[txf_id].vlan_n_ctrl_flags, ctl_flags);
+
+ /* turn on statistics collection */
+ dev->txf_active |= ((u64) 1 << txf_id);
+}
+
+/**
+ * bna_set_pause_config()
+ *
+ * Enable/disable Tx/Rx pause through F/W
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] pause - pointer to struct bna_pause_config
+ *
+ * @return BNA_OK in case of success BNA_FAIL otherwise.
+ */
+enum bna_status_e
+bna_set_pause_config(struct bna_dev *dev, struct bna_pause_config *pause,
+ void *cbarg)
+{
+ struct bfi_ll_set_pause_req ll_req;
+
+ bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_SET_PAUSE_REQ, 0);
+
+ ll_req.tx_pause = pause->tx_pause;
+ ll_req.rx_pause = pause->rx_pause;
+
+
+ /* send to f/w */
+ return bna_mbox_send(dev, &ll_req, sizeof(ll_req), cbarg);
+}
+
+/**
+ * bna_mtu_info()
+ *
+ * Send MTU information to F/W.
+ * This is required to do PAUSE efficiently.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] mtu - current mtu size
+ * @param[in] cbarg - argument for the callback function
+ *
+ * @return BNA_OK in case of success BNA_FAIL otherwise.
+ */
+enum bna_status_e
+bna_mtu_info(struct bna_dev *dev, u16 mtu, void *cbarg)
+{
+ struct bfi_ll_mtu_info_req ll_req;
+
+ bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0);
+ ll_req.mtu = htons(mtu);
+
+
+ /* send to f/w */
+ return bna_mbox_send(dev, &ll_req, sizeof(ll_req), cbarg);
+}
+
+
+/* Currently we assume just 2 columns, col 0 = small, col 1 = large */
+u32 intr_mod_vector[BNA_LOAD_TYPES + 1][BNA_BIAS_TYPES] = {
+ {12, 12},
+ {6, 10},
+ {5, 10},
+ {4, 8},
+ {3, 6},
+ {3, 6},
+ {2, 4},
+ {1, 2},
+};
+
+/**
+ * Returns the coalescing timer value
+ */
+u8
+bna_calc_coalescing_timer(struct bna_dev *dev, struct bna_pkt_rate *pkt)
+{
+ u32 load, bias;
+ u32 pkt_rt = 0, small_rt, large_rt;
+
+
+ small_rt = pkt->small_pkt_cnt;
+ large_rt = pkt->large_pkt_cnt;
+
+ pkt_rt = small_rt + large_rt;
+
+ if (pkt_rt < BNA_10K_PKT_RATE)
+ load = BNA_LOW_LOAD_4;
+ else if (pkt_rt < BNA_20K_PKT_RATE)
+ load = BNA_LOW_LOAD_3;
+ else if (pkt_rt < BNA_30K_PKT_RATE)
+ load = BNA_LOW_LOAD_2;
+ else if (pkt_rt < BNA_40K_PKT_RATE)
+ load = BNA_LOW_LOAD_1;
+ else if (pkt_rt < BNA_50K_PKT_RATE)
+ load = BNA_HIGH_LOAD_1;
+ else if (pkt_rt < BNA_60K_PKT_RATE)
+ load = BNA_HIGH_LOAD_2;
+ else if (pkt_rt < BNA_80K_PKT_RATE)
+ load = BNA_HIGH_LOAD_3;
+ else
+ load = BNA_HIGH_LOAD_4;
+
+ if (small_rt > (large_rt << 1))
+ bias = 0;
+ else
+ bias = 1;
+
+ pkt->small_pkt_cnt = pkt->large_pkt_cnt = 0;
+ return intr_mod_vector[load][bias];
+}
diff -ruP net-next-2.6-orig/drivers/net/bna/bna_queue.c net-next-2.6-mod/drivers/net/bna/bna_queue.c
--- net-next-2.6-orig/drivers/net/bna/bna_queue.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bna_queue.c 2009-11-12 19:03:38.553339000 -0800
@@ -0,0 +1,451 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * @file bna_queue.c BNA Queues
+ */
+
+#include <cna.h>
+#include "bna.h"
+#include "bna_hwreg.h"
+#include "bna_priv.h"
+#include <bfi/bfi_ll.h>
+
+
+#define BNA_Q_IDLE_STATE 0x00008001
+/*
+ *-----------------------------------------------------------------------------
+ * bna_txq_config()
+ *
+ * For TxQ "txq_id", it configures the Tx-Queue as specified by "cfg_ptr".
+ *-----------------------------------------------------------------------------
+ */
+void
+bna_txq_config(struct bna_dev *dev, struct bna_txq *q_ptr,
+ unsigned int txq_id, const struct bna_txq_config *cfg_ptr)
+{
+ struct bna_rxtx_q_mem *q_mem;
+ struct bna_txq_mem txq_cfg, *txq_mem;
+ const struct bna_qpt *qpt = &cfg_ptr->qpt;
+ struct bna_dma_addr cur_q_addr;
+ struct bna_doorbell_qset *qset;
+ u32 pg_num;
+
+ BNA_ASSERT(txq_id < BNA_TXQ_ID_MAX);
+ /* Check if the depth is a power of 2 */
+ BNA_ASSERT(BNA_POWER_OF_2(q_ptr->q.q_depth));
+
+
+ cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr));
+
+ /*
+ * Fill out structure, to be subsequently written
+ * to hardware
+ */
+ txq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb;
+ txq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb;
+
+ /* FIXME */
+ txq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
+ txq_cfg.cur_q_entry_hi = cur_q_addr.msb;
+
+ txq_cfg.pg_cnt_n_prd_ptr = (qpt->page_count << 16) | 0x0;
+
+ /* Is the entry size in words ? Check */
+ txq_cfg.entry_n_pg_size =
+ ((BNA_TXQ_ENTRY_SIZE >> 2) << 16) | (qpt->page_size >> 2);
+ txq_cfg.int_blk_n_cns_ptr =
+ ((((u8) cfg_ptr->
+ ib_seg_index) << 24) | (((u8) cfg_ptr->
+ ib_id) << 16) | 0x0);
+ txq_cfg.cns_ptr2_n_q_state = BNA_Q_IDLE_STATE;
+ txq_cfg.nxt_qid_n_fid_n_pri =
+ (((cfg_ptr->txf_id & 0x3f) << 3) | (cfg_ptr->priority & 0x3));
+ txq_cfg.wvc_n_cquota_n_rquota =
+ (((cfg_ptr->wrr_quota & 0xfff) << 12) | (cfg_ptr->
+ wrr_quota & 0xfff));
+
+ pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + dev->port,
+ HQM_RXTX_Q_RAM_BASE_OFFSET);
+
+ bna_reg_write(dev->regs.page_addr, pg_num);
+ /* Write to h/w */
+ q_mem = (struct bna_rxtx_q_mem *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, HQM_RXTX_Q_RAM_BASE_OFFSET);
+
+ txq_mem = &q_mem[txq_id].txq;
+
+ /*
+ * The following 4 lines, is a hack b'cos the H/W needs to read
+ * these DMA addresses as little endian
+ */
+ bna_mem_writew(&txq_mem->pg_tbl_addr_lo,
+ htonl(txq_cfg.pg_tbl_addr_lo));
+ bna_mem_writew(&txq_mem->pg_tbl_addr_hi,
+ htonl(txq_cfg.pg_tbl_addr_hi));
+ bna_mem_writew(&txq_mem->cur_q_entry_lo,
+ htonl(txq_cfg.cur_q_entry_lo));
+ bna_mem_writew(&txq_mem->cur_q_entry_hi,
+ htonl(txq_cfg.cur_q_entry_hi));
+
+ bna_mem_writew(&txq_mem->pg_cnt_n_prd_ptr, txq_cfg.pg_cnt_n_prd_ptr);
+ bna_mem_writew(&txq_mem->entry_n_pg_size, txq_cfg.entry_n_pg_size);
+ bna_mem_writew(&txq_mem->int_blk_n_cns_ptr, txq_cfg.int_blk_n_cns_ptr);
+ bna_mem_writew(&txq_mem->cns_ptr2_n_q_state,
+ txq_cfg.cns_ptr2_n_q_state);
+ bna_mem_writew(&txq_mem->nxt_qid_n_fid_n_pri,
+ txq_cfg.nxt_qid_n_fid_n_pri);
+ bna_mem_writew(&txq_mem->wvc_n_cquota_n_rquota,
+ txq_cfg.wvc_n_cquota_n_rquota);
+
+
+ qset = (struct bna_doorbell_qset *)
+ BNA_GET_DOORBELL_BASE_ADDR(dev->bar0);
+ q_ptr->doorbell = &qset[txq_id].txq[0];
+
+ q_ptr->q.producer_index = 0;
+ q_ptr->q.consumer_index = 0;
+}
+
+
+/**
+ * bna_txq_stop()
+ *
+ * Stops the TxQ identified by the TxQ Id.
+ * Should be called with a lock held
+ * The driver should wait for the response to
+ * conclude if the Q stop is successful or not.
+ *
+ * @param[in] q_id - Id of the TxQ
+ *
+ * @return BNA_OK in case of success, else BNA_FAIL
+ */
+enum bna_status_e
+bna_txq_stop(struct bna_dev *dev, u32 txq_id)
+{
+ struct bfi_ll_q_stop_req ll_req;
+ u64 bit_mask = 1 << txq_id;
+
+ ll_req.mh.msg_class = BFI_MC_LL;
+ ll_req.mh.msg_id = BFI_LL_H2I_TXQ_STOP_REQ;
+ ll_req.mh.mtag.i2htok = 0;
+
+ ll_req.q_id_mask[0] = htonl((u32) bit_mask);
+ ll_req.q_id_mask[1] = htonl((u32) (bit_mask >> 32));
+
+ /* send to f/w */
+ return bna_mbox_send(dev, &ll_req, sizeof(ll_req), dev->cbarg);
+}
+
+/*
+ *-----------------------------------------------------------------------------
+ * bna_rxq_config()
+ *
+ * For RxQ "rxq_id", it configures the Rx-Queue as specified by "cfg_ptr".
+ *-----------------------------------------------------------------------------
+ */
+void
+bna_rxq_config(struct bna_dev *dev, struct bna_rxq *q_ptr,
+ unsigned int rxq_id, const struct bna_rxq_config *cfg_ptr)
+{
+ struct bna_rxtx_q_mem *q_mem;
+ struct bna_rxq_mem rxq_cfg, *rxq_mem;
+ const struct bna_qpt *qpt = &cfg_ptr->qpt;
+ struct bna_dma_addr cur_q_addr;
+ struct bna_doorbell_qset *qset;
+ u32 pg_num;
+
+
+ BNA_ASSERT(rxq_id < BNA_RXQ_ID_MAX);
+
+ /* Check if the depth is a power of 2 */
+ BNA_ASSERT(BNA_POWER_OF_2(q_ptr->q.q_depth));
+
+ cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr));
+ /*
+ * Fill out structure, to be subsequently written
+ * to hardware
+ */
+ rxq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb;
+ rxq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb;
+ rxq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
+ rxq_cfg.cur_q_entry_hi = cur_q_addr.msb;
+
+ rxq_cfg.pg_cnt_n_prd_ptr = (qpt->page_count << 16) | 0x0;
+ rxq_cfg.entry_n_pg_size =
+ ((BNA_RXQ_ENTRY_SIZE >> 2) << 16) | (qpt->page_size >> 2);
+ rxq_cfg.sg_n_cq_n_cns_ptr = (((u8) cfg_ptr->cq_id) << 16) | 0x0;
+ rxq_cfg.buf_sz_n_q_state =
+ (cfg_ptr->buffer_size << 16) | BNA_Q_IDLE_STATE;
+ rxq_cfg.next_qid = 0x0 | (0x3 << 8);
+
+ /* Write the page number register */
+ pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + dev->port,
+ HQM_RXTX_Q_RAM_BASE_OFFSET);
+ bna_reg_write(dev->regs.page_addr, pg_num);
+
+ /* Write to h/w */
+ q_mem = (struct bna_rxtx_q_mem *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, HQM_RXTX_Q_RAM_BASE_OFFSET);
+ rxq_mem = &q_mem[rxq_id].rxq;
+
+ bna_mem_writew(&rxq_mem->pg_tbl_addr_lo,
+ htonl(rxq_cfg.pg_tbl_addr_lo));
+ bna_mem_writew(&rxq_mem->pg_tbl_addr_hi,
+ htonl(rxq_cfg.pg_tbl_addr_hi));
+ bna_mem_writew(&rxq_mem->cur_q_entry_lo,
+ htonl(rxq_cfg.cur_q_entry_lo));
+ bna_mem_writew(&rxq_mem->cur_q_entry_hi,
+ htonl(rxq_cfg.cur_q_entry_hi));
+
+ bna_mem_writew(&rxq_mem->pg_cnt_n_prd_ptr, rxq_cfg.pg_cnt_n_prd_ptr);
+ bna_mem_writew(&rxq_mem->entry_n_pg_size, rxq_cfg.entry_n_pg_size);
+ bna_mem_writew(&rxq_mem->sg_n_cq_n_cns_ptr, rxq_cfg.sg_n_cq_n_cns_ptr);
+ bna_mem_writew(&rxq_mem->buf_sz_n_q_state, rxq_cfg.buf_sz_n_q_state);
+ bna_mem_writew(&rxq_mem->next_qid, rxq_cfg.next_qid);
+
+
+ qset = (struct bna_doorbell_qset *)
+ BNA_GET_DOORBELL_BASE_ADDR(dev->bar0);
+ q_ptr->doorbell = &qset[rxq_id].rxq[0];
+
+ q_ptr->q.producer_index = 0;
+ q_ptr->q.consumer_index = 0;
+}
+
+
+/**
+ * bna_rxq_stop()
+ *
+ * Stops the RxQ identified by the RxQ Id.
+ * Should be called with a lock held
+ * The driver should wait for the response to
+ * conclude if the Q stop is successful or not.
+ *
+ * @param[in] q_id - Id of the RxQ
+ *
+ * @return BNA_OK in case of success, else BNA_FAIL
+ */
+enum bna_status_e
+bna_rxq_stop(struct bna_dev *dev, u32 rxq_id)
+{
+ struct bfi_ll_q_stop_req ll_req;
+ u64 bit_mask = 1 << rxq_id;
+
+ ll_req.mh.msg_class = BFI_MC_LL;
+ ll_req.mh.msg_id = BFI_LL_H2I_RXQ_STOP_REQ;
+ ll_req.mh.mtag.i2htok = 0;
+
+ ll_req.q_id_mask[0] = htonl((u32) bit_mask);
+ ll_req.q_id_mask[1] = htonl((u32) (bit_mask >> 32));
+
+ /* send to f/w */
+ return bna_mbox_send(dev, &ll_req, sizeof(ll_req), dev->cbarg);
+}
+
+enum bna_status_e
+bna_multi_rxq_stop(struct bna_dev *dev, u64 rxq_id_mask)
+{
+ struct bfi_ll_q_stop_req ll_req;
+
+ bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RXQ_STOP_REQ, 0);
+
+ ll_req.q_id_mask[0] = htonl((u32) rxq_id_mask);
+ ll_req.q_id_mask[1] = htonl((u32) (rxq_id_mask >> 32));
+
+ /* send to f/w */
+ return bna_mbox_send(dev, &ll_req, sizeof(ll_req), dev->cbarg);
+}
+
+/*
+ *-----------------------------------------------------------------------------
+ * bna_cq_config()
+ *
+ * For CQ "cq_id", it configures the Rx-Completion Queue as specified by
+ * "cfg_ptr".
+ *-----------------------------------------------------------------------------
+ */
+void
+bna_cq_config(struct bna_dev *dev, struct bna_cq *q_ptr, unsigned int cq_id,
+ const struct bna_cq_config *cfg_ptr)
+{
+ struct bna_cq_mem cq_cfg, *cq_mem;
+ const struct bna_qpt *qpt = &cfg_ptr->qpt;
+ struct bna_dma_addr cur_q_addr;
+ u32 pg_num;
+
+ BNA_ASSERT(cq_id < BNA_CQ_ID_MAX);
+
+ /* Check if the depth is a power of 2 */
+ /* How do we ensure this ? */
+ BNA_ASSERT(BNA_POWER_OF_2(q_ptr->q.q_depth));
+
+ cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr));
+
+ /*
+ * Fill out structure, to be subsequently written
+ * to hardware
+ */
+ cq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb;
+ cq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb;
+ cq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
+ cq_cfg.cur_q_entry_hi = cur_q_addr.msb;
+
+ cq_cfg.pg_cnt_n_prd_ptr = (qpt->page_count << 16) | 0x0;
+ cq_cfg.entry_n_pg_size =
+ ((BNA_CQ_ENTRY_SIZE >> 2) << 16) | (qpt->page_size >> 2);
+ cq_cfg.int_blk_n_cns_ptr =
+ ((((u8) cfg_ptr->
+ ib_seg_index) << 24) | (((u8) cfg_ptr->
+ ib_id) << 16) | 0x0);
+ cq_cfg.q_state = BNA_Q_IDLE_STATE;
+
+ /* Write the page number register */
+ pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + dev->port,
+ HQM_CQ_RAM_BASE_OFFSET);
+
+ bna_reg_write(dev->regs.page_addr, pg_num);
+ /* H/W write */
+ cq_mem = (struct bna_cq_mem *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, HQM_CQ_RAM_BASE_OFFSET);
+ bna_mem_writew(&cq_mem[cq_id].pg_tbl_addr_lo,
+ htonl(cq_cfg.pg_tbl_addr_lo));
+ bna_mem_writew(&cq_mem[cq_id].pg_tbl_addr_hi,
+ htonl(cq_cfg.pg_tbl_addr_hi));
+ bna_mem_writew(&cq_mem[cq_id].cur_q_entry_lo,
+ htonl(cq_cfg.cur_q_entry_lo));
+ bna_mem_writew(&cq_mem[cq_id].cur_q_entry_hi,
+ htonl(cq_cfg.cur_q_entry_hi));
+
+ bna_mem_writew(&cq_mem[cq_id].pg_cnt_n_prd_ptr,
+ cq_cfg.pg_cnt_n_prd_ptr);
+ bna_mem_writew(&cq_mem[cq_id].entry_n_pg_size, cq_cfg.entry_n_pg_size);
+ bna_mem_writew(&cq_mem[cq_id].int_blk_n_cns_ptr,
+ cq_cfg.int_blk_n_cns_ptr);
+ bna_mem_writew(&cq_mem[cq_id].q_state, cq_cfg.q_state);
+
+
+ q_ptr->q.producer_index = 0;
+ q_ptr->q.consumer_index = 0;
+
+}
+
+/*
+ * bna_ib_idx_reset()
+ *
+ * For the specified IB, it clears the IB index
+ *
+ * @param[in] cfg_ptr - pointer to IB Configuration Structure.
+ *
+ * @return none
+ */
+void
+bna_ib_idx_reset(struct bna_dev *dev, const struct bna_ib_config *cfg_ptr)
+{
+ u32 i, pg_num, *ib_idx;
+
+ pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + dev->port,
+ HQM_INDX_TBL_RAM_BASE_OFFSET);
+ bna_reg_write(dev->regs.page_addr, pg_num);
+
+ ib_idx = (u32 *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, HQM_INDX_TBL_RAM_BASE_OFFSET);
+ ib_idx += cfg_ptr->index_table_offset;
+ for (i = 0; i < cfg_ptr->seg_size; i++)
+ *ib_idx++ = 0;
+}
+
+/*
+ * bna_ib_config_set()
+ *
+ * For IB "ib_id", it configures the Interrupt Block specified by "cfg_ptr".
+ *
+ * @param[in] ib_ptr - pointer to IB Data Structure.
+ * @param[in] ib_id - interrupt-block ID
+ * @param[in] cfg_ptr - pointer to IB Configuration Structure.
+ *
+ * @return BNA_OK or BNA_FAIL
+ */
+void
+bna_ib_config_set(struct bna_dev *dev, struct bna_ib *ib_ptr,
+ unsigned int ib_id, const struct bna_ib_config *cfg_ptr)
+{
+ struct bna_ib_blk_mem ib_cfg, *ib_mem;
+ u32 pg_num;
+ struct bna_doorbell_qset *qset;
+
+
+ BNA_ASSERT(ib_id < BNA_IB_ID_MAX);
+
+ ib_cfg.host_addr_lo = (u32) (cfg_ptr->ib_seg_addr.lsb);
+ ib_cfg.host_addr_hi = (u32) (cfg_ptr->ib_seg_addr.msb);
+
+ ib_cfg.clsc_n_ctrl_n_msix =
+ ((cfg_ptr->coalescing_timer << 16) | (cfg_ptr->
+ control_flags << 8) |
+ (cfg_ptr->msix_vector));
+ ib_cfg.ipkt_n_ent_n_idxof =
+ ((cfg_ptr->interpkt_timer & 0xf) << 16) | (cfg_ptr->
+ seg_size << 8) |
+ (cfg_ptr->index_table_offset);
+ ib_cfg.ipkt_cnt_cfg_n_unacked = (cfg_ptr->interpkt_count << 24);
+
+ /* Write the page number register */
+ pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + dev->port,
+ HQM_IB_RAM_BASE_OFFSET);
+ bna_reg_write(dev->regs.page_addr, pg_num);
+
+ ib_mem = (struct bna_ib_blk_mem *)
+ BNA_GET_MEM_BASE_ADDR(dev->bar0, HQM_IB_RAM_BASE_OFFSET);
+
+ bna_mem_writew(&ib_mem[ib_id].host_addr_lo,
+ htonl(ib_cfg.host_addr_lo));
+ bna_mem_writew(&ib_mem[ib_id].host_addr_hi,
+ htonl(ib_cfg.host_addr_hi));
+
+ bna_mem_writew(&ib_mem[ib_id].clsc_n_ctrl_n_msix,
+ ib_cfg.clsc_n_ctrl_n_msix);
+ bna_mem_writew(&ib_mem[ib_id].ipkt_n_ent_n_idxof,
+ ib_cfg.ipkt_n_ent_n_idxof);
+ bna_mem_writew(&ib_mem[ib_id].ipkt_cnt_cfg_n_unacked,
+ ib_cfg.ipkt_cnt_cfg_n_unacked);
+
+
+ qset = (struct bna_doorbell_qset *)
+ BNA_GET_DOORBELL_BASE_ADDR(dev->bar0);
+ ib_ptr->doorbell_addr =
+ (&qset[ib_id >> 1].ib0[(ib_id & 0x1) * (0x20 >> 2)]);
+
+ ib_ptr->doorbell_ack =
+ BNA_DOORBELL_IB_INT_ACK(cfg_ptr->coalescing_timer, 0);
+
+ bna_ib_idx_reset(dev, cfg_ptr);
+}
+
+/*
+ * bna_ib_disable()
+ *
+ * Disables the Interrupt Block "ib_id".
+ *
+ * @param[in] ib_ptr - pointer to IB Data Structure.
+ *
+ * @return None
+ */
+void
+bna_ib_disable(struct bna_dev *bna_dev, const struct bna_ib *ib_ptr)
+{
+ bna_reg_write(ib_ptr->doorbell_addr, BNA_DOORBELL_IB_INT_DISABLE);
+}
diff -ruP net-next-2.6-orig/drivers/net/bna/bnad_ethtool.c net-next-2.6-mod/drivers/net/bna/bnad_ethtool.c
--- net-next-2.6-orig/drivers/net/bna/bnad_ethtool.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bnad_ethtool.c 2009-11-12 19:03:38.561336000 -0800
@@ -0,0 +1,1117 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ */
+
+/**
+ * bna_ethtool.c Brocade 10G PCIe Ethernet driver.
+ */
+
+#include <linux/types.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/skbuff.h>
+#include <linux/if_ether.h>
+#include <linux/ethtool.h>
+#include <linux/rtnetlink.h>
+
+#include "bnad.h"
+#include <cna.h>
+#include "bna_hwreg.h"
+#include "bna_iocll.h"
+#include "bnad_defs.h"
+#include "phyport_defs.h"
+
+#define BNAD_ETHTOOL_STATS_NUM \
+ (sizeof(struct net_device_stats) / sizeof(unsigned long) + \
+ sizeof(struct bnad_drv_stats) / sizeof(u64) + \
+ (offsetof(struct bna_stats, rxf_stats[0]) + \
+ sizeof(struct bna_stats_txf)) / sizeof(u64))
+
+static char *bnad_net_stats_strings[BNAD_ETHTOOL_STATS_NUM] = {
+ "rx_packets",
+ "tx_packets",
+ "rx_bytes",
+ "tx_bytes",
+ "rx_errors",
+ "tx_errors",
+ "rx_dropped",
+ "tx_dropped",
+ "multicast",
+ "collisions",
+
+ "rx_length_errors",
+ "rx_over_errors",
+ "rx_crc_errors",
+ "rx_frame_errors",
+ "rx_fifo_errors",
+ "rx_missed_errors",
+
+ "tx_aborted_errors",
+ "tx_carrier_errors",
+ "tx_fifo_errors",
+ "tx_heartbeat_errors",
+ "tx_window_errors",
+
+ "rx_compressed",
+ "tx_compressed",
+
+ "netif_queue_stop",
+ "netif_queue_wakeup",
+ "tso4",
+ "tso6",
+ "tso_err",
+ "tcpcsum_offload",
+ "udpcsum_offload",
+ "csum_help",
+ "csum_help_err",
+ "hw_stats_updates",
+ "napi_complete",
+
+ "mac_frame_64",
+ "mac_frame_65_127",
+ "mac_frame_128_255",
+ "mac_frame_256_511",
+ "mac_frame_512_1023",
+ "mac_frame_1024_1518",
+ "mac_frame_1518_1522",
+ "mac_rx_bytes",
+ "mac_rx_packets",
+ "mac_rx_fcs_error",
+ "mac_rx_multicast",
+ "mac_rx_broadcast",
+ "mac_rx_control_frames",
+ "mac_rx_pause",
+ "mac_rx_unknown_opcode",
+ "mac_rx_alignment_error",
+ "mac_rx_frame_length_error",
+ "mac_rx_code_error",
+ "mac_rx_carrier_sense_error",
+ "mac_rx_undersize",
+ "mac_rx_oversize",
+ "mac_rx_fragments",
+ "mac_rx_jabber",
+ "mac_rx_drop",
+
+ "bpc_rx_pause_0",
+ "bpc_rx_pause_1",
+ "bpc_rx_pause_2",
+ "bpc_rx_pause_3",
+ "bpc_rx_pause_4",
+ "bpc_rx_pause_5",
+ "bpc_rx_pause_6",
+ "bpc_rx_pause_7",
+ "bpc_rx_zero_pause_0",
+ "bpc_rx_zero_pause_1",
+ "bpc_rx_zero_pause_2",
+ "bpc_rx_zero_pause_3",
+ "bpc_rx_zero_pause_4",
+ "bpc_rx_zero_pause_5",
+ "bpc_rx_zero_pause_6",
+ "bpc_rx_zero_pause_7",
+ "bpc_rx_first_pause_0",
+ "bpc_rx_first_pause_1",
+ "bpc_rx_first_pause_2",
+ "bpc_rx_first_pause_3",
+ "bpc_rx_first_pause_4",
+ "bpc_rx_first_pause_5",
+ "bpc_rx_first_pause_6",
+ "bpc_rx_first_pause_7",
+
+ "rad_rx_frames",
+ "rad_rx_octets",
+ "rad_rx_vlan_frames",
+ "rad_rx_ucast",
+ "rad_rx_ucast_octets",
+ "rad_rx_ucast_vlan",
+ "rad_rx_mcast",
+ "rad_rx_mcast_octets",
+ "rad_rx_mcast_vlan",
+ "rad_rx_bcast",
+ "rad_rx_bcast_octets",
+ "rad_rx_bcast_vlan",
+ "rad_rx_drops",
+
+ "fc_rx_ucast_octets",
+ "fc_rx_ucast",
+ "fc_rx_ucast_vlan",
+ "fc_rx_mcast_octets",
+ "fc_rx_mcast",
+ "fc_rx_mcast_vlan",
+ "fc_rx_bcast_octets",
+ "fc_rx_bcast",
+ "fc_rx_bcast_vlan",
+
+ "mac_tx_bytes",
+ "mac_tx_packets",
+ "mac_tx_multicast",
+ "mac_tx_broadcast",
+ "mac_tx_pause",
+ "mac_tx_deferral",
+ "mac_tx_excessive_deferral",
+ "mac_tx_single_collision",
+ "mac_tx_muliple_collision",
+ "mac_tx_late_collision",
+ "mac_tx_excessive_collision",
+ "mac_tx_total_collision",
+ "mac_tx_pause_honored",
+ "mac_tx_drop",
+ "mac_tx_jabber",
+ "mac_tx_fcs_error",
+ "mac_tx_control_frame",
+ "mac_tx_oversize",
+ "mac_tx_undersize",
+ "mac_tx_fragments",
+
+ "bpc_tx_pause_0",
+ "bpc_tx_pause_1",
+ "bpc_tx_pause_2",
+ "bpc_tx_pause_3",
+ "bpc_tx_pause_4",
+ "bpc_tx_pause_5",
+ "bpc_tx_pause_6",
+ "bpc_tx_pause_7",
+ "bpc_tx_zero_pause_0",
+ "bpc_tx_zero_pause_1",
+ "bpc_tx_zero_pause_2",
+ "bpc_tx_zero_pause_3",
+ "bpc_tx_zero_pause_4",
+ "bpc_tx_zero_pause_5",
+ "bpc_tx_zero_pause_6",
+ "bpc_tx_zero_pause_7",
+ "bpc_tx_first_pause_0",
+ "bpc_tx_first_pause_1",
+ "bpc_tx_first_pause_2",
+ "bpc_tx_first_pause_3",
+ "bpc_tx_first_pause_4",
+ "bpc_tx_first_pause_5",
+ "bpc_tx_first_pause_6",
+ "bpc_tx_first_pause_7",
+
+ "fc_tx_ucast_octets",
+ "fc_tx_ucast",
+ "fc_tx_ucast_vlan",
+ "fc_tx_mcast_octets",
+ "fc_tx_mcast",
+ "fc_tx_mcast_vlan",
+ "fc_tx_bcast_octets",
+ "fc_tx_bcast",
+ "fc_tx_bcast_vlan",
+ "fc_tx_parity_errors",
+ "fc_tx_timeout",
+ "fc_tx_fid_parity_errors",
+
+ "txf0_ucast_octets",
+ "txf0_ucast",
+ "txf0_ucast_vlan",
+ "txf0_mcast_octets",
+ "txf0_mcast",
+ "txf0_mcast_vlan",
+ "txf0_bcast_octets",
+ "txf0_bcast",
+ "txf0_bcast_vlan",
+ "txf0_errors",
+ "txf0_filter_vlan",
+ "txf0_filter_mac_sa"
+};
+
+static int bnad_get_regs_len(struct net_device *netdev);
+static int bnad_get_stats_count_locked(struct net_device *netdev);
+
+static int
+bnad_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ struct bna_port_param port_param;
+
+ spin_lock_irq(&bnad->priv_lock);
+ bna_port_param_get(bnad->priv, &port_param);
+ spin_unlock_irq(&bnad->priv_lock);
+
+ if (port_param.speed == BNA_LINK_SPEED_10Gbps) {
+ cmd->supported = SUPPORTED_10000baseT_Full;
+ cmd->advertising = ADVERTISED_10000baseT_Full;
+ }
+
+ if (port_param.autoneg) {
+ cmd->supported |= SUPPORTED_Autoneg;
+ cmd->advertising |= ADVERTISED_Autoneg;
+ cmd->autoneg = AUTONEG_ENABLE;
+ } else
+ cmd->autoneg = AUTONEG_DISABLE;
+ cmd->supported |= SUPPORTED_FIBRE;
+ cmd->advertising |= ADVERTISED_FIBRE;
+ cmd->port = PORT_FIBRE;
+ cmd->phy_address = 0;
+
+ if (netif_carrier_ok(netdev)) {
+ cmd->speed = SPEED_10000;
+ cmd->duplex = DUPLEX_FULL;
+ } else {
+ cmd->speed = -1;
+ cmd->duplex = -1;
+ }
+ cmd->transceiver = XCVR_EXTERNAL;
+ cmd->maxtxpkt = 0;
+ cmd->maxrxpkt = 0;
+
+ return 0;
+}
+
+static int
+bnad_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
+{
+ /* 10G full duplex setting supported only */
+ if (cmd->autoneg == AUTONEG_ENABLE) {
+ return -EOPNOTSUPP;
+ } else {
+ if ((cmd->speed == SPEED_10000) && (cmd->duplex == DUPLEX_FULL))
+ return 0;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static void
+bnad_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ struct bfa_ioc_attr *ioc_attr;
+
+ strcpy(drvinfo->driver, BNAD_NAME);
+ strcpy(drvinfo->version, BNAD_VERSION);
+
+ ioc_attr = kzalloc(sizeof(*ioc_attr), GFP_KERNEL);
+ if (ioc_attr) {
+ memset(ioc_attr, 0, sizeof(*ioc_attr));
+ spin_lock_irq(&bnad->priv_lock);
+ bna_iocll_getattr(bnad->priv, ioc_attr);
+ spin_unlock_irq(&bnad->priv_lock);
+
+ strncpy(drvinfo->fw_version, ioc_attr->adapter_attr.fw_ver,
+ sizeof(drvinfo->fw_version) - 1);
+ kfree(ioc_attr);
+ }
+
+ strncpy(drvinfo->bus_info, pci_name(bnad->pcidev), ETHTOOL_BUSINFO_LEN);
+}
+
+static int
+get_regs(struct bnad *bnad, u32 * regs)
+{
+ int num = 0, i;
+ u32 reg_addr;
+
+#define BNAD_GET_REG(addr) \
+do { \
+ if (regs) \
+ regs[num++] = readl(bnad->bar0 + (addr)); \
+ else \
+ num++; \
+} while (0)
+
+ spin_lock_irq(&bnad->priv_lock);
+
+ /* DMA Block Internal Registers */
+ BNAD_GET_REG(DMA_CTRL_REG0);
+ BNAD_GET_REG(DMA_CTRL_REG1);
+ BNAD_GET_REG(DMA_ERR_INT_STATUS);
+ BNAD_GET_REG(DMA_ERR_INT_ENABLE);
+ BNAD_GET_REG(DMA_ERR_INT_STATUS_SET);
+
+ /* APP Block Register Address Offset from BAR0 */
+ BNAD_GET_REG(HOSTFN0_INT_STATUS);
+ BNAD_GET_REG(HOSTFN0_INT_MASK);
+ BNAD_GET_REG(HOST_PAGE_NUM_FN0);
+ BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN0);
+ BNAD_GET_REG(FN0_PCIE_ERR_REG);
+ BNAD_GET_REG(FN0_ERR_TYPE_STATUS_REG);
+ BNAD_GET_REG(FN0_ERR_TYPE_MSK_STATUS_REG);
+
+ BNAD_GET_REG(HOSTFN1_INT_STATUS);
+ BNAD_GET_REG(HOSTFN1_INT_MASK);
+ BNAD_GET_REG(HOST_PAGE_NUM_FN1);
+ BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN1);
+ BNAD_GET_REG(FN1_PCIE_ERR_REG);
+ BNAD_GET_REG(FN1_ERR_TYPE_STATUS_REG);
+ BNAD_GET_REG(FN1_ERR_TYPE_MSK_STATUS_REG);
+
+ BNAD_GET_REG(PCIE_MISC_REG);
+
+ BNAD_GET_REG(HOST_SEM0_REG);
+ BNAD_GET_REG(HOST_SEM1_REG);
+ BNAD_GET_REG(HOST_SEM2_REG);
+ BNAD_GET_REG(HOST_SEM3_REG);
+ BNAD_GET_REG(HOST_SEM0_INFO_REG);
+ BNAD_GET_REG(HOST_SEM1_INFO_REG);
+ BNAD_GET_REG(HOST_SEM2_INFO_REG);
+ BNAD_GET_REG(HOST_SEM3_INFO_REG);
+
+ BNAD_GET_REG(TEMPSENSE_CNTL_REG);
+ BNAD_GET_REG(TEMPSENSE_STAT_REG);
+
+ BNAD_GET_REG(APP_LOCAL_ERR_STAT);
+ BNAD_GET_REG(APP_LOCAL_ERR_MSK);
+
+ BNAD_GET_REG(PCIE_LNK_ERR_STAT);
+ BNAD_GET_REG(PCIE_LNK_ERR_MSK);
+
+ BNAD_GET_REG(FCOE_FIP_ETH_TYPE);
+ BNAD_GET_REG(RESV_ETH_TYPE);
+
+ BNAD_GET_REG(HOSTFN2_INT_STATUS);
+ BNAD_GET_REG(HOSTFN2_INT_MASK);
+ BNAD_GET_REG(HOST_PAGE_NUM_FN2);
+ BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN2);
+ BNAD_GET_REG(FN2_PCIE_ERR_REG);
+ BNAD_GET_REG(FN2_ERR_TYPE_STATUS_REG);
+ BNAD_GET_REG(FN2_ERR_TYPE_MSK_STATUS_REG);
+
+ BNAD_GET_REG(HOSTFN3_INT_STATUS);
+ BNAD_GET_REG(HOSTFN3_INT_MASK);
+ BNAD_GET_REG(HOST_PAGE_NUM_FN3);
+ BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN3);
+ BNAD_GET_REG(FN3_PCIE_ERR_REG);
+ BNAD_GET_REG(FN3_ERR_TYPE_STATUS_REG);
+ BNAD_GET_REG(FN3_ERR_TYPE_MSK_STATUS_REG);
+
+ /* Host Command Status Registers */
+ reg_addr = HOST_CMDSTS0_CLR_REG;
+ for (i = 0; i < 16; i++) {
+ BNAD_GET_REG(reg_addr);
+ BNAD_GET_REG(reg_addr + 4);
+ BNAD_GET_REG(reg_addr + 8);
+ reg_addr += 0x10;
+ }
+
+ /* Function ID register */
+ BNAD_GET_REG(FNC_ID_REG);
+
+ /* Function personality register */
+ BNAD_GET_REG(FNC_PERS_REG);
+
+ /* Operation mode register */
+ BNAD_GET_REG(OP_MODE);
+
+ /* LPU0 Registers */
+ BNAD_GET_REG(LPU0_MBOX_CTL_REG);
+ BNAD_GET_REG(LPU0_MBOX_CMD_REG);
+ BNAD_GET_REG(LPU0_MBOX_LINK_0REG);
+ BNAD_GET_REG(LPU1_MBOX_LINK_0REG);
+ BNAD_GET_REG(LPU0_MBOX_STATUS_0REG);
+ BNAD_GET_REG(LPU1_MBOX_STATUS_0REG);
+ BNAD_GET_REG(LPU0_ERR_STATUS_REG);
+ BNAD_GET_REG(LPU0_ERR_SET_REG);
+
+ /* LPU1 Registers */
+ BNAD_GET_REG(LPU1_MBOX_CTL_REG);
+ BNAD_GET_REG(LPU1_MBOX_CMD_REG);
+ BNAD_GET_REG(LPU0_MBOX_LINK_1REG);
+ BNAD_GET_REG(LPU1_MBOX_LINK_1REG);
+ BNAD_GET_REG(LPU0_MBOX_STATUS_1REG);
+ BNAD_GET_REG(LPU1_MBOX_STATUS_1REG);
+ BNAD_GET_REG(LPU1_ERR_STATUS_REG);
+ BNAD_GET_REG(LPU1_ERR_SET_REG);
+
+ /* PSS Registers */
+ BNAD_GET_REG(PSS_CTL_REG);
+ BNAD_GET_REG(PSS_ERR_STATUS_REG);
+ BNAD_GET_REG(ERR_STATUS_SET);
+ BNAD_GET_REG(PSS_RAM_ERR_STATUS_REG);
+
+ /* Catapult CPQ Registers */
+ BNAD_GET_REG(HOSTFN0_LPU0_MBOX0_CMD_STAT);
+ BNAD_GET_REG(HOSTFN0_LPU1_MBOX0_CMD_STAT);
+ BNAD_GET_REG(LPU0_HOSTFN0_MBOX0_CMD_STAT);
+ BNAD_GET_REG(LPU1_HOSTFN0_MBOX0_CMD_STAT);
+
+ BNAD_GET_REG(HOSTFN0_LPU0_MBOX1_CMD_STAT);
+ BNAD_GET_REG(HOSTFN0_LPU1_MBOX1_CMD_STAT);
+ BNAD_GET_REG(LPU0_HOSTFN0_MBOX1_CMD_STAT);
+ BNAD_GET_REG(LPU1_HOSTFN0_MBOX1_CMD_STAT);
+
+ BNAD_GET_REG(HOSTFN1_LPU0_MBOX0_CMD_STAT);
+ BNAD_GET_REG(HOSTFN1_LPU1_MBOX0_CMD_STAT);
+ BNAD_GET_REG(LPU0_HOSTFN1_MBOX0_CMD_STAT);
+ BNAD_GET_REG(LPU1_HOSTFN1_MBOX0_CMD_STAT);
+
+ BNAD_GET_REG(HOSTFN1_LPU0_MBOX1_CMD_STAT);
+ BNAD_GET_REG(HOSTFN1_LPU1_MBOX1_CMD_STAT);
+ BNAD_GET_REG(LPU0_HOSTFN1_MBOX1_CMD_STAT);
+ BNAD_GET_REG(LPU1_HOSTFN1_MBOX1_CMD_STAT);
+
+ BNAD_GET_REG(HOSTFN2_LPU0_MBOX0_CMD_STAT);
+ BNAD_GET_REG(HOSTFN2_LPU1_MBOX0_CMD_STAT);
+ BNAD_GET_REG(LPU0_HOSTFN2_MBOX0_CMD_STAT);
+ BNAD_GET_REG(LPU1_HOSTFN2_MBOX0_CMD_STAT);
+
+ BNAD_GET_REG(HOSTFN2_LPU0_MBOX1_CMD_STAT);
+ BNAD_GET_REG(HOSTFN2_LPU1_MBOX1_CMD_STAT);
+ BNAD_GET_REG(LPU0_HOSTFN2_MBOX1_CMD_STAT);
+ BNAD_GET_REG(LPU1_HOSTFN2_MBOX1_CMD_STAT);
+
+ BNAD_GET_REG(HOSTFN3_LPU0_MBOX0_CMD_STAT);
+ BNAD_GET_REG(HOSTFN3_LPU1_MBOX0_CMD_STAT);
+ BNAD_GET_REG(LPU0_HOSTFN3_MBOX0_CMD_STAT);
+ BNAD_GET_REG(LPU1_HOSTFN3_MBOX0_CMD_STAT);
+
+ BNAD_GET_REG(HOSTFN3_LPU0_MBOX1_CMD_STAT);
+ BNAD_GET_REG(HOSTFN3_LPU1_MBOX1_CMD_STAT);
+ BNAD_GET_REG(LPU0_HOSTFN3_MBOX1_CMD_STAT);
+ BNAD_GET_REG(LPU1_HOSTFN3_MBOX1_CMD_STAT);
+
+ /* Host Function Force Parity Error Registers */
+ BNAD_GET_REG(HOSTFN0_LPU_FORCE_PERR);
+ BNAD_GET_REG(HOSTFN1_LPU_FORCE_PERR);
+ BNAD_GET_REG(HOSTFN2_LPU_FORCE_PERR);
+ BNAD_GET_REG(HOSTFN3_LPU_FORCE_PERR);
+
+ /* LL Port[0|1] Halt Mask Registers */
+ BNAD_GET_REG(LL_HALT_MSK_P0);
+ BNAD_GET_REG(LL_HALT_MSK_P1);
+
+ /* LL Port[0|1] Error Mask Registers */
+ BNAD_GET_REG(LL_ERR_MSK_P0);
+ BNAD_GET_REG(LL_ERR_MSK_P1);
+
+ /* EMC FLI Registers */
+ BNAD_GET_REG(FLI_CMD_REG);
+ BNAD_GET_REG(FLI_ADDR_REG);
+ BNAD_GET_REG(FLI_CTL_REG);
+ BNAD_GET_REG(FLI_WRDATA_REG);
+ BNAD_GET_REG(FLI_RDDATA_REG);
+ BNAD_GET_REG(FLI_DEV_STATUS_REG);
+ BNAD_GET_REG(FLI_SIG_WD_REG);
+
+ BNAD_GET_REG(FLI_DEV_VENDOR_REG);
+ BNAD_GET_REG(FLI_ERR_STATUS_REG);
+
+ /* RxAdm 0 Registers */
+ BNAD_GET_REG(RAD0_CTL_REG);
+ BNAD_GET_REG(RAD0_PE_PARM_REG);
+ BNAD_GET_REG(RAD0_BCN_REG);
+ BNAD_GET_REG(RAD0_DEFAULT_REG);
+ BNAD_GET_REG(RAD0_PROMISC_REG);
+ BNAD_GET_REG(RAD0_BCNQ_REG);
+ BNAD_GET_REG(RAD0_DEFAULTQ_REG);
+
+ BNAD_GET_REG(RAD0_ERR_STS);
+ BNAD_GET_REG(RAD0_SET_ERR_STS);
+ BNAD_GET_REG(RAD0_ERR_INT_EN);
+ BNAD_GET_REG(RAD0_FIRST_ERR);
+ BNAD_GET_REG(RAD0_FORCE_ERR);
+
+ BNAD_GET_REG(RAD0_MAC_MAN_1H);
+ BNAD_GET_REG(RAD0_MAC_MAN_1L);
+ BNAD_GET_REG(RAD0_MAC_MAN_2H);
+ BNAD_GET_REG(RAD0_MAC_MAN_2L);
+ BNAD_GET_REG(RAD0_MAC_MAN_3H);
+ BNAD_GET_REG(RAD0_MAC_MAN_3L);
+ BNAD_GET_REG(RAD0_MAC_MAN_4H);
+ BNAD_GET_REG(RAD0_MAC_MAN_4L);
+
+ BNAD_GET_REG(RAD0_LAST4_IP);
+
+ /* RxAdm 1 Registers */
+ BNAD_GET_REG(RAD1_CTL_REG);
+ BNAD_GET_REG(RAD1_PE_PARM_REG);
+ BNAD_GET_REG(RAD1_BCN_REG);
+ BNAD_GET_REG(RAD1_DEFAULT_REG);
+ BNAD_GET_REG(RAD1_PROMISC_REG);
+ BNAD_GET_REG(RAD1_BCNQ_REG);
+ BNAD_GET_REG(RAD1_DEFAULTQ_REG);
+
+ BNAD_GET_REG(RAD1_ERR_STS);
+ BNAD_GET_REG(RAD1_SET_ERR_STS);
+ BNAD_GET_REG(RAD1_ERR_INT_EN);
+
+ /* TxA0 Registers */
+ BNAD_GET_REG(TXA0_CTRL_REG);
+ /* TxA0 TSO Sequence # Registers (RO) */
+ for (i = 0; i < 8; i++) {
+ BNAD_GET_REG(TXA0_TSO_TCP_SEQ_REG(i));
+ BNAD_GET_REG(TXA0_TSO_IP_INFO_REG(i));
+ }
+
+ /* TxA1 Registers */
+ BNAD_GET_REG(TXA1_CTRL_REG);
+ /* TxA1 TSO Sequence # Registers (RO) */
+ for (i = 0; i < 8; i++) {
+ BNAD_GET_REG(TXA1_TSO_TCP_SEQ_REG(i));
+ BNAD_GET_REG(TXA1_TSO_IP_INFO_REG(i));
+ }
+
+ /* RxA Registers */
+ BNAD_GET_REG(RXA0_CTL_REG);
+ BNAD_GET_REG(RXA1_CTL_REG);
+
+ /* PLB0 Registers */
+ BNAD_GET_REG(PLB0_ECM_TIMER_REG);
+ BNAD_GET_REG(PLB0_RL_CTL);
+ for (i = 0; i < 8; i++)
+ BNAD_GET_REG(PLB0_RL_MAX_BC(i));
+ BNAD_GET_REG(PLB0_RL_TU_PRIO);
+ for (i = 0; i < 8; i++)
+ BNAD_GET_REG(PLB0_RL_BYTE_CNT(i));
+ BNAD_GET_REG(PLB0_RL_MIN_REG);
+ BNAD_GET_REG(PLB0_RL_MAX_REG);
+ BNAD_GET_REG(PLB0_EMS_ADD_REG);
+
+ /* PLB1 Registers */
+ BNAD_GET_REG(PLB1_ECM_TIMER_REG);
+ BNAD_GET_REG(PLB1_RL_CTL);
+ for (i = 0; i < 8; i++)
+ BNAD_GET_REG(PLB1_RL_MAX_BC(i));
+ BNAD_GET_REG(PLB1_RL_TU_PRIO);
+ for (i = 0; i < 8; i++)
+ BNAD_GET_REG(PLB1_RL_BYTE_CNT(i));
+ BNAD_GET_REG(PLB1_RL_MIN_REG);
+ BNAD_GET_REG(PLB1_RL_MAX_REG);
+ BNAD_GET_REG(PLB1_EMS_ADD_REG);
+
+ /* HQM Control Register */
+ BNAD_GET_REG(HQM0_CTL_REG);
+ BNAD_GET_REG(HQM0_RXQ_STOP_SEM);
+ BNAD_GET_REG(HQM0_TXQ_STOP_SEM);
+ BNAD_GET_REG(HQM1_CTL_REG);
+ BNAD_GET_REG(HQM1_RXQ_STOP_SEM);
+ BNAD_GET_REG(HQM1_TXQ_STOP_SEM);
+
+ /* LUT Registers */
+ BNAD_GET_REG(LUT0_ERR_STS);
+ BNAD_GET_REG(LUT0_SET_ERR_STS);
+ BNAD_GET_REG(LUT1_ERR_STS);
+ BNAD_GET_REG(LUT1_SET_ERR_STS);
+
+ /* TRC Registers */
+ BNAD_GET_REG(TRC_CTL_REG);
+ BNAD_GET_REG(TRC_MODS_REG);
+ BNAD_GET_REG(TRC_TRGC_REG);
+ BNAD_GET_REG(TRC_CNT1_REG);
+ BNAD_GET_REG(TRC_CNT2_REG);
+ BNAD_GET_REG(TRC_NXTS_REG);
+ BNAD_GET_REG(TRC_DIRR_REG);
+ for (i = 0; i < 10; i++)
+ BNAD_GET_REG(TRC_TRGM_REG(i));
+ for (i = 0; i < 10; i++)
+ BNAD_GET_REG(TRC_NXTM_REG(i));
+ for (i = 0; i < 10; i++)
+ BNAD_GET_REG(TRC_STRM_REG(i));
+
+ spin_unlock_irq(&bnad->priv_lock);
+#undef BNAD_GET_REG
+ return num;
+}
+
+static int
+bnad_get_regs_len(struct net_device *netdev)
+{
+ int ret = get_regs(netdev_priv(netdev), NULL) * sizeof(u32);
+ return ret;
+}
+
+static void
+bnad_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *buf)
+{
+ memset(buf, 0, bnad_get_regs_len(netdev));
+ get_regs(netdev_priv(netdev), buf);
+}
+
+static void
+bnad_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wolinfo)
+{
+ wolinfo->supported = 0;
+ wolinfo->wolopts = 0;
+}
+
+static int
+bnad_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ coalesce->rx_coalesce_usecs =
+ bnad->rx_coalescing_timeo * BNAD_COALESCING_TIMER_UNIT;
+ coalesce->rx_max_coalesced_frames = bnad->rx_interpkt_count;
+ coalesce->rx_coalesce_usecs_irq = bnad->rx_interpkt_timeo;
+ coalesce->tx_coalesce_usecs =
+ bnad->tx_coalescing_timeo * BNAD_COALESCING_TIMER_UNIT;
+ coalesce->tx_max_coalesced_frames = bnad->tx_interpkt_count;
+
+ coalesce->use_adaptive_rx_coalesce = bnad->rx_dyn_coalesce_on;
+ return 0;
+}
+
+static int
+bnad_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int i, err = 0, reset = 0;
+ u16 ib_id;
+
+ if (coalesce->rx_coalesce_usecs == 0 ||
+ coalesce->rx_coalesce_usecs >
+ BNAD_MAX_COALESCING_TIMEO * BNAD_COALESCING_TIMER_UNIT)
+ return -EINVAL;
+ if (coalesce->rx_max_coalesced_frames > BNAD_MAX_INTERPKT_COUNT)
+ return -EINVAL;
+ if (coalesce->rx_coalesce_usecs_irq == 0 ||
+ coalesce->rx_coalesce_usecs_irq > BNAD_MAX_INTERPKT_TIMEO)
+ return -EINVAL;
+
+ if (coalesce->tx_coalesce_usecs == 0 ||
+ coalesce->tx_coalesce_usecs >
+ BNAD_MAX_COALESCING_TIMEO * BNAD_COALESCING_TIMER_UNIT)
+ return -EINVAL;
+ if (coalesce->tx_max_coalesced_frames > BNAD_MAX_INTERPKT_COUNT)
+ return -EINVAL;
+
+ bnad_conf_lock();
+ spin_lock_irq(&bnad->priv_lock);
+
+ bnad->rx_dyn_coalesce_on = coalesce->use_adaptive_rx_coalesce;
+ if (bnad->rx_coalescing_timeo == 0)
+ bnad->rx_coalescing_timeo = 1;
+ if (bnad->state == BNAD_S_OPEN && !BNAD_NOT_READY(bnad)) {
+ for (i = 0; i < bnad->cq_num; i++) {
+ ib_id = bnad->cq_table[i].cq_config.ib_id;
+ bnad->ib_table[ib_id].ib_config.coalescing_timer =
+ bnad->rx_coalescing_timeo;
+ if (!bnad->rx_dyn_coalesce_on) {
+ bnad->cq_table[i].rx_coalescing_timeo =
+ bnad->rx_coalescing_timeo;
+ }
+ }
+ }
+ if (coalesce->rx_max_coalesced_frames != bnad->rx_interpkt_count) {
+ bnad->rx_interpkt_count = coalesce->rx_max_coalesced_frames;
+ reset++;
+ }
+ if (coalesce->rx_coalesce_usecs_irq != bnad->rx_interpkt_timeo) {
+ bnad->rx_interpkt_timeo = coalesce->rx_coalesce_usecs_irq;
+ reset++;
+ }
+
+ bnad->tx_coalescing_timeo =
+ coalesce->tx_coalesce_usecs / BNAD_COALESCING_TIMER_UNIT;
+ if (bnad->tx_coalescing_timeo == 0)
+ bnad->tx_coalescing_timeo = 1;
+ if (bnad->state == BNAD_S_OPEN && !BNAD_NOT_READY(bnad)) {
+ for (i = 0; i < bnad->txq_num; i++) {
+ ib_id = bnad->txq_table[i].txq_config.ib_id;
+ bnad->ib_table[ib_id].ib_config.coalescing_timer =
+ bnad->tx_coalescing_timeo;
+ }
+ }
+ if (coalesce->tx_max_coalesced_frames != bnad->tx_interpkt_count) {
+ bnad->tx_interpkt_count = coalesce->tx_max_coalesced_frames;
+ reset++;
+ }
+
+ spin_unlock_irq(&bnad->priv_lock);
+
+ if (reset)
+ err = bnad_sw_reset_locked(netdev);
+
+ bnad_conf_unlock();
+
+ return err;
+}
+
+static void
+bnad_get_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *ringparam)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ ringparam->rx_max_pending = BNAD_MAX_Q_DEPTH / bnad_rxqs_per_cq;
+ ringparam->rx_mini_max_pending = 0;
+ ringparam->rx_jumbo_max_pending = 0;
+ ringparam->tx_max_pending = BNAD_MAX_Q_DEPTH;
+
+ ringparam->rx_pending = bnad->rxq_depth;
+ ringparam->rx_mini_max_pending = 0;
+ ringparam->rx_jumbo_max_pending = 0;
+ ringparam->tx_pending = bnad->txq_depth;
+}
+
+static int
+bnad_set_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *ringparam)
+{
+ int err = 0;
+ struct bnad *bnad = netdev_priv(netdev);
+
+ bnad_conf_lock();
+ if (ringparam->rx_pending == bnad->rxq_depth &&
+ ringparam->tx_pending == bnad->txq_depth) {
+ bnad_conf_unlock();
+ return 0;
+ }
+
+ if (ringparam->rx_pending < BNAD_MIN_Q_DEPTH ||
+ ringparam->rx_pending > BNAD_MAX_Q_DEPTH / bnad_rxqs_per_cq ||
+ !BNA_POWER_OF_2(ringparam->rx_pending)) {
+ bnad_conf_unlock();
+ return -EINVAL;
+ }
+ if (ringparam->tx_pending < BNAD_MIN_Q_DEPTH ||
+ ringparam->tx_pending > BNAD_MAX_Q_DEPTH ||
+ !BNA_POWER_OF_2(ringparam->tx_pending)) {
+ bnad_conf_unlock();
+ return -EINVAL;
+ }
+
+ if (ringparam->rx_pending != bnad->rxq_depth) {
+ bnad->rxq_depth = ringparam->rx_pending;
+ bnad->config |= BNAD_CF_RXQ_DEPTH;
+ }
+ if (ringparam->tx_pending != bnad->txq_depth) {
+ bnad->txq_depth = ringparam->tx_pending;
+ bnad->config |= BNAD_CF_TXQ_DEPTH;
+ }
+
+ err = bnad_sw_reset_locked(netdev);
+
+ bnad_conf_unlock();
+ return err;
+}
+
+static void
+bnad_get_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *pauseparam)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ pauseparam->autoneg = 0;
+ pauseparam->rx_pause = bnad->pause_config.rx_pause;
+ pauseparam->tx_pause = bnad->pause_config.tx_pause;
+}
+
+static int
+bnad_set_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *pauseparam)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ if (pauseparam->autoneg == AUTONEG_ENABLE)
+ return -EINVAL;
+
+ bnad_conf_lock();
+ if (pauseparam->rx_pause != bnad->pause_config.rx_pause ||
+ pauseparam->tx_pause != bnad->pause_config.tx_pause) {
+ bnad->pause_config.rx_pause = pauseparam->rx_pause;
+ bnad->pause_config.tx_pause = pauseparam->tx_pause;
+ spin_lock_irq(&bnad->priv_lock);
+ bna_set_pause_config(bnad->priv, &bnad->pause_config, bnad);
+ spin_unlock_irq(&bnad->priv_lock);
+ }
+ bnad_conf_unlock();
+ return 0;
+}
+
+static u32
+bnad_get_rx_csum(struct net_device *netdev)
+{
+ u32 rx_csum;
+ struct bnad *bnad = netdev_priv(netdev);
+
+ rx_csum = bnad->rx_csum;
+ return rx_csum;
+}
+
+static int
+bnad_set_rx_csum(struct net_device *netdev, u32 rx_csum)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ bnad_conf_lock();
+ bnad->rx_csum = rx_csum;
+ bnad_conf_unlock();
+ return 0;
+}
+
+static int
+bnad_set_tx_csum(struct net_device *netdev, u32 tx_csum)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ bnad_conf_lock();
+ if (tx_csum) {
+ netdev->features |= NETIF_F_IP_CSUM;
+ netdev->features |= NETIF_F_IPV6_CSUM;
+ } else {
+ netdev->features &= ~NETIF_F_IP_CSUM;
+ netdev->features &= ~NETIF_F_IPV6_CSUM;
+ }
+ bnad_conf_unlock();
+ return 0;
+}
+
+static int
+bnad_set_tso(struct net_device *netdev, u32 tso)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+
+ bnad_conf_lock();
+ if (tso) {
+ netdev->features |= NETIF_F_TSO;
+ netdev->features |= NETIF_F_TSO6;
+ } else {
+ netdev->features &= ~NETIF_F_TSO;
+ netdev->features &= ~NETIF_F_TSO6;
+ }
+ bnad_conf_unlock();
+ return 0;
+}
+
+static void
+bnad_get_strings(struct net_device *netdev, u32 stringset, u8 * string)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int i;
+ bnad_conf_lock();
+
+ switch (stringset) {
+ case ETH_SS_STATS:
+ for (i = 0; i < BNAD_ETHTOOL_STATS_NUM; i++) {
+ BNA_ASSERT(strlen(bnad_net_stats_strings[i]) <
+ ETH_GSTRING_LEN);
+ memcpy(string, bnad_net_stats_strings[i],
+ ETH_GSTRING_LEN);
+ string += ETH_GSTRING_LEN;
+ }
+
+ i = 0;
+ sprintf(string, "rxf%d_ucast_octets", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxf%d_ucast", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxf%d_ucast_vlan", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxf%d_mcast_octets", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxf%d_mcast", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxf%d_mcast_vlan", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxf%d_bcast_octets", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxf%d_bcast", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxf%d_bcast_vlan", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxf%d_frame_drops", i);
+ string += ETH_GSTRING_LEN;
+
+ sprintf(string, "netif_queue_stopped");
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "bna_state");
+ string += ETH_GSTRING_LEN;
+
+ for (i = 0; i < bnad->cq_num; i++) {
+ sprintf(string, "cq%d_producer_index", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "cq%d_consumer_index", i);
+ string += ETH_GSTRING_LEN;
+ }
+
+ for (i = 0; i < bnad->rxq_num; i++) {
+ sprintf(string, "rxq%d_packets", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxq%d_bytes", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxq%d_packets_with_error", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxq%d_allocbuf_failed", i);
+ string += ETH_GSTRING_LEN;
+
+ sprintf(string, "rxq%d_producer_index", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "rxq%d_consumer_index", i);
+ string += ETH_GSTRING_LEN;
+ }
+
+ for (i = 0; i < bnad->txq_num; i++) {
+ sprintf(string, "txq%d_packets", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "txq%d_bytes", i);
+ string += ETH_GSTRING_LEN;
+
+ sprintf(string, "txq%d_producer_index", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "txq%d_consumer_index", i);
+ string += ETH_GSTRING_LEN;
+ sprintf(string, "txq%d_hw_consumer_index", i);
+ string += ETH_GSTRING_LEN;
+ }
+ break;
+
+ default:
+ break;
+}
+
+bnad_conf_unlock();
+}
+
+
+static void
+bnad_get_ethtool_stats(struct net_device *netdev, struct ethtool_stats *stats,
+ u64 *buf)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int i, bi;
+ unsigned long *net_stats;
+ u64 *stats64;
+
+ bnad_conf_lock();
+ if (bnad_get_stats_count_locked(netdev) != stats->n_stats)
+ goto mismatch;
+
+ bi = 0;
+ memset(buf, 0, stats->n_stats * sizeof(u64));
+ bnad_get_stats(netdev);
+
+ net_stats = (unsigned long *)&bnad->net_stats;
+ for (i = 0; i < sizeof(struct net_device_stats) / sizeof(unsigned long);
+ i++)
+ buf[bi++] = net_stats[i];
+
+ stats64 = (u64 *)&bnad->stats;
+ for (i = 0; i < sizeof(struct bnad_drv_stats) / sizeof(u64); i++)
+ buf[bi++] = stats64[i];
+
+ stats64 = (u64 *) bnad->hw_stats;
+ for (i = 0;
+ i < offsetof(struct bna_stats, rxf_stats[0]) / sizeof(u64);
+ i++)
+ buf[bi++] = stats64[i];
+
+ stats64 = (u64 *)&bnad->hw_stats->txf_stats[0];
+ for (i = 0; i < sizeof(struct bna_stats_txf) / sizeof(u64); i++)
+ buf[bi++] = stats64[i];
+
+ stats64 = (u64 *)&bnad->hw_stats->rxf_stats[0];
+ for (i = 0; i < sizeof(struct bna_stats_rxf) / sizeof(u64); i++)
+ buf[bi++] = stats64[i];
+
+ buf[bi++] = netif_queue_stopped(netdev);
+ buf[bi++] = bnad->state;
+
+ if (bnad->cq_table && bnad->rxq_table && bnad->txq_table) {
+ for (i = 0; i < bnad->cq_num; i++) {
+ buf[bi++] = bnad->cq_table[i].cq.q.producer_index;
+ buf[bi++] = bnad->cq_table[i].cq.q.consumer_index;
+ }
+
+ for (i = 0; i < bnad->rxq_num; i++) {
+ buf[bi++] = bnad->rxq_table[i].rx_packets;
+ buf[bi++] = bnad->rxq_table[i].rx_bytes;
+ buf[bi++] = bnad->rxq_table[i].rx_packets_with_error;
+ buf[bi++] = bnad->rxq_table[i].rxbuf_alloc_failed;
+
+ buf[bi++] = bnad->rxq_table[i].rxq.q.producer_index;
+ buf[bi++] = bnad->rxq_table[i].rxq.q.consumer_index;
+ }
+ for (i = 0; i < bnad->txq_num; i++) {
+ buf[bi++] = bnad->txq_table[i].tx_packets;
+ buf[bi++] = bnad->txq_table[i].tx_bytes;
+
+ buf[bi++] = bnad->txq_table[i].txq.q.producer_index;
+ buf[bi++] = bnad->txq_table[i].txq.q.consumer_index;
+ buf[bi++] = *(bnad->txq_table[i].hw_consumer_index);
+ }
+ }
+
+mismatch:
+ bnad_conf_unlock();
+}
+
+
+static int
+bnad_get_stats_count_locked(struct net_device *netdev)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int count;
+
+ count = BNAD_ETHTOOL_STATS_NUM + 10 + bnad->rxq_num * 4
+ + bnad->txq_num * 2;
+
+ /* netif_queue_stopped, state */
+ count += 2;
+
+ /* CQ producer_index, consumer_index */
+ count += bnad->cq_num * 2;
+
+ /* RxQ producer_index, consumer_index */
+ count += bnad->rxq_num * 2;
+
+ /* TxQ producer_index, consumer_index, hw_consumer_index */
+ count += bnad->txq_num * 3;
+ return count;
+}
+
+static int
+bnad_get_sset_count(struct net_device *netdev, int stringset)
+{
+ struct bnad *bnad = netdev_priv(netdev);
+ int count;
+
+ switch (stringset) {
+ case ETH_SS_STATS:
+ bnad_conf_lock();
+ count = bnad_get_stats_count_locked(netdev);
+ bnad_conf_unlock();
+ return count;
+ default:
+ return -EINVAL;
+ }
+}
+
+static struct ethtool_ops bnad_ethtool_ops = {
+ .get_settings = bnad_get_settings,
+ .set_settings = bnad_set_settings,
+ .get_drvinfo = bnad_get_drvinfo,
+ .get_regs_len = bnad_get_regs_len,
+ .get_regs = bnad_get_regs,
+ .get_wol = bnad_get_wol,
+ .get_msglevel = bnad_get_msglevel,
+ .set_msglevel = bnad_set_msglevel,
+ .get_link = ethtool_op_get_link,
+ .get_coalesce = bnad_get_coalesce,
+ .set_coalesce = bnad_set_coalesce,
+ .get_ringparam = bnad_get_ringparam,
+ .set_ringparam = bnad_set_ringparam,
+ .get_pauseparam = bnad_get_pauseparam,
+ .set_pauseparam = bnad_set_pauseparam,
+ .get_rx_csum = bnad_get_rx_csum,
+ .set_rx_csum = bnad_set_rx_csum,
+ .get_tx_csum = ethtool_op_get_tx_csum,
+ .set_tx_csum = bnad_set_tx_csum,
+ .get_sg = ethtool_op_get_sg,
+ .set_sg = ethtool_op_set_sg,
+ .get_tso = ethtool_op_get_tso,
+ .set_tso = bnad_set_tso,
+ .get_strings = bnad_get_strings,
+ .get_ethtool_stats = bnad_get_ethtool_stats,
+ .get_sset_count = bnad_get_sset_count
+};
+
+void
+bnad_set_ethtool_ops(struct net_device *netdev)
+{
+ SET_ETHTOOL_OPS(netdev, &bnad_ethtool_ops);
+}
^ permalink raw reply
* Subject: [PATCH 5/6] bna: Brocade 10Gb Ethernet device driver
From: Rasesh Mody @ 2009-11-13 3:46 UTC (permalink / raw)
To: netdev; +Cc: adapter_linux_open_src_team
From: Rasesh Mody <rmody@brocade.com>
This is patch 5/6 which contains linux driver source for
Brocade's BR1010/BR1020 10Gb CEE capable ethernet adapter.
Source is based against net-next-2.6.
We wish this patch to be considered for inclusion in net-next-2.6
Signed-off-by: Rasesh Mody <rmody@brocade.com>
---
bfa_callback_priv.h | 60 +++
bfa_fwimg_priv.h | 34 ++
include/bfi/bfi.h | 176 ++++++++++
include/bfi/bfi_boot.h | 37 ++
include/bfi/bfi_cee.h | 116 ++++++
include/bfi/bfi_ctreg.h | 637 ++++++++++++++++++++++++++++++++++++++
include/bfi/bfi_ioc.h | 204 ++++++++++++
include/bfi/bfi_ll.h | 434 +++++++++++++++++++++++++
include/cee/bfa_cee.h | 77 ++++
include/cna/pstats/ethport_defs.h | 37 ++
include/cna/pstats/phyport_defs.h | 206 ++++++++++++
include/cs/bfa_debug.h | 47 ++
include/cs/bfa_q.h | 84 +++++
include/cs/bfa_sm.h | 81 ++++
include/cs/bfa_trc.h | 179 ++++++++++
include/defs/bfa_defs_adapter.h | 85 +++++
include/defs/bfa_defs_cee.h | 156 +++++++++
include/defs/bfa_defs_ioc.h | 154 +++++++++
include/defs/bfa_defs_mfg.h | 144 ++++++++
include/defs/bfa_defs_pci.h | 44 ++
include/defs/bfa_defs_status.h | 267 +++++++++++++++
include/defs/bfa_defs_version.h | 25 +
include/protocol/types.h | 44 ++
23 files changed, 3328 insertions(+)
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_callback_priv.h net-next-2.6-mod/drivers/net/bna/bfa_callback_priv.h
--- net-next-2.6-orig/drivers/net/bna/bfa_callback_priv.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_callback_priv.h 2009-11-12 19:03:39.168339000 -0800
@@ -0,0 +1,60 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __BFA_CALLBACK_PRIV_H__
+#define __BFA_CALLBACK_PRIV_H__
+
+#include <cs/bfa_q.h>
+
+typedef void (*bfa_cb_cbfn_t) (void *cbarg, bool complete);
+
+/**
+ * Generic BFA callback element.
+ */
+struct bfa_cb_qe {
+ struct list_head qe;
+ bfa_cb_cbfn_t cbfn;
+ bool once;
+ u32 rsvd;
+ void *cbarg;
+};
+
+#define bfa_cb_queue(__bfa, __hcb_qe, __cbfn, __cbarg) do { \
+ (__hcb_qe)->cbfn = (__cbfn); \
+ (__hcb_qe)->cbarg = (__cbarg); \
+ list_add_tail(&(__hcb_qe)->qe, &(__bfa)->comp_q); \
+} while (0)
+
+#define bfa_cb_dequeue(__hcb_qe) list_del(&(__hcb_qe)->qe)
+
+#define bfa_cb_queue_once(__bfa, __hcb_qe, __cbfn, __cbarg) do { \
+ (__hcb_qe)->cbfn = (__cbfn); \
+ (__hcb_qe)->cbarg = (__cbarg); \
+ if (!(__hcb_qe)->once) { \
+ list_add_tail((__hcb_qe), &(__bfa)->comp_q); \
+ (__hcb_qe)->once = true; \
+ } \
+} while (0)
+
+#define bfa_cb_queue_done(__hcb_qe) do { \
+ (__hcb_qe)->once = false; \
+} while (0)
+
+#endif /* __BFA_CALLBACK_PRIV_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_fwimg_priv.h net-next-2.6-mod/drivers/net/bna/bfa_fwimg_priv.h
--- net-next-2.6-orig/drivers/net/bna/bfa_fwimg_priv.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_fwimg_priv.h 2009-11-12 19:03:39.175343000 -0800
@@ -0,0 +1,34 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __BFA_FWIMG_PRIV_H__
+#define __BFA_FWIMG_PRIV_H__
+
+#define BFI_FLASH_CHUNK_SZ 256 /* Flash chunk size */
+#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
+
+extern u32 *bfi_image_ct_get_chunk(u32 off);
+extern u32 bfi_image_ct_size;
+extern u32 *bfi_image_cb_get_chunk(u32 off);
+extern u32 bfi_image_cb_size;
+extern u32 *bfi_image_cb;
+extern u32 *bfi_image_ct;
+
+#endif /* __BFA_FWIMG_PRIV_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/bfi/bfi.h net-next-2.6-mod/drivers/net/bna/include/bfi/bfi.h
--- net-next-2.6-orig/drivers/net/bna/include/bfi/bfi.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/bfi/bfi.h 2009-11-12 19:03:39.216346000 -0800
@@ -0,0 +1,176 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __BFI_H__
+#define __BFI_H__
+
+#include <cna.h>
+#include <defs/bfa_defs_status.h>
+
+#pragma pack(1)
+
+/**
+ * Msg header common to all msgs
+ */
+struct bfi_mhdr {
+ u8 msg_class; /* @ref bfi_mclass_t */
+ u8 msg_id; /* msg opcode with in the class */
+ union {
+ struct {
+ u8 rsvd;
+ u8 lpu_id; /* msg destination */
+ } h2i;
+ u16 i2htok; /* token in msgs to host */
+ } mtag;
+};
+
+#define bfi_h2i_set(_mh, _mc, _op, _lpuid) do { \
+ (_mh).msg_class = (_mc); \
+ (_mh).msg_id = (_op); \
+ (_mh).mtag.h2i.lpu_id = (_lpuid); \
+} while (0)
+
+#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
+ (_mh).msg_class = (_mc); \
+ (_mh).msg_id = (_op); \
+ (_mh).mtag.i2htok = (_i2htok); \
+} while (0)
+
+/*
+ * Message opcodes: 0-127 to firmware, 128-255 to host
+ */
+#define BFI_I2H_OPCODE_BASE 128
+#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
+
+/**
+ ****************************************************************************
+ *
+ * Scatter Gather Element and Page definition
+ *
+ ****************************************************************************
+ */
+
+#define BFI_SGE_INLINE 1
+#define BFI_SGE_INLINE_MAX (BFI_SGE_INLINE + 1)
+
+/**
+ * SG Flags
+ */
+enum {
+ BFI_SGE_DATA = 0, /* data address, not last */
+ BFI_SGE_DATA_CPL = 1, /* data addr, last in current page */
+ BFI_SGE_DATA_LAST = 3, /* data address, last */
+ BFI_SGE_LINK = 2, /* link address */
+ BFI_SGE_PGDLEN = 2, /* cumulative data length for page */
+};
+
+/**
+ * DMA addresses
+ */
+union bfi_addr_u {
+ struct {
+ u32 addr_lo;
+ u32 addr_hi;
+ } a32;
+};
+
+/**
+ * Scatter Gather Element
+ */
+struct bfi_sge {
+#ifdef __BIGENDIAN
+ u32 flags:2,
+ rsvd:2,
+ sg_len:28;
+#else
+ u32 sg_len:28,
+ rsvd:2,
+ flags:2;
+#endif
+ union bfi_addr_u sga;
+};
+
+/**
+ * Scatter Gather Page
+ */
+#define BFI_SGPG_DATA_SGES 7
+#define BFI_SGPG_SGES_MAX (BFI_SGPG_DATA_SGES + 1)
+#define BFI_SGPG_RSVD_WD_LEN 8
+struct bfi_sgpg {
+ struct bfi_sge sges[BFI_SGPG_SGES_MAX];
+ u32 rsvd[BFI_SGPG_RSVD_WD_LEN];
+};
+
+/*
+ * Large Message structure - 128 Bytes size Msgs
+ */
+#define BFI_LMSG_SZ 128
+#define BFI_LMSG_PL_WSZ \
+ ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4)
+
+struct bfi_msg {
+ struct bfi_mhdr mhdr;
+ u32 pl[BFI_LMSG_PL_WSZ];
+};
+
+/**
+ * Mailbox message structure
+ */
+#define BFI_MBMSG_SZ 7
+struct bfi_mbmsg {
+ struct bfi_mhdr mh;
+ u32 pl[BFI_MBMSG_SZ];
+};
+
+/**
+ * Message Classes
+ */
+enum bfi_mclass {
+ BFI_MC_IOC = 1, /* IO Controller (IOC) */
+ BFI_MC_DIAG = 2, /* Diagnostic Msgs */
+ BFI_MC_FLASH = 3, /* Flash message class */
+ BFI_MC_CEE = 4, /* CEE */
+ BFI_MC_FCPORT = 5, /* FC port */
+ BFI_MC_IOCFC = 6, /* FC - IO Controller (IOC) */
+ BFI_MC_LL = 7, /* Link Layer */
+ BFI_MC_UF = 8, /* Unsolicited frame receive */
+ BFI_MC_FCXP = 9, /* FC Transport */
+ BFI_MC_LPS = 10, /* lport fc login services */
+ BFI_MC_RPORT = 11, /* Remote port */
+ BFI_MC_ITNIM = 12, /* I-T nexus (Initiator mode) */
+ BFI_MC_IOIM_READ = 13, /* read IO (Initiator mode) */
+ BFI_MC_IOIM_WRITE = 14, /* write IO (Initiator mode) */
+ BFI_MC_IOIM_IO = 15, /* IO (Initiator mode) */
+ BFI_MC_IOIM = 16, /* IO (Initiator mode) */
+ BFI_MC_IOIM_IOCOM = 17, /* good IO completion */
+ BFI_MC_TSKIM = 18, /* Initiator Task management */
+ BFI_MC_SBOOT = 19, /* SAN boot services */
+ BFI_MC_IPFC = 20, /* IP over FC Msgs */
+ BFI_MC_PORT = 21, /* Physical port */
+ BFI_MC_MAX = 32
+};
+
+#define BFI_IOC_MAX_CQS 4
+#define BFI_IOC_MAX_CQS_ASIC 8
+#define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */
+
+#pragma pack()
+
+#endif /* __BFI_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_boot.h net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_boot.h
--- net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_boot.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_boot.h 2009-11-12 19:03:39.225336000 -0800
@@ -0,0 +1,37 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+/*
+ * bfi_boot.h
+ */
+
+#ifndef __BFI_BOOT_H__
+#define __BFI_BOOT_H__
+
+#define BFI_BOOT_TYPE_OFF 8
+#define BFI_BOOT_PARAM_OFF 12
+
+#define BFI_BOOT_TYPE_NORMAL 0 /* param is device id */
+#define BFI_BOOT_TYPE_FLASH 1
+#define BFI_BOOT_TYPE_MEMTEST 2
+
+#define BFI_BOOT_MEMTEST_RES_ADDR 0x900
+#define BFI_BOOT_MEMTEST_RES_SIG 0xA0A1A2A3
+
+#endif
diff -ruP net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_cee.h net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_cee.h
--- net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_cee.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_cee.h 2009-11-12 19:03:39.240336000 -0800
@@ -0,0 +1,116 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/**
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * bfi_dcbx.h BFI Interface (Mailbox commands and related structures)
+ * between host driver and DCBX/LLDP firmware module.
+ *
+**/
+
+#ifndef __BFI_CEE_H__
+#define __BFI_CEE_H__
+
+#include <bfi/bfi.h>
+
+#pragma pack(1)
+
+
+enum bfi_cee_h2i_msgs_e {
+ BFI_CEE_H2I_GET_CFG_REQ = 1,
+ BFI_CEE_H2I_RESET_STATS = 2,
+ BFI_CEE_H2I_GET_STATS_REQ = 3,
+};
+
+
+enum bfi_cee_i2h_msgs_e {
+ BFI_CEE_I2H_GET_CFG_RSP = BFA_I2HM(1),
+ BFI_CEE_I2H_RESET_STATS_RSP = BFA_I2HM(2),
+ BFI_CEE_I2H_GET_STATS_RSP = BFA_I2HM(3),
+};
+
+
+/* Data structures */
+
+/*
+ * BFI_CEE_H2I_RESET_STATS
+ */
+struct bfi_lldp_reset_stats {
+ struct bfi_mhdr mh;
+};
+
+/*
+ * BFI_CEE_H2I_RESET_STATS
+ */
+struct bfi_cee_reset_stats {
+ struct bfi_mhdr mh;
+};
+
+/*
+ * BFI_CEE_H2I_GET_CFG_REQ
+ */
+struct bfi_cee_get_req {
+ struct bfi_mhdr mh;
+ union bfi_addr_u dma_addr;
+};
+
+
+/*
+ * BFI_CEE_I2H_GET_CFG_RSP
+ */
+struct bfi_cee_get_rsp {
+ struct bfi_mhdr mh;
+ u8 cmd_status;
+ u8 rsvd[3];
+};
+
+/*
+ * BFI_CEE_H2I_GET_STATS_REQ
+ */
+struct bfi_cee_stats_req {
+ struct bfi_mhdr mh;
+ union bfi_addr_u dma_addr;
+};
+
+
+/*
+ * BFI_CEE_I2H_GET_STATS_RSP
+ */
+struct bfi_cee_stats_rsp {
+ struct bfi_mhdr mh;
+ u8 cmd_status;
+ u8 rsvd[3];
+};
+
+
+
+union bfi_cee_h2i_msg_u {
+ struct bfi_mhdr mh;
+ struct bfi_cee_get_req get_req;
+ struct bfi_cee_stats_req stats_req;
+};
+
+
+union bfi_cee_i2h_msg_u {
+ struct bfi_mhdr mh;
+ struct bfi_cee_get_rsp get_rsp;
+ struct bfi_cee_stats_rsp stats_rsp;
+};
+
+#pragma pack()
+
+
+#endif /* __BFI_CEE_H__ */
+
diff -ruP net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_ctreg.h net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_ctreg.h
--- net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_ctreg.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_ctreg.h 2009-11-12 19:03:39.247341000 -0800
@@ -0,0 +1,637 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ */
+/*
+ * bfi_ctreg.h catapult host block register definitions
+ *
+ * !!! Do not edit. Auto generated. !!!
+ */
+
+#ifndef __BFI_CTREG_H__
+#define __BFI_CTREG_H__
+
+
+#define HOSTFN0_LPU_MBOX0_0 0x00019200
+#define HOSTFN1_LPU_MBOX0_8 0x00019260
+#define LPU_HOSTFN0_MBOX0_0 0x00019280
+#define LPU_HOSTFN1_MBOX0_8 0x000192e0
+#define HOSTFN2_LPU_MBOX0_0 0x00019400
+#define HOSTFN3_LPU_MBOX0_8 0x00019460
+#define LPU_HOSTFN2_MBOX0_0 0x00019480
+#define LPU_HOSTFN3_MBOX0_8 0x000194e0
+#define HOSTFN0_INT_STATUS 0x00014000
+#define __HOSTFN0_HALT_OCCURRED 0x01000000
+#define __HOSTFN0_INT_STATUS_LVL_MK 0x00f00000
+#define __HOSTFN0_INT_STATUS_LVL_SH 20
+#define __HOSTFN0_INT_STATUS_LVL(_v) ((_v) << __HOSTFN0_INT_STATUS_LVL_SH)
+#define __HOSTFN0_INT_STATUS_P_MK 0x000f0000
+#define __HOSTFN0_INT_STATUS_P_SH 16
+#define __HOSTFN0_INT_STATUS_P(_v) ((_v) << __HOSTFN0_INT_STATUS_P_SH)
+#define __HOSTFN0_INT_STATUS_F 0x0000ffff
+#define HOSTFN0_INT_MSK 0x00014004
+#define HOST_PAGE_NUM_FN0 0x00014008
+#define __HOST_PAGE_NUM_FN 0x000001ff
+#define HOST_MSIX_ERR_INDEX_FN0 0x0001400c
+#define __MSIX_ERR_INDEX_FN 0x000001ff
+#define HOSTFN1_INT_STATUS 0x00014100
+#define __HOSTFN1_HALT_OCCURRED 0x01000000
+#define __HOSTFN1_INT_STATUS_LVL_MK 0x00f00000
+#define __HOSTFN1_INT_STATUS_LVL_SH 20
+#define __HOSTFN1_INT_STATUS_LVL(_v) ((_v) << __HOSTFN1_INT_STATUS_LVL_SH)
+#define __HOSTFN1_INT_STATUS_P_MK 0x000f0000
+#define __HOSTFN1_INT_STATUS_P_SH 16
+#define __HOSTFN1_INT_STATUS_P(_v) ((_v) << __HOSTFN1_INT_STATUS_P_SH)
+#define __HOSTFN1_INT_STATUS_F 0x0000ffff
+#define HOSTFN1_INT_MSK 0x00014104
+#define HOST_PAGE_NUM_FN1 0x00014108
+#define HOST_MSIX_ERR_INDEX_FN1 0x0001410c
+#define APP_PLL_425_CTL_REG 0x00014204
+#define __P_425_PLL_LOCK 0x80000000
+#define __APP_PLL_425_SRAM_USE_100MHZ 0x00100000
+#define __APP_PLL_425_RESET_TIMER_MK 0x000e0000
+#define __APP_PLL_425_RESET_TIMER_SH 17
+#define __APP_PLL_425_RESET_TIMER(_v) ((_v) << __APP_PLL_425_RESET_TIMER_SH)
+#define __APP_PLL_425_LOGIC_SOFT_RESET 0x00010000
+#define __APP_PLL_425_CNTLMT0_1_MK 0x0000c000
+#define __APP_PLL_425_CNTLMT0_1_SH 14
+#define __APP_PLL_425_CNTLMT0_1(_v) ((_v) << __APP_PLL_425_CNTLMT0_1_SH)
+#define __APP_PLL_425_JITLMT0_1_MK 0x00003000
+#define __APP_PLL_425_JITLMT0_1_SH 12
+#define __APP_PLL_425_JITLMT0_1(_v) ((_v) << __APP_PLL_425_JITLMT0_1_SH)
+#define __APP_PLL_425_HREF 0x00000800
+#define __APP_PLL_425_HDIV 0x00000400
+#define __APP_PLL_425_P0_1_MK 0x00000300
+#define __APP_PLL_425_P0_1_SH 8
+#define __APP_PLL_425_P0_1(_v) ((_v) << __APP_PLL_425_P0_1_SH)
+#define __APP_PLL_425_Z0_2_MK 0x000000e0
+#define __APP_PLL_425_Z0_2_SH 5
+#define __APP_PLL_425_Z0_2(_v) ((_v) << __APP_PLL_425_Z0_2_SH)
+#define __APP_PLL_425_RSEL200500 0x00000010
+#define __APP_PLL_425_ENARST 0x00000008
+#define __APP_PLL_425_BYPASS 0x00000004
+#define __APP_PLL_425_LRESETN 0x00000002
+#define __APP_PLL_425_ENABLE 0x00000001
+#define APP_PLL_312_CTL_REG 0x00014208
+#define __P_312_PLL_LOCK 0x80000000
+#define __ENABLE_MAC_AHB_1 0x00800000
+#define __ENABLE_MAC_AHB_0 0x00400000
+#define __ENABLE_MAC_1 0x00200000
+#define __ENABLE_MAC_0 0x00100000
+#define __APP_PLL_312_RESET_TIMER_MK 0x000e0000
+#define __APP_PLL_312_RESET_TIMER_SH 17
+#define __APP_PLL_312_RESET_TIMER(_v) ((_v) << __APP_PLL_312_RESET_TIMER_SH)
+#define __APP_PLL_312_LOGIC_SOFT_RESET 0x00010000
+#define __APP_PLL_312_CNTLMT0_1_MK 0x0000c000
+#define __APP_PLL_312_CNTLMT0_1_SH 14
+#define __APP_PLL_312_CNTLMT0_1(_v) ((_v) << __APP_PLL_312_CNTLMT0_1_SH)
+#define __APP_PLL_312_JITLMT0_1_MK 0x00003000
+#define __APP_PLL_312_JITLMT0_1_SH 12
+#define __APP_PLL_312_JITLMT0_1(_v) ((_v) << __APP_PLL_312_JITLMT0_1_SH)
+#define __APP_PLL_312_HREF 0x00000800
+#define __APP_PLL_312_HDIV 0x00000400
+#define __APP_PLL_312_P0_1_MK 0x00000300
+#define __APP_PLL_312_P0_1_SH 8
+#define __APP_PLL_312_P0_1(_v) ((_v) << __APP_PLL_312_P0_1_SH)
+#define __APP_PLL_312_Z0_2_MK 0x000000e0
+#define __APP_PLL_312_Z0_2_SH 5
+#define __APP_PLL_312_Z0_2(_v) ((_v) << __APP_PLL_312_Z0_2_SH)
+#define __APP_PLL_312_RSEL200500 0x00000010
+#define __APP_PLL_312_ENARST 0x00000008
+#define __APP_PLL_312_BYPASS 0x00000004
+#define __APP_PLL_312_LRESETN 0x00000002
+#define __APP_PLL_312_ENABLE 0x00000001
+#define MBIST_CTL_REG 0x00014220
+#define __EDRAM_BISTR_START 0x00000004
+#define __MBIST_RESET 0x00000002
+#define __MBIST_START 0x00000001
+#define MBIST_STAT_REG 0x00014224
+#define __EDRAM_BISTR_STATUS 0x00000008
+#define __EDRAM_BISTR_DONE 0x00000004
+#define __MEM_BIT_STATUS 0x00000002
+#define __MBIST_DONE 0x00000001
+#define HOST_SEM0_REG 0x00014230
+#define __HOST_SEMAPHORE 0x00000001
+#define HOST_SEM1_REG 0x00014234
+#define HOST_SEM2_REG 0x00014238
+#define HOST_SEM3_REG 0x0001423c
+#define HOST_SEM0_INFO_REG 0x00014240
+#define HOST_SEM1_INFO_REG 0x00014244
+#define HOST_SEM2_INFO_REG 0x00014248
+#define HOST_SEM3_INFO_REG 0x0001424c
+#define ETH_MAC_SER_REG 0x00014288
+#define __APP_EMS_CKBUFAMPIN 0x00000020
+#define __APP_EMS_REFCLKSEL 0x00000010
+#define __APP_EMS_CMLCKSEL 0x00000008
+#define __APP_EMS_REFCKBUFEN2 0x00000004
+#define __APP_EMS_REFCKBUFEN1 0x00000002
+#define __APP_EMS_CHANNEL_SEL 0x00000001
+#define HOSTFN2_INT_STATUS 0x00014300
+#define __HOSTFN2_HALT_OCCURRED 0x01000000
+#define __HOSTFN2_INT_STATUS_LVL_MK 0x00f00000
+#define __HOSTFN2_INT_STATUS_LVL_SH 20
+#define __HOSTFN2_INT_STATUS_LVL(_v) ((_v) << __HOSTFN2_INT_STATUS_LVL_SH)
+#define __HOSTFN2_INT_STATUS_P_MK 0x000f0000
+#define __HOSTFN2_INT_STATUS_P_SH 16
+#define __HOSTFN2_INT_STATUS_P(_v) ((_v) << __HOSTFN2_INT_STATUS_P_SH)
+#define __HOSTFN2_INT_STATUS_F 0x0000ffff
+#define HOSTFN2_INT_MSK 0x00014304
+#define HOST_PAGE_NUM_FN2 0x00014308
+#define HOST_MSIX_ERR_INDEX_FN2 0x0001430c
+#define HOSTFN3_INT_STATUS 0x00014400
+#define __HALT_OCCURRED 0x01000000
+#define __HOSTFN3_INT_STATUS_LVL_MK 0x00f00000
+#define __HOSTFN3_INT_STATUS_LVL_SH 20
+#define __HOSTFN3_INT_STATUS_LVL(_v) ((_v) << __HOSTFN3_INT_STATUS_LVL_SH)
+#define __HOSTFN3_INT_STATUS_P_MK 0x000f0000
+#define __HOSTFN3_INT_STATUS_P_SH 16
+#define __HOSTFN3_INT_STATUS_P(_v) ((_v) << __HOSTFN3_INT_STATUS_P_SH)
+#define __HOSTFN3_INT_STATUS_F 0x0000ffff
+#define HOSTFN3_INT_MSK 0x00014404
+#define HOST_PAGE_NUM_FN3 0x00014408
+#define HOST_MSIX_ERR_INDEX_FN3 0x0001440c
+#define FNC_ID_REG 0x00014600
+#define __FUNCTION_NUMBER 0x00000007
+#define FNC_PERS_REG 0x00014604
+#define __F3_FUNCTION_ACTIVE 0x80000000
+#define __F3_FUNCTION_MODE 0x40000000
+#define __F3_PORT_MAP_MK 0x30000000
+#define __F3_PORT_MAP_SH 28
+#define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH)
+#define __F3_VM_MODE 0x08000000
+#define __F3_INTX_STATUS_MK 0x07000000
+#define __F3_INTX_STATUS_SH 24
+#define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH)
+#define __F2_FUNCTION_ACTIVE 0x00800000
+#define __F2_FUNCTION_MODE 0x00400000
+#define __F2_PORT_MAP_MK 0x00300000
+#define __F2_PORT_MAP_SH 20
+#define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH)
+#define __F2_VM_MODE 0x00080000
+#define __F2_INTX_STATUS_MK 0x00070000
+#define __F2_INTX_STATUS_SH 16
+#define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH)
+#define __F1_FUNCTION_ACTIVE 0x00008000
+#define __F1_FUNCTION_MODE 0x00004000
+#define __F1_PORT_MAP_MK 0x00003000
+#define __F1_PORT_MAP_SH 12
+#define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH)
+#define __F1_VM_MODE 0x00000800
+#define __F1_INTX_STATUS_MK 0x00000700
+#define __F1_INTX_STATUS_SH 8
+#define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH)
+#define __F0_FUNCTION_ACTIVE 0x00000080
+#define __F0_FUNCTION_MODE 0x00000040
+#define __F0_PORT_MAP_MK 0x00000030
+#define __F0_PORT_MAP_SH 4
+#define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH)
+#define __F0_VM_MODE 0x00000008
+#define __F0_INTX_STATUS 0x00000007
+enum {
+ __F0_INTX_STATUS_MSIX = 0x0,
+ __F0_INTX_STATUS_INTA = 0x1,
+ __F0_INTX_STATUS_INTB = 0x2,
+ __F0_INTX_STATUS_INTC = 0x3,
+ __F0_INTX_STATUS_INTD = 0x4,
+};
+#define OP_MODE 0x0001460c
+#define __APP_ETH_CLK_LOWSPEED 0x00000004
+#define __GLOBAL_CORECLK_HALFSPEED 0x00000002
+#define __GLOBAL_FCOE_MODE 0x00000001
+#define HOST_SEM4_REG 0x00014610
+#define HOST_SEM5_REG 0x00014614
+#define HOST_SEM6_REG 0x00014618
+#define HOST_SEM7_REG 0x0001461c
+#define HOST_SEM4_INFO_REG 0x00014620
+#define HOST_SEM5_INFO_REG 0x00014624
+#define HOST_SEM6_INFO_REG 0x00014628
+#define HOST_SEM7_INFO_REG 0x0001462c
+#define HOSTFN0_LPU0_MBOX0_CMD_STAT 0x00019000
+#define __HOSTFN0_LPU0_MBOX0_INFO_MK 0xfffffffe
+#define __HOSTFN0_LPU0_MBOX0_INFO_SH 1
+#define __HOSTFN0_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU0_MBOX0_INFO_SH)
+#define __HOSTFN0_LPU0_MBOX0_CMD_STATUS 0x00000001
+#define HOSTFN0_LPU1_MBOX0_CMD_STAT 0x00019004
+#define __HOSTFN0_LPU1_MBOX0_INFO_MK 0xfffffffe
+#define __HOSTFN0_LPU1_MBOX0_INFO_SH 1
+#define __HOSTFN0_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU1_MBOX0_INFO_SH)
+#define __HOSTFN0_LPU1_MBOX0_CMD_STATUS 0x00000001
+#define LPU0_HOSTFN0_MBOX0_CMD_STAT 0x00019008
+#define __LPU0_HOSTFN0_MBOX0_INFO_MK 0xfffffffe
+#define __LPU0_HOSTFN0_MBOX0_INFO_SH 1
+#define __LPU0_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN0_MBOX0_INFO_SH)
+#define __LPU0_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
+#define LPU1_HOSTFN0_MBOX0_CMD_STAT 0x0001900c
+#define __LPU1_HOSTFN0_MBOX0_INFO_MK 0xfffffffe
+#define __LPU1_HOSTFN0_MBOX0_INFO_SH 1
+#define __LPU1_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN0_MBOX0_INFO_SH)
+#define __LPU1_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
+#define HOSTFN1_LPU0_MBOX0_CMD_STAT 0x00019010
+#define __HOSTFN1_LPU0_MBOX0_INFO_MK 0xfffffffe
+#define __HOSTFN1_LPU0_MBOX0_INFO_SH 1
+#define __HOSTFN1_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU0_MBOX0_INFO_SH)
+#define __HOSTFN1_LPU0_MBOX0_CMD_STATUS 0x00000001
+#define HOSTFN1_LPU1_MBOX0_CMD_STAT 0x00019014
+#define __HOSTFN1_LPU1_MBOX0_INFO_MK 0xfffffffe
+#define __HOSTFN1_LPU1_MBOX0_INFO_SH 1
+#define __HOSTFN1_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU1_MBOX0_INFO_SH)
+#define __HOSTFN1_LPU1_MBOX0_CMD_STATUS 0x00000001
+#define LPU0_HOSTFN1_MBOX0_CMD_STAT 0x00019018
+#define __LPU0_HOSTFN1_MBOX0_INFO_MK 0xfffffffe
+#define __LPU0_HOSTFN1_MBOX0_INFO_SH 1
+#define __LPU0_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN1_MBOX0_INFO_SH)
+#define __LPU0_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
+#define LPU1_HOSTFN1_MBOX0_CMD_STAT 0x0001901c
+#define __LPU1_HOSTFN1_MBOX0_INFO_MK 0xfffffffe
+#define __LPU1_HOSTFN1_MBOX0_INFO_SH 1
+#define __LPU1_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN1_MBOX0_INFO_SH)
+#define __LPU1_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
+#define HOSTFN2_LPU0_MBOX0_CMD_STAT 0x00019150
+#define __HOSTFN2_LPU0_MBOX0_INFO_MK 0xfffffffe
+#define __HOSTFN2_LPU0_MBOX0_INFO_SH 1
+#define __HOSTFN2_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU0_MBOX0_INFO_SH)
+#define __HOSTFN2_LPU0_MBOX0_CMD_STATUS 0x00000001
+#define HOSTFN2_LPU1_MBOX0_CMD_STAT 0x00019154
+#define __HOSTFN2_LPU1_MBOX0_INFO_MK 0xfffffffe
+#define __HOSTFN2_LPU1_MBOX0_INFO_SH 1
+#define __HOSTFN2_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU1_MBOX0_INFO_SH)
+#define __HOSTFN2_LPU1_MBOX0BOX0_CMD_STATUS 0x00000001
+#define LPU0_HOSTFN2_MBOX0_CMD_STAT 0x00019158
+#define __LPU0_HOSTFN2_MBOX0_INFO_MK 0xfffffffe
+#define __LPU0_HOSTFN2_MBOX0_INFO_SH 1
+#define __LPU0_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN2_MBOX0_INFO_SH)
+#define __LPU0_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
+#define LPU1_HOSTFN2_MBOX0_CMD_STAT 0x0001915c
+#define __LPU1_HOSTFN2_MBOX0_INFO_MK 0xfffffffe
+#define __LPU1_HOSTFN2_MBOX0_INFO_SH 1
+#define __LPU1_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN2_MBOX0_INFO_SH)
+#define __LPU1_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
+#define HOSTFN3_LPU0_MBOX0_CMD_STAT 0x00019160
+#define __HOSTFN3_LPU0_MBOX0_INFO_MK 0xfffffffe
+#define __HOSTFN3_LPU0_MBOX0_INFO_SH 1
+#define __HOSTFN3_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU0_MBOX0_INFO_SH)
+#define __HOSTFN3_LPU0_MBOX0_CMD_STATUS 0x00000001
+#define HOSTFN3_LPU1_MBOX0_CMD_STAT 0x00019164
+#define __HOSTFN3_LPU1_MBOX0_INFO_MK 0xfffffffe
+#define __HOSTFN3_LPU1_MBOX0_INFO_SH 1
+#define __HOSTFN3_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU1_MBOX0_INFO_SH)
+#define __HOSTFN3_LPU1_MBOX0_CMD_STATUS 0x00000001
+#define LPU0_HOSTFN3_MBOX0_CMD_STAT 0x00019168
+#define __LPU0_HOSTFN3_MBOX0_INFO_MK 0xfffffffe
+#define __LPU0_HOSTFN3_MBOX0_INFO_SH 1
+#define __LPU0_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN3_MBOX0_INFO_SH)
+#define __LPU0_HOSTFN3_MBOX0_CMD_STATUS 0x00000001
+#define LPU1_HOSTFN3_MBOX0_CMD_STAT 0x0001916c
+#define __LPU1_HOSTFN3_MBOX0_INFO_MK 0xfffffffe
+#define __LPU1_HOSTFN3_MBOX0_INFO_SH 1
+#define __LPU1_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN3_MBOX0_INFO_SH)
+#define __LPU1_HOSTFN3_MBOX0_CMD_STATUS 0x00000001
+#define FW_INIT_HALT_P0 0x000191ac
+#define __FW_INIT_HALT_P 0x00000001
+#define FW_INIT_HALT_P1 0x000191bc
+#define CPE_PI_PTR_Q0 0x00038000
+#define __CPE_PI_UNUSED_MK 0xffff0000
+#define __CPE_PI_UNUSED_SH 16
+#define __CPE_PI_UNUSED(_v) ((_v) << __CPE_PI_UNUSED_SH)
+#define __CPE_PI_PTR 0x0000ffff
+#define CPE_PI_PTR_Q1 0x00038040
+#define CPE_CI_PTR_Q0 0x00038004
+#define __CPE_CI_UNUSED_MK 0xffff0000
+#define __CPE_CI_UNUSED_SH 16
+#define __CPE_CI_UNUSED(_v) ((_v) << __CPE_CI_UNUSED_SH)
+#define __CPE_CI_PTR 0x0000ffff
+#define CPE_CI_PTR_Q1 0x00038044
+#define CPE_DEPTH_Q0 0x00038008
+#define __CPE_DEPTH_UNUSED_MK 0xf8000000
+#define __CPE_DEPTH_UNUSED_SH 27
+#define __CPE_DEPTH_UNUSED(_v) ((_v) << __CPE_DEPTH_UNUSED_SH)
+#define __CPE_MSIX_VEC_INDEX_MK 0x07ff0000
+#define __CPE_MSIX_VEC_INDEX_SH 16
+#define __CPE_MSIX_VEC_INDEX(_v) ((_v) << __CPE_MSIX_VEC_INDEX_SH)
+#define __CPE_DEPTH 0x0000ffff
+#define CPE_DEPTH_Q1 0x00038048
+#define CPE_QCTRL_Q0 0x0003800c
+#define __CPE_CTRL_UNUSED30_MK 0xfc000000
+#define __CPE_CTRL_UNUSED30_SH 26
+#define __CPE_CTRL_UNUSED30(_v) ((_v) << __CPE_CTRL_UNUSED30_SH)
+#define __CPE_FUNC_INT_CTRL_MK 0x03000000
+#define __CPE_FUNC_INT_CTRL_SH 24
+#define __CPE_FUNC_INT_CTRL(_v) ((_v) << __CPE_FUNC_INT_CTRL_SH)
+enum {
+ __CPE_FUNC_INT_CTRL_DISABLE = 0x0,
+ __CPE_FUNC_INT_CTRL_F2NF = 0x1,
+ __CPE_FUNC_INT_CTRL_3QUART = 0x2,
+ __CPE_FUNC_INT_CTRL_HALF = 0x3,
+};
+#define __CPE_CTRL_UNUSED20_MK 0x00f00000
+#define __CPE_CTRL_UNUSED20_SH 20
+#define __CPE_CTRL_UNUSED20(_v) ((_v) << __CPE_CTRL_UNUSED20_SH)
+#define __CPE_SCI_TH_MK 0x000f0000
+#define __CPE_SCI_TH_SH 16
+#define __CPE_SCI_TH(_v) ((_v) << __CPE_SCI_TH_SH)
+#define __CPE_CTRL_UNUSED10_MK 0x0000c000
+#define __CPE_CTRL_UNUSED10_SH 14
+#define __CPE_CTRL_UNUSED10(_v) ((_v) << __CPE_CTRL_UNUSED10_SH)
+#define __CPE_ACK_PENDING 0x00002000
+#define __CPE_CTRL_UNUSED40_MK 0x00001c00
+#define __CPE_CTRL_UNUSED40_SH 10
+#define __CPE_CTRL_UNUSED40(_v) ((_v) << __CPE_CTRL_UNUSED40_SH)
+#define __CPE_PCIEID_MK 0x00000300
+#define __CPE_PCIEID_SH 8
+#define __CPE_PCIEID(_v) ((_v) << __CPE_PCIEID_SH)
+#define __CPE_CTRL_UNUSED00_MK 0x000000fe
+#define __CPE_CTRL_UNUSED00_SH 1
+#define __CPE_CTRL_UNUSED00(_v) ((_v) << __CPE_CTRL_UNUSED00_SH)
+#define __CPE_ESIZE 0x00000001
+#define CPE_QCTRL_Q1 0x0003804c
+#define __CPE_CTRL_UNUSED31_MK 0xfc000000
+#define __CPE_CTRL_UNUSED31_SH 26
+#define __CPE_CTRL_UNUSED31(_v) ((_v) << __CPE_CTRL_UNUSED31_SH)
+#define __CPE_CTRL_UNUSED21_MK 0x00f00000
+#define __CPE_CTRL_UNUSED21_SH 20
+#define __CPE_CTRL_UNUSED21(_v) ((_v) << __CPE_CTRL_UNUSED21_SH)
+#define __CPE_CTRL_UNUSED11_MK 0x0000c000
+#define __CPE_CTRL_UNUSED11_SH 14
+#define __CPE_CTRL_UNUSED11(_v) ((_v) << __CPE_CTRL_UNUSED11_SH)
+#define __CPE_CTRL_UNUSED41_MK 0x00001c00
+#define __CPE_CTRL_UNUSED41_SH 10
+#define __CPE_CTRL_UNUSED41(_v) ((_v) << __CPE_CTRL_UNUSED41_SH)
+#define __CPE_CTRL_UNUSED01_MK 0x000000fe
+#define __CPE_CTRL_UNUSED01_SH 1
+#define __CPE_CTRL_UNUSED01(_v) ((_v) << __CPE_CTRL_UNUSED01_SH)
+#define RME_PI_PTR_Q0 0x00038020
+#define __LATENCY_TIME_STAMP_MK 0xffff0000
+#define __LATENCY_TIME_STAMP_SH 16
+#define __LATENCY_TIME_STAMP(_v) ((_v) << __LATENCY_TIME_STAMP_SH)
+#define __RME_PI_PTR 0x0000ffff
+#define RME_PI_PTR_Q1 0x00038060
+#define RME_CI_PTR_Q0 0x00038024
+#define __DELAY_TIME_STAMP_MK 0xffff0000
+#define __DELAY_TIME_STAMP_SH 16
+#define __DELAY_TIME_STAMP(_v) ((_v) << __DELAY_TIME_STAMP_SH)
+#define __RME_CI_PTR 0x0000ffff
+#define RME_CI_PTR_Q1 0x00038064
+#define RME_DEPTH_Q0 0x00038028
+#define __RME_DEPTH_UNUSED_MK 0xf8000000
+#define __RME_DEPTH_UNUSED_SH 27
+#define __RME_DEPTH_UNUSED(_v) ((_v) << __RME_DEPTH_UNUSED_SH)
+#define __RME_MSIX_VEC_INDEX_MK 0x07ff0000
+#define __RME_MSIX_VEC_INDEX_SH 16
+#define __RME_MSIX_VEC_INDEX(_v) ((_v) << __RME_MSIX_VEC_INDEX_SH)
+#define __RME_DEPTH 0x0000ffff
+#define RME_DEPTH_Q1 0x00038068
+#define RME_QCTRL_Q0 0x0003802c
+#define __RME_INT_LATENCY_TIMER_MK 0xff000000
+#define __RME_INT_LATENCY_TIMER_SH 24
+#define __RME_INT_LATENCY_TIMER(_v) ((_v) << __RME_INT_LATENCY_TIMER_SH)
+#define __RME_INT_DELAY_TIMER_MK 0x00ff0000
+#define __RME_INT_DELAY_TIMER_SH 16
+#define __RME_INT_DELAY_TIMER(_v) ((_v) << __RME_INT_DELAY_TIMER_SH)
+#define __RME_INT_DELAY_DISABLE 0x00008000
+#define __RME_DLY_DELAY_DISABLE 0x00004000
+#define __RME_ACK_PENDING 0x00002000
+#define __RME_FULL_INTERRUPT_DISABLE 0x00001000
+#define __RME_CTRL_UNUSED10_MK 0x00000c00
+#define __RME_CTRL_UNUSED10_SH 10
+#define __RME_CTRL_UNUSED10(_v) ((_v) << __RME_CTRL_UNUSED10_SH)
+#define __RME_PCIEID_MK 0x00000300
+#define __RME_PCIEID_SH 8
+#define __RME_PCIEID(_v) ((_v) << __RME_PCIEID_SH)
+#define __RME_CTRL_UNUSED00_MK 0x000000fe
+#define __RME_CTRL_UNUSED00_SH 1
+#define __RME_CTRL_UNUSED00(_v) ((_v) << __RME_CTRL_UNUSED00_SH)
+#define __RME_ESIZE 0x00000001
+#define RME_QCTRL_Q1 0x0003806c
+#define __RME_CTRL_UNUSED11_MK 0x00000c00
+#define __RME_CTRL_UNUSED11_SH 10
+#define __RME_CTRL_UNUSED11(_v) ((_v) << __RME_CTRL_UNUSED11_SH)
+#define __RME_CTRL_UNUSED01_MK 0x000000fe
+#define __RME_CTRL_UNUSED01_SH 1
+#define __RME_CTRL_UNUSED01(_v) ((_v) << __RME_CTRL_UNUSED01_SH)
+#define PSS_CTL_REG 0x00018800
+#define __PSS_I2C_CLK_DIV_MK 0x007f0000
+#define __PSS_I2C_CLK_DIV_SH 16
+#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH)
+#define __PSS_LMEM_INIT_DONE 0x00001000
+#define __PSS_LMEM_RESET 0x00000200
+#define __PSS_LMEM_INIT_EN 0x00000100
+#define __PSS_LPU1_RESET 0x00000002
+#define __PSS_LPU0_RESET 0x00000001
+#define PSS_ERR_STATUS_REG 0x00018810
+#define __PSS_LPU1_TCM_READ_ERR 0x00200000
+#define __PSS_LPU0_TCM_READ_ERR 0x00100000
+#define __PSS_LMEM5_CORR_ERR 0x00080000
+#define __PSS_LMEM4_CORR_ERR 0x00040000
+#define __PSS_LMEM3_CORR_ERR 0x00020000
+#define __PSS_LMEM2_CORR_ERR 0x00010000
+#define __PSS_LMEM1_CORR_ERR 0x00008000
+#define __PSS_LMEM0_CORR_ERR 0x00004000
+#define __PSS_LMEM5_UNCORR_ERR 0x00002000
+#define __PSS_LMEM4_UNCORR_ERR 0x00001000
+#define __PSS_LMEM3_UNCORR_ERR 0x00000800
+#define __PSS_LMEM2_UNCORR_ERR 0x00000400
+#define __PSS_LMEM1_UNCORR_ERR 0x00000200
+#define __PSS_LMEM0_UNCORR_ERR 0x00000100
+#define __PSS_BAL_PERR 0x00000080
+#define __PSS_DIP_IF_ERR 0x00000040
+#define __PSS_IOH_IF_ERR 0x00000020
+#define __PSS_TDS_IF_ERR 0x00000010
+#define __PSS_RDS_IF_ERR 0x00000008
+#define __PSS_SGM_IF_ERR 0x00000004
+#define __PSS_LPU1_RAM_ERR 0x00000002
+#define __PSS_LPU0_RAM_ERR 0x00000001
+#define ERR_SET_REG 0x00018818
+#define __PSS_ERR_STATUS_SET 0x003fffff
+#define HQM_QSET0_RXQ_DRBL_P0 0x00038000
+#define __RXQ0_ADD_VECTORS_P 0x80000000
+#define __RXQ0_STOP_P 0x40000000
+#define __RXQ0_PRD_PTR_P 0x0000ffff
+#define HQM_QSET1_RXQ_DRBL_P0 0x00038080
+#define __RXQ1_ADD_VECTORS_P 0x80000000
+#define __RXQ1_STOP_P 0x40000000
+#define __RXQ1_PRD_PTR_P 0x0000ffff
+#define HQM_QSET0_RXQ_DRBL_P1 0x0003c000
+#define HQM_QSET1_RXQ_DRBL_P1 0x0003c080
+#define HQM_QSET0_TXQ_DRBL_P0 0x00038020
+#define __TXQ0_ADD_VECTORS_P 0x80000000
+#define __TXQ0_STOP_P 0x40000000
+#define __TXQ0_PRD_PTR_P 0x0000ffff
+#define HQM_QSET1_TXQ_DRBL_P0 0x000380a0
+#define __TXQ1_ADD_VECTORS_P 0x80000000
+#define __TXQ1_STOP_P 0x40000000
+#define __TXQ1_PRD_PTR_P 0x0000ffff
+#define HQM_QSET0_TXQ_DRBL_P1 0x0003c020
+#define HQM_QSET1_TXQ_DRBL_P1 0x0003c0a0
+#define HQM_QSET0_IB_DRBL_1_P0 0x00038040
+#define __IB1_0_ACK_P 0x80000000
+#define __IB1_0_DISABLE_P 0x40000000
+#define __IB1_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff
+#define HQM_QSET1_IB_DRBL_1_P0 0x000380c0
+#define __IB1_1_ACK_P 0x80000000
+#define __IB1_1_DISABLE_P 0x40000000
+#define __IB1_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff
+#define HQM_QSET0_IB_DRBL_1_P1 0x0003c040
+#define HQM_QSET1_IB_DRBL_1_P1 0x0003c0c0
+#define HQM_QSET0_IB_DRBL_2_P0 0x00038060
+#define __IB2_0_ACK_P 0x80000000
+#define __IB2_0_DISABLE_P 0x40000000
+#define __IB2_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff
+#define HQM_QSET1_IB_DRBL_2_P0 0x000380e0
+#define __IB2_1_ACK_P 0x80000000
+#define __IB2_1_DISABLE_P 0x40000000
+#define __IB2_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff
+#define HQM_QSET0_IB_DRBL_2_P1 0x0003c060
+#define HQM_QSET1_IB_DRBL_2_P1 0x0003c0e0
+
+
+/*
+ * These definitions are either in error/missing in spec. Its auto-generated
+ * from hard coded values in regparse.pl.
+ */
+#define __EMPHPOST_AT_4G_MK_FIX 0x0000001c
+#define __EMPHPOST_AT_4G_SH_FIX 0x00000002
+#define __EMPHPRE_AT_4G_FIX 0x00000003
+#define __SFP_TXRATE_EN_FIX 0x00000100
+#define __SFP_RXRATE_EN_FIX 0x00000080
+
+
+/*
+ * These register definitions are auto-generated from hard coded values
+ * in regparse.pl.
+ */
+
+
+/*
+ * These register mapping definitions are auto-generated from mapping tables
+ * in regparse.pl.
+ */
+#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG
+#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG
+#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
+#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
+#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
+
+#define CPE_DEPTH_Q(__n) \
+ (CPE_DEPTH_Q0 + (__n) * (CPE_DEPTH_Q1 - CPE_DEPTH_Q0))
+#define CPE_QCTRL_Q(__n) \
+ (CPE_QCTRL_Q0 + (__n) * (CPE_QCTRL_Q1 - CPE_QCTRL_Q0))
+#define CPE_PI_PTR_Q(__n) \
+ (CPE_PI_PTR_Q0 + (__n) * (CPE_PI_PTR_Q1 - CPE_PI_PTR_Q0))
+#define CPE_CI_PTR_Q(__n) \
+ (CPE_CI_PTR_Q0 + (__n) * (CPE_CI_PTR_Q1 - CPE_CI_PTR_Q0))
+#define RME_DEPTH_Q(__n) \
+ (RME_DEPTH_Q0 + (__n) * (RME_DEPTH_Q1 - RME_DEPTH_Q0))
+#define RME_QCTRL_Q(__n) \
+ (RME_QCTRL_Q0 + (__n) * (RME_QCTRL_Q1 - RME_QCTRL_Q0))
+#define RME_PI_PTR_Q(__n) \
+ (RME_PI_PTR_Q0 + (__n) * (RME_PI_PTR_Q1 - RME_PI_PTR_Q0))
+#define RME_CI_PTR_Q(__n) \
+ (RME_CI_PTR_Q0 + (__n) * (RME_CI_PTR_Q1 - RME_CI_PTR_Q0))
+#define HQM_QSET_RXQ_DRBL_P0(__n) \
+ (HQM_QSET0_RXQ_DRBL_P0 + \
+ (__n) * (HQM_QSET1_RXQ_DRBL_P0 - HQM_QSET0_RXQ_DRBL_P0))
+#define HQM_QSET_TXQ_DRBL_P0(__n) \
+ (HQM_QSET0_TXQ_DRBL_P0 + \
+ (__n) * (HQM_QSET1_TXQ_DRBL_P0 - HQM_QSET0_TXQ_DRBL_P0))
+#define HQM_QSET_IB_DRBL_1_P0(__n) \
+ (HQM_QSET0_IB_DRBL_1_P0 + \
+ (__n) * (HQM_QSET1_IB_DRBL_1_P0 - HQM_QSET0_IB_DRBL_1_P0))
+#define HQM_QSET_IB_DRBL_2_P0(__n) \
+ (HQM_QSET0_IB_DRBL_2_P0 + \
+ (__n) * (HQM_QSET1_IB_DRBL_2_P0 - HQM_QSET0_IB_DRBL_2_P0))
+#define HQM_QSET_RXQ_DRBL_P1(__n) \
+ (HQM_QSET0_RXQ_DRBL_P1 + \
+ (__n) * (HQM_QSET1_RXQ_DRBL_P1 - HQM_QSET0_RXQ_DRBL_P1))
+#define HQM_QSET_TXQ_DRBL_P1(__n) \
+ (HQM_QSET0_TXQ_DRBL_P1 + \
+ (__n) * (HQM_QSET1_TXQ_DRBL_P1 - HQM_QSET0_TXQ_DRBL_P1))
+#define HQM_QSET_IB_DRBL_1_P1(__n) \
+ (HQM_QSET0_IB_DRBL_1_P1 + \
+ (__n) * (HQM_QSET1_IB_DRBL_1_P1 - HQM_QSET0_IB_DRBL_1_P1))
+#define HQM_QSET_IB_DRBL_2_P1(__n) \
+ (HQM_QSET0_IB_DRBL_2_P1 + \
+ (__n) * (HQM_QSET1_IB_DRBL_2_P1 - HQM_QSET0_IB_DRBL_2_P1))
+
+#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
+#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
+#define CPE_Q_MASK(__q) ((__q) & 0x3)
+#define RME_Q_MASK(__q) ((__q) & 0x3)
+
+
+/*
+ * PCI MSI-X vector defines
+ */
+enum {
+ BFA_MSIX_CPE_Q0 = 0,
+ BFA_MSIX_CPE_Q1 = 1,
+ BFA_MSIX_CPE_Q2 = 2,
+ BFA_MSIX_CPE_Q3 = 3,
+ BFA_MSIX_RME_Q0 = 4,
+ BFA_MSIX_RME_Q1 = 5,
+ BFA_MSIX_RME_Q2 = 6,
+ BFA_MSIX_RME_Q3 = 7,
+ BFA_MSIX_LPU_ERR = 8,
+ BFA_MSIX_CT_MAX = 9,
+};
+
+/*
+ * And corresponding host interrupt status bit field defines
+ */
+#define __HFN_INT_CPE_Q0 0x00000001U
+#define __HFN_INT_CPE_Q1 0x00000002U
+#define __HFN_INT_CPE_Q2 0x00000004U
+#define __HFN_INT_CPE_Q3 0x00000008U
+#define __HFN_INT_CPE_Q4 0x00000010U
+#define __HFN_INT_CPE_Q5 0x00000020U
+#define __HFN_INT_CPE_Q6 0x00000040U
+#define __HFN_INT_CPE_Q7 0x00000080U
+#define __HFN_INT_RME_Q0 0x00000100U
+#define __HFN_INT_RME_Q1 0x00000200U
+#define __HFN_INT_RME_Q2 0x00000400U
+#define __HFN_INT_RME_Q3 0x00000800U
+#define __HFN_INT_RME_Q4 0x00001000U
+#define __HFN_INT_RME_Q5 0x00002000U
+#define __HFN_INT_RME_Q6 0x00004000U
+#define __HFN_INT_RME_Q7 0x00008000U
+#define __HFN_INT_ERR_EMC 0x00010000U
+#define __HFN_INT_ERR_LPU0 0x00020000U
+#define __HFN_INT_ERR_LPU1 0x00040000U
+#define __HFN_INT_ERR_PSS 0x00080000U
+#define __HFN_INT_MBOX_LPU0 0x00100000U
+#define __HFN_INT_MBOX_LPU1 0x00200000U
+#define __HFN_INT_MBOX1_LPU0 0x00400000U
+#define __HFN_INT_MBOX1_LPU1 0x00800000U
+#define __HFN_INT_LL_HALT 0x01000000U
+#define __HFN_INT_CPE_MASK 0x000000ffU
+#define __HFN_INT_RME_MASK 0x0000ff00U
+
+
+/*
+ * catapult memory map.
+ */
+#define LL_PGN_HQM0 0x0096
+#define LL_PGN_HQM1 0x0097
+#define PSS_SMEM_PAGE_START 0x8000
+#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15))
+#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff)
+
+/*
+ * End of catapult memory map
+ */
+
+
+#endif /* __BFI_CTREG_H__ */
+
diff -ruP net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_ioc.h net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_ioc.h
--- net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_ioc.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_ioc.h 2009-11-12 19:03:39.232339000 -0800
@@ -0,0 +1,204 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __BFI_IOC_H__
+#define __BFI_IOC_H__
+
+#include "bfi.h"
+#include <defs/bfa_defs_ioc.h>
+
+#pragma pack(1)
+
+enum bfi_ioc_h2i_msgs {
+ BFI_IOC_H2I_ENABLE_REQ = 1,
+ BFI_IOC_H2I_DISABLE_REQ = 2,
+ BFI_IOC_H2I_GETATTR_REQ = 3,
+ BFI_IOC_H2I_DBG_SYNC = 4,
+ BFI_IOC_H2I_DBG_DUMP = 5,
+};
+
+enum bfi_ioc_i2h_msgs {
+ BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
+ BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
+ BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
+ BFI_IOC_I2H_READY_EVENT = BFA_I2HM(4),
+ BFI_IOC_I2H_HBEAT = BFA_I2HM(5),
+};
+
+/**
+ * BFI_IOC_H2I_GETATTR_REQ message
+ */
+struct bfi_ioc_getattr_req {
+ struct bfi_mhdr mh;
+ union bfi_addr_u attr_addr;
+};
+
+struct bfi_ioc_attr {
+ wwn_t mfg_wwn;
+ struct mac mfg_mac;
+ u16 rsvd_a;
+ char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
+ u8 pcie_gen;
+ u8 pcie_lanes_orig;
+ u8 pcie_lanes;
+ u8 rx_bbcredit; /* receive buffer credits */
+ u32 adapter_prop; /* adapter properties */
+ u16 maxfrsize; /* max receive frame size */
+ char asic_rev;
+ u8 rsvd_b;
+ char fw_version[BFA_VERSION_LEN];
+ char optrom_version[BFA_VERSION_LEN];
+ struct bfa_mfg_vpd vpd;
+};
+
+/**
+ * BFI_IOC_I2H_GETATTR_REPLY message
+ */
+struct bfi_ioc_getattr_reply {
+ struct bfi_mhdr mh; /* Common msg header */
+ u8 status; /* cfg reply status */
+ u8 rsvd[3];
+};
+
+/**
+ * Firmware memory page offsets
+ */
+#define BFI_IOC_SMEM_PG0_CB (0x40)
+#define BFI_IOC_SMEM_PG0_CT (0x180)
+
+/**
+ * Firmware trace offset
+ */
+#define BFI_IOC_TRC_OFF (0x4b00)
+#define BFI_IOC_TRC_ENTS 256
+
+#define BFI_IOC_FW_SIGNATURE (0xbfadbfad)
+#define BFI_IOC_MD5SUM_SZ 4
+struct bfi_ioc_image_hdr {
+ u32 signature; /* constant signature */
+ u32 rsvd_a;
+ u32 exec; /* exec vector */
+ u32 param; /* parameters */
+ u32 rsvd_b[4];
+ u32 md5sum[BFI_IOC_MD5SUM_SZ];
+};
+
+/**
+ * BFI_IOC_I2H_READY_EVENT message
+ */
+struct bfi_ioc_rdy_event {
+ struct bfi_mhdr mh; /* common msg header */
+ u8 init_status; /* init event status */
+ u8 rsvd[3];
+};
+
+struct bfi_ioc_hbeat {
+ struct bfi_mhdr mh; /* common msg header */
+ u32 hb_count; /* current heart beat count */
+};
+
+/**
+ * IOC hardware/firmware state
+ */
+enum bfi_ioc_state {
+ BFI_IOC_UNINIT = 0, /* not initialized */
+ BFI_IOC_INITING = 1, /* h/w is being initialized */
+ BFI_IOC_HWINIT = 2, /* h/w is initialized */
+ BFI_IOC_CFG = 3, /* IOC configuration in progress */
+ BFI_IOC_OP = 4, /* IOC is operational */
+ BFI_IOC_DISABLING = 5, /* IOC is being disabled */
+ BFI_IOC_DISABLED = 6, /* IOC is disabled */
+ BFI_IOC_CFG_DISABLED = 7, /* IOC is being disabled;transient */
+ BFI_IOC_FAIL = 8, /* IOC heart-beat failure */
+ BFI_IOC_MEMTEST = 9, /* IOC is doing memtest */
+};
+
+#define BFI_IOC_ENDIAN_SIG 0x12345678
+
+enum {
+ BFI_ADAPTER_TYPE_FC = 0x01, /* FC adapters */
+ BFI_ADAPTER_TYPE_MK = 0x0f0000, /* adapter type mask */
+ BFI_ADAPTER_TYPE_SH = 16, /* adapter type shift */
+ BFI_ADAPTER_NPORTS_MK = 0xff00, /* number of ports mask */
+ BFI_ADAPTER_NPORTS_SH = 8, /* number of ports shift */
+ BFI_ADAPTER_SPEED_MK = 0xff, /* adapter speed mask */
+ BFI_ADAPTER_SPEED_SH = 0, /* adapter speed shift */
+ BFI_ADAPTER_PROTO = 0x100000, /* prototype adapaters */
+ BFI_ADAPTER_TTV = 0x200000, /* TTV debug capable */
+ BFI_ADAPTER_UNSUPP = 0x400000, /* unknown adapter type */
+};
+
+#define BFI_ADAPTER_GETP(__prop, __adap_prop) \
+ (((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \
+ BFI_ADAPTER_ ## __prop ## _SH)
+#define BFI_ADAPTER_SETP(__prop, __val) \
+ ((__val) << BFI_ADAPTER_ ## __prop ## _SH)
+#define BFI_ADAPTER_IS_PROTO(__adap_type) \
+ ((__adap_type) & BFI_ADAPTER_PROTO)
+#define BFI_ADAPTER_IS_TTV(__adap_type) \
+ ((__adap_type) & BFI_ADAPTER_TTV)
+#define BFI_ADAPTER_IS_UNSUPP(__adap_type) \
+ ((__adap_type) & BFI_ADAPTER_UNSUPP)
+#define BFI_ADAPTER_IS_SPECIAL(__adap_type) \
+ ((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \
+ BFI_ADAPTER_UNSUPP))
+
+/**
+ * BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages
+ */
+struct bfi_ioc_ctrl_req {
+ struct bfi_mhdr mh;
+ u8 ioc_class;
+ u8 rsvd[3];
+};
+
+/**
+ * BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages
+ */
+struct bfi_ioc_ctrl_reply {
+ struct bfi_mhdr mh; /* Common msg header */
+ u8 status; /* enable/disable status */
+ u8 rsvd[3];
+};
+
+#define BFI_IOC_MSGSZ 8
+/**
+ * H2I Messages
+ */
+union bfi_ioc_h2i_msg_u {
+ struct bfi_mhdr mh;
+ struct bfi_ioc_ctrl_req enable_req;
+ struct bfi_ioc_ctrl_req disable_req;
+ struct bfi_ioc_getattr_req getattr_req;
+ u32 mboxmsg[BFI_IOC_MSGSZ];
+};
+
+/**
+ * I2H Messages
+ */
+union bfi_ioc_i2h_msg_u {
+ struct bfi_mhdr mh;
+ struct bfi_ioc_rdy_event rdy_event;
+ u32 mboxmsg[BFI_IOC_MSGSZ];
+};
+
+#pragma pack()
+
+#endif /* __BFI_IOC_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_ll.h net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_ll.h
--- net-next-2.6-orig/drivers/net/bna/include/bfi/bfi_ll.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/bfi/bfi_ll.h 2009-11-12 19:03:39.255336000 -0800
@@ -0,0 +1,434 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * file bfi_if.h BNA Hardware and Firmware Interface
+ */
+#ifndef __BFI_LL_H__
+#define __BFI_LL_H__
+
+#include <bfi/bfi.h>
+#include <defs/bfa_defs_ioc.h>
+
+#pragma pack(1)
+
+/**
+ * "enums" for all LL mailbox messages other than IOC
+ */
+enum {
+ BFI_LL_H2I_MAC_UCAST_SET_REQ = 1,
+ BFI_LL_H2I_MAC_UCAST_ADD_REQ = 2,
+ BFI_LL_H2I_MAC_UCAST_DEL_REQ = 3,
+
+ BFI_LL_H2I_MAC_MCAST_ADD_REQ = 4,
+ BFI_LL_H2I_MAC_MCAST_DEL_REQ = 5,
+ BFI_LL_H2I_MAC_MCAST_FILTER_REQ = 6,
+ BFI_LL_H2I_MAC_MCAST_DEL_ALL_REQ = 7,
+
+ BFI_LL_H2I_PORT_ADMIN_REQ = 8,
+ BFI_LL_H2I_STATS_GET_REQ = 9,
+ BFI_LL_H2I_STATS_CLEAR_REQ = 10,
+
+ BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ = 11,
+ BFI_LL_H2I_RXF_DEFAULT_SET_REQ = 12,
+
+ BFI_LL_H2I_TXQ_STOP_REQ = 13,
+ BFI_LL_H2I_RXQ_STOP_REQ = 14,
+
+ BFI_LL_H2I_DIAG_LOOPBACK_REQ = 15,
+
+ BFI_LL_H2I_SET_PAUSE_REQ = 16,
+ BFI_LL_H2I_MTU_INFO_REQ = 17,
+
+ BFI_LL_H2I_RX_REQ = 18,
+};
+
+enum {
+ BFI_LL_I2H_MAC_UCAST_SET_RSP = BFA_I2HM(1),
+ BFI_LL_I2H_MAC_UCAST_ADD_RSP = BFA_I2HM(2),
+ BFI_LL_I2H_MAC_UCAST_DEL_RSP = BFA_I2HM(3),
+
+ BFI_LL_I2H_MAC_MCAST_ADD_RSP = BFA_I2HM(4),
+ BFI_LL_I2H_MAC_MCAST_DEL_RSP = BFA_I2HM(5),
+ BFI_LL_I2H_MAC_MCAST_FILTER_RSP = BFA_I2HM(6),
+ BFI_LL_I2H_MAC_MCAST_DEL_ALL_RSP = BFA_I2HM(7),
+
+ BFI_LL_I2H_PORT_ADMIN_RSP = BFA_I2HM(8),
+ BFI_LL_I2H_STATS_GET_RSP = BFA_I2HM(9),
+ BFI_LL_I2H_STATS_CLEAR_RSP = BFA_I2HM(10),
+
+ BFI_LL_I2H_RXF_PROMISCUOUS_SET_RSP = BFA_I2HM(11),
+ BFI_LL_I2H_RXF_DEFAULT_SET_RSP = BFA_I2HM(12),
+
+ BFI_LL_I2H_TXQ_STOP_RSP = BFA_I2HM(13),
+ BFI_LL_I2H_RXQ_STOP_RSP = BFA_I2HM(14),
+
+ BFI_LL_I2H_DIAG_LOOPBACK_RSP = BFA_I2HM(15),
+
+ BFI_LL_I2H_SET_PAUSE_RSP = BFA_I2HM(16),
+
+ BFI_LL_I2H_MTU_INFO_RSP = BFA_I2HM(17),
+ BFI_LL_I2H_RX_RSP = BFA_I2HM(18),
+
+ BFI_LL_I2H_LINK_DOWN_AEN = BFA_I2HM(19),
+ BFI_LL_I2H_LINK_UP_AEN = BFA_I2HM(20),
+};
+
+/**
+ * BFI_LL_H2I_MAC_UCAST_SET_REQ
+ * BFI_LL_H2I_MAC_UCAST_ADD_REQ
+ * BFI_LL_H2I_MAC_UCAST_DEL_REQ
+ * BFI_LL_H2I_MAC_MCAST_ADD_REQ
+ * BFI_LL_H2I_MAC_MCAST_DEL_REQ
+ */
+struct bfi_ll_mac_addr_req {
+ struct bfi_mhdr mh; /* common msg header */
+ u8 rxf_id;
+ u8 rsvd1[3];
+ struct mac mac_addr;
+ u8 rsvd2[2];
+};
+
+/**
+ * BFI_LL_H2I_MAC_MCAST_FILTER_REQ
+ */
+struct bfi_ll_mcast_filter_req {
+ struct bfi_mhdr mh; /* common msg header */
+ u8 rxf_id;
+ u8 enable;
+ u8 rsvd[2];
+};
+
+/**
+ * BFI_LL_H2I_MAC_MCAST_DEL_ALL_REQ
+ */
+struct bfi_ll_mcast_del_all_req {
+ struct bfi_mhdr mh; /* common msg header */
+ u8 rxf_id;
+ u8 rsvd[3];
+};
+
+/**
+ * BFI_LL_H2I_TXQ_STOP_REQ
+ * BFI_LL_H2I_RXQ_STOP_REQ
+ */
+struct bfi_ll_q_stop_req {
+ struct bfi_mhdr mh; /* common msg header */
+ u32 q_id_mask[2]; /* bit-mask for queue ids */
+};
+
+/**
+ * BFI_LL_I2H_STATS_GET_REQ
+ * BFI_LL_I2H_STATS_CLEAR_REQ
+ */
+struct bfi_ll_stats_req {
+ struct bfi_mhdr mh; /* common msg header */
+/* bit-mask for non-function statistics */
+ u16 stats_mask;
+ u8 rsvd[2];
+ u32 rxf_id_mask[2]; /* bit-mask for RxF Statistics */
+ u32 txf_id_mask[2]; /* bit-mask for TxF Statistics */
+ union bfi_addr_u host_buffer; /* where statistics are returned */
+};
+
+
+
+#define BFI_LL_STATS_MAC (1 << 0) /* MAC Statistics */
+#define BFI_LL_STATS_BPC (1 << 1) /* Pause Stats from BPC */
+#define BFI_LL_STATS_RAD (1 << 2) /* Rx Admission Statistics */
+#define BFI_LL_STATS_RX_FC (1 << 3) /* Rx FC Stats from RxA */
+#define BFI_LL_STATS_TX_FC (1 << 4) /* Tx FC Stats from TxA */
+#define BFI_LL_STATS_ALL 0x1f
+
+
+
+struct bfi_ll_port_admin_req {
+ struct bfi_mhdr mh; /* common msg header */
+ u8 up;
+ u8 rsvd[3];
+};
+
+/**
+ * BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ
+ * BFI_LL_H2I_RXF_DEFAULT_SET_REQ
+ */
+struct bfi_ll_rxf_req {
+ struct bfi_mhdr mh; /* common msg header */
+ u8 rxf_id;
+ u8 enable;
+ u8 rsvd[2];
+};
+
+/**
+ * BFI_LL_H2I_RX_REQ
+ */
+struct bfi_ll_rxf_multi_req {
+ struct bfi_mhdr mh; /* common msg header */
+ u32 rxf_id_mask[2];
+ u8 enable;
+ u8 rsvd[3];
+};
+
+/**
+ * BFI_LL_H2I_DIAG_LOOPBACK
+ */
+struct bfi_ll_diag_lb_req{
+struct bfi_mhdr mh; /* 4 bytes */
+u8 enable; /* =1 : enable, =0 : disable */
+u8 mode; /* cable or Serdes */
+u8 rsvd[2];
+};
+
+
+enum {
+ BFI_LL_DIAG_LB_OPMODE_EXT = 0,
+ BFI_LL_DIAG_LB_OPMODE_CBL = 1,
+};
+
+/**
+ * BFI_LL_H2I_SET_PAUSE_REQ
+ */
+struct bfi_ll_set_pause_req {
+ struct bfi_mhdr mh;
+ u8 tx_pause; /* 1 = enable, 0 = disable */
+ u8 rx_pause; /* 1 = enable, 0 = disable */
+ u8 rsvd[2];
+};
+
+/**
+ * BFI_LL_H2I_MTU_INFO_REQ
+ */
+struct bfi_ll_mtu_info_req {
+ struct bfi_mhdr mh;
+ u16 mtu;
+ u8 rsvd[2];
+};
+
+/**
+ * Response header format used by all responses
+ * For both responses and asynchronous notifications
+ */
+struct bfi_ll_rsp {
+ struct bfi_mhdr mh; /* common msg header */
+ u8 error;
+ u8 rsvd[3];
+};
+
+/**
+ * BFI_LL_I2H_LINK_DOWN_AEN
+ * BFI_LL_I2H_LINK_UP_AEN
+ */
+struct bfi_ll_aen {
+ struct bfi_mhdr mh; /* common msg header */
+ u32 reason;
+ u8 cee_linkup;
+ u8 prio_map; /* LL priority bit-map */
+ u8 rsvd[2];
+};
+
+/**
+ * The following error codes can be returned
+ * by the mbox commands
+ */
+enum {
+ BFI_LL_CMD_OK = 0,
+ BFI_LL_CMD_FAIL = 1,
+ BFI_LL_CMD_DUP_ENTRY = 2, /* Duplicate entry in CAM */
+ BFI_LL_CMD_CAM_FULL = 3, /* CAM is full */
+ BFI_LL_CMD_NOT_OWNER = 4, /* Not permitted, b'cos not owner */
+ BFI_LL_CMD_NOT_EXEC = 5, /* Was not sent to f/w at all */
+};
+
+/* Statistics */
+#define BFI_LL_TXF_ID_MAX 64
+#define BFI_LL_RXF_ID_MAX 64
+
+/* TxF Frame Statistics */
+struct bfi_ll_stats_txf {
+ u64 ucast_octets;
+ u64 ucast;
+ u64 ucast_vlan;
+
+ u64 mcast_octets;
+ u64 mcast;
+ u64 mcast_vlan;
+
+ u64 bcast_octets;
+ u64 bcast;
+ u64 bcast_vlan;
+
+ u64 errors;
+ u64 filter_vlan; /* frames filtered due to VLAN */
+ u64 filter_mac_sa; /* frames filtered due to SA check */
+};
+
+
+/* RxF Frame Statistics */
+struct bfi_ll_stats_rxf {
+ u64 ucast_octets;
+ u64 ucast;
+ u64 ucast_vlan;
+
+ u64 mcast_octets;
+ u64 mcast;
+ u64 mcast_vlan;
+
+ u64 bcast_octets;
+ u64 bcast;
+ u64 bcast_vlan;
+ u64 frame_drops;
+};
+
+
+/* FC Tx Frame Statistics */
+struct bfi_ll_stats_fc_tx {
+ u64 txf_ucast_octets;
+ u64 txf_ucast;
+ u64 txf_ucast_vlan;
+
+ u64 txf_mcast_octets;
+ u64 txf_mcast;
+ u64 txf_mcast_vlan;
+
+ u64 txf_bcast_octets;
+ u64 txf_bcast;
+ u64 txf_bcast_vlan;
+
+ u64 txf_parity_errors;
+ u64 txf_timeout;
+ u64 txf_fid_parity_errors;
+};
+
+
+/* FC Rx Frame Statistics */
+struct bfi_ll_stats_fc_rx {
+ u64 rxf_ucast_octets;
+ u64 rxf_ucast;
+ u64 rxf_ucast_vlan;
+
+ u64 rxf_mcast_octets;
+ u64 rxf_mcast;
+ u64 rxf_mcast_vlan;
+
+ u64 rxf_bcast_octets;
+ u64 rxf_bcast;
+ u64 rxf_bcast_vlan;
+};
+
+
+/* RAD Frame Statistics */
+struct bfi_ll_stats_rad {
+ u64 rx_frames;
+ u64 rx_octets;
+ u64 rx_vlan_frames;
+
+ u64 rx_ucast;
+ u64 rx_ucast_octets;
+ u64 rx_ucast_vlan;
+
+ u64 rx_mcast;
+ u64 rx_mcast_octets;
+ u64 rx_mcast_vlan;
+
+ u64 rx_bcast;
+ u64 rx_bcast_octets;
+ u64 rx_bcast_vlan;
+
+ u64 rx_drops;
+};
+
+
+/* BPC Tx Registers */
+struct bfi_ll_stats_bpc {
+ /* transmit stats */
+ u64 tx_pause[8];
+ u64 tx_zero_pause[8]; /* Pause cancellation */
+ u64 tx_first_pause[8];/* Pause initiation rather than retention*/
+
+ /* receive stats */
+ u64 rx_pause[8];
+ u64 rx_zero_pause[8]; /* Pause cancellation */
+ u64 rx_first_pause[8];/* Pause initiation rather than retention*/
+};
+
+
+/* MAC Rx Statistics */
+struct bfi_ll_stats_mac {
+ u64 frame_64; /* both rx and tx counter */
+ u64 frame_65_127; /* both rx and tx counter */
+ u64 frame_128_255; /* both rx and tx counter */
+ u64 frame_256_511; /* both rx and tx counter */
+ u64 frame_512_1023; /* both rx and tx counter */
+ u64 frame_1024_1518; /* both rx and tx counter */
+ u64 frame_1519_1522; /* both rx and tx counter */
+
+ /* receive stats */
+ u64 rx_bytes;
+ u64 rx_packets;
+ u64 rx_fcs_error;
+ u64 rx_multicast;
+ u64 rx_broadcast;
+ u64 rx_control_frames;
+ u64 rx_pause;
+ u64 rx_unknown_opcode;
+ u64 rx_alignment_error;
+ u64 rx_frame_length_error;
+ u64 rx_code_error;
+ u64 rx_carrier_sense_error;
+ u64 rx_undersize;
+ u64 rx_oversize;
+ u64 rx_fragments;
+ u64 rx_jabber;
+ u64 rx_drop;
+
+ /* transmit stats */
+ u64 tx_bytes;
+ u64 tx_packets;
+ u64 tx_multicast;
+ u64 tx_broadcast;
+ u64 tx_pause;
+ u64 tx_deferral;
+ u64 tx_excessive_deferral;
+ u64 tx_single_collision;
+ u64 tx_muliple_collision;
+ u64 tx_late_collision;
+ u64 tx_excessive_collision;
+ u64 tx_total_collision;
+ u64 tx_pause_honored;
+ u64 tx_drop;
+ u64 tx_jabber;
+ u64 tx_fcs_error;
+ u64 tx_control_frame;
+ u64 tx_oversize;
+ u64 tx_undersize;
+ u64 tx_fragments;
+};
+
+
+/* Complete statistics */
+struct bfi_ll_stats {
+ struct bfi_ll_stats_mac mac_stats;
+ struct bfi_ll_stats_bpc bpc_stats;
+ struct bfi_ll_stats_rad rad_stats;
+ struct bfi_ll_stats_fc_rx fc_rx_stats;
+ struct bfi_ll_stats_fc_tx fc_tx_stats;
+ struct bfi_ll_stats_rxf rxf_stats[BFI_LL_RXF_ID_MAX];
+ struct bfi_ll_stats_txf txf_stats[BFI_LL_TXF_ID_MAX];
+};
+
+#pragma pack()
+
+#endif /* __BFI_LL_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/cee/bfa_cee.h net-next-2.6-mod/drivers/net/bna/include/cee/bfa_cee.h
--- net-next-2.6-orig/drivers/net/bna/include/cee/bfa_cee.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/cee/bfa_cee.h 2009-11-12 19:03:39.267342000 -0800
@@ -0,0 +1,77 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * @file bfa_cee.h CEE common module header file.
+ */
+
+#ifndef __BFA_CEE_H__
+#define __BFA_CEE_H__
+
+#include <defs/bfa_defs_cee.h>
+#include <bfa_ioc.h>
+#include <cs/bfa_trc.h>
+
+typedef void (*bfa_cee_get_attr_cbfn_t) (void *dev, bfa_status_t status);
+typedef void (*bfa_cee_get_stats_cbfn_t) (void *dev, bfa_status_t status);
+typedef void (*bfa_cee_reset_stats_cbfn_t) (void *dev, bfa_status_t status);
+typedef void (*bfa_cee_hbfail_cbfn_t) (void *dev, bfa_status_t status);
+
+struct bfa_cee_cbfn {
+ bfa_cee_get_attr_cbfn_t get_attr_cbfn;
+ void *get_attr_cbarg;
+ bfa_cee_get_stats_cbfn_t get_stats_cbfn;
+ void *get_stats_cbarg;
+ bfa_cee_reset_stats_cbfn_t reset_stats_cbfn;
+ void *reset_stats_cbarg;
+};
+
+struct bfa_cee {
+ void *dev;
+ bool get_attr_pending;
+ bool get_stats_pending;
+ bool reset_stats_pending;
+ bfa_status_t get_attr_status;
+ bfa_status_t get_stats_status;
+ bfa_status_t reset_stats_status;
+ struct bfa_cee_cbfn cbfn;
+ struct bfa_ioc_hbfail_notify hbfail;
+ struct bfa_trc_mod *trcmod;
+ struct bfa_log_mod *logmod;
+ struct bfa_cee_attr *attr;
+ struct bfa_cee_stats *stats;
+ struct bfa_dma attr_dma;
+ struct bfa_dma stats_dma;
+ struct bfa_ioc *ioc;
+ struct bfa_mbox_cmd get_cfg_mb;
+ struct bfa_mbox_cmd get_stats_mb;
+ struct bfa_mbox_cmd reset_stats_mb;
+};
+
+u32 bfa_cee_meminfo(void);
+void bfa_cee_mem_claim(struct bfa_cee *cee, u8 *dma_kva,
+ u64 dma_pa);
+void bfa_cee_attach(struct bfa_cee *cee, struct bfa_ioc *ioc, void *dev,
+ struct bfa_trc_mod *trcmod, struct bfa_log_mod *logmod);
+void bfa_cee_detach(struct bfa_cee *cee);
+bfa_status_t bfa_cee_get_attr(struct bfa_cee *cee,
+ struct bfa_cee_attr *attr, bfa_cee_get_attr_cbfn_t cbfn, void *cbarg);
+bfa_status_t bfa_cee_get_stats(struct bfa_cee *cee,
+ struct bfa_cee_stats *stats, bfa_cee_get_stats_cbfn_t cbfn, void *cbarg);
+bfa_status_t bfa_cee_reset_stats(struct bfa_cee *cee,
+ bfa_cee_reset_stats_cbfn_t cbfn, void *cbarg);
+
+#endif /* __BFA_CEE_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/cna/pstats/ethport_defs.h net-next-2.6-mod/drivers/net/bna/include/cna/pstats/ethport_defs.h
--- net-next-2.6-orig/drivers/net/bna/include/cna/pstats/ethport_defs.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/cna/pstats/ethport_defs.h 2009-11-12 19:03:39.319335000 -0800
@@ -0,0 +1,37 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __ETHPORT_DEFS_H__
+#define __ETHPORT_DEFS_H__
+
+struct bnad_drv_stats {
+ u64 netif_queue_stop;
+ u64 netif_queue_wakeup;
+ u64 tso4;
+ u64 tso6;
+ u64 tso_err;
+ u64 tcpcsum_offload;
+ u64 udpcsum_offload;
+ u64 csum_help;
+ u64 csum_help_err;
+ u64 hw_stats_updates;
+ u64 napi_complete;
+};
+#endif
diff -ruP net-next-2.6-orig/drivers/net/bna/include/cna/pstats/phyport_defs.h net-next-2.6-mod/drivers/net/bna/include/cna/pstats/phyport_defs.h
--- net-next-2.6-orig/drivers/net/bna/include/cna/pstats/phyport_defs.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/cna/pstats/phyport_defs.h 2009-11-12 19:03:39.326339000 -0800
@@ -0,0 +1,206 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __PHYPORT_DEFS_H__
+#define __PHYPORT_DEFS_H__
+
+#define BNA_TXF_ID_MAX 64
+#define BNA_RXF_ID_MAX 64
+
+/* Statistics */
+
+/* TxF Frame Statistics */
+struct bna_stats_txf {
+ u64 ucast_octets;
+ u64 ucast;
+ u64 ucast_vlan;
+
+ u64 mcast_octets;
+ u64 mcast;
+ u64 mcast_vlan;
+
+ u64 bcast_octets;
+ u64 bcast;
+ u64 bcast_vlan;
+
+ u64 errors;
+ u64 filter_vlan; /* frames filtered due to VLAN */
+ u64 filter_mac_sa; /* frames filtered due to SA check */
+};
+
+
+/* RxF Frame Statistics */
+struct bna_stats_rxf {
+ u64 ucast_octets;
+ u64 ucast;
+ u64 ucast_vlan;
+
+ u64 mcast_octets;
+ u64 mcast;
+ u64 mcast_vlan;
+
+ u64 bcast_octets;
+ u64 bcast;
+ u64 bcast_vlan;
+ u64 frame_drops;
+};
+
+
+/* FC Tx Frame Statistics */
+struct bna_stats_fc_tx {
+ u64 txf_ucast_octets;
+ u64 txf_ucast;
+ u64 txf_ucast_vlan;
+
+ u64 txf_mcast_octets;
+ u64 txf_mcast;
+ u64 txf_mcast_vlan;
+
+ u64 txf_bcast_octets;
+ u64 txf_bcast;
+ u64 txf_bcast_vlan;
+
+ u64 txf_parity_errors;
+ u64 txf_timeout;
+ u64 txf_fid_parity_errors;
+};
+
+
+/* FC Rx Frame Statistics */
+struct bna_stats_fc_rx {
+ u64 rxf_ucast_octets;
+ u64 rxf_ucast;
+ u64 rxf_ucast_vlan;
+
+ u64 rxf_mcast_octets;
+ u64 rxf_mcast;
+ u64 rxf_mcast_vlan;
+
+ u64 rxf_bcast_octets;
+ u64 rxf_bcast;
+ u64 rxf_bcast_vlan;
+};
+
+
+/* RAD Frame Statistics */
+struct cna_stats_rad {
+ u64 rx_frames;
+ u64 rx_octets;
+ u64 rx_vlan_frames;
+
+ u64 rx_ucast;
+ u64 rx_ucast_octets;
+ u64 rx_ucast_vlan;
+
+ u64 rx_mcast;
+ u64 rx_mcast_octets;
+ u64 rx_mcast_vlan;
+
+ u64 rx_bcast;
+ u64 rx_bcast_octets;
+ u64 rx_bcast_vlan;
+
+ u64 rx_drops;
+};
+
+
+/* BPC Tx Registers */
+struct cna_stats_bpc_tx {
+ u64 tx_pause[8];
+ u64 tx_zero_pause[8]; /* Pause cancellation */
+ u64 tx_first_pause[8];/* Pause initiation rather than retention*/
+};
+
+
+/* BPC Rx Registers */
+struct cna_stats_bpc_rx {
+ u64 rx_pause[8];
+ u64 rx_zero_pause[8]; /* Pause cancellation */
+ u64 rx_first_pause[8];/* Pause initiation rather than retention*/
+};
+
+
+/* MAC Rx Statistics */
+struct cna_stats_mac_rx {
+ u64 frame_64; /* both rx and tx counter */
+ u64 frame_65_127; /* both rx and tx counter */
+ u64 frame_128_255; /* both rx and tx counter */
+ u64 frame_256_511; /* both rx and tx counter */
+ u64 frame_512_1023; /* both rx and tx counter */
+ u64 frame_1024_1518; /* both rx and tx counter */
+ u64 frame_1518_1522; /* both rx and tx counter */
+ u64 rx_bytes;
+ u64 rx_packets;
+ u64 rx_fcs_error;
+ u64 rx_multicast;
+ u64 rx_broadcast;
+ u64 rx_control_frames;
+ u64 rx_pause;
+ u64 rx_unknown_opcode;
+ u64 rx_alignment_error;
+ u64 rx_frame_length_error;
+ u64 rx_code_error;
+ u64 rx_carrier_sense_error;
+ u64 rx_undersize;
+ u64 rx_oversize;
+ u64 rx_fragments;
+ u64 rx_jabber;
+ u64 rx_drop;
+};
+
+
+/* MAC Tx Statistics */
+struct cna_stats_mac_tx {
+ u64 tx_bytes;
+ u64 tx_packets;
+ u64 tx_multicast;
+ u64 tx_broadcast;
+ u64 tx_pause;
+ u64 tx_deferral;
+ u64 tx_excessive_deferral;
+ u64 tx_single_collision;
+ u64 tx_muliple_collision;
+ u64 tx_late_collision;
+ u64 tx_excessive_collision;
+ u64 tx_total_collision;
+ u64 tx_pause_honored;
+ u64 tx_drop;
+ u64 tx_jabber;
+ u64 tx_fcs_error;
+ u64 tx_control_frame;
+ u64 tx_oversize;
+ u64 tx_undersize;
+ u64 tx_fragments;
+};
+
+/* Complete statistics */
+struct bna_stats {
+ struct cna_stats_mac_rx mac_rx_stats;
+ struct cna_stats_bpc_rx bpc_rx_stats;
+ struct cna_stats_rad rad_stats;
+ struct bna_stats_fc_rx fc_rx_stats;
+ struct cna_stats_mac_tx mac_tx_stats;
+ struct cna_stats_bpc_tx bpc_tx_stats;
+ struct bna_stats_fc_tx fc_tx_stats;
+ struct bna_stats_rxf rxf_stats[BNA_TXF_ID_MAX];
+ struct bna_stats_txf txf_stats[BNA_RXF_ID_MAX];
+};
+
+#endif
diff -ruP net-next-2.6-orig/drivers/net/bna/include/cs/bfa_debug.h net-next-2.6-mod/drivers/net/bna/include/cs/bfa_debug.h
--- net-next-2.6-orig/drivers/net/bna/include/cs/bfa_debug.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/cs/bfa_debug.h 2009-11-12 19:03:39.384336000 -0800
@@ -0,0 +1,47 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+/**
+ * bfa_debug.h BFA debug interfaces
+ */
+
+#ifndef __BFA_DEBUG_H__
+#define __BFA_DEBUG_H__
+
+#define bfa_assert(__cond) do { \
+ if (!(__cond)) \
+ bfa_panic(__LINE__, __FILE__, #__cond); \
+} while (0)
+
+#define bfa_sm_fault(__mod, __event) do { \
+ bfa_sm_panic((__mod)->logm, __LINE__, __FILE__, __event); \
+} while (0)
+
+#ifndef BFA_PERF_BUILD
+#define bfa_assert_fp(__cond) bfa_assert(__cond)
+#else
+#define bfa_assert_fp(__cond)
+#endif
+
+struct bfa_log_mod;
+void bfa_panic(int line, char *file, char *panicstr);
+void bfa_sm_panic(struct bfa_log_mod *logm, int line, char *file, int event);
+
+#endif /* __BFA_DEBUG_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/cs/bfa_q.h net-next-2.6-mod/drivers/net/bna/include/cs/bfa_q.h
--- net-next-2.6-orig/drivers/net/bna/include/cs/bfa_q.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/cs/bfa_q.h 2009-11-12 19:03:39.349336000 -0800
@@ -0,0 +1,84 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+/**
+ * bfa_q.h Circular queue definitions.
+ */
+
+#ifndef __BFA_Q_H__
+#define __BFA_Q_H__
+
+#define bfa_q_first(_q) ((void *)(((struct list_head *) (_q))->next))
+#define bfa_q_next(_qe) (((struct list_head *) (_qe))->next)
+#define bfa_q_prev(_qe) (((struct list_head *) (_qe))->prev)
+
+/*
+ * bfa_q_qe_init - to initialize a queue element
+ */
+#define bfa_q_qe_init(_qe) { \
+ bfa_q_next(_qe) = (struct list_head *) NULL; \
+ bfa_q_prev(_qe) = (struct list_head *) NULL; \
+}
+
+/*
+ * bfa_q_deq - dequeue an element from head of the queue
+ */
+#define bfa_q_deq(_q, _qe) { \
+ if (!list_empty(_q)) { \
+ (*((struct list_head **) (_qe))) = bfa_q_next(_q); \
+ bfa_q_prev(bfa_q_next(*((struct list_head **) _qe))) = \
+ (struct list_head *) (_q); \
+ bfa_q_next(_q) = bfa_q_next(*((struct list_head **) _qe)); \
+ BFA_Q_DBG_INIT(*((struct list_head **) _qe)); \
+ } else { \
+ *((struct list_head **) (_qe)) = (struct list_head *) NULL; \
+ } \
+}
+
+/*
+ * bfa_q_deq_tail - dequeue an element from tail of the queue
+ */
+#define bfa_q_deq_tail(_q, _qe) { \
+ if (!list_empty(_q)) { \
+ *((struct list_head **) (_qe)) = bfa_q_prev(_q); \
+ bfa_q_next(bfa_q_prev(*((struct list_head **) _qe))) = \
+ (struct list_head *) (_q); \
+ bfa_q_prev(_q) = bfa_q_prev(*(struct list_head **) _qe); \
+ BFA_Q_DBG_INIT(*((struct list_head **) _qe)); \
+ } else { \
+ *((struct list_head **) (_qe)) = (struct list_head *) NULL; \
+ } \
+}
+
+/*
+ * #ifdef BFA_DEBUG (Using bfa_assert to check for debug_build is not
+ * consistent across modules)
+ */
+#ifndef BFA_PERF_BUILD
+#define BFA_Q_DBG_INIT(_qe) bfa_q_qe_init(_qe)
+#else
+#define BFA_Q_DBG_INIT(_qe)
+#endif
+
+#define bfa_q_is_on_q(_q, _qe) \
+ bfa_q_is_on_q_func(_q, (struct list_head *)(_qe))
+extern int bfa_q_is_on_q_func(struct list_head *q, struct list_head *qe);
+
+#endif
diff -ruP net-next-2.6-orig/drivers/net/bna/include/cs/bfa_sm.h net-next-2.6-mod/drivers/net/bna/include/cs/bfa_sm.h
--- net-next-2.6-orig/drivers/net/bna/include/cs/bfa_sm.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/cs/bfa_sm.h 2009-11-12 19:03:39.356348000 -0800
@@ -0,0 +1,81 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+/**
+ * bfasm.h State machine defines
+ */
+
+#ifndef __BFA_SM_H__
+#define __BFA_SM_H__
+
+typedef void (*bfa_sm_t)(void *sm, int event);
+
+/**
+ * oc - object class eg. bfa_ioc
+ * st - state, eg. reset
+ * otype - object type, eg. struct bfa_ioc
+ * etype - object type, eg. enum ioc_event
+ */
+#define bfa_sm_state_decl(oc, st, otype, etype) \
+ static void oc ## _sm_ ## st(otype * fsm, etype event)
+
+#define bfa_sm_set_state(_sm, _state) ((_sm)->sm = (bfa_sm_t)(_state))
+#define bfa_sm_send_event(_sm, _event) ((_sm)->sm((_sm), (_event)))
+#define bfa_sm_get_state(_sm) ((_sm)->sm)
+#define bfa_sm_cmp_state(_sm, _state) ((_sm)->sm == (bfa_sm_t)(_state))
+
+/**
+ * For converting from state machine function to state encoding.
+ */
+struct bfa_sm_table {
+ bfa_sm_t sm; /* state machine function */
+ int state; /* state machine encoding */
+ char *name; /* state name for display */
+};
+#define BFA_SM(_sm) ((bfa_sm_t)(_sm))
+
+int bfa_sm_to_state(struct bfa_sm_table *smt, bfa_sm_t sm);
+
+/**
+ * State machine with entry actions.
+ */
+typedef void (*bfa_fsm_t)(void *fsm, int event);
+
+/**
+ * oc - object class eg. bfa_ioc
+ * st - state, eg. reset
+ * otype - object type, eg. struct bfa_ioc
+ * etype - object type, eg. enum ioc_event
+ */
+#define bfa_fsm_state_decl(oc, st, otype, etype) \
+ static void oc ## _sm_ ## st(otype * fsm, etype event); \
+ static void oc ## _sm_ ## st ## _entry(otype * fsm)
+
+#define bfa_fsm_set_state(_fsm, _state) do { \
+ (_fsm)->fsm = (bfa_fsm_t)(_state); \
+ _state ## _entry(_fsm); \
+} while (0)
+
+#define bfa_fsm_send_event(_fsm, _event) \
+ ((_fsm)->fsm((_fsm), (_event)))
+#define bfa_fsm_cmp_state(_fsm, _state) \
+ ((_fsm)->fsm == (bfa_fsm_t)(_state))
+
+#endif
diff -ruP net-next-2.6-orig/drivers/net/bna/include/cs/bfa_trc.h net-next-2.6-mod/drivers/net/bna/include/cs/bfa_trc.h
--- net-next-2.6-orig/drivers/net/bna/include/cs/bfa_trc.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/cs/bfa_trc.h 2009-11-12 19:03:39.364335000 -0800
@@ -0,0 +1,179 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+#ifndef __BFA_TRC_H__
+#define __BFA_TRC_H__
+
+#include <cna.h>
+
+#ifndef BFA_TRC_MAX
+#define BFA_TRC_MAX (4 * 1024)
+#endif
+
+#ifndef BFA_TRC_TS
+#define BFA_TRC_TS(_trcm) ((_trcm)->ticks++)
+#endif
+
+struct bfa_trc {
+#ifdef __BIGENDIAN
+ u16 fileno;
+ u16 line;
+#else
+ u16 line;
+ u16 fileno;
+#endif
+ u32 timestamp;
+ union {
+ struct {
+ u32 rsvd;
+ u32 u32;
+ } u32;
+ u64 u64;
+ } data;
+};
+
+
+struct bfa_trc_mod {
+ u32 head;
+ u32 tail;
+ u32 ntrc;
+ u32 stopped;
+ u32 ticks;
+ u32 rsvd[3];
+ struct bfa_trc trc[BFA_TRC_MAX];
+};
+
+
+enum {
+ BFA_TRC_FW = 1, /* firmware modules */
+ BFA_TRC_HAL = 2, /* BFA modules */
+ BFA_TRC_FCS = 3, /* BFA FCS modules */
+ BFA_TRC_LDRV = 4, /* Linux driver modules */
+ BFA_TRC_SDRV = 5, /* Solaris driver modules */
+ BFA_TRC_VDRV = 6, /* vmware driver modules */
+ BFA_TRC_WDRV = 7, /* windows driver modules */
+ BFA_TRC_AEN = 8, /* AEN module */
+ BFA_TRC_BIOS = 9, /* bios driver modules */
+ BFA_TRC_EFI = 10, /* EFI driver modules */
+ BNA_TRC_WDRV = 11, /* BNA windows driver modules */
+ BNA_TRC_VDRV = 12, /* BNA vmware driver modules */
+ BNA_TRC_SDRV = 13, /* BNA Solaris driver modules */
+ BNA_TRC_LDRV = 14, /* BNA Linux driver modules */
+ BNA_TRC_HAL = 15, /* BNA modules */
+ BFA_TRC_CNA = 16, /* Common modules */
+ BNA_TRC_IMDRV = 17 /* BNA windows intermediate driver modules */
+};
+#define BFA_TRC_MOD_SH 10
+#define BFA_TRC_MOD(__mod) ((BFA_TRC_ ## __mod) << BFA_TRC_MOD_SH)
+
+/**
+ * Define a new tracing file (module). Module should match one defined above.
+ */
+#define BFA_TRC_FILE(__mod, __submod) \
+ static int __trc_fileno = ((BFA_TRC_ ## __mod ## _ ## __submod) | \
+ BFA_TRC_MOD(__mod))
+
+
+#define bfa_trc32(_trcp, _data) \
+ __bfa_trc((_trcp)->trcmod, __trc_fileno, __LINE__, (u32)_data)
+
+
+#ifndef BFA_BOOT_BUILD
+#define bfa_trc(_trcp, _data) \
+ __bfa_trc((_trcp)->trcmod, __trc_fileno, __LINE__, (u64)_data)
+#else
+void bfa_boot_trc(struct bfa_trc_mod *trcmod, u16 fileno,
+ u16 line, u32 data);
+#define bfa_trc(_trcp, _data) \
+ bfa_boot_trc((_trcp)->trcmod, __trc_fileno, __LINE__, (u32)_data)
+#endif
+
+
+static inline void
+bfa_trc_init(struct bfa_trc_mod *trcm)
+{
+ trcm->head = trcm->tail = trcm->stopped = 0;
+ trcm->ntrc = BFA_TRC_MAX;
+}
+
+
+static inline void
+bfa_trc_stop(struct bfa_trc_mod *trcm)
+{
+ trcm->stopped = 1;
+}
+
+#ifdef FWTRC
+extern void dc_flush(void *data);
+#else
+#define dc_flush(data)
+#endif
+
+
+static inline void
+__bfa_trc(struct bfa_trc_mod *trcm, int fileno, int line, u64 data)
+{
+ int tail = trcm->tail;
+ struct bfa_trc *trc = &trcm->trc[tail];
+
+ if (trcm->stopped)
+ return;
+
+ trc->fileno = (u16) fileno;
+ trc->line = (u16) line;
+ trc->data.u64 = data;
+ trc->timestamp = BFA_TRC_TS(trcm);
+ dc_flush(trc);
+
+ trcm->tail = (trcm->tail + 1) & (BFA_TRC_MAX - 1);
+ if (trcm->tail == trcm->head)
+ trcm->head = (trcm->head + 1) & (BFA_TRC_MAX - 1);
+ dc_flush(trcm);
+}
+
+
+static inline void
+__bfa_trc32(struct bfa_trc_mod *trcm, int fileno, int line, u32 data)
+{
+ int tail = trcm->tail;
+ struct bfa_trc *trc = &trcm->trc[tail];
+
+ if (trcm->stopped)
+ return;
+
+ trc->fileno = (u16) fileno;
+ trc->line = (u16) line;
+ trc->data.u32.u32 = data;
+ trc->timestamp = BFA_TRC_TS(trcm);
+ dc_flush(trc);
+
+ trcm->tail = (trcm->tail + 1) & (BFA_TRC_MAX - 1);
+ if (trcm->tail == trcm->head)
+ trcm->head = (trcm->head + 1) & (BFA_TRC_MAX - 1);
+ dc_flush(trcm);
+}
+
+#ifndef BFA_PERF_BUILD
+#define bfa_trc_fp(_trcp, _data) bfa_trc(_trcp, _data)
+#else
+#define bfa_trc_fp(_trcp, _data)
+#endif
+
+#endif /* __BFA_TRC_H__ */
+
diff -ruP net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_adapter.h net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_adapter.h
--- net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_adapter.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_adapter.h 2009-11-12 19:03:39.406338000 -0800
@@ -0,0 +1,85 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+#ifndef __BFA_DEFS_ADAPTER_H__
+#define __BFA_DEFS_ADAPTER_H__
+
+#include <protocol/types.h>
+#include <defs/bfa_defs_version.h>
+#include <defs/bfa_defs_mfg.h>
+
+/**
+ * BFA adapter level attributes.
+ */
+enum {
+ BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE),
+ /*
+ *!< adapter serial num length
+ */
+ BFA_ADAPTER_MODEL_NAME_LEN = 16, /* model name length */
+ BFA_ADAPTER_MODEL_DESCR_LEN = 128, /* model description length */
+ BFA_ADAPTER_MFG_NAME_LEN = 8, /* manufacturer name length */
+ BFA_ADAPTER_SYM_NAME_LEN = 64, /* adapter symbolic name length */
+ BFA_ADAPTER_OS_TYPE_LEN = 64, /* adapter os type length */
+};
+
+struct bfa_adapter_attr {
+ char manufacturer[BFA_ADAPTER_MFG_NAME_LEN];
+ char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
+ u32 rsvd1;
+ char model[BFA_ADAPTER_MODEL_NAME_LEN];
+ char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN];
+ wwn_t pwwn;
+ char node_symname[FC_SYMNAME_MAX];
+ char hw_ver[BFA_VERSION_LEN];
+ char fw_ver[BFA_VERSION_LEN];
+ char optrom_ver[BFA_VERSION_LEN];
+ char os_type[BFA_ADAPTER_OS_TYPE_LEN];
+ struct bfa_mfg_vpd vpd;
+ struct mac mac;
+
+ u8 nports;
+ u8 max_speed;
+ u8 prototype;
+ char asic_rev;
+
+ u8 pcie_gen;
+ u8 pcie_lanes_orig;
+ u8 pcie_lanes;
+ u8 cna_capable;
+};
+
+/**
+ * BFA adapter level events
+ * Arguments below are in BFAL context from Mgmt
+ * BFA_PORT_AEN_ADD: [in]: None [out]: serial_num, pwwn, nports
+ * BFA_PORT_AEN_REMOVE: [in]: pwwn [out]: serial_num, pwwn, nports
+ */
+enum bfa_adapter_aen_event {
+ BFA_ADAPTER_AEN_ADD = 1, /* New Adapter found event */
+ BFA_ADAPTER_AEN_REMOVE = 2, /* Adapter removed event */
+};
+
+struct bfa_adapter_aen_data {
+ char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
+ u32 nports; /* Number of NPorts */
+ wwn_t pwwn; /* WWN of one of its physical port */
+};
+
+#endif /* __BFA_DEFS_ADAPTER_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_cee.h net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_cee.h
--- net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_cee.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_cee.h 2009-11-12 19:03:39.435338000 -0800
@@ -0,0 +1,156 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * bfa_defs_cee.h Interface declarations between host based
+ * BFAL and DCBX/LLDP module in Firmware
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+#ifndef __BFA_DEFS_CEE_H__
+#define __BFA_DEFS_CEE_H__
+
+#include <protocol/types.h>
+
+#pragma pack(1)
+
+#define BFA_CEE_LLDP_MAX_STRING_LEN (128)
+
+#define BFA_CEE_LLDP_SYS_CAP_OTHER 0x0001
+#define BFA_CEE_LLDP_SYS_CAP_REPEATER 0x0002
+#define BFA_CEE_LLDP_SYS_CAP_MAC_BRIDGE 0x0004
+#define BFA_CEE_LLDP_SYS_CAP_WLAN_AP 0x0008
+#define BFA_CEE_LLDP_SYS_CAP_ROUTER 0x0010
+#define BFA_CEE_LLDP_SYS_CAP_TELEPHONE 0x0020
+#define BFA_CEE_LLDP_SYS_CAP_DOCSIS_CD 0x0040
+#define BFA_CEE_LLDP_SYS_CAP_STATION 0x0080
+#define BFA_CEE_LLDP_SYS_CAP_CVLAN 0x0100
+#define BFA_CEE_LLDP_SYS_CAP_SVLAN 0x0200
+#define BFA_CEE_LLDP_SYS_CAP_TPMR 0x0400
+
+
+/* LLDP string type */
+struct bfa_cee_lldp_str {
+ u8 sub_type;
+ u8 len;
+ u8 rsvd[2];
+ u8 value[BFA_CEE_LLDP_MAX_STRING_LEN];
+};
+
+
+/* LLDP paramters */
+struct bfa_cee_lldp_cfg {
+ struct bfa_cee_lldp_str chassis_id;
+ struct bfa_cee_lldp_str port_id;
+ struct bfa_cee_lldp_str port_desc;
+ struct bfa_cee_lldp_str sys_name;
+ struct bfa_cee_lldp_str sys_desc;
+ struct bfa_cee_lldp_str mgmt_addr;
+ u16 time_to_interval;
+ u16 enabled_system_cap;
+};
+
+enum bfa_cee_dcbx_version_e {
+ DCBX_PROTOCOL_PRECEE = 1,
+ DCBX_PROTOCOL_CEE = 2,
+};
+
+enum bfa_cee_lls_e {
+ CEE_LLS_DOWN_NO_TLV = 0, /* LLS is down bcoz TLV not sent by the peer */
+ CEE_LLS_DOWN = 1, /* LLS is down as advertised by the peer */
+ CEE_LLS_UP = 2,
+};
+
+/* CEE/DCBX parameters */
+struct bfa_cee_dcbx_cfg {
+ u8 pgid[8];
+ u8 pg_percentage[8];
+ u8 pfc_enabled; /* bitmap of priorties with PFC enabled */
+ u8 fcoe_user_priority; /* bitmap of priorities for FcoE traffic */
+ u8 dcbx_version; /* operating version:CEE or preCEE */
+ u8 lls_fcoe; /* FCoE Logical Link Status */
+ u8 lls_lan; /* LAN Logical Link Status */
+ u8 rsvd[3];
+};
+
+/* CEE status */
+/* Making this to tri-state for the benefit of port list command */
+enum bfa_cee_status_e {
+ CEE_UP = 0,
+ CEE_PHY_UP = 1,
+ CEE_LOOPBACK = 2,
+ CEE_PHY_DOWN = 3,
+};
+
+/* CEE Query */
+struct bfa_cee_attr {
+ u8 cee_status;
+ u8 error_reason;
+ struct bfa_cee_lldp_cfg lldp_remote;
+ struct bfa_cee_dcbx_cfg dcbx_remote;
+ struct mac src_mac;
+ u8 link_speed;
+ u8 nw_priority;
+ u8 filler[2];
+};
+
+
+
+
+/* LLDP/DCBX/CEE Statistics */
+
+struct bfa_cee_lldp_stats {
+ u32 frames_transmitted;
+ u32 frames_aged_out;
+ u32 frames_discarded;
+ u32 frames_in_error;
+ u32 frames_rcvd;
+ u32 tlvs_discarded;
+ u32 tlvs_unrecognized;
+};
+
+struct bfa_cee_dcbx_stats {
+ u32 subtlvs_unrecognized;
+ u32 negotiation_failed;
+ u32 remote_cfg_changed;
+ u32 tlvs_received;
+ u32 tlvs_invalid;
+ u32 seqno;
+ u32 ackno;
+ u32 recvd_seqno;
+ u32 recvd_ackno;
+};
+
+struct bfa_cee_cfg_stats {
+ u32 cee_status_down;
+ u32 cee_status_up;
+ u32 cee_hw_cfg_changed;
+ u32 recvd_invalid_cfg;
+};
+
+
+struct bfa_cee_stats {
+ struct bfa_cee_lldp_stats lldp_stats;
+ struct bfa_cee_dcbx_stats dcbx_stats;
+ struct bfa_cee_cfg_stats cfg_stats;
+};
+
+#pragma pack()
+
+
+#endif /* __BFA_DEFS_CEE_H__ */
+
+
diff -ruP net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_ioc.h net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_ioc.h
--- net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_ioc.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_ioc.h 2009-11-12 19:03:39.442329000 -0800
@@ -0,0 +1,154 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __BFA_DEFS_IOC_H__
+#define __BFA_DEFS_IOC_H__
+
+#include <protocol/types.h>
+#include <defs/bfa_defs_version.h>
+#include <defs/bfa_defs_adapter.h>
+
+enum {
+ BFA_IOC_DRIVER_LEN = 16,
+ BFA_IOC_CHIP_REV_LEN = 8,
+};
+
+/**
+ * Driver and firmware versions.
+ */
+struct bfa_ioc_driver_attr {
+ char driver[BFA_IOC_DRIVER_LEN]; /* driver name */
+ char driver_ver[BFA_VERSION_LEN]; /* driver version */
+ char fw_ver[BFA_VERSION_LEN]; /* firmware version*/
+ char bios_ver[BFA_VERSION_LEN]; /* bios version */
+ char efi_ver[BFA_VERSION_LEN]; /* EFI version */
+ char ob_ver[BFA_VERSION_LEN]; /* openboot version*/
+};
+
+/**
+ * IOC PCI device attributes
+ */
+struct bfa_ioc_pci_attr {
+ u16 vendor_id; /* PCI vendor ID */
+ u16 device_id; /* PCI device ID */
+ u16 ssid; /* subsystem ID */
+ u16 ssvid; /* subsystem vendor ID */
+ u32 pcifn; /* PCI device function */
+ u32 rsvd; /* padding */
+ u8 chip_rev[BFA_IOC_CHIP_REV_LEN]; /* chip revision */
+};
+
+/**
+ * IOC states
+ */
+enum bfa_ioc_state {
+ BFA_IOC_RESET = 1, /* IOC is in reset state */
+ BFA_IOC_SEMWAIT = 2, /* Waiting for IOC hardware semaphore */
+ BFA_IOC_HWINIT = 3, /* IOC hardware is being initialized */
+ BFA_IOC_GETATTR = 4, /* IOC is being configured */
+ BFA_IOC_OPERATIONAL = 5, /* IOC is operational */
+ BFA_IOC_INITFAIL = 6, /* IOC hardware failure */
+ BFA_IOC_HBFAIL = 7, /* IOC heart-beat failure */
+ BFA_IOC_DISABLING = 8, /* IOC is being disabled */
+ BFA_IOC_DISABLED = 9, /* IOC is disabled */
+ BFA_IOC_FWMISMATCH = 10, /* IOC firmware different from drivers */
+};
+
+/**
+ * IOC firmware stats
+ */
+struct bfa_fw_ioc_stats {
+ u32 hb_count;
+ u32 cfg_reqs;
+ u32 enable_reqs;
+ u32 disable_reqs;
+ u32 stats_reqs;
+ u32 clrstats_reqs;
+ u32 unknown_reqs;
+ u32 ic_reqs; /* interrupt coalesce reqs */
+};
+
+/**
+ * IOC driver stats
+ */
+struct bfa_ioc_drv_stats {
+ u32 ioc_isrs;
+ u32 ioc_enables;
+ u32 ioc_disables;
+ u32 ioc_hbfails;
+ u32 ioc_boots;
+ u32 stats_tmos;
+ u32 hb_count;
+ u32 disable_reqs;
+ u32 enable_reqs;
+ u32 disable_replies;
+ u32 enable_replies;
+};
+
+/**
+ * IOC statistics
+ */
+struct bfa_ioc_stats {
+ struct bfa_ioc_drv_stats drv_stats; /* driver IOC stats */
+ struct bfa_fw_ioc_stats fw_stats; /* firmware IOC stats */
+};
+
+
+enum bfa_ioc_type_e {
+ BFA_IOC_TYPE_FC = 1,
+ BFA_IOC_TYPE_FCoE = 2,
+ BFA_IOC_TYPE_LL = 3,
+};
+
+/**
+ * IOC attributes returned in queries
+ */
+struct bfa_ioc_attr {
+ enum bfa_ioc_type_e ioc_type;
+ enum bfa_ioc_state state; /* IOC state */
+ struct bfa_adapter_attr adapter_attr; /* HBA attributes */
+ struct bfa_ioc_driver_attr driver_attr; /* driver attr */
+ struct bfa_ioc_pci_attr pci_attr;
+ u8 port_id; /* port number */
+ u8 rsvd[7]; /* 64bit align */
+};
+
+/**
+ * BFA IOC level events
+ */
+enum bfa_ioc_aen_event {
+ BFA_IOC_AEN_HBGOOD = 1, /* Heart Beat restore event */
+ BFA_IOC_AEN_HBFAIL = 2, /* Heart Beat failure event */
+ BFA_IOC_AEN_ENABLE = 3, /* IOC enabled event */
+ BFA_IOC_AEN_DISABLE = 4, /* IOC disabled event */
+ BFA_IOC_AEN_FWMISMATCH = 5, /* IOC firmware mismatch */
+};
+
+/**
+ * BFA IOC level event data, now just a place holder
+ */
+struct bfa_ioc_aen_data {
+ wwn_t pwwn;
+ s16 ioc_type;
+ struct mac mac;
+};
+
+#endif /* __BFA_DEFS_IOC_H__ */
+
diff -ruP net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_mfg.h net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_mfg.h
--- net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_mfg.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_mfg.h 2009-11-12 19:03:39.427341000 -0800
@@ -0,0 +1,144 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+#ifndef __BFA_DEFS_MFG_H__
+#define __BFA_DEFS_MFG_H__
+
+#include <cna.h>
+
+/**
+ * Manufacturing block version
+ */
+#define BFA_MFG_VERSION 2
+
+/**
+ * Manufacturing block encrypted version
+ */
+#define BFA_MFG_ENC_VER 2
+
+/**
+ * Manufacturing block version 1 length
+ */
+#define BFA_MFG_VER1_LEN 128
+
+/**
+ * Manufacturing block header length
+ */
+#define BFA_MFG_HDR_LEN 4
+
+/**
+ * Checksum size
+ */
+#define BFA_MFG_CHKSUM_SIZE 16
+
+/**
+ * Manufacturing block encrypted version
+ */
+#define BFA_MFG_ENC_VER 2
+
+/**
+ * Manufacturing block version 1 length
+ */
+#define BFA_MFG_VER1_LEN 128
+
+/**
+ * Manufacturing block header length
+ */
+#define BFA_MFG_HDR_LEN 4
+
+/**
+ * Checksum size
+ */
+#define BFA_MFG_CHKSUM_SIZE 16
+
+/**
+ * Manufacturing block format
+ */
+#define BFA_MFG_SERIALNUM_SIZE 11
+#define BFA_MFG_PARTNUM_SIZE 14
+#define BFA_MFG_SUPPLIER_ID_SIZE 10
+#define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20
+#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
+#define BFA_MFG_SUPPLIER_REVISION_SIZE 4
+#define STRSZ(_n) (((_n) + 4) & ~3)
+
+/**
+ * Manufacturing card type
+ */
+enum {
+ BFA_MFG_TYPE_CB_MAX = 825, /* Crossbow card type max */
+ BFA_MFG_TYPE_FC8P2 = 825, /* 8G 2port FC card */
+ BFA_MFG_TYPE_FC8P1 = 815, /* 8G 1port FC card */
+ BFA_MFG_TYPE_FC4P2 = 425, /* 4G 2port FC card */
+ BFA_MFG_TYPE_FC4P1 = 415, /* 4G 1port FC card */
+ BFA_MFG_TYPE_CNA10P2 = 1020, /* 10G 2port CNA card */
+ BFA_MFG_TYPE_CNA10P1 = 1010, /* 10G 1port CNA card */
+};
+
+#pragma pack(1)
+
+/**
+ * Card type to port number conversion
+ */
+#define bfa_mfg_type2port_num(card_type) (((card_type) / 10) % 10)
+
+
+/**
+ * All numerical fields are in big-endian format.
+ */
+struct bfa_mfg_block {
+};
+
+/**
+ * VPD data length
+ */
+#define BFA_MFG_VPD_LEN 512
+
+#define BFA_MFG_VPD_PCI_HDR_OFF 137
+#define BFA_MFG_VPD_PCI_VER_MASK 0x07 /* version mask 3 bits */
+#define BFA_MFG_VPD_PCI_VDR_MASK 0xf8 /* vendor mask 5 bits */
+
+/**
+ * VPD vendor tag
+ */
+enum {
+ BFA_MFG_VPD_UNKNOWN = 0, /* vendor unknown */
+ BFA_MFG_VPD_IBM = 1, /* vendor IBM */
+ BFA_MFG_VPD_HP = 2, /* vendor HP */
+ BFA_MFG_VPD_PCI_IBM = 0x08, /* PCI VPD IBM */
+ BFA_MFG_VPD_PCI_HP = 0x10, /* PCI VPD HP */
+ BFA_MFG_VPD_PCI_BRCD = 0xf8, /* PCI VPD Brocade */
+};
+
+/**
+ * All numerical fields are in big-endian format.
+ */
+struct bfa_mfg_vpd {
+ u8 version; /* vpd data version */
+ u8 vpd_sig[3]; /* characters 'V', 'P', 'D' */
+ u8 chksum; /* u8 checksum */
+ u8 vendor; /* vendor */
+ u8 len; /* vpd data length excluding header */
+ u8 rsv;
+ u8 data[BFA_MFG_VPD_LEN]; /* vpd data */
+};
+
+#pragma pack()
+
+#endif /* __BFA_DEFS_MFG_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_pci.h net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_pci.h
--- net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_pci.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_pci.h 2009-11-12 19:03:39.413337000 -0800
@@ -0,0 +1,44 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __BFA_DEFS_PCI_H__
+#define __BFA_DEFS_PCI_H__
+
+/**
+ * PCI device and vendor ID information
+ */
+enum {
+ BFA_PCI_VENDOR_ID_BROCADE = 0x1657,
+ BFA_PCI_DEVICE_ID_FC_8G2P = 0x13,
+ BFA_PCI_DEVICE_ID_FC_8G1P = 0x17,
+ BFA_PCI_DEVICE_ID_CT = 0x14,
+};
+
+/**
+ * PCI sub-system device and vendor ID information
+ */
+enum {
+ BFA_PCI_FCOE_SSDEVICE_ID = 0x14,
+};
+
+#define BFA_PCI_ACCESS_RANGES 1 /* Maximum number of device address ranges
+ * mapped through different BAR(s). */
+
+#endif /* __BFA_DEFS_PCI_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_status.h net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_status.h
--- net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_status.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_status.h 2009-11-12 19:03:39.450319000 -0800
@@ -0,0 +1,267 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+#ifndef __BFA_DEFS_STATUS_H__
+#define __BFA_DEFS_STATUS_H__
+
+/**
+ * API status return values
+ *
+ * NOTE: The error msgs are auto generated from the comments. Only singe line
+ * comments are supported
+ */
+enum bfa_status {
+ BFA_STATUS_OK = 0, /* Success */
+ BFA_STATUS_FAILED = 1, /* Operation failed */
+ BFA_STATUS_EINVAL = 2, /* Invalid params Check input
+ * parameters */
+ BFA_STATUS_ENOMEM = 3, /* Out of resources */
+ BFA_STATUS_ENOSYS = 4, /* Function not implemented */
+ BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if
+ * persists, contact support */
+ BFA_STATUS_EPROTOCOL = 6, /* Protocol error */
+ BFA_STATUS_ENOFCPORTS = 7, /* No FC ports resources */
+ BFA_STATUS_NOFLASH = 8, /* Flash not present */
+ BFA_STATUS_BADFLASH = 9, /* Flash is corrupted or bad */
+ BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */
+ BFA_STATUS_UNKNOWN_VFID = 11, /* VF_ID not found */
+ BFA_STATUS_DATACORRUPTED = 12, /* Diag returned data corrupted
+ * contact support */
+ BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */
+ BFA_STATUS_ABORTED = 14, /* Operation aborted */
+ BFA_STATUS_NODEV = 15, /* Dev is not present */
+ BFA_STATUS_HDMA_FAILED = 16, /* Host dma failed contact support */
+ BFA_STATUS_FLASH_BAD_LEN = 17, /* Flash bad length */
+ BFA_STATUS_UNKNOWN_LWWN = 18, /* LPORT PWWN not found */
+ BFA_STATUS_UNKNOWN_RWWN = 19, /* RPORT PWWN not found */
+ BFA_STATUS_FCPT_LS_RJT = 20, /* Got LS_RJT for FC Pass
+ * through Req */
+ BFA_STATUS_VPORT_EXISTS = 21, /* VPORT already exists */
+ BFA_STATUS_VPORT_MAX = 22, /* Reached max VPORT supported
+ * limit */
+ BFA_STATUS_UNSUPP_SPEED = 23, /* Invalid Speed Check speed
+ * setting */
+ BFA_STATUS_INVLD_DFSZ = 24, /* Invalid Max data field size */
+ BFA_STATUS_CNFG_FAILED = 25, /* Setting can not be persisted */
+ BFA_STATUS_CMD_NOTSUPP = 26, /* Command/API not supported */
+ BFA_STATUS_NO_ADAPTER = 27, /* No Brocade Adapter Found */
+ BFA_STATUS_LINKDOWN = 28, /* Link is down - Check or replace
+ * SFP/cable */
+ BFA_STATUS_FABRIC_RJT = 29, /* Reject from attached fabric */
+ BFA_STATUS_UNKNOWN_VWWN = 30, /* VPORT PWWN not found */
+ BFA_STATUS_NSLOGIN_FAILED = 31, /* Nameserver login failed */
+ BFA_STATUS_NO_RPORTS = 32, /* No remote ports found */
+ BFA_STATUS_NSQUERY_FAILED = 33, /* Nameserver query failed */
+ BFA_STATUS_PORT_OFFLINE = 34, /* Port is not online */
+ BFA_STATUS_RPORT_OFFLINE = 35, /* RPORT is not online */
+ BFA_STATUS_TGTOPEN_FAILED = 36, /* Remote SCSI target open failed */
+ BFA_STATUS_BAD_LUNS = 37, /* No valid LUNs found */
+ BFA_STATUS_IO_FAILURE = 38, /* SCSI target IO failure */
+ BFA_STATUS_NO_FABRIC = 39, /* No switched fabric present */
+ BFA_STATUS_EBADF = 40, /* Bad file descriptor */
+ BFA_STATUS_EINTR = 41, /* A signal was caught during ioctl */
+ BFA_STATUS_EIO = 42, /* I/O error */
+ BFA_STATUS_ENOTTY = 43, /* Inappropriate I/O control
+ * operation */
+ BFA_STATUS_ENXIO = 44, /* No such device or address */
+ BFA_STATUS_EFOPEN = 45, /* Failed to open file */
+ BFA_STATUS_VPORT_WWN_BP = 46, /* WWN is same as base port's WWN */
+ BFA_STATUS_PORT_NOT_DISABLED = 47, /* Port not disabled disable port
+ * first */
+ BFA_STATUS_BADFRMHDR = 48, /* Bad frame header */
+ BFA_STATUS_BADFRMSZ = 49, /* Bad frame size check and replace
+ * SFP/cable */
+ BFA_STATUS_MISSINGFRM = 50, /* Missing frame check and replace
+ * SFP/cable */
+ BFA_STATUS_LINKTIMEOUT = 51, /* Link timeout check and replace
+ * SFP/cable */
+ BFA_STATUS_NO_FCPIM_NEXUS = 52, /* No FCP Nexus exists with the
+ * rport */
+ BFA_STATUS_CHECKSUM_FAIL = 53, /* checksum failure */
+ BFA_STATUS_GZME_FAILED = 54, /* Get zone member query failed */
+ BFA_STATUS_SCSISTART_REQD = 55, /* SCSI disk require START command */
+ BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists
+ * contact support */
+ BFA_STATUS_INVALID_WWN = 57, /* Invalid WWN */
+ BFA_STATUS_MISMATCH = 58, /* Version mismatch */
+ BFA_STATUS_IOC_ENABLED = 59, /* IOC is already enabled */
+ BFA_STATUS_ADAPTER_ENABLED = 60, /* Adapter is not disabled disable
+ * adapter first */
+ BFA_STATUS_IOC_NON_OP = 61, /* IOC is not operational. Enable IOC
+ * and if it still fails,
+ * contact support */
+ BFA_STATUS_ADDR_MAP_FAILURE = 62, /* PCI base address not mapped
+ * in OS */
+ BFA_STATUS_SAME_NAME = 63, /* Name exists! use a different
+ * name */
+ BFA_STATUS_PENDING = 64, /* API completes asynchronously */
+ BFA_STATUS_8G_SPD = 65, /* Speed setting not valid for
+ * 8G HBA */
+ BFA_STATUS_4G_SPD = 66, /* Speed setting not valid for
+ * 4G HBA */
+ BFA_STATUS_AD_IS_ENABLE = 67, /* Adapter is already enabled */
+ BFA_STATUS_EINVAL_TOV = 68, /* Invalid path failover TOV */
+ BFA_STATUS_EINVAL_QDEPTH = 69, /* Invalid queue depth value */
+ BFA_STATUS_VERSION_FAIL = 70, /* Application/Driver version
+ * mismatch */
+ BFA_STATUS_DIAG_BUSY = 71, /* diag busy */
+ BFA_STATUS_BEACON_ON = 72, /* Port Beacon already on */
+ BFA_STATUS_BEACON_OFF = 73, /* Port Beacon already off */
+ BFA_STATUS_LBEACON_ON = 74, /* Link End-to-End Beacon already
+ * on */
+ BFA_STATUS_LBEACON_OFF = 75, /* Link End-to-End Beacon already
+ * off */
+ BFA_STATUS_PORT_NOT_INITED = 76, /* Port not initialized */
+ BFA_STATUS_RPSC_ENABLED = 77, /* Target has a valid speed */
+ BFA_STATUS_ENOFSAVE = 78, /* No saved firmware trace */
+ BFA_STATUS_BAD_FILE = 79, /* Not a valid Brocade Boot Code
+ * file */
+ BFA_STATUS_RLIM_EN = 80, /* Target rate limiting is already
+ * enabled */
+ BFA_STATUS_RLIM_DIS = 81, /* Target rate limiting is already
+ * disabled */
+ BFA_STATUS_IOC_DISABLED = 82, /* IOC is already disabled */
+ BFA_STATUS_ADAPTER_DISABLED = 83, /* Adapter is already disabled */
+ BFA_STATUS_BIOS_DISABLED = 84, /* Bios is already disabled */
+ BFA_STATUS_AUTH_ENABLED = 85, /* Authentication is already
+ * enabled */
+ BFA_STATUS_AUTH_DISABLED = 86, /* Authentication is already
+ * disabled */
+ BFA_STATUS_ERROR_TRL_ENABLED = 87, /* Target rate limiting is
+ * enabled */
+ BFA_STATUS_ERROR_QOS_ENABLED = 88, /* QoS is enabled */
+ BFA_STATUS_NO_SFP_DEV = 89, /* No SFP device check or replace SFP */
+ BFA_STATUS_MEMTEST_FAILED = 90, /* Memory test failed contact
+ * support */
+ BFA_STATUS_INVALID_DEVID = 91, /* Invalid device id provided */
+ BFA_STATUS_QOS_ENABLED = 92, /* QOS is already enabled */
+ BFA_STATUS_QOS_DISABLED = 93, /* QOS is already disabled */
+ BFA_STATUS_INCORRECT_DRV_CONFIG = 94, /* Check configuration
+ * key/value pair */
+ BFA_STATUS_REG_FAIL = 95, /* Can't read windows registry */
+ BFA_STATUS_IM_INV_CODE = 96, /* Invalid IOCTL code */
+ BFA_STATUS_IM_INV_VLAN = 97, /* Invalid VLAN ID */
+ BFA_STATUS_IM_INV_ADAPT_NAME = 98, /* Invalid adapter name */
+ BFA_STATUS_IM_LOW_RESOURCES = 99, /* Memory allocation failure in
+ * driver */
+ BFA_STATUS_IM_VLANID_IS_PVID = 100, /* Given VLAN id same as PVID */
+ BFA_STATUS_IM_VLANID_EXISTS = 101, /* Given VLAN id already exists */
+ BFA_STATUS_IM_FW_UPDATE_FAIL = 102, /* Updating firmware with new
+ * VLAN ID failed */
+ BFA_STATUS_PORTLOG_ENABLED = 103, /* Port Log is already enabled */
+ BFA_STATUS_PORTLOG_DISABLED = 104, /* Port Log is already disabled */
+ BFA_STATUS_FILE_NOT_FOUND = 105, /* Specified file could not be
+ * found */
+ BFA_STATUS_QOS_FC_ONLY = 106, /* QOS can be enabled for FC mode
+ * only */
+ BFA_STATUS_RLIM_FC_ONLY = 107, /* RATELIM can be enabled for FC mode
+ * only */
+ BFA_STATUS_CT_SPD = 108, /* Invalid speed selection for Catapult. */
+ BFA_STATUS_LEDTEST_OP = 109, /* LED test is operating */
+ BFA_STATUS_CEE_NOT_DN = 110, /* eth port is not at down state, please
+ * bring down first */
+ BFA_STATUS_10G_SPD = 111, /* Speed setting not valid for 10G HBA */
+ BFA_STATUS_IM_INV_TEAM_NAME = 112, /* Invalid team name */
+ BFA_STATUS_IM_DUP_TEAM_NAME = 113, /* Given team name already
+ * exists */
+ BFA_STATUS_IM_ADAPT_ALREADY_IN_TEAM = 114, /* Given adapter is part
+ * of another team or VLANS
+ * exist */
+ BFA_STATUS_IM_ADAPT_HAS_VLANS = 115, /* Adapter has VLANs configured.
+ * Delete all VLANs to become part
+ * of team */
+ BFA_STATUS_IM_PVID_MISMATCH = 116, /* Mismatching PVIDs configured
+ * for adapters */
+ BFA_STATUS_IM_LINK_SPEED_MISMATCH = 117, /* Mismatching link speeds
+ * configured for adapters */
+ BFA_STATUS_IM_MTU_MISMATCH = 118, /* Mismatching MTUs configured for
+ * adapters */
+ BFA_STATUS_IM_RSS_MISMATCH = 119, /* Mismatching RSS parameters
+ * configured for adapters */
+ BFA_STATUS_IM_HDS_MISMATCH = 120, /* Mismatching HDS parameters
+ * configured for adapters */
+ BFA_STATUS_IM_OFFLOAD_MISMATCH = 121, /* Mismatching offload
+ * parameters configured for
+ * adapters */
+ BFA_STATUS_IM_PORT_PARAMS = 122, /* Error setting port parameters */
+ BFA_STATUS_IM_PORT_NOT_IN_TEAM = 123, /* Port is not part of team */
+ BFA_STATUS_IM_CANNOT_REM_PRI = 124, /* Primary adapter cannot be
+ * removed. Change primary before
+ * removing */
+ BFA_STATUS_IM_MAX_PORTS_REACHED = 125, /* Exceeding maximum ports
+ * per team */
+ BFA_STATUS_IM_LAST_PORT_DELETE = 126, /* Last port in team being
+ * deleted */
+ BFA_STATUS_IM_NO_DRIVER = 127, /* IM driver is not installed */
+ BFA_STATUS_IM_MAX_VLANS_REACHED = 128, /* Exceeding maximum VLANs
+ * per port */
+ BFA_STATUS_TOMCAT_SPD_NOT_ALLOWED = 129, /* Bios speed config not
+ * allowed for CNA */
+ BFA_STATUS_NO_MINPORT_DRIVER = 130, /* Miniport driver is not
+ * loaded */
+ BFA_STATUS_CARD_TYPE_MISMATCH = 131, /* Card type mismatch */
+ BFA_STATUS_BAD_ASICBLK = 132, /* Bad ASIC block */
+ BFA_STATUS_NO_DRIVER = 133, /* Brocade adapter/driver not installed
+ * or loaded */
+ BFA_STATUS_INVALID_MAC = 134, /* Invalid mac address */
+ BFA_STATUS_IM_NO_VLAN = 135, /* No VLANs configured on the adapter */
+ BFA_STATUS_IM_ETH_LB_FAILED = 136, /* Ethernet loopback test failed */
+ BFA_STATUS_IM_PVID_REMOVE = 137, /* Cannot remove port vlan (PVID) */
+ BFA_STATUS_IM_PVID_EDIT = 138, /* Cannot edit port vlan (PVID) */
+ BFA_STATUS_CNA_NO_BOOT = 139, /* Boot upload not allowed for CNA */
+ BFA_STATUS_IM_PVID_NON_ZERO = 140, /* Port VLAN ID (PVID) is Set to
+ * Non-Zero Value */
+ BFA_STATUS_IM_INETCFG_LOCK_FAILED = 141, /* Acquiring Network
+ * Subsytem Lock Failed.Please
+ * try after some time */
+ BFA_STATUS_IM_GET_INETCFG_FAILED = 142, /* Acquiring Network Subsytem
+ * handle Failed. Please try
+ * after some time */
+ BFA_STATUS_IM_NOT_BOUND = 143, /* IM driver is not active */
+ BFA_STATUS_INSUFFICIENT_PERMS = 144, /* User doesn't have sufficient
+ * permissions to execute the BCU
+ * application */
+ BFA_STATUS_IM_INV_VLAN_NAME = 145, /* Invalid/Reserved Vlan name
+ * string. The name is not allowed
+ * for the normal Vlans */
+ BFA_STATUS_CMD_NOTSUPP_CNA = 146, /* Command not supported for CNA */
+ BFA_STATUS_IM_PASSTHRU_EDIT = 147, /* Can not edit passthru vlan id */
+ BFA_STATUS_IM_BIND_FAILED = 148, /*! < IM Driver bind operation
+ * failed */
+ BFA_STATUS_IM_UNBIND_FAILED = 149, /* ! < IM Driver unbind operation
+ * failed */
+ BFA_STATUS_IM_PORT_IN_TEAM = 150, /* Port is already part of the
+ * team */
+ BFA_STATUS_IM_VLAN_NOT_FOUND = 151, /* VLAN ID doesn't exists */
+ BFA_STATUS_IM_TEAM_NOT_FOUND = 152, /* Teaming configuration doesn't
+ * exists */
+ BFA_STATUS_IM_TEAM_CFG_NOT_ALLOWED = 153, /* Given settings are not
+ * allowed for the current
+ * Teaming mode */
+ BFA_STATUS_MAX_VAL /* Unknown error code */
+};
+#define bfa_status_t enum bfa_status
+
+enum bfa_eproto_status {
+ BFA_EPROTO_BAD_ACCEPT = 0,
+ BFA_EPROTO_UNKNOWN_RSP = 1
+};
+#define bfa_eproto_status_t enum bfa_eproto_status
+
+#endif /* __BFA_DEFS_STATUS_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_version.h net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_version.h
--- net-next-2.6-orig/drivers/net/bna/include/defs/bfa_defs_version.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/defs/bfa_defs_version.h 2009-11-12 19:03:39.420336000 -0800
@@ -0,0 +1,25 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+#ifndef __BFA_DEFS_VERSION_H__
+#define __BFA_DEFS_VERSION_H__
+
+#define BFA_VERSION_LEN 64
+
+#endif
diff -ruP net-next-2.6-orig/drivers/net/bna/include/protocol/types.h net-next-2.6-mod/drivers/net/bna/include/protocol/types.h
--- net-next-2.6-orig/drivers/net/bna/include/protocol/types.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/include/protocol/types.h 2009-11-12 19:03:39.462309000 -0800
@@ -0,0 +1,44 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+/**
+ * types.h Protocol defined base types
+ */
+
+#ifndef __TYPES_H__
+#define __TYPES_H__
+
+#include <cna.h>
+
+#define wwn_t u64
+#define lun_t u64
+
+#define WWN_NULL (0)
+#define FC_SYMNAME_MAX 256 /* max name server symbolic name size */
+#define FC_ALPA_MAX 128
+
+#pragma pack(1)
+
+#define MAC_ADDRLEN (6)
+struct mac { u8 mac[MAC_ADDRLEN]; };
+
+#pragma pack()
+
+#endif
^ permalink raw reply
* Subject: [PATCH 3/6] bna: Brocade 10Gb Ethernet device driver
From: Rasesh Mody @ 2009-11-13 3:46 UTC (permalink / raw)
To: netdev; +Cc: adapter_linux_open_src_team
From: Rasesh Mody <rmody@brocade.com>
This is patch 3/6 which contains linux driver source for
Brocade's BR1010/BR1020 10Gb CEE capable ethernet adapter.
Source is based against net-next-2.6.
We wish this patch to be considered for inclusion in net-next-2.6
Signed-off-by: Rasesh Mody <rmody@brocade.com>
---
bfa_cee.c | 473 +++++++++++++
bfa_csdebug.c | 69 ++
bfa_ioc.c | 2001 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
bfa_ioc_ct.c | 414 ++++++++++++
bfa_sm.c | 41 +
bna_if.c | 574 ++++++++++++++++
bna_iocll.h | 65 +
bna_priv.h | 482 +++++++++++++
bnad_compat.h | 95 ++
bnad_defs.h | 37 +
cna.h | 82 ++
11 files changed, 4333 insertions(+)
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_cee.c net-next-2.6-mod/drivers/net/bna/bfa_cee.c
--- net-next-2.6-orig/drivers/net/bna/bfa_cee.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_cee.c 2009-11-12 19:03:38.660342000 -0800
@@ -0,0 +1,473 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * @file bfa_cee.c CEE module source file.
+ */
+
+#include <defs/bfa_defs_cee.h>
+#include <cs/bfa_trc.h>
+#include <cs/bfa_debug.h>
+#include <cee/bfa_cee.h>
+#include <bfi/bfi_cee.h>
+#include <bfi/bfi.h>
+#include <bfa_ioc.h>
+
+
+#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
+#define bfa_lpuid(__arg) bfa_ioc_portid(&(__arg)->ioc)
+
+static void bfa_cee_format_lldp_cfg(struct bfa_cee_lldp_cfg *lldp_cfg);
+static void
+bfa_cee_format_dcbcx_stats(struct bfa_cee_dcbx_stats *dcbcx_stats);
+static void bfa_cee_format_lldp_stats(struct bfa_cee_lldp_stats *lldp_stats);
+static void bfa_cee_format_cfg_stats(struct bfa_cee_cfg_stats *cfg_stats);
+static void bfa_cee_format_cee_cfg(void *buffer);
+static void bfa_cee_format_cee_stats(void *buffer);
+
+static void
+bfa_cee_format_cee_stats(void *buffer)
+{
+ struct bfa_cee_stats *cee_stats = buffer;
+ bfa_cee_format_dcbcx_stats(&cee_stats->dcbx_stats);
+ bfa_cee_format_lldp_stats(&cee_stats->lldp_stats);
+ bfa_cee_format_cfg_stats(&cee_stats->cfg_stats);
+}
+
+static void
+bfa_cee_format_cee_cfg(void *buffer)
+{
+ struct bfa_cee_attr *cee_cfg = buffer;
+ bfa_cee_format_lldp_cfg(&cee_cfg->lldp_remote);
+}
+
+
+static void
+bfa_cee_format_dcbcx_stats(struct bfa_cee_dcbx_stats *dcbcx_stats)
+{
+ dcbcx_stats->subtlvs_unrecognized =
+ ntohl(dcbcx_stats->subtlvs_unrecognized);
+ dcbcx_stats->negotiation_failed =
+ ntohl(dcbcx_stats->negotiation_failed);
+ dcbcx_stats->remote_cfg_changed =
+ ntohl(dcbcx_stats->remote_cfg_changed);
+ dcbcx_stats->tlvs_received =
+ ntohl(dcbcx_stats->tlvs_received);
+ dcbcx_stats->tlvs_invalid =
+ ntohl(dcbcx_stats->tlvs_invalid);
+ dcbcx_stats->seqno =
+ ntohl(dcbcx_stats->seqno);
+ dcbcx_stats->ackno =
+ ntohl(dcbcx_stats->ackno);
+ dcbcx_stats->recvd_seqno =
+ ntohl(dcbcx_stats->recvd_seqno);
+ dcbcx_stats->recvd_ackno =
+ ntohl(dcbcx_stats->recvd_ackno);
+}
+
+static void
+bfa_cee_format_lldp_stats(struct bfa_cee_lldp_stats *lldp_stats)
+{
+ lldp_stats->frames_transmitted =
+ ntohl(lldp_stats->frames_transmitted);
+ lldp_stats->frames_aged_out =
+ ntohl(lldp_stats->frames_aged_out);
+ lldp_stats->frames_discarded =
+ ntohl(lldp_stats->frames_discarded);
+ lldp_stats->frames_in_error =
+ ntohl(lldp_stats->frames_in_error);
+ lldp_stats->frames_rcvd =
+ ntohl(lldp_stats->frames_rcvd);
+ lldp_stats->tlvs_discarded =
+ ntohl(lldp_stats->tlvs_discarded);
+ lldp_stats->tlvs_unrecognized =
+ ntohl(lldp_stats->tlvs_unrecognized);
+}
+
+static void
+bfa_cee_format_cfg_stats(struct bfa_cee_cfg_stats *cfg_stats)
+{
+ cfg_stats->cee_status_down =
+ ntohl(cfg_stats->cee_status_down);
+ cfg_stats->cee_status_up =
+ ntohl(cfg_stats->cee_status_up);
+ cfg_stats->cee_hw_cfg_changed =
+ ntohl(cfg_stats->cee_hw_cfg_changed);
+ cfg_stats->recvd_invalid_cfg =
+ ntohl(cfg_stats->recvd_invalid_cfg);
+}
+
+static void
+bfa_cee_format_lldp_cfg(struct bfa_cee_lldp_cfg *lldp_cfg)
+{
+ lldp_cfg->time_to_interval =
+ ntohs(lldp_cfg->time_to_interval);
+ lldp_cfg->enabled_system_cap =
+ ntohs(lldp_cfg->enabled_system_cap);
+}
+
+
+/**
+ * bfa_cee_attr_meminfo()
+ *
+ *
+ * @param[in] void
+ *
+ * @return Size of DMA region
+ */
+static u32
+bfa_cee_attr_meminfo(void)
+{
+ return BFA_ROUNDUP(sizeof(struct bfa_cee_attr), BFA_DMA_ALIGN_SZ);
+}
+/**
+ * bfa_cee_stats_meminfo()
+ *
+ *
+ * @param[in] void
+ *
+ * @return Size of DMA region
+ */
+static u32
+bfa_cee_stats_meminfo(void)
+{
+ return BFA_ROUNDUP(sizeof(struct bfa_cee_stats), BFA_DMA_ALIGN_SZ);
+}
+
+/**
+ * bfa_cee_get_attr_isr()
+ *
+ *
+ * @param[in] cee - Pointer to the CEE module
+ * status - Return status from the f/w
+ *
+ * @return void
+ */
+static void
+bfa_cee_get_attr_isr(struct bfa_cee *cee, bfa_status_t status)
+{
+ cee->get_attr_status = status;
+ if (status == BFA_STATUS_OK) {
+ /* The requested data has been copied to the DMA area,
+ * process it.
+ */
+ memcpy(cee->attr, cee->attr_dma.kva,
+ sizeof(struct bfa_cee_attr));
+ bfa_cee_format_cee_cfg(cee->attr);
+ }
+ cee->get_attr_pending = false;
+ if (cee->cbfn.get_attr_cbfn)
+ cee->cbfn.get_attr_cbfn(cee->cbfn.get_attr_cbarg, status);
+}
+
+/**
+ * bfa_cee_get_attr_isr()
+ *
+ *
+ * @param[in] cee - Pointer to the CEE module
+ * status - Return status from the f/w
+ *
+ * @return void
+ */
+static void
+bfa_cee_get_stats_isr(struct bfa_cee *cee, bfa_status_t status)
+{
+ cee->get_stats_status = status;
+ if (status == BFA_STATUS_OK) {
+ /* The requested data has been copied to the DMA area,
+ * process it.
+ */
+ memcpy(cee->stats, cee->stats_dma.kva,
+ sizeof(struct bfa_cee_stats));
+ bfa_cee_format_cee_stats(cee->stats);
+ }
+ cee->get_stats_pending = false;
+ if (cee->cbfn.get_stats_cbfn)
+ cee->cbfn.get_stats_cbfn(cee->cbfn.get_stats_cbarg, status);
+}
+
+/**
+ * bfa_cee_get_attr_isr()
+ *
+ *
+ * @param[in] cee - Pointer to the CEE module
+ * status - Return status from the f/w
+ *
+ * @return void
+ */
+static void
+bfa_cee_reset_stats_isr(struct bfa_cee *cee, bfa_status_t status)
+{
+ cee->reset_stats_status = status;
+ cee->reset_stats_pending = false;
+ if (cee->cbfn.reset_stats_cbfn)
+ cee->cbfn.reset_stats_cbfn(cee->cbfn.reset_stats_cbarg, status);
+}
+/**
+ * bfa_cee_meminfo()
+ *
+ *
+ * @param[in] void
+ *
+ * @return Size of DMA region
+ */
+u32
+bfa_cee_meminfo(void)
+{
+ return bfa_cee_attr_meminfo() + bfa_cee_stats_meminfo();
+}
+
+/**
+ * bfa_cee_mem_claim()
+ *
+ *
+ * @param[in] cee CEE module pointer
+ * dma_kva Kernel Virtual Address of CEE DMA Memory
+ * dma_pa Physical Address of CEE DMA Memory
+ *
+ * @return void
+ */
+void
+bfa_cee_mem_claim(struct bfa_cee *cee, u8 *dma_kva, u64 dma_pa)
+{
+ cee->attr_dma.kva = dma_kva;
+ cee->attr_dma.pa = dma_pa;
+ cee->stats_dma.kva = dma_kva + bfa_cee_attr_meminfo();
+ cee->stats_dma.pa = dma_pa + bfa_cee_attr_meminfo();
+ cee->attr = (struct bfa_cee_attr *) dma_kva;
+ cee->stats =
+ (struct bfa_cee_stats *) (dma_kva + bfa_cee_attr_meminfo());
+}
+
+/**
+ * bfa_cee_get_attr()
+ *
+ * Send the request to the f/w to fetch CEE attributes.
+ *
+ * @param[in] Pointer to the CEE module data structure.
+ *
+ * @return Status
+ */
+
+bfa_status_t
+bfa_cee_get_attr(struct bfa_cee *cee, struct bfa_cee_attr *attr,
+ bfa_cee_get_attr_cbfn_t cbfn, void *cbarg)
+{
+ struct bfi_cee_get_req *cmd;
+
+ bfa_assert((cee != NULL) && (cee->ioc != NULL));
+ if (!bfa_ioc_is_operational(cee->ioc))
+ return BFA_STATUS_IOC_FAILURE;
+ if (cee->get_attr_pending == true)
+ return BFA_STATUS_DEVBUSY;
+ cee->get_attr_pending = true;
+ cmd = (struct bfi_cee_get_req *) cee->get_cfg_mb.msg;
+ cee->attr = attr;
+ cee->cbfn.get_attr_cbfn = cbfn;
+ cee->cbfn.get_attr_cbarg = cbarg;
+ bfi_h2i_set(cmd->mh, BFI_MC_CEE, BFI_CEE_H2I_GET_CFG_REQ,
+ bfa_ioc_portid(cee->ioc));
+ bfa_dma_be_addr_set(cmd->dma_addr, cee->attr_dma.pa);
+ bfa_ioc_mbox_queue(cee->ioc, &cee->get_cfg_mb);
+
+ return BFA_STATUS_OK;
+}
+
+/**
+ * bfa_cee_get_stats()
+ *
+ * Send the request to the f/w to fetch CEE statistics.
+ *
+ * @param[in] Pointer to the CEE module data structure.
+ *
+ * @return Status
+ */
+
+bfa_status_t
+bfa_cee_get_stats(struct bfa_cee *cee, struct bfa_cee_stats *stats,
+ bfa_cee_get_stats_cbfn_t cbfn, void *cbarg)
+{
+ struct bfi_cee_get_req *cmd;
+
+ bfa_assert((cee != NULL) && (cee->ioc != NULL));
+
+ if (!bfa_ioc_is_operational(cee->ioc))
+ return BFA_STATUS_IOC_FAILURE;
+ if (cee->get_stats_pending == true)
+ return BFA_STATUS_DEVBUSY;
+ cee->get_stats_pending = true;
+ cmd = (struct bfi_cee_get_req *) cee->get_stats_mb.msg;
+ cee->stats = stats;
+ cee->cbfn.get_stats_cbfn = cbfn;
+ cee->cbfn.get_stats_cbarg = cbarg;
+ bfi_h2i_set(cmd->mh, BFI_MC_CEE, BFI_CEE_H2I_GET_STATS_REQ,
+ bfa_ioc_portid(cee->ioc));
+ bfa_dma_be_addr_set(cmd->dma_addr, cee->stats_dma.pa);
+ bfa_ioc_mbox_queue(cee->ioc, &cee->get_stats_mb);
+
+ return BFA_STATUS_OK;
+}
+
+/**
+ * bfa_cee_reset_stats()
+ *
+ *
+ * @param[in] Pointer to the CEE module data structure.
+ *
+ * @return Status
+ */
+
+bfa_status_t
+bfa_cee_reset_stats(struct bfa_cee *cee, bfa_cee_reset_stats_cbfn_t cbfn,
+ void *cbarg)
+{
+ struct bfi_cee_reset_stats *cmd;
+
+ bfa_assert((cee != NULL) && (cee->ioc != NULL));
+ if (!bfa_ioc_is_operational(cee->ioc))
+ return BFA_STATUS_IOC_FAILURE;
+ if (cee->reset_stats_pending == true)
+ return BFA_STATUS_DEVBUSY;
+ cee->reset_stats_pending = true;
+ cmd = (struct bfi_cee_reset_stats *) cee->reset_stats_mb.msg;
+ cee->cbfn.reset_stats_cbfn = cbfn;
+ cee->cbfn.reset_stats_cbarg = cbarg;
+ bfi_h2i_set(cmd->mh, BFI_MC_CEE, BFI_CEE_H2I_RESET_STATS,
+ bfa_ioc_portid(cee->ioc));
+ bfa_ioc_mbox_queue(cee->ioc, &cee->reset_stats_mb);
+ return BFA_STATUS_OK;
+}
+
+
+/**
+ * bfa_cee_isrs()
+ *
+ *
+ * @param[in] Pointer to the CEE module data structure.
+ *
+ * @return void
+ */
+
+void
+bfa_cee_isr(void *cbarg, struct bfi_mbmsg *m)
+{
+ union bfi_cee_i2h_msg_u *msg;
+ struct bfi_cee_get_rsp *get_rsp;
+ struct bfa_cee *cee = (struct bfa_cee *) cbarg;
+ msg = (union bfi_cee_i2h_msg_u *) m;
+ get_rsp = (struct bfi_cee_get_rsp *) m;
+ switch (msg->mh.msg_id) {
+ case BFI_CEE_I2H_GET_CFG_RSP:
+ bfa_cee_get_attr_isr(cee, get_rsp->cmd_status);
+ break;
+ case BFI_CEE_I2H_GET_STATS_RSP:
+ bfa_cee_get_stats_isr(cee, get_rsp->cmd_status);
+ break;
+ case BFI_CEE_I2H_RESET_STATS_RSP:
+ bfa_cee_reset_stats_isr(cee, get_rsp->cmd_status);
+ break;
+ default:
+ bfa_assert(0);
+ }
+}
+
+/**
+ * bfa_cee_hbfail()
+ *
+ *
+ * @param[in] Pointer to the CEE module data structure.
+ *
+ * @return void
+ */
+
+void
+bfa_cee_hbfail(void *arg)
+{
+ struct bfa_cee *cee;
+ cee = (struct bfa_cee *) arg;
+
+ if (cee->get_attr_pending == true) {
+ cee->get_attr_status = BFA_STATUS_FAILED;
+ cee->get_attr_pending = false;
+ if (cee->cbfn.get_attr_cbfn) {
+ cee->cbfn.get_attr_cbfn(cee->cbfn.get_attr_cbarg,
+ BFA_STATUS_FAILED);
+ }
+ }
+ if (cee->get_stats_pending == true) {
+ cee->get_stats_status = BFA_STATUS_FAILED;
+ cee->get_stats_pending = false;
+ if (cee->cbfn.get_stats_cbfn) {
+ cee->cbfn.get_stats_cbfn(cee->cbfn.get_stats_cbarg,
+ BFA_STATUS_FAILED);
+ }
+ }
+ if (cee->reset_stats_pending == true) {
+ cee->reset_stats_status = BFA_STATUS_FAILED;
+ cee->reset_stats_pending = false;
+ if (cee->cbfn.reset_stats_cbfn) {
+ cee->cbfn.reset_stats_cbfn(cee->cbfn.reset_stats_cbarg,
+ BFA_STATUS_FAILED);
+ }
+ }
+}
+
+/**
+ * bfa_cee_attach()
+ *
+ *
+ * @param[in] cee - Pointer to the CEE module data structure
+ * ioc - Pointer to the ioc module data structure
+ * dev - Pointer to the device driver module data structure
+ * The device driver specific mbox ISR functions have
+ * this pointer as one of the parameters.
+ * trcmod -
+ * logmod -
+ *
+ * @return void
+ */
+void
+bfa_cee_attach(struct bfa_cee *cee, struct bfa_ioc *ioc,
+ void *dev,
+ struct bfa_trc_mod *trcmod,
+ struct bfa_log_mod *logmod)
+{
+ bfa_assert(cee != NULL);
+ cee->dev = dev;
+ cee->trcmod = trcmod;
+ cee->logmod = logmod;
+ cee->ioc = ioc;
+
+ bfa_ioc_mbox_regisr(cee->ioc, BFI_MC_CEE, bfa_cee_isr, cee);
+ bfa_ioc_hbfail_init(&cee->hbfail, bfa_cee_hbfail, cee);
+ bfa_ioc_hbfail_register(cee->ioc, &cee->hbfail);
+}
+
+/**
+ * bfa_cee_detach()
+ *
+ *
+ * @param[in] cee - Pointer to the CEE module data structure
+ *
+ * @return void
+ */
+void
+bfa_cee_detach(struct bfa_cee *cee)
+{
+ /*For now, just check if there is some ioctl pending
+ *and mark that as failed?*/
+ /* bfa_cee_hbfail(cee); */
+}
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_csdebug.c net-next-2.6-mod/drivers/net/bna/bfa_csdebug.c
--- net-next-2.6-orig/drivers/net/bna/bfa_csdebug.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_csdebug.c 2009-11-12 19:03:38.668337000 -0800
@@ -0,0 +1,69 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+/**
+ * pbind.c BFA FC Persistent target binding
+ */
+
+#include <cs/bfa_debug.h>
+#include <cna.h>
+#include <cs/bfa_q.h>
+#include <cna.h>
+
+/**
+ * cs_debug_api
+ */
+
+
+void
+bfa_panic(int line, char *file, char *panicstr)
+{
+
+ DPRINTK(ERR, "Assertion failure: %s:%d: %s",
+ file, line, panicstr);
+ bfa_os_panic();
+}
+
+void
+bfa_sm_panic(struct bfa_log_mod *logm, int line, char *file, int event)
+{
+
+ DPRINTK(ERR, "SM Assertion failure: %s:%d: event = %d",
+ file, line, event);
+ bfa_os_panic();
+}
+
+int
+bfa_q_is_on_q_func(struct list_head *q, struct list_head *qe)
+{
+ struct list_head *tqe;
+
+ tqe = bfa_q_next(q);
+ while (tqe != q) {
+ if (tqe == qe)
+ return 1;
+ tqe = bfa_q_next(tqe);
+ if (tqe == NULL)
+ break;
+ }
+ return 0;
+}
+
+
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_ioc.c net-next-2.6-mod/drivers/net/bna/bfa_ioc.c
--- net-next-2.6-orig/drivers/net/bna/bfa_ioc.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_ioc.c 2009-11-12 19:03:38.675356000 -0800
@@ -0,0 +1,2001 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#include <bfa_ioc.h>
+#include <bfa_fwimg_priv.h>
+#include <cs/bfa_debug.h>
+#include <bfi/bfi_ioc.h>
+#include <bfi/bfi_ctreg.h>
+#include <defs/bfa_defs_pci.h>
+#include <cna.h>
+
+
+/**
+ * IOC local definitions
+ */
+#define BFA_IOC_TOV 2000 /* msecs */
+#define BFA_IOC_HWSEM_TOV 500 /* msecs */
+#define BFA_IOC_HB_TOV 500 /* msecs */
+#define BFA_IOC_HWINIT_MAX 2
+#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
+#define BFA_IOC_TOV_RECOVER BFA_IOC_HB_TOV
+
+#define bfa_ioc_timer_start(__ioc) \
+ bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->ioc_timer, \
+ bfa_ioc_timeout, (__ioc), BFA_IOC_TOV)
+#define bfa_ioc_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->ioc_timer)
+
+#define BFA_DBG_FWTRC_ENTS (BFI_IOC_TRC_ENTS)
+#define BFA_DBG_FWTRC_LEN \
+ (BFA_DBG_FWTRC_ENTS * sizeof(struct bfa_trc) + \
+ (sizeof(struct bfa_trc_mod) - \
+ BFA_TRC_MAX * sizeof(struct bfa_trc)))
+#define BFA_DBG_FWTRC_OFF(_fn) (BFI_IOC_TRC_OFF + BFA_DBG_FWTRC_LEN * (_fn))
+
+/**
+ * Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details.
+ */
+
+#define bfa_ioc_firmware_lock(__ioc) \
+ ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
+#define bfa_ioc_firmware_unlock(__ioc) \
+ ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
+#define bfa_ioc_fwimg_get_chunk(__ioc, __off) \
+ ((__ioc)->ioc_hwif->ioc_fwimg_get_chunk(__ioc, __off))
+#define bfa_ioc_fwimg_get_size(__ioc) \
+ ((__ioc)->ioc_hwif->ioc_fwimg_get_size(__ioc))
+#define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc))
+#define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc))
+#define bfa_ioc_notify_hbfail(__ioc) \
+ ((__ioc)->ioc_hwif->ioc_notify_hbfail(__ioc))
+
+bool bfa_auto_recover = true;
+
+/*
+ * forward declarations
+ */
+static void bfa_ioc_hw_sem_get(struct bfa_ioc *ioc);
+static void bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc);
+static void bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force);
+static void bfa_ioc_timeout(void *ioc);
+static void bfa_ioc_send_enable(struct bfa_ioc *ioc);
+static void bfa_ioc_send_disable(struct bfa_ioc *ioc);
+static void bfa_ioc_send_getattr(struct bfa_ioc *ioc);
+static void bfa_ioc_hb_monitor(struct bfa_ioc *ioc);
+static void bfa_ioc_hb_stop(struct bfa_ioc *ioc);
+static void bfa_ioc_reset(struct bfa_ioc *ioc, bool force);
+static void bfa_ioc_mbox_poll(struct bfa_ioc *ioc);
+static void bfa_ioc_mbox_hbfail(struct bfa_ioc *ioc);
+static void bfa_ioc_recover(struct bfa_ioc *ioc);
+static void bfa_ioc_disable_comp(struct bfa_ioc *ioc);
+static void bfa_ioc_lpu_stop(struct bfa_ioc *ioc);
+
+/**
+ * hal_ioc_sm
+ */
+
+/**
+ * IOC state machine events
+ */
+enum ioc_event {
+ IOC_E_ENABLE = 1, /* IOC enable request */
+ IOC_E_DISABLE = 2, /* IOC disable request */
+ IOC_E_TIMEOUT = 3, /* f/w response timeout */
+ IOC_E_FWREADY = 4, /* f/w initialization done */
+ IOC_E_FWRSP_GETATTR = 5, /* IOC get attribute response */
+ IOC_E_FWRSP_ENABLE = 6, /* enable f/w response */
+ IOC_E_FWRSP_DISABLE = 7, /* disable f/w response */
+ IOC_E_HBFAIL = 8, /* heartbeat failure */
+ IOC_E_HWERROR = 9, /* hardware error interrupt */
+ IOC_E_SEMLOCKED = 10, /* h/w semaphore is locked */
+ IOC_E_DETACH = 11, /* driver detach cleanup */
+};
+
+
+bfa_fsm_state_decl(bfa_ioc, reset, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, fwcheck, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, mismatch, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, semwait, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, hwinit, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, enabling, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, getattr, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, op, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, initfail, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, hbfail, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, disabling, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, disabled, struct bfa_ioc, enum ioc_event);
+
+static struct bfa_sm_table ioc_sm_table[] = {
+ {BFA_SM(bfa_ioc_sm_reset), BFA_IOC_RESET},
+ {BFA_SM(bfa_ioc_sm_fwcheck), BFA_IOC_FWMISMATCH},
+ {BFA_SM(bfa_ioc_sm_mismatch), BFA_IOC_FWMISMATCH},
+ {BFA_SM(bfa_ioc_sm_semwait), BFA_IOC_SEMWAIT},
+ {BFA_SM(bfa_ioc_sm_hwinit), BFA_IOC_HWINIT},
+ {BFA_SM(bfa_ioc_sm_enabling), BFA_IOC_HWINIT},
+ {BFA_SM(bfa_ioc_sm_getattr), BFA_IOC_GETATTR},
+ {BFA_SM(bfa_ioc_sm_op), BFA_IOC_OPERATIONAL},
+ {BFA_SM(bfa_ioc_sm_initfail), BFA_IOC_INITFAIL},
+ {BFA_SM(bfa_ioc_sm_hbfail), BFA_IOC_HBFAIL},
+ {BFA_SM(bfa_ioc_sm_disabling), BFA_IOC_DISABLING},
+ {BFA_SM(bfa_ioc_sm_disabled), BFA_IOC_DISABLED},
+};
+
+/**
+ * Reset entry actions -- initialize state machine
+ */
+static void
+bfa_ioc_sm_reset_entry(struct bfa_ioc *ioc)
+{
+ ioc->retry_count = 0;
+ ioc->auto_recover = bfa_auto_recover;
+}
+
+/**
+ * Beginning state. IOC is in reset state.
+ */
+static void
+bfa_ioc_sm_reset(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_ENABLE:
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_fwcheck);
+ break;
+
+ case IOC_E_DISABLE:
+ bfa_ioc_disable_comp(ioc);
+ break;
+
+ case IOC_E_DETACH:
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+/**
+ * Semaphore should be acquired for version check.
+ */
+static void
+bfa_ioc_sm_fwcheck_entry(struct bfa_ioc *ioc)
+{
+ bfa_ioc_hw_sem_get(ioc);
+}
+
+/**
+ * Awaiting h/w semaphore to continue with version check.
+ */
+static void
+bfa_ioc_sm_fwcheck(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_SEMLOCKED:
+ if (bfa_ioc_firmware_lock(ioc)) {
+ ioc->retry_count = 0;
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_hwinit);
+ } else {
+ bfa_ioc_hw_sem_release(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_mismatch);
+ }
+ break;
+
+ case IOC_E_DISABLE:
+ bfa_ioc_disable_comp(ioc);
+ /* fall through */
+
+ case IOC_E_DETACH:
+ bfa_ioc_hw_sem_get_cancel(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+ break;
+
+ case IOC_E_FWREADY:
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+/**
+ * Notify enable completion callback and generate mismatch AEN.
+ */
+static void
+bfa_ioc_sm_mismatch_entry(struct bfa_ioc *ioc)
+{
+ /**
+ * Provide enable completion callback and AEN notification only once.
+ */
+ if (ioc->retry_count == 0)
+ ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
+ ioc->retry_count++;
+ bfa_ioc_timer_start(ioc);
+}
+
+/**
+ * Awaiting firmware version match.
+ */
+static void
+bfa_ioc_sm_mismatch(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_TIMEOUT:
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_fwcheck);
+ break;
+
+ case IOC_E_DISABLE:
+ bfa_ioc_disable_comp(ioc);
+ /* fall through */
+
+ case IOC_E_DETACH:
+ bfa_ioc_timer_stop(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+ break;
+
+ case IOC_E_FWREADY:
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+/**
+ * Request for semaphore.
+ */
+static void
+bfa_ioc_sm_semwait_entry(struct bfa_ioc *ioc)
+{
+ bfa_ioc_hw_sem_get(ioc);
+}
+
+/**
+ * Awaiting semaphore for h/w initialzation.
+ */
+static void
+bfa_ioc_sm_semwait(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_SEMLOCKED:
+ ioc->retry_count = 0;
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_hwinit);
+ break;
+
+ case IOC_E_DISABLE:
+ bfa_ioc_hw_sem_get_cancel(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+
+static void
+bfa_ioc_sm_hwinit_entry(struct bfa_ioc *ioc)
+{
+ bfa_ioc_timer_start(ioc);
+ bfa_ioc_reset(ioc, false);
+}
+
+/**
+ * Hardware is being initialized. Interrupts are enabled.
+ * Holding hardware semaphore lock.
+ */
+static void
+bfa_ioc_sm_hwinit(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_FWREADY:
+ bfa_ioc_timer_stop(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
+ break;
+
+ case IOC_E_HWERROR:
+ bfa_ioc_timer_stop(ioc);
+ /* fall through */
+
+ case IOC_E_TIMEOUT:
+ ioc->retry_count++;
+ if (ioc->retry_count < BFA_IOC_HWINIT_MAX) {
+ bfa_ioc_timer_start(ioc);
+ bfa_ioc_reset(ioc, true);
+ break;
+ }
+
+ bfa_ioc_hw_sem_release(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_initfail);
+ break;
+
+ case IOC_E_DISABLE:
+ bfa_ioc_hw_sem_release(ioc);
+ bfa_ioc_timer_stop(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+
+static void
+bfa_ioc_sm_enabling_entry(struct bfa_ioc *ioc)
+{
+ bfa_ioc_timer_start(ioc);
+ bfa_ioc_send_enable(ioc);
+}
+
+/**
+ * Host IOC function is being enabled, awaiting response from firmware.
+ * Semaphore is acquired.
+ */
+static void
+bfa_ioc_sm_enabling(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_FWRSP_ENABLE:
+ bfa_ioc_timer_stop(ioc);
+ bfa_ioc_hw_sem_release(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
+ break;
+
+ case IOC_E_HWERROR:
+ bfa_ioc_timer_stop(ioc);
+ /* fall through */
+
+ case IOC_E_TIMEOUT:
+ ioc->retry_count++;
+ if (ioc->retry_count < BFA_IOC_HWINIT_MAX) {
+ bfa_reg_write(ioc->ioc_regs.ioc_fwstate,
+ BFI_IOC_UNINIT);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_hwinit);
+ break;
+ }
+
+ bfa_ioc_hw_sem_release(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_initfail);
+ break;
+
+ case IOC_E_DISABLE:
+ bfa_ioc_timer_stop(ioc);
+ bfa_ioc_hw_sem_release(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+ break;
+
+ case IOC_E_FWREADY:
+ bfa_ioc_send_enable(ioc);
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+
+static void
+bfa_ioc_sm_getattr_entry(struct bfa_ioc *ioc)
+{
+ bfa_ioc_timer_start(ioc);
+ bfa_ioc_send_getattr(ioc);
+}
+
+/**
+ * IOC configuration in progress. Timer is active.
+ */
+static void
+bfa_ioc_sm_getattr(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_FWRSP_GETATTR:
+ bfa_ioc_timer_stop(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_op);
+ break;
+
+ case IOC_E_HWERROR:
+ bfa_ioc_timer_stop(ioc);
+ /* fall through */
+
+ case IOC_E_TIMEOUT:
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_initfail);
+ break;
+
+ case IOC_E_DISABLE:
+ bfa_ioc_timer_stop(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+
+static void
+bfa_ioc_sm_op_entry(struct bfa_ioc *ioc)
+{
+ ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_OK);
+ bfa_ioc_hb_monitor(ioc);
+}
+
+static void
+bfa_ioc_sm_op(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_ENABLE:
+ break;
+
+ case IOC_E_DISABLE:
+ bfa_ioc_hb_stop(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
+ break;
+
+ case IOC_E_HWERROR:
+ case IOC_E_FWREADY:
+ /**
+ * Hard error or IOC recovery by other function.
+ * Treat it same as heartbeat failure.
+ */
+ bfa_ioc_hb_stop(ioc);
+ /* !!! fall through !!! */
+
+ case IOC_E_HBFAIL:
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_hbfail);
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+
+static void
+bfa_ioc_sm_disabling_entry(struct bfa_ioc *ioc)
+{
+ bfa_ioc_timer_start(ioc);
+ bfa_ioc_send_disable(ioc);
+}
+
+/**
+ * IOC is being disabled
+ */
+static void
+bfa_ioc_sm_disabling(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_FWRSP_DISABLE:
+ bfa_ioc_timer_stop(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+ break;
+
+ case IOC_E_HWERROR:
+ bfa_ioc_timer_stop(ioc);
+ /*
+ * !!! fall through !!!
+ */
+
+ case IOC_E_TIMEOUT:
+ bfa_reg_write(ioc->ioc_regs.ioc_fwstate, BFI_IOC_FAIL);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+/**
+ * IOC disable completion entry.
+ */
+static void
+bfa_ioc_sm_disabled_entry(struct bfa_ioc *ioc)
+{
+ bfa_ioc_disable_comp(ioc);
+}
+
+static void
+bfa_ioc_sm_disabled(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_ENABLE:
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_semwait);
+ break;
+
+ case IOC_E_DISABLE:
+ ioc->cbfn->disable_cbfn(ioc->bfa);
+ break;
+
+ case IOC_E_FWREADY:
+ break;
+
+ case IOC_E_DETACH:
+ bfa_ioc_firmware_unlock(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+
+static void
+bfa_ioc_sm_initfail_entry(struct bfa_ioc *ioc)
+{
+ ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
+ bfa_ioc_timer_start(ioc);
+}
+
+/**
+ * Hardware initialization failed.
+ */
+static void
+bfa_ioc_sm_initfail(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+ case IOC_E_DISABLE:
+ bfa_ioc_timer_stop(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+ break;
+
+ case IOC_E_DETACH:
+ bfa_ioc_timer_stop(ioc);
+ bfa_ioc_firmware_unlock(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+ break;
+
+ case IOC_E_TIMEOUT:
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_semwait);
+ break;
+
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+
+static void
+bfa_ioc_sm_hbfail_entry(struct bfa_ioc *ioc)
+{
+ struct list_head *qe;
+ struct bfa_ioc_hbfail_notify *notify;
+
+ /**
+ * Mark IOC as failed in hardware and stop firmware.
+ */
+ bfa_ioc_lpu_stop(ioc);
+ bfa_reg_write(ioc->ioc_regs.ioc_fwstate, BFI_IOC_FAIL);
+
+ /**
+ * Notify other functions on HB failure.
+ */
+ bfa_ioc_notify_hbfail(ioc);
+
+ /**
+ * Notify driver and common modules registered for notification.
+ */
+ ioc->cbfn->hbfail_cbfn(ioc->bfa);
+ list_for_each(qe, &ioc->hb_notify_q) {
+ notify = (struct bfa_ioc_hbfail_notify *) qe;
+ notify->cbfn(notify->cbarg);
+ }
+
+ /**
+ * Flush any queued up mailbox requests.
+ */
+ bfa_ioc_mbox_hbfail(ioc);
+
+ /**
+ * Trigger auto-recovery after a delay.
+ */
+ if (ioc->auto_recover) {
+ bfa_timer_begin(ioc->timer_mod, &ioc->ioc_timer,
+ bfa_ioc_timeout, ioc, BFA_IOC_TOV_RECOVER);
+ }
+}
+
+/**
+ * IOC heartbeat failure.
+ */
+static void
+bfa_ioc_sm_hbfail(struct bfa_ioc *ioc, enum ioc_event event)
+{
+
+ switch (event) {
+
+ case IOC_E_ENABLE:
+ ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
+ break;
+
+ case IOC_E_DISABLE:
+ if (ioc->auto_recover)
+ bfa_ioc_timer_stop(ioc);
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+ break;
+
+ case IOC_E_TIMEOUT:
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_semwait);
+ break;
+
+ case IOC_E_FWREADY:
+ /**
+ * Recovery is already initiated by other function.
+ */
+ break;
+
+ case IOC_E_HWERROR:
+ /*
+ * HB failure notification, ignore.
+ */
+ break;
+ default:
+ bfa_sm_fault(ioc, event);
+ }
+}
+
+
+
+/**
+ * hal_ioc_pvt BFA IOC private functions
+ */
+
+static void
+bfa_ioc_disable_comp(struct bfa_ioc *ioc)
+{
+ struct list_head *qe;
+ struct bfa_ioc_hbfail_notify *notify;
+
+ ioc->cbfn->disable_cbfn(ioc->bfa);
+
+ /**
+ * Notify common modules registered for notification.
+ */
+ list_for_each(qe, &ioc->hb_notify_q) {
+ notify = (struct bfa_ioc_hbfail_notify *) qe;
+ notify->cbfn(notify->cbarg);
+ }
+}
+
+void
+bfa_ioc_sem_timeout(void *ioc_arg)
+{
+ struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
+
+ bfa_ioc_hw_sem_get(ioc);
+}
+
+bool
+bfa_ioc_sem_get(bfa_addr_t sem_reg)
+{
+ u32 r32;
+ int cnt = 0;
+#define BFA_SEM_SPINCNT 3000
+
+ r32 = bfa_reg_read(sem_reg);
+
+ while (r32 && (cnt < BFA_SEM_SPINCNT)) {
+ cnt++;
+ udelay(2);
+ r32 = bfa_reg_read(sem_reg);
+ }
+
+ if (r32 == 0)
+ return true;
+
+ bfa_assert(cnt < BFA_SEM_SPINCNT);
+ return false;
+}
+
+void
+bfa_ioc_sem_release(bfa_addr_t sem_reg)
+{
+ bfa_reg_write(sem_reg, 1);
+}
+
+static void
+bfa_ioc_hw_sem_get(struct bfa_ioc *ioc)
+{
+ u32 r32;
+
+ /**
+ * First read to the semaphore register will return 0, subsequent reads
+ * will return 1. Semaphore is released by writing 1 to the register
+ */
+ r32 = bfa_reg_read(ioc->ioc_regs.ioc_sem_reg);
+ if (r32 == 0) {
+ bfa_fsm_send_event(ioc, IOC_E_SEMLOCKED);
+ return;
+ }
+
+ bfa_timer_begin(ioc->timer_mod, &ioc->sem_timer, bfa_ioc_sem_timeout,
+ ioc, BFA_IOC_HWSEM_TOV);
+}
+
+void
+bfa_ioc_hw_sem_release(struct bfa_ioc *ioc)
+{
+ bfa_reg_write(ioc->ioc_regs.ioc_sem_reg, 1);
+}
+
+static void
+bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc)
+{
+ bfa_timer_stop(&ioc->sem_timer);
+}
+
+/**
+ * Initialize LPU local memory (aka secondary memory / SRAM)
+ */
+static void
+bfa_ioc_lmem_init(struct bfa_ioc *ioc)
+{
+ u32 pss_ctl;
+ int i;
+#define PSS_LMEM_INIT_TIME 10000
+
+ pss_ctl = bfa_reg_read(ioc->ioc_regs.pss_ctl_reg);
+ pss_ctl &= ~__PSS_LMEM_RESET;
+ pss_ctl |= __PSS_LMEM_INIT_EN;
+
+ /*
+ * i2c workaround 12.5khz clock
+ */
+ pss_ctl |= __PSS_I2C_CLK_DIV(3UL);
+ bfa_reg_write(ioc->ioc_regs.pss_ctl_reg, pss_ctl);
+
+ /**
+ * wait for memory initialization to be complete
+ */
+ i = 0;
+ do {
+ pss_ctl = bfa_reg_read(ioc->ioc_regs.pss_ctl_reg);
+ i++;
+ } while (!(pss_ctl & __PSS_LMEM_INIT_DONE) && (i < PSS_LMEM_INIT_TIME));
+
+ /**
+ * If memory initialization is not successful, IOC timeout will catch
+ * such failures.
+ */
+ bfa_assert(pss_ctl & __PSS_LMEM_INIT_DONE);
+
+ pss_ctl &= ~(__PSS_LMEM_INIT_DONE | __PSS_LMEM_INIT_EN);
+ bfa_reg_write(ioc->ioc_regs.pss_ctl_reg, pss_ctl);
+}
+
+static void
+bfa_ioc_lpu_start(struct bfa_ioc *ioc)
+{
+ u32 pss_ctl;
+
+ /**
+ * Take processor out of reset.
+ */
+ pss_ctl = bfa_reg_read(ioc->ioc_regs.pss_ctl_reg);
+ pss_ctl &= ~__PSS_LPU0_RESET;
+
+ bfa_reg_write(ioc->ioc_regs.pss_ctl_reg, pss_ctl);
+}
+
+static void
+bfa_ioc_lpu_stop(struct bfa_ioc *ioc)
+{
+ u32 pss_ctl;
+
+ /**
+ * Put processors in reset.
+ */
+ pss_ctl = bfa_reg_read(ioc->ioc_regs.pss_ctl_reg);
+ pss_ctl |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET);
+
+ bfa_reg_write(ioc->ioc_regs.pss_ctl_reg, pss_ctl);
+}
+
+/**
+ * Get driver and firmware versions.
+ */
+void
+bfa_ioc_fwver_get(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
+{
+ u32 pgnum, pgoff;
+ u32 loff = 0;
+ int i;
+ u32 *fwsig = (u32 *) fwhdr;
+
+ pgnum = bfa_ioc_smem_pgnum(ioc, loff);
+ pgoff = bfa_ioc_smem_pgoff(ioc, loff);
+ bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum);
+
+ for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32));
+ i++) {
+ fwsig[i] =
+ bfa_mem_read(ioc->ioc_regs.smem_page_start, loff);
+ loff += sizeof(u32);
+ }
+}
+
+/**
+ * Returns TRUE if same.
+ */
+bool
+bfa_ioc_fwver_cmp(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
+{
+ struct bfi_ioc_image_hdr *drv_fwhdr;
+ int i;
+
+ drv_fwhdr =
+ (struct bfi_ioc_image_hdr *) bfa_ioc_fwimg_get_chunk(ioc, 0);
+
+ for (i = 0; i < BFI_IOC_MD5SUM_SZ; i++) {
+ if (fwhdr->md5sum[i] != drv_fwhdr->md5sum[i])
+ return false;
+ }
+
+ return true;
+}
+
+/**
+ * Return true if current running version is valid. Firmware signature and
+ * execution context (driver/bios) must match.
+ */
+static bool
+bfa_ioc_fwver_valid(struct bfa_ioc *ioc)
+{
+ struct bfi_ioc_image_hdr fwhdr, *drv_fwhdr;
+
+ /**
+ * If bios/efi boot (flash based) -- return true
+ */
+ if (bfa_ioc_fwimg_get_size(ioc) < BFA_IOC_FWIMG_MINSZ)
+ return true;
+
+ bfa_ioc_fwver_get(ioc, &fwhdr);
+ drv_fwhdr =
+ (struct bfi_ioc_image_hdr *) bfa_ioc_fwimg_get_chunk(ioc, 0);
+
+ if (fwhdr.signature != drv_fwhdr->signature)
+ return false;
+
+ if (fwhdr.exec != drv_fwhdr->exec)
+ return false;
+
+ return bfa_ioc_fwver_cmp(ioc, &fwhdr);
+}
+
+/**
+ * Conditionally flush any pending message from firmware at start.
+ */
+static void
+bfa_ioc_msgflush(struct bfa_ioc *ioc)
+{
+ u32 r32;
+
+ r32 = bfa_reg_read(ioc->ioc_regs.lpu_mbox_cmd);
+ if (r32)
+ bfa_reg_write(ioc->ioc_regs.lpu_mbox_cmd, 1);
+}
+
+
+static void
+bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force)
+{
+ enum bfi_ioc_state ioc_fwstate;
+ bool fwvalid;
+
+ ioc_fwstate = bfa_reg_read(ioc->ioc_regs.ioc_fwstate);
+
+ if (force)
+ ioc_fwstate = BFI_IOC_UNINIT;
+
+
+ /**
+ * check if firmware is valid
+ */
+ fwvalid = (ioc_fwstate == BFI_IOC_UNINIT) ?
+ false : bfa_ioc_fwver_valid(ioc);
+
+ if (!fwvalid) {
+ bfa_ioc_boot(ioc, BFI_BOOT_TYPE_NORMAL, ioc->pcidev.device_id);
+ return;
+ }
+
+ /**
+ * If hardware initialization is in progress (initialized by other IOC),
+ * just wait for an initialization completion interrupt.
+ */
+ if (ioc_fwstate == BFI_IOC_INITING) {
+ ioc->cbfn->reset_cbfn(ioc->bfa);
+ return;
+ }
+
+ /**
+ * If IOC function is disabled and firmware version is same,
+ * just re-enable IOC.
+ */
+ if (ioc_fwstate == BFI_IOC_DISABLED || ioc_fwstate == BFI_IOC_OP) {
+
+ /**
+ * When using MSI-X any pending firmware ready event should
+ * be flushed. Otherwise MSI-X interrupts are not delivered.
+ */
+ bfa_ioc_msgflush(ioc);
+ ioc->cbfn->reset_cbfn(ioc->bfa);
+ bfa_fsm_send_event(ioc, IOC_E_FWREADY);
+ return;
+ }
+
+ /**
+ * Initialize the h/w for any other states.
+ */
+ bfa_ioc_boot(ioc, BFI_BOOT_TYPE_NORMAL, ioc->pcidev.device_id);
+}
+
+static void
+bfa_ioc_timeout(void *ioc_arg)
+{
+ struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
+
+ bfa_fsm_send_event(ioc, IOC_E_TIMEOUT);
+}
+
+void
+bfa_ioc_mbox_send(struct bfa_ioc *ioc, void *ioc_msg, int len)
+{
+ u32 *msgp = (u32 *) ioc_msg;
+ u32 i;
+
+
+ bfa_assert(len <= BFI_IOC_MSGLEN_MAX);
+
+ /*
+ * first write msg to mailbox registers
+ */
+ for (i = 0; i < len / sizeof(u32); i++)
+ bfa_reg_write(ioc->ioc_regs.hfn_mbox + i * sizeof(u32),
+ bfa_wtole(msgp[i]));
+
+ for (; i < BFI_IOC_MSGLEN_MAX / sizeof(u32); i++)
+ bfa_reg_write(ioc->ioc_regs.hfn_mbox + i * sizeof(u32), 0);
+
+ /*
+ * write 1 to mailbox CMD to trigger LPU event
+ */
+ bfa_reg_write(ioc->ioc_regs.hfn_mbox_cmd, 1);
+ (void) bfa_reg_read(ioc->ioc_regs.hfn_mbox_cmd);
+}
+
+static void
+bfa_ioc_send_enable(struct bfa_ioc *ioc)
+{
+ struct bfi_ioc_ctrl_req enable_req;
+
+ bfi_h2i_set(enable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_ENABLE_REQ,
+ bfa_ioc_portid(ioc));
+ enable_req.ioc_class = ioc->ioc_mc;
+ bfa_ioc_mbox_send(ioc, &enable_req, sizeof(struct bfi_ioc_ctrl_req));
+}
+
+static void
+bfa_ioc_send_disable(struct bfa_ioc *ioc)
+{
+ struct bfi_ioc_ctrl_req disable_req;
+
+ bfi_h2i_set(disable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_DISABLE_REQ,
+ bfa_ioc_portid(ioc));
+ bfa_ioc_mbox_send(ioc, &disable_req, sizeof(struct bfi_ioc_ctrl_req));
+}
+
+static void
+bfa_ioc_send_getattr(struct bfa_ioc *ioc)
+{
+ struct bfi_ioc_getattr_req attr_req;
+
+ bfi_h2i_set(attr_req.mh, BFI_MC_IOC, BFI_IOC_H2I_GETATTR_REQ,
+ bfa_ioc_portid(ioc));
+ bfa_dma_be_addr_set(attr_req.attr_addr, ioc->attr_dma.pa);
+ bfa_ioc_mbox_send(ioc, &attr_req, sizeof(attr_req));
+}
+
+static void
+bfa_ioc_hb_check(void *cbarg)
+{
+ struct bfa_ioc *ioc = cbarg;
+ u32 hb_count;
+
+ hb_count = bfa_reg_read(ioc->ioc_regs.heartbeat);
+ if (ioc->hb_count == hb_count) {
+
+ DPRINTK(CRIT, "Firmware heartbeat failure at %d", hb_count);
+ bfa_ioc_recover(ioc);
+ return;
+ } else {
+ ioc->hb_count = hb_count;
+ }
+
+ bfa_ioc_mbox_poll(ioc);
+ bfa_timer_begin(ioc->timer_mod, &ioc->ioc_timer, bfa_ioc_hb_check,
+ ioc, BFA_IOC_HB_TOV);
+}
+
+static void
+bfa_ioc_hb_monitor(struct bfa_ioc *ioc)
+{
+ ioc->hb_count = bfa_reg_read(ioc->ioc_regs.heartbeat);
+ bfa_timer_begin(ioc->timer_mod, &ioc->ioc_timer, bfa_ioc_hb_check,
+ ioc, BFA_IOC_HB_TOV);
+}
+
+static void
+bfa_ioc_hb_stop(struct bfa_ioc *ioc)
+{
+ bfa_timer_stop(&ioc->ioc_timer);
+}
+
+
+/**
+ * Initiate a full firmware download.
+ */
+static void
+bfa_ioc_download_fw(struct bfa_ioc *ioc, u32 boot_type,
+ u32 boot_param)
+{
+ u32 *fwimg;
+ u32 pgnum, pgoff;
+ u32 loff = 0;
+ u32 chunkno = 0;
+ u32 i;
+
+ /**
+ * Initialize LMEM first before code download
+ */
+ bfa_ioc_lmem_init(ioc);
+
+ /**
+ * Flash based firmware boot
+ */
+ if (bfa_ioc_fwimg_get_size(ioc) < BFA_IOC_FWIMG_MINSZ)
+ boot_type = BFI_BOOT_TYPE_FLASH;
+ fwimg = bfa_ioc_fwimg_get_chunk(ioc, chunkno);
+
+ pgnum = bfa_ioc_smem_pgnum(ioc, loff);
+ pgoff = bfa_ioc_smem_pgoff(ioc, loff);
+
+ bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum);
+
+ for (i = 0; i < bfa_ioc_fwimg_get_size(ioc); i++) {
+
+ if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) {
+ chunkno = BFA_IOC_FLASH_CHUNK_NO(i);
+ fwimg = bfa_ioc_fwimg_get_chunk(ioc,
+ BFA_IOC_FLASH_CHUNK_ADDR(chunkno));
+ }
+
+ /**
+ * write smem
+ */
+ bfa_mem_write(ioc->ioc_regs.smem_page_start, loff,
+ fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)]);
+
+ loff += sizeof(u32);
+
+ /**
+ * handle page offset wrap around
+ */
+ loff = PSS_SMEM_PGOFF(loff);
+ if (loff == 0) {
+ pgnum++;
+ bfa_reg_write(ioc->ioc_regs.host_page_num_fn,
+ pgnum);
+ }
+ }
+
+ bfa_reg_write(ioc->ioc_regs.host_page_num_fn,
+ bfa_ioc_smem_pgnum(ioc, 0));
+
+ /*
+ * Set boot type and boot param at the end.
+ */
+ bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_TYPE_OFF,
+ bfa_swap32(boot_type));
+ bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_PARAM_OFF,
+ bfa_swap32(boot_param));
+}
+
+static void
+bfa_ioc_reset(struct bfa_ioc *ioc, bool force)
+{
+ bfa_ioc_hwinit(ioc, force);
+}
+
+/**
+ * Update BFA configuration from firmware configuration.
+ */
+static void
+bfa_ioc_getattr_reply(struct bfa_ioc *ioc)
+{
+ struct bfi_ioc_attr *attr = ioc->attr;
+
+ attr->adapter_prop = ntohl(attr->adapter_prop);
+ attr->maxfrsize = ntohs(attr->maxfrsize);
+
+ bfa_fsm_send_event(ioc, IOC_E_FWRSP_GETATTR);
+}
+
+/**
+ * Attach time initialization of mbox logic.
+ */
+static void
+bfa_ioc_mbox_attach(struct bfa_ioc *ioc)
+{
+ struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
+ int mc;
+
+ INIT_LIST_HEAD(&mod->cmd_q);
+ for (mc = 0; mc < BFI_MC_MAX; mc++) {
+ mod->mbhdlr[mc].cbfn = NULL;
+ mod->mbhdlr[mc].cbarg = ioc->bfa;
+ }
+}
+
+/**
+ * Mbox poll timer -- restarts any pending mailbox requests.
+ */
+static void
+bfa_ioc_mbox_poll(struct bfa_ioc *ioc)
+{
+ struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
+ struct bfa_mbox_cmd *cmd;
+ u32 stat;
+
+ /**
+ * If no command pending, do nothing
+ */
+ if (list_empty(&mod->cmd_q))
+ return;
+
+ /**
+ * If previous command is not yet fetched by firmware, do nothing
+ */
+ stat = bfa_reg_read(ioc->ioc_regs.hfn_mbox_cmd);
+ if (stat)
+ return;
+
+ /**
+ * Enqueue command to firmware.
+ */
+ bfa_q_deq(&mod->cmd_q, &cmd);
+ bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
+}
+
+/**
+ * Cleanup any pending requests.
+ */
+static void
+bfa_ioc_mbox_hbfail(struct bfa_ioc *ioc)
+{
+ struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
+ struct bfa_mbox_cmd *cmd;
+
+ while (!list_empty(&mod->cmd_q))
+ bfa_q_deq(&mod->cmd_q, &cmd);
+}
+
+
+
+/**
+ * hal_ioc_public
+ */
+
+/**
+ * Interface used by diag module to do firmware boot with memory test
+ * as the entry vector.
+ */
+void
+bfa_ioc_boot(struct bfa_ioc *ioc, u32 boot_type, u32 boot_param)
+{
+ bfa_addr_t rb;
+
+ bfa_ioc_stats(ioc, ioc_boots);
+
+ if (bfa_ioc_pll_init(ioc) != BFA_STATUS_OK)
+ return;
+
+ /**
+ * Initialize IOC state of all functions on a chip reset.
+ */
+ rb = ioc->pcidev.pci_bar_kva;
+ if (boot_param == BFI_BOOT_TYPE_MEMTEST) {
+ bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_MEMTEST);
+ bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_MEMTEST);
+ } else {
+ bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_INITING);
+ bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_INITING);
+ }
+
+ bfa_ioc_download_fw(ioc, boot_type, boot_param);
+
+ /**
+ * Enable interrupts just before starting LPU
+ */
+ ioc->cbfn->reset_cbfn(ioc->bfa);
+ bfa_ioc_lpu_start(ioc);
+}
+
+/**
+ * Enable/disable IOC failure auto recovery.
+ */
+void
+bfa_ioc_auto_recover(bool auto_recover)
+{
+ bfa_auto_recover = auto_recover;
+}
+
+
+
+bool
+bfa_ioc_is_operational(struct bfa_ioc *ioc)
+{
+ return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_op);
+}
+
+void
+bfa_ioc_msgget(struct bfa_ioc *ioc, void *mbmsg)
+{
+ u32 *msgp = mbmsg;
+ u32 r32;
+ int i;
+
+ /**
+ * read the MBOX msg
+ */
+ for (i = 0; i < (sizeof(union bfi_ioc_i2h_msg_u) / sizeof(u32));
+ i++) {
+ r32 = bfa_reg_read(ioc->ioc_regs.lpu_mbox +
+ i * sizeof(u32));
+ msgp[i] = htonl(r32);
+ }
+
+ /**
+ * turn off mailbox interrupt by clearing mailbox status
+ */
+ bfa_reg_write(ioc->ioc_regs.lpu_mbox_cmd, 1);
+ bfa_reg_read(ioc->ioc_regs.lpu_mbox_cmd);
+}
+
+void
+bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *m)
+{
+ union bfi_ioc_i2h_msg_u *msg;
+
+ msg = (union bfi_ioc_i2h_msg_u *) m;
+
+ bfa_ioc_stats(ioc, ioc_isrs);
+
+ switch (msg->mh.msg_id) {
+ case BFI_IOC_I2H_HBEAT:
+ break;
+
+ case BFI_IOC_I2H_READY_EVENT:
+ bfa_fsm_send_event(ioc, IOC_E_FWREADY);
+ break;
+
+ case BFI_IOC_I2H_ENABLE_REPLY:
+ bfa_fsm_send_event(ioc, IOC_E_FWRSP_ENABLE);
+ break;
+
+ case BFI_IOC_I2H_DISABLE_REPLY:
+ bfa_fsm_send_event(ioc, IOC_E_FWRSP_DISABLE);
+ break;
+
+ case BFI_IOC_I2H_GETATTR_REPLY:
+ bfa_ioc_getattr_reply(ioc);
+ break;
+
+ default:
+ bfa_assert(0);
+ }
+}
+
+/**
+ * IOC attach time initialization and setup.
+ *
+ * @param[in] ioc memory for IOC
+ * @param[in] bfa driver instance structure
+ * @param[in] trcmod kernel trace module
+ * @param[in] aen kernel aen event module
+ * @param[in] logm kernel logging module
+ */
+void
+bfa_ioc_attach(struct bfa_ioc *ioc, void *bfa, struct bfa_ioc_cbfn *cbfn,
+ struct bfa_timer_mod *timer_mod, struct bfa_trc_mod *trcmod,
+ struct bfa_aen *aen, struct bfa_log_mod *logm)
+{
+ ioc->bfa = bfa;
+ ioc->cbfn = cbfn;
+ ioc->timer_mod = timer_mod;
+ ioc->trcmod = trcmod;
+ ioc->aen = aen;
+ ioc->logm = logm;
+ ioc->fcmode = false;
+ ioc->pllinit = false;
+ ioc->dbg_fwsave_once = true;
+
+ bfa_ioc_mbox_attach(ioc);
+ INIT_LIST_HEAD(&ioc->hb_notify_q);
+
+ bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+}
+
+/**
+ * Driver detach time IOC cleanup.
+ */
+void
+bfa_ioc_detach(struct bfa_ioc *ioc)
+{
+ bfa_fsm_send_event(ioc, IOC_E_DETACH);
+}
+
+/**
+ * Setup IOC PCI properties.
+ *
+ * @param[in] pcidev PCI device information for this IOC
+ */
+void
+bfa_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
+ enum bfi_mclass mc)
+{
+ ioc->ioc_mc = mc;
+ ioc->pcidev = *pcidev;
+ ioc->ctdev = (ioc->pcidev.device_id == BFA_PCI_DEVICE_ID_CT);
+ ioc->cna = ioc->ctdev && !ioc->fcmode;
+
+ /**
+ * Set asic specific interfaces. See bfa_ioc_cb.c and bfa_ioc_ct.c
+ */
+ bfa_ioc_set_ct_hwif(ioc);
+
+
+ bfa_ioc_map_port(ioc);
+ bfa_ioc_reg_init(ioc);
+}
+
+/**
+ * Initialize IOC dma memory
+ *
+ * @param[in] dm_kva kernel virtual address of IOC dma memory
+ * @param[in] dm_pa physical address of IOC dma memory
+ */
+void
+bfa_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa)
+{
+ /**
+ * dma memory for firmware attribute
+ */
+ ioc->attr_dma.kva = dm_kva;
+ ioc->attr_dma.pa = dm_pa;
+ ioc->attr = (struct bfi_ioc_attr *) dm_kva;
+}
+
+/**
+ * Return size of dma memory required.
+ */
+u32
+bfa_ioc_meminfo(void)
+{
+ return BFA_ROUNDUP(sizeof(struct bfi_ioc_attr), BFA_DMA_ALIGN_SZ);
+}
+
+void
+bfa_ioc_enable(struct bfa_ioc *ioc)
+{
+ bfa_ioc_stats(ioc, ioc_enables);
+ ioc->dbg_fwsave_once = true;
+
+ bfa_fsm_send_event(ioc, IOC_E_ENABLE);
+}
+
+void
+bfa_ioc_disable(struct bfa_ioc *ioc)
+{
+ bfa_ioc_stats(ioc, ioc_disables);
+ bfa_fsm_send_event(ioc, IOC_E_DISABLE);
+}
+
+/**
+ * Returns memory required for saving firmware trace in case of crash.
+ * Driver must call this interface to allocate memory required for
+ * automatic saving of firmware trace. Driver should call
+ * bfa_ioc_debug_memclaim() right after bfa_ioc_attach() to setup this
+ * trace memory.
+ */
+int
+bfa_ioc_debug_trcsz(bool auto_recover)
+{
+ return (auto_recover) ? BFA_DBG_FWTRC_LEN : 0;
+}
+
+/**
+ * Initialize memory for saving firmware trace. Driver must initialize
+ * trace memory before call bfa_ioc_enable().
+ */
+void
+bfa_ioc_debug_memclaim(struct bfa_ioc *ioc, void *dbg_fwsave)
+{
+ ioc->dbg_fwsave = dbg_fwsave;
+ ioc->dbg_fwsave_len = bfa_ioc_debug_trcsz(ioc->auto_recover);
+}
+
+u32
+bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr)
+{
+ return PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, fmaddr);
+}
+
+u32
+bfa_ioc_smem_pgoff(struct bfa_ioc *ioc, u32 fmaddr)
+{
+ return PSS_SMEM_PGOFF(fmaddr);
+}
+
+/**
+ * Register mailbox message handler functions
+ *
+ * @param[in] ioc IOC instance
+ * @param[in] mcfuncs message class handler functions
+ */
+void
+bfa_ioc_mbox_register(struct bfa_ioc *ioc, bfa_ioc_mbox_mcfunc_t *mcfuncs)
+{
+ struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
+ int mc;
+
+ for (mc = 0; mc < BFI_MC_MAX; mc++)
+ mod->mbhdlr[mc].cbfn = mcfuncs[mc];
+}
+
+/**
+ * Register mailbox message handler function, to be called by common modules
+ */
+void
+bfa_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
+ bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg)
+{
+ struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
+
+ mod->mbhdlr[mc].cbfn = cbfn;
+ mod->mbhdlr[mc].cbarg = cbarg;
+}
+
+/**
+ * Queue a mailbox command request to firmware. Waits if mailbox is busy.
+ * Responsibility of caller to serialize
+ *
+ * @param[in] ioc IOC instance
+ * @param[i] cmd Mailbox command
+ */
+void
+bfa_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd)
+{
+ struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
+ u32 stat;
+
+ /**
+ * If a previous command is pending, queue new command
+ */
+ if (!list_empty(&mod->cmd_q)) {
+ list_add_tail(&cmd->qe, &mod->cmd_q);
+ return;
+ }
+
+ /**
+ * If mailbox is busy, queue command for poll timer
+ */
+ stat = bfa_reg_read(ioc->ioc_regs.hfn_mbox_cmd);
+ if (stat) {
+ list_add_tail(&cmd->qe, &mod->cmd_q);
+ return;
+ }
+
+ /**
+ * mailbox is free -- queue command to firmware
+ */
+ bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
+}
+
+/**
+ * Handle mailbox interrupts
+ */
+void
+bfa_ioc_mbox_isr(struct bfa_ioc *ioc)
+{
+ struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
+ struct bfi_mbmsg m;
+ int mc;
+
+ bfa_ioc_msgget(ioc, &m);
+
+ /**
+ * Treat IOC message class as special.
+ */
+ mc = m.mh.msg_class;
+ if (mc == BFI_MC_IOC) {
+ bfa_ioc_isr(ioc, &m);
+ return;
+ }
+
+ if ((mc > BFI_MC_MAX) || (mod->mbhdlr[mc].cbfn == NULL)) {
+ bfa_assert(0);
+ bfa_trc_stop(ioc->trcmod);
+ return;
+ }
+
+ mod->mbhdlr[mc].cbfn(mod->mbhdlr[mc].cbarg, &m);
+}
+
+void
+bfa_ioc_error_isr(struct bfa_ioc *ioc)
+{
+ bfa_fsm_send_event(ioc, IOC_E_HWERROR);
+}
+
+#ifndef BFA_BIOS_BUILD
+
+/**
+ * return true if IOC is disabled
+ */
+bool
+bfa_ioc_is_disabled(struct bfa_ioc *ioc)
+{
+ return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabling) ||
+ bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled);
+}
+
+/**
+ * return true if IOC firmware is different.
+ */
+bool
+bfa_ioc_fw_mismatch(struct bfa_ioc *ioc)
+{
+ return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_reset) ||
+ bfa_fsm_cmp_state(ioc, bfa_ioc_sm_fwcheck) ||
+ bfa_fsm_cmp_state(ioc, bfa_ioc_sm_mismatch);
+}
+
+#define bfa_ioc_state_disabled(__sm) \
+ (((__sm) == BFI_IOC_UNINIT) || \
+ ((__sm) == BFI_IOC_INITING) || \
+ ((__sm) == BFI_IOC_HWINIT) || \
+ ((__sm) == BFI_IOC_DISABLED) || \
+ ((__sm) == BFI_IOC_FAIL) || \
+ ((__sm) == BFI_IOC_CFG_DISABLED))
+
+/**
+ * Check if adapter is disabled -- both IOCs should be in a disabled
+ * state.
+ */
+bool
+bfa_ioc_adapter_is_disabled(struct bfa_ioc *ioc)
+{
+ u32 ioc_state;
+ bfa_addr_t rb = ioc->pcidev.pci_bar_kva;
+
+ if (!bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled))
+ return false;
+
+ ioc_state = bfa_reg_read(rb + BFA_IOC0_STATE_REG);
+ if (!bfa_ioc_state_disabled(ioc_state))
+ return false;
+
+ ioc_state = bfa_reg_read(rb + BFA_IOC1_STATE_REG);
+ if (!bfa_ioc_state_disabled(ioc_state))
+ return false;
+
+ return true;
+}
+
+/**
+ * Add to IOC heartbeat failure notification queue. To be used by common
+ * modules such as cee, port, diag.
+ */
+void
+bfa_ioc_hbfail_register(struct bfa_ioc *ioc,
+ struct bfa_ioc_hbfail_notify *notify)
+{
+ list_add_tail(¬ify->qe, &ioc->hb_notify_q);
+}
+
+#define BFA_MFG_NAME "Brocade"
+void
+bfa_ioc_get_adapter_attr(struct bfa_ioc *ioc,
+ struct bfa_adapter_attr *ad_attr)
+{
+ struct bfi_ioc_attr *ioc_attr;
+
+ ioc_attr = ioc->attr;
+
+ bfa_ioc_get_adapter_serial_num(ioc, ad_attr->serial_num);
+ bfa_ioc_get_adapter_fw_ver(ioc, ad_attr->fw_ver);
+ bfa_ioc_get_adapter_optrom_ver(ioc, ad_attr->optrom_ver);
+ bfa_ioc_get_adapter_manufacturer(ioc, ad_attr->manufacturer);
+ memcpy(&ad_attr->vpd, &ioc_attr->vpd,
+ sizeof(struct bfa_mfg_vpd));
+
+ ad_attr->nports = bfa_ioc_get_nports(ioc);
+ ad_attr->max_speed = bfa_ioc_speed_sup(ioc);
+
+ bfa_ioc_get_adapter_model(ioc, ad_attr->model);
+ /* For now, model descr uses same model string */
+ bfa_ioc_get_adapter_model(ioc, ad_attr->model_descr);
+
+ if (BFI_ADAPTER_IS_SPECIAL(ioc_attr->adapter_prop))
+ ad_attr->prototype = 1;
+ else
+ ad_attr->prototype = 0;
+
+ ad_attr->pwwn = bfa_ioc_get_pwwn(ioc);
+ ad_attr->mac = bfa_ioc_get_mac(ioc);
+
+ ad_attr->pcie_gen = ioc_attr->pcie_gen;
+ ad_attr->pcie_lanes = ioc_attr->pcie_lanes;
+ ad_attr->pcie_lanes_orig = ioc_attr->pcie_lanes_orig;
+ ad_attr->asic_rev = ioc_attr->asic_rev;
+
+ bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver);
+
+ ad_attr->cna_capable = ioc->cna;
+}
+
+enum bfa_ioc_type_e
+bfa_ioc_get_type(struct bfa_ioc *ioc)
+{
+ if (!ioc->ctdev || ioc->fcmode)
+ return BFA_IOC_TYPE_FC;
+ else if (ioc->ioc_mc == BFI_MC_IOCFC)
+ return BFA_IOC_TYPE_FCoE;
+ else if (ioc->ioc_mc == BFI_MC_LL)
+ return BFA_IOC_TYPE_LL;
+ else {
+ bfa_assert(ioc->ioc_mc == BFI_MC_LL);
+ return BFA_IOC_TYPE_LL;
+ }
+}
+
+void
+bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, char *serial_num)
+{
+ memset((void *)serial_num, 0, BFA_ADAPTER_SERIAL_NUM_LEN);
+ memcpy((void *)serial_num,
+ (void *)ioc->attr->brcd_serialnum,
+ BFA_ADAPTER_SERIAL_NUM_LEN);
+}
+
+void
+bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc, char *fw_ver)
+{
+ memset((void *)fw_ver, 0, BFA_VERSION_LEN);
+ memcpy(fw_ver, ioc->attr->fw_version, BFA_VERSION_LEN);
+}
+
+void
+bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc, char *chip_rev)
+{
+ bfa_assert(chip_rev);
+
+ memset((void *)chip_rev, 0, BFA_IOC_CHIP_REV_LEN);
+
+ chip_rev[0] = 'R';
+ chip_rev[1] = 'e';
+ chip_rev[2] = 'v';
+ chip_rev[3] = '-';
+ chip_rev[4] = ioc->attr->asic_rev;
+ chip_rev[5] = '\0';
+}
+
+void
+bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc, char *optrom_ver)
+{
+ memset((void *)optrom_ver, 0, BFA_VERSION_LEN);
+ memcpy(optrom_ver, ioc->attr->optrom_version,
+ BFA_VERSION_LEN);
+}
+
+void
+bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc, char *manufacturer)
+{
+ memset((void *)manufacturer, 0, BFA_ADAPTER_MFG_NAME_LEN);
+ memcpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN);
+}
+
+void
+bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model)
+{
+ struct bfi_ioc_attr *ioc_attr;
+ u8 nports;
+ u8 max_speed;
+
+ bfa_assert(model);
+ memset((void *)model, 0, BFA_ADAPTER_MODEL_NAME_LEN);
+
+ ioc_attr = ioc->attr;
+
+ nports = bfa_ioc_get_nports(ioc);
+ max_speed = bfa_ioc_speed_sup(ioc);
+
+ /**
+ * model name
+ */
+ if (max_speed == 10) {
+ strcpy(model, "BR-10?0");
+ model[5] = '0' + nports;
+ } else {
+ strcpy(model, "Brocade-??5");
+ model[8] = '0' + max_speed;
+ model[9] = '0' + nports;
+ }
+}
+
+enum bfa_ioc_state
+bfa_ioc_get_state(struct bfa_ioc *ioc)
+{
+ return bfa_sm_to_state(ioc_sm_table, ioc->fsm);
+}
+
+void
+bfa_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr)
+{
+ memset((void *)ioc_attr, 0, sizeof(struct bfa_ioc_attr));
+
+ ioc_attr->state = bfa_ioc_get_state(ioc);
+ ioc_attr->port_id = ioc->port_id;
+
+ ioc_attr->ioc_type = bfa_ioc_get_type(ioc);
+
+ bfa_ioc_get_adapter_attr(ioc, &ioc_attr->adapter_attr);
+
+ ioc_attr->pci_attr.device_id = ioc->pcidev.device_id;
+ ioc_attr->pci_attr.pcifn = ioc->pcidev.pci_func;
+ bfa_ioc_get_pci_chip_rev(ioc, ioc_attr->pci_attr.chip_rev);
+}
+
+/**
+ * hal_wwn_public
+ */
+wwn_t
+bfa_ioc_get_pwwn(struct bfa_ioc *ioc)
+{
+ union {
+ wwn_t wwn;
+ u8 byte[sizeof(wwn_t)];
+ } w;
+
+ w.wwn = ioc->attr->mfg_wwn;
+
+ if (bfa_ioc_portid(ioc) == 1)
+ w.byte[7]++;
+
+ return w.wwn;
+}
+
+wwn_t
+bfa_ioc_get_nwwn(struct bfa_ioc *ioc)
+{
+ union {
+ wwn_t wwn;
+ u8 byte[sizeof(wwn_t)];
+ } w;
+
+ w.wwn = ioc->attr->mfg_wwn;
+
+ if (bfa_ioc_portid(ioc) == 1)
+ w.byte[7]++;
+
+ w.byte[0] = 0x20;
+
+ return w.wwn;
+}
+
+wwn_t
+bfa_ioc_get_wwn_naa5(struct bfa_ioc *ioc, u16 inst)
+{
+ union {
+ wwn_t wwn;
+ u8 byte[sizeof(wwn_t)];
+ } w, w5;
+
+
+ w.wwn = ioc->attr->mfg_wwn;
+ w5.byte[0] = 0x50 | w.byte[2] >> 4;
+ w5.byte[1] = w.byte[2] << 4 | w.byte[3] >> 4;
+ w5.byte[2] = w.byte[3] << 4 | w.byte[4] >> 4;
+ w5.byte[3] = w.byte[4] << 4 | w.byte[5] >> 4;
+ w5.byte[4] = w.byte[5] << 4 | w.byte[6] >> 4;
+ w5.byte[5] = w.byte[6] << 4 | w.byte[7] >> 4;
+ w5.byte[6] = w.byte[7] << 4 | (inst & 0x0f00) >> 8;
+ w5.byte[7] = (inst & 0xff);
+
+ return w5.wwn;
+}
+
+u64
+bfa_ioc_get_adid(struct bfa_ioc *ioc)
+{
+ return ioc->attr->mfg_wwn;
+}
+
+struct mac
+bfa_ioc_get_mac(struct bfa_ioc *ioc)
+{
+ struct mac mac;
+
+ mac = ioc->attr->mfg_mac;
+ mac.mac[MAC_ADDRLEN - 1] += bfa_ioc_pcifn(ioc);
+
+ return mac;
+}
+
+void
+bfa_ioc_set_fcmode(struct bfa_ioc *ioc)
+{
+ ioc->fcmode = true;
+ ioc->port_id = bfa_ioc_pcifn(ioc);
+}
+
+bool
+bfa_ioc_get_fcmode(struct bfa_ioc *ioc)
+{
+ return ioc->fcmode || (ioc->pcidev.device_id != BFA_PCI_DEVICE_ID_CT);
+}
+
+/**
+ * Retrieve saved firmware trace from a prior IOC failure.
+ */
+bfa_status_t
+bfa_ioc_debug_fwsave(struct bfa_ioc *ioc, void *trcdata, int *trclen)
+{
+ int tlen;
+
+ if (ioc->dbg_fwsave_len == 0)
+ return BFA_STATUS_ENOFSAVE;
+
+ tlen = *trclen;
+ if (tlen > ioc->dbg_fwsave_len)
+ tlen = ioc->dbg_fwsave_len;
+
+ memcpy(trcdata, ioc->dbg_fwsave, tlen);
+ *trclen = tlen;
+ return BFA_STATUS_OK;
+}
+
+/**
+ * Clear saved firmware trace
+ */
+void
+bfa_ioc_debug_fwsave_clear(struct bfa_ioc *ioc)
+{
+ ioc->dbg_fwsave_once = true;
+}
+
+/**
+ * Retrieve saved firmware trace from a prior IOC failure.
+ */
+bfa_status_t
+bfa_ioc_debug_fwtrc(struct bfa_ioc *ioc, void *trcdata, int *trclen)
+{
+ u32 pgnum;
+ u32 loff = BFA_DBG_FWTRC_OFF(bfa_ioc_portid(ioc));
+ int i, tlen;
+ u32 *tbuf = trcdata, r32;
+
+
+ pgnum = bfa_ioc_smem_pgnum(ioc, loff);
+ loff = bfa_ioc_smem_pgoff(ioc, loff);
+
+ /*
+ * Hold semaphore to serialize pll init and fwtrc.
+ */
+ if (false == bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg))
+ return BFA_STATUS_FAILED;
+
+ bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum);
+
+ tlen = *trclen;
+ if (tlen > BFA_DBG_FWTRC_LEN)
+ tlen = BFA_DBG_FWTRC_LEN;
+ tlen /= sizeof(u32);
+
+
+ for (i = 0; i < tlen; i++) {
+ r32 = bfa_mem_read(ioc->ioc_regs.smem_page_start, loff);
+ tbuf[i] = ntohl(r32);
+ loff += sizeof(u32);
+
+ /**
+ * handle page offset wrap around
+ */
+ loff = PSS_SMEM_PGOFF(loff);
+ if (loff == 0) {
+ pgnum++;
+ bfa_reg_write(ioc->ioc_regs.host_page_num_fn,
+ pgnum);
+ }
+ }
+ bfa_reg_write(ioc->ioc_regs.host_page_num_fn,
+ bfa_ioc_smem_pgnum(ioc, 0));
+
+ /*
+ * release semaphore.
+ */
+ bfa_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg);
+
+
+ *trclen = tlen * sizeof(u32);
+ return BFA_STATUS_OK;
+}
+
+/**
+ * Save firmware trace if configured.
+ */
+static void
+bfa_ioc_debug_save(struct bfa_ioc *ioc)
+{
+ int tlen;
+
+ if (ioc->dbg_fwsave_len) {
+ tlen = ioc->dbg_fwsave_len;
+ bfa_ioc_debug_fwtrc(ioc, ioc->dbg_fwsave, &tlen);
+ }
+}
+
+/**
+ * Firmware failure detected. Start recovery actions.
+ */
+static void
+bfa_ioc_recover(struct bfa_ioc *ioc)
+{
+ if (ioc->dbg_fwsave_once) {
+ ioc->dbg_fwsave_once = false;
+ bfa_ioc_debug_save(ioc);
+ }
+
+ bfa_ioc_stats(ioc, ioc_hbfails);
+ bfa_fsm_send_event(ioc, IOC_E_HBFAIL);
+}
+
+#else
+
+static void
+bfa_ioc_recover(struct bfa_ioc *ioc)
+{
+ bfa_assert(0);
+}
+
+#endif
+
+
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_ioc_ct.c net-next-2.6-mod/drivers/net/bna/bfa_ioc_ct.c
--- net-next-2.6-orig/drivers/net/bna/bfa_ioc_ct.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_ioc_ct.c 2009-11-12 19:03:38.683343000 -0800
@@ -0,0 +1,414 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#include <bfa_ioc.h>
+#include <bfa_fwimg_priv.h>
+#include <cs/bfa_debug.h>
+#include <bfi/bfi_ioc.h>
+#include <bfi/bfi_ctreg.h>
+#include <defs/bfa_defs_pci.h>
+
+
+/*
+ * forward declarations
+ */
+static bfa_status_t bfa_ioc_ct_pll_init(struct bfa_ioc *ioc);
+static bool bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc);
+static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);
+static u32 *bfa_ioc_ct_fwimg_get_chunk(struct bfa_ioc *ioc,
+ u32 off);
+static u32 bfa_ioc_ct_fwimg_get_size(struct bfa_ioc *ioc);
+static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);
+static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);
+static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);
+static void bfa_ioc_ct_notify_hbfail(struct bfa_ioc *ioc);
+static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
+
+struct bfa_ioc_hwif hwif_ct = {
+ bfa_ioc_ct_pll_init,
+ bfa_ioc_ct_firmware_lock,
+ bfa_ioc_ct_firmware_unlock,
+ bfa_ioc_ct_fwimg_get_chunk,
+ bfa_ioc_ct_fwimg_get_size,
+ bfa_ioc_ct_reg_init,
+ bfa_ioc_ct_map_port,
+ bfa_ioc_ct_isr_mode_set,
+ bfa_ioc_ct_notify_hbfail,
+ bfa_ioc_ct_ownership_reset,
+};
+
+/**
+ * Called from bfa_ioc_attach() to map asic specific calls.
+ */
+void
+bfa_ioc_set_ct_hwif(struct bfa_ioc *ioc)
+{
+ ioc->ioc_hwif = &hwif_ct;
+}
+
+static u32 *
+bfa_ioc_ct_fwimg_get_chunk(struct bfa_ioc *ioc, u32 off)
+{
+ return bfi_image_ct_get_chunk(off);
+}
+
+static u32
+bfa_ioc_ct_fwimg_get_size(struct bfa_ioc *ioc)
+{
+ return bfi_image_ct_size;
+}
+
+/**
+ * Return true if firmware of current driver matches the running firmware.
+ */
+static bool
+bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc)
+{
+ enum bfi_ioc_state ioc_fwstate;
+ u32 usecnt;
+ struct bfi_ioc_image_hdr fwhdr;
+
+ /**
+ * Firmware match check is relevant only for CNA.
+ */
+ if (!ioc->cna)
+ return true;
+
+ /**
+ * If bios boot (flash based) -- do not increment usage count
+ */
+ if (bfa_ioc_ct_fwimg_get_size(ioc) < BFA_IOC_FWIMG_MINSZ)
+ return true;
+
+ bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
+ usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg);
+
+ /**
+ * If usage count is 0, always return TRUE.
+ */
+ if (usecnt == 0) {
+ bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 1);
+ bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
+ return true;
+ }
+
+ ioc_fwstate = bfa_reg_read(ioc->ioc_regs.ioc_fwstate);
+
+ /**
+ * Use count cannot be non-zero and chip in uninitialized state.
+ */
+ bfa_assert(ioc_fwstate != BFI_IOC_UNINIT);
+
+ /**
+ * Check if another driver with a different firmware is active
+ */
+ bfa_ioc_fwver_get(ioc, &fwhdr);
+ if (!bfa_ioc_fwver_cmp(ioc, &fwhdr)) {
+ bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
+ return false;
+ }
+
+ /**
+ * Same firmware version. Increment the reference count.
+ */
+ usecnt++;
+ bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt);
+ bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
+ return true;
+}
+
+static void
+bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc)
+{
+ u32 usecnt;
+
+ /**
+ * Firmware lock is relevant only for CNA.
+ * If bios boot (flash based) -- do not decrement usage count
+ */
+ if (!ioc->cna || bfa_ioc_ct_fwimg_get_size(ioc) < BFA_IOC_FWIMG_MINSZ)
+ return;
+
+ /**
+ * decrement usage count
+ */
+ bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
+ usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg);
+ bfa_assert(usecnt > 0);
+
+ usecnt--;
+ bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt);
+
+ bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
+}
+
+/**
+ * Notify other functions on HB failure.
+ */
+static void
+bfa_ioc_ct_notify_hbfail(struct bfa_ioc *ioc)
+{
+ if (ioc->cna) {
+ bfa_reg_write(ioc->ioc_regs.ll_halt, __FW_INIT_HALT_P);
+ /* Wait for halt to take effect */
+ bfa_reg_read(ioc->ioc_regs.ll_halt);
+ } else {
+ bfa_reg_write(ioc->ioc_regs.err_set, __PSS_ERR_STATUS_SET);
+ bfa_reg_read(ioc->ioc_regs.err_set);
+ }
+}
+
+/**
+ * Host to LPU mailbox message addresses
+ */
+static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
+ { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
+ { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
+ { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
+ { HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 }
+};
+
+/**
+ * Host <-> LPU mailbox command/status registers - port 0
+ */
+static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = {
+ { HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT },
+ { HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT },
+ { HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT },
+ { HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT }
+};
+
+/**
+ * Host <-> LPU mailbox command/status registers - port 1
+ */
+static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = {
+ { HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT },
+ { HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT },
+ { HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT },
+ { HOSTFN3_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN3_MBOX0_CMD_STAT }
+};
+
+static void
+bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
+{
+ bfa_addr_t rb;
+ int pcifn = bfa_ioc_pcifn(ioc);
+
+ rb = bfa_ioc_bar0(ioc);
+
+ ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
+ ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
+ ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
+
+ if (ioc->port_id == 0) {
+ ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
+ ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
+ ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn;
+ ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu;
+ ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
+ } else {
+ ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
+ ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
+ ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn;
+ ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu;
+ ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
+ }
+
+ /*
+ * PSS control registers
+ */
+ ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
+ ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
+ ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG);
+ ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG);
+
+ /*
+ * IOC semaphore registers and serialization
+ */
+ ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
+ ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
+ ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
+ ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
+
+ /**
+ * sram memory access
+ */
+ ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
+ ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
+
+ /*
+ * err set reg : for notification of hb failure in fcmode
+ */
+ ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
+}
+
+/**
+ * Initialize IOC to port mapping.
+ */
+
+#define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8)
+static void
+bfa_ioc_ct_map_port(struct bfa_ioc *ioc)
+{
+ bfa_addr_t rb = ioc->pcidev.pci_bar_kva;
+ u32 r32;
+
+ /**
+ * For catapult, base port id on personality register and IOC type
+ */
+ r32 = bfa_reg_read(rb + FNC_PERS_REG);
+ r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
+ ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
+
+}
+
+/**
+ * Set interrupt mode for a function: INTX or MSIX
+ */
+static void
+bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix)
+{
+ bfa_addr_t rb = ioc->pcidev.pci_bar_kva;
+ u32 r32, mode;
+
+ r32 = bfa_reg_read(rb + FNC_PERS_REG);
+
+ mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
+ __F0_INTX_STATUS;
+
+ /**
+ * If already in desired mode, do not change anything
+ */
+ if (!msix && mode)
+ return;
+
+ if (msix)
+ mode = __F0_INTX_STATUS_MSIX;
+ else
+ mode = __F0_INTX_STATUS_INTA;
+
+ r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
+ r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
+
+ bfa_reg_write(rb + FNC_PERS_REG, r32);
+}
+
+static bfa_status_t
+bfa_ioc_ct_pll_init(struct bfa_ioc *ioc)
+{
+ bfa_addr_t rb = ioc->pcidev.pci_bar_kva;
+ u32 pll_sclk, pll_fclk, r32;
+
+ /*
+ * Hold semaphore so that nobody can access the chip during init.
+ */
+ bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg);
+
+ pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST |
+ __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) |
+ __APP_PLL_312_JITLMT0_1(3U) |
+ __APP_PLL_312_CNTLMT0_1(1U);
+ pll_fclk = __APP_PLL_425_LRESETN | __APP_PLL_425_ENARST |
+ __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) |
+ __APP_PLL_425_JITLMT0_1(3U) |
+ __APP_PLL_425_CNTLMT0_1(1U);
+
+ /**
+ * For catapult, choose operational mode FC/FCoE
+ */
+ if (ioc->fcmode) {
+ bfa_reg_write((rb + OP_MODE), 0);
+ bfa_reg_write((rb + ETH_MAC_SER_REG),
+ __APP_EMS_CMLCKSEL |
+ __APP_EMS_REFCKBUFEN2 |
+ __APP_EMS_CHANNEL_SEL);
+ } else {
+ ioc->pllinit = true;
+ bfa_reg_write((rb + OP_MODE), __GLOBAL_FCOE_MODE);
+ bfa_reg_write((rb + ETH_MAC_SER_REG),
+ __APP_EMS_REFCKBUFEN1);
+ }
+
+ bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT);
+ bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT);
+
+ bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU);
+ bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU);
+ bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU);
+ bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU);
+ bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU);
+ bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU);
+
+ bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk |
+ __APP_PLL_312_LOGIC_SOFT_RESET);
+ bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
+ __APP_PLL_425_LOGIC_SOFT_RESET);
+ bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk |
+ __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE);
+ bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
+ __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE);
+
+ /**
+ * Wait for PLLs to lock.
+ */
+ bfa_reg_read(rb + HOSTFN0_INT_MSK);
+ udelay(2000);
+ bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU);
+ bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU);
+
+ bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk |
+ __APP_PLL_312_ENABLE);
+ bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
+ __APP_PLL_425_ENABLE);
+
+ bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START);
+ udelay(1000);
+ r32 = bfa_reg_read((rb + MBIST_STAT_REG));
+ /*
+ * release semaphore.
+ */
+ bfa_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg);
+
+ return BFA_STATUS_OK;
+}
+
+/**
+ * Cleanup hw semaphore and usecnt registers
+ */
+static void
+bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc)
+{
+
+ if (ioc->cna) {
+ bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
+ bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 0);
+ bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
+ }
+
+ /*
+ * Read the hw sem reg to make sure that it is locked
+ * before we clear it. If it is not locked, writing 1
+ * will lock it instead of clearing it.
+ */
+ bfa_reg_read(ioc->ioc_regs.ioc_sem_reg);
+ bfa_ioc_hw_sem_release(ioc);
+}
+
+
diff -ruP net-next-2.6-orig/drivers/net/bna/bfa_sm.c net-next-2.6-mod/drivers/net/bna/bfa_sm.c
--- net-next-2.6-orig/drivers/net/bna/bfa_sm.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bfa_sm.c 2009-11-12 19:03:38.691336000 -0800
@@ -0,0 +1,41 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+/**
+ * bfasm.c BFA State machine utility functions
+ */
+
+#include <cs/bfa_sm.h>
+
+/**
+ * cs_sm_api
+ */
+
+int
+bfa_sm_to_state(struct bfa_sm_table *smt, bfa_sm_t sm)
+{
+ int i = 0;
+
+ while (smt[i].sm && smt[i].sm != sm)
+ i++;
+ return smt[i].state;
+}
+
+
diff -ruP net-next-2.6-orig/drivers/net/bna/bna_if.c net-next-2.6-mod/drivers/net/bna/bna_if.c
--- net-next-2.6-orig/drivers/net/bna/bna_if.c 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bna_if.c 2009-11-12 19:03:38.699344000 -0800
@@ -0,0 +1,574 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * file bna_if.c BNA Hardware and Firmware Interface
+ */
+#include <cna.h>
+#include "bna.h"
+#include "bna_hwreg.h"
+#include "bna_priv.h"
+#include "bna_iocll.h"
+#include "bna_intr.h"
+#include <bfi/bfi_cee.h>
+#include <protocol/types.h>
+#include <cee/bfa_cee.h>
+
+
+
+
+#define BNA_FLASH_DMA_BUF_SZ 0x010000 /* 64K */
+
+#define DO_CALLBACK(cbfn) \
+do { \
+ if (mb_cbfns->cbfn) { \
+ if (qe && qe->cbarg) { \
+ (mb_cbfns->cbfn)(qe->cbarg, status); \
+ } else { \
+ (mb_cbfns->cbfn)(dev->cbarg, status); \
+ } \
+ } \
+} while (0)
+
+#define DO_DIAG_CALLBACK(cbfn, data) \
+do { \
+ if (mb_cbfns->cbfn) { \
+ if (qe && qe->cbarg) { \
+ (mb_cbfns->cbfn)(qe->cbarg, data, status); \
+ } else { \
+ (mb_cbfns->cbfn)(dev->cbarg, data, status); \
+ } \
+ } \
+} while (0)
+
+#define bna_mbox_q_is_empty(mb_q) \
+ ((mb_q)->producer_index == \
+ (mb_q)->consumer_index)
+
+#define bna_mbox_q_first(mb_q) \
+ (&(mb_q)->mb_qe[(mb_q)->consumer_index])
+
+/**
+ * bna_register_callback()
+ *
+ * Function called by the driver to register a callback
+ * with the BNA
+ *
+ * @param[in] bna_dev - Opaque handle to BNA private device
+ * @param[in] cbfns - Structure for the callback functions.
+ * @param[in] cbarg - Argument to use with the callback
+ * @param[in] cmd_code - Command code exported to the drivers
+ *
+ * @return void
+ */
+void bna_register_callback(struct bna_dev *dev, struct bna_mbox_cbfn *cbfns,
+ void *cbarg)
+{
+ memcpy(&dev->mb_cbfns, cbfns, sizeof(dev->mb_cbfns));
+ dev->cbarg = cbarg;
+}
+
+void
+bna_mbox_q_init(struct bna_mbox_q *q)
+{
+ BNA_ASSERT(BNA_POWER_OF_2(BNA_MAX_MBOX_CMD_QUEUE));
+
+ q->producer_index = q->consumer_index = 0;
+ q->posted = NULL;
+}
+
+static struct bna_mbox_cmd_qe *
+bna_mbox_enq(struct bna_mbox_q *mbox_q, void *cmd, u32 cmd_len,
+ void *cbarg)
+{
+ struct bna_mbox_cmd_qe *qe;
+
+ if (!BNA_QE_FREE_CNT(mbox_q, BNA_MAX_MBOX_CMD_QUEUE))
+ return NULL;
+
+ qe = &mbox_q->mb_qe[mbox_q->producer_index];
+ BNA_QE_INDX_ADD(mbox_q->producer_index, 1, BNA_MAX_MBOX_CMD_QUEUE);
+ memcpy(&qe->cmd.msg[0], cmd, cmd_len);
+ qe->cmd_len = cmd_len;
+ qe->cbarg = cbarg;
+
+ return qe;
+}
+
+static void
+bna_mbox_deq(struct bna_mbox_q *mbox_q)
+{
+
+ /* Free one from the head */
+ BNA_QE_INDX_ADD(mbox_q->consumer_index, 1, BNA_MAX_MBOX_CMD_QUEUE);
+}
+
+static void
+bna_do_stats_update(struct bna_dev *dev, u8 status)
+{
+ if (status != BFI_LL_CMD_OK)
+ return;
+
+ bna_stats_process(dev);
+}
+
+static void
+bna_do_drv_ll_cb(struct bna_dev *dev, u8 cmd_code, u8 status,
+ struct bna_mbox_cmd_qe *qe)
+{
+ struct bna_mbox_cbfn *mb_cbfns = &dev->mb_cbfns;
+
+ switch (cmd_code) {
+ case BFI_LL_I2H_MAC_UCAST_SET_RSP:
+ DO_CALLBACK(ucast_set_cb);
+ break;
+ case BFI_LL_I2H_MAC_UCAST_ADD_RSP:
+ DO_CALLBACK(ucast_add_cb);
+ break;
+ case BFI_LL_I2H_MAC_UCAST_DEL_RSP:
+ DO_CALLBACK(ucast_del_cb);
+ break;
+ case BFI_LL_I2H_MAC_MCAST_ADD_RSP:
+ DO_CALLBACK(mcast_add_cb);
+ break;
+ case BFI_LL_I2H_MAC_MCAST_DEL_RSP:
+ DO_CALLBACK(mcast_del_cb);
+ break;
+ case BFI_LL_I2H_MAC_MCAST_FILTER_RSP:
+ DO_CALLBACK(mcast_filter_cb);
+ break;
+ case BFI_LL_I2H_MAC_MCAST_DEL_ALL_RSP:
+ DO_CALLBACK(mcast_del_all_cb);
+ break;
+ case BFI_LL_I2H_RXF_PROMISCUOUS_SET_RSP:
+ DO_CALLBACK(set_promisc_cb);
+ break;
+ case BFI_LL_I2H_RXF_DEFAULT_SET_RSP:
+ DO_CALLBACK(set_default_cb);
+ break;
+ case BFI_LL_I2H_TXQ_STOP_RSP:
+ DO_CALLBACK(txq_stop_cb);
+ break;
+ case BFI_LL_I2H_RXQ_STOP_RSP:
+ DO_CALLBACK(rxq_stop_cb);
+ break;
+ case BFI_LL_I2H_PORT_ADMIN_RSP:
+ DO_CALLBACK(port_admin_cb);
+ break;
+ case BFI_LL_I2H_STATS_GET_RSP:
+ bna_do_stats_update(dev, status);
+ DO_CALLBACK(stats_get_cb);
+ break;
+ case BFI_LL_I2H_STATS_CLEAR_RSP:
+ DO_CALLBACK(stats_clr_cb);
+ break;
+ case BFI_LL_I2H_LINK_DOWN_AEN:
+ DO_CALLBACK(link_down_cb);
+ break;
+ case BFI_LL_I2H_LINK_UP_AEN:
+ DO_CALLBACK(link_up_cb);
+ break;
+ case BFI_LL_I2H_DIAG_LOOPBACK_RSP:
+ DO_CALLBACK(set_diag_lb_cb);
+ break;
+ case BFI_LL_I2H_SET_PAUSE_RSP:
+ DO_CALLBACK(set_pause_cb);
+ break;
+ case BFI_LL_I2H_MTU_INFO_RSP:
+ DO_CALLBACK(mtu_info_cb);
+ break;
+ case BFI_LL_I2H_RX_RSP:
+ DO_CALLBACK(rxf_cb);
+ break;
+ default:
+ break;
+ }
+}
+
+static enum bna_status_e
+bna_flush_mbox_q(struct bna_dev *dev, u8 wait_for_rsp)
+{
+ struct bna_mbox_q *q;
+ struct bna_mbox_cmd_qe *qe = NULL;
+ u8 msg_id = 0, msg_class = 0;
+
+ q = &dev->mbox_q;
+
+ if (bna_mbox_q_is_empty(q))
+ return BNA_OK;
+ if (q->posted != NULL && wait_for_rsp) {
+ qe = (struct bna_mbox_cmd_qe *)(q->posted);
+ /* The driver has to retry */
+ return BNA_BUSY;
+ }
+
+ while (!bna_mbox_q_is_empty(q)) {
+ qe = bna_mbox_q_first(q);
+ msg_class = ((struct bfi_mhdr *)(&qe->cmd.msg[0]))->msg_class;
+ msg_id = ((struct bfi_mhdr *)(&qe->cmd.msg[0]))->msg_id;
+
+
+ BNA_ASSERT(msg_class == BFI_MC_LL);
+ bna_do_drv_ll_cb(dev, BFA_I2HM(msg_id), BFI_LL_CMD_NOT_EXEC,
+ qe);
+ bna_mbox_deq(q);
+ }
+ /* Reinit the queue, i.e prod = cons = 0; */
+ bna_mbox_q_init(q);
+ return BNA_OK;
+}
+
+enum bna_status_e
+bna_cleanup(void *bna_dev)
+{
+ struct bna_dev *dev = (struct bna_dev *) bna_dev;
+
+ dev->msg_ctr = 0;
+
+ memset(&dev->mb_msg, 0, sizeof(dev->mb_msg));
+
+ return bna_flush_mbox_q(dev, 0);
+}
+
+/**
+ * Check both command queues
+ * Write to mailbox if required
+ */
+static enum bna_status_e
+bna_chk_n_snd_q(struct bna_dev *dev)
+{
+ struct bna_mbox_cmd_qe *qe = NULL;
+ struct bna_mbox_q *q;
+ struct bfi_mhdr *mh = NULL;
+
+ q = &dev->mbox_q;
+
+ if (bna_mbox_q_is_empty(q))
+ return BNA_OK;
+ if (q->posted != NULL)
+ return BNA_OK;
+
+ qe = bna_mbox_q_first(q);
+ /* Do not post any more commands if disable pending */
+ if (dev->ioc_disable_pending == 1)
+ return BNA_OK;
+
+ mh = ((struct bfi_mhdr *)(&qe->cmd.msg[0]));
+ mh->mtag.i2htok = htons(dev->msg_ctr);
+ dev->msg_ctr++;
+ bfa_ioc_mbox_queue(&dev->ioc, &qe->cmd);
+ q->posted = qe;
+
+ return BNA_OK;
+}
+
+enum bna_status_e
+bna_mbox_send(struct bna_dev *dev, void *cmd, u32 cmd_len, void *cbarg)
+{
+ struct bna_mbox_cmd_qe *qe;
+ struct bna_mbox_q *q;
+ struct bfi_mhdr *mh = (struct bfi_mhdr *)cmd;
+
+ char message[BNA_MESSAGE_SIZE];
+ BNA_ASSERT(cmd_len <= BNA_MAX_MBOX_CMD_LEN);
+
+ if (dev->ioc_disable_pending) {
+ sprintf(message,
+ "IOC Disable is pending : Cannot queue Cmd "
+ "class %d id %d", mh->msg_class, mh->msg_id);
+ DPRINTK(INFO, "%s", message);
+ return BNA_AGAIN;
+ }
+
+ if (!bfa_ioc_is_operational(&dev->ioc)) {
+ sprintf(message,
+ "IOC is not operational : Cannot queue Cmd "
+ "class %d id %d", mh->msg_class, mh->msg_id);
+ DPRINTK(INFO, "%s", message);
+ return BNA_AGAIN;
+ }
+
+ q = &dev->mbox_q;
+ qe = bna_mbox_enq(q, cmd, cmd_len, cbarg);
+ if (qe == NULL) {
+ sprintf(message, "No free Mbox Command Element");
+ DPRINTK(INFO, "%s", message);
+ return BNA_FAIL;
+ }
+ return bna_chk_n_snd_q(dev);
+}
+
+
+/**
+ * Returns 1, if this is an aen, 0 otherwise
+ */
+static int
+bna_is_aen(u8 msg_id)
+{
+ return (msg_id == BFI_LL_I2H_LINK_DOWN_AEN ||
+ msg_id == BFI_LL_I2H_LINK_UP_AEN);
+}
+
+static void
+bna_err_handler(struct bna_dev *dev, u32 intr_status)
+{
+ u32 curr_mask, init_halt;
+ char message[BNA_MESSAGE_SIZE];
+
+ sprintf(message, "HW ERROR : INT statux 0x%x on port %d",
+ intr_status, dev->port);
+ DPRINTK(INFO, "%s", message);
+
+ if (intr_status & __HALT_STATUS_BITS) {
+ init_halt = bfa_reg_read(dev->ioc.ioc_regs.ll_halt);
+ init_halt &= ~__FW_INIT_HALT_P;
+ bfa_reg_write(dev->ioc.ioc_regs.ll_halt, init_halt);
+ }
+
+ bfa_ioc_error_isr(&dev->ioc);
+
+ /*
+ * Disable all the bits in interrupt mask, including
+ * the mbox & error bits.
+ * This is required so that once h/w error hits, we don't
+ * get into a loop.
+ */
+ bna_intx_disable(dev, &curr_mask);
+
+}
+
+void
+bna_ll_isr(void *llarg, struct bfi_mbmsg *msg)
+{
+ u32 aen = 0;
+ struct bna_dev *dev = (struct bna_dev *) llarg;
+ struct bna_mbox_cmd_qe *qe = NULL;
+ struct bna_mbox_q *mbox_q = NULL;
+ struct bfi_ll_rsp *mb_rsp = NULL;
+ char message[BNA_MESSAGE_SIZE];
+
+ mb_rsp = (struct bfi_ll_rsp *)(msg);
+
+ BNA_ASSERT(mb_rsp->mh.msg_class == BFI_MC_LL);
+
+ aen = bna_is_aen(mb_rsp->mh.msg_id);
+ if (!aen) {
+ mbox_q = &dev->mbox_q;
+
+ BNA_ASSERT(!bna_mbox_q_is_empty(mbox_q));
+ qe = bna_mbox_q_first(mbox_q);
+ BNA_ASSERT(mbox_q->posted == qe);
+
+ if (BFA_I2HM(((struct bfi_mhdr *)(&qe->cmd.msg[0]))->msg_id)
+ != mb_rsp->mh.msg_id) {
+ sprintf(message,
+ "Invalid Rsp Msg %d:%d (Expected %d:%d) "
+ "on %d", mb_rsp->mh.msg_class,
+ mb_rsp->mh.msg_id,
+ ((struct bfi_mhdr *)(&qe->cmd.
+ msg[0]))->
+ msg_class,
+ BFA_I2HM(((struct bfi_mhdr *)
+ (&qe->cmd.msg[0]))->msg_id),
+ dev->port);
+ DPRINTK(INFO, "%s", message);
+ BNA_ASSERT(0);
+ return;
+ }
+ bna_mbox_deq(mbox_q);
+ mbox_q->posted = NULL;
+ }
+
+ memcpy(&dev->mb_msg, msg, sizeof(dev->mb_msg));
+
+ bna_do_drv_ll_cb(dev, mb_rsp->mh.msg_id, mb_rsp->error, qe);
+
+ bna_chk_n_snd_q(dev);
+}
+
+
+void
+bna_mbox_err_handler(struct bna_dev *dev, u32 intr_status)
+{
+ if (BNA_IS_ERR_INTR(intr_status)) {
+ bna_err_handler(dev, intr_status);
+ return;
+ }
+
+ if (BNA_IS_MBOX_INTR(intr_status))
+ bfa_ioc_mbox_isr(&dev->ioc);
+}
+
+/**
+ * bna_port_admin()
+ *
+ * Enable (up) or disable (down) the interface administratively.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[in] enable - enable/disable the interface.
+ *
+ * @return BNA_OK or BNA_FAIL
+ */
+enum bna_status_e
+bna_port_admin(struct bna_dev *bna_dev, enum bna_enable_e enable)
+{
+ struct bna_dev *dev = (struct bna_dev *) bna_dev;
+ struct bfi_ll_port_admin_req ll_req;
+
+
+ ll_req.mh.msg_class = BFI_MC_LL;
+ ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
+ ll_req.mh.mtag.i2htok = 0;
+
+ ll_req.up = enable;
+
+ /* send to f/w */
+ return bna_mbox_send(dev, &ll_req, sizeof(ll_req), dev->cbarg);
+}
+
+/**
+ * bna_port_param_get()
+ *
+ * Get the port parameters.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[out] param_ptr - pointer to where the parameters will be returned.
+ *
+ * @return void
+ */
+void
+bna_port_param_get(struct bna_dev *dev, struct bna_port_param *param_ptr)
+{
+ param_ptr->supported = BNA_TRUE;
+ param_ptr->advertising = BNA_TRUE;
+ param_ptr->speed = BNA_LINK_SPEED_10Gbps;
+ param_ptr->duplex = BNA_TRUE;
+ param_ptr->autoneg = BNA_FALSE;
+ param_ptr->port = dev->port;
+}
+
+/**
+ * bna_port_mac_get()
+ *
+ * Get the Burnt-in or permanent MAC address. This function does not return
+ * the MAC set thru bna_rxf_ucast_mac_set() but the one that is assigned to
+ * the port upon reset.
+ *
+ * @param[in] dev - pointer to BNA device structure
+ * @param[out] mac_ptr - Burnt-in or permanent MAC address.
+ *
+ * @return void
+ */
+void
+bna_port_mac_get(struct bna_dev *bna_dev, struct mac *mac_ptr)
+{
+ struct bna_dev *dev = (struct bna_dev *) bna_dev;
+
+ *mac_ptr = bfa_ioc_get_mac(&dev->ioc);
+}
+
+/**
+ * IOC Integration
+ */
+
+/**
+ * bfa_iocll_cbfn
+ * Structure for callbacks to be implemented by
+ * the driver.
+ */
+static struct bfa_ioc_cbfn bfa_iocll_cbfn = {
+ bna_iocll_enable_cbfn,
+ bna_iocll_disable_cbfn,
+ bna_iocll_hbfail_cbfn,
+ bna_iocll_reset_cbfn
+};
+
+
+static void
+bna_iocll_memclaim(struct bna_dev *dev, struct bna_meminfo *mi)
+{
+
+ bfa_ioc_mem_claim(&dev->ioc, mi[BNA_DMA_MEM_T_ATTR].kva,
+ mi[BNA_DMA_MEM_T_ATTR].dma);
+
+ bfa_ioc_debug_memclaim(&dev->ioc, mi[BNA_KVA_MEM_T_FWTRC].kva);
+}
+
+void
+bna_iocll_meminfo(struct bna_dev *dev, struct bna_meminfo *mi)
+{
+
+
+ mi[BNA_DMA_MEM_T_ATTR].len =
+ BNA_ALIGN(bfa_ioc_meminfo(), BNA_PAGE_SIZE);
+
+ mi[BNA_KVA_MEM_T_FWTRC].len = bfa_ioc_debug_trcsz(true);
+}
+
+void
+bna_iocll_attach(struct bna_dev *dev, void *bnad, struct bna_meminfo *meminfo,
+ struct bfa_pcidev *pcidev, struct bfa_trc_mod *trcmod,
+ struct bfa_aen *aen, struct bfa_log_mod *logm)
+{
+ bfa_ioc_attach(&dev->ioc, bnad, &bfa_iocll_cbfn, &dev->timer_mod,
+ trcmod, aen, logm);
+ bfa_ioc_pci_init(&dev->ioc, pcidev, BFI_MC_LL);
+
+ bfa_ioc_mbox_regisr(&dev->ioc, BFI_MC_LL, bna_ll_isr, dev);
+ bna_iocll_memclaim(dev, meminfo);
+
+
+ bfa_timer_init(&dev->timer_mod);
+
+}
+
+/**
+ * FIXME :
+ * Either the driver or CAL should serialize
+ * this IOC disable
+ * Currently this is happening indirectly b'cos
+ * bfa_ioc_disable() is not called if there
+ * is an outstanding cmd in the queue, which
+ * could not be flushed.
+ */
+enum bna_status_e
+bna_iocll_disable(struct bna_dev *dev)
+{
+ enum bna_status_e ret;
+ char message[BNA_MESSAGE_SIZE];
+
+ dev->ioc_disable_pending = 1;
+ ret = bna_flush_mbox_q(dev, 1);
+ if (ret != BNA_OK) {
+ sprintf(message, "Unable to flush Mbox Queues [%d]",
+ ret);
+ DPRINTK(INFO, "%s", message);
+ return ret;
+ }
+
+ bfa_ioc_disable(&dev->ioc);
+ dev->ioc_disable_pending = 0;
+
+ return BNA_OK;
+}
+
+/* Dummy */
+/* FIXME : Delete once bfa_diag.c is fixed */
+void
+bfa_fcport_beacon(struct bfa *bfa, bool beacon,
+ bool link_e2e_beacon)
+{
+}
diff -ruP net-next-2.6-orig/drivers/net/bna/bna_iocll.h net-next-2.6-mod/drivers/net/bna/bna_iocll.h
--- net-next-2.6-orig/drivers/net/bna/bna_iocll.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bna_iocll.h 2009-11-12 19:03:38.706336000 -0800
@@ -0,0 +1,65 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See LICENSE.bna for copyright and licensing details.
+ */
+
+#ifndef __BNA_IOCLL_H__
+#define __BNA_IOCLL_H__
+
+#include <bfa_ioc.h>
+#include <bfa_timer.h>
+#include <bfi/bfi_ll.h>
+
+#define BNA_IOC_TIMER_PERIOD BFA_TIMER_FREQ
+
+/*
+ * LL specific IOC functions.
+ */
+void bna_iocll_meminfo(struct bna_dev *bna_dev, struct bna_meminfo *meminfo);
+void bna_iocll_attach(struct bna_dev *bna_dev, void *bnad,
+ struct bna_meminfo *meminfo, struct bfa_pcidev *pcidev,
+ struct bfa_trc_mod *trcmod, struct bfa_aen *aen,
+ struct bfa_log_mod *logmod);
+enum bna_status_e bna_iocll_disable(struct bna_dev *bna_dev);
+#define bna_iocll_detach(dev) bfa_ioc_detach(&((dev)->ioc))
+#define bna_iocll_enable(dev) bfa_ioc_enable(&((dev)->ioc))
+#define bna_iocll_debug_fwsave(dev, trc_data, trc_len) \
+ bfa_ioc_debug_fwsave(&((dev)->ioc), (trc_data), (trc_len))
+#define bna_iocll_debug_fwtrc(dev, trc_data, trc_len) \
+ bfa_ioc_debug_fwtrc(&((dev)->ioc), (trc_data), (trc_len))
+#define bna_iocll_timer(dev) bfa_timer_beat(&((dev)->timer_mod))
+#define bna_iocll_getstats(dev, ioc_stats) \
+ bfa_ioc_fetch_stats(&((dev)->ioc), (ioc_stats))
+#define bna_iocll_resetstats(dev) bfa_ioc_clr_stats(&((dev)->ioc))
+#define bna_iocll_getattr(dev, ioc_attr) \
+ bfa_ioc_get_attr(&((dev)->ioc), (ioc_attr))
+#define bna_iocll_getstate(dev) \
+ bfa_ioc_get_state(&((dev)->ioc))
+#define bna_iocll_get_serial_num(_dev, _serial_num) \
+ bfa_ioc_get_adapter_serial_num(&((_dev)->ioc), (_serial_num))
+
+
+/**
+ * Callback functions to be implemented by the driver
+ */
+void bna_iocll_enable_cbfn(void *bnad, enum bfa_status status);
+void bna_iocll_disable_cbfn(void *bnad);
+void bna_iocll_hbfail_cbfn(void *bnad);
+void bna_iocll_reset_cbfn(void *bnad);
+
+#endif /* __BNA_IOCLL_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/bna_priv.h net-next-2.6-mod/drivers/net/bna/bna_priv.h
--- net-next-2.6-orig/drivers/net/bna/bna_priv.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bna_priv.h 2009-11-12 19:03:38.713337000 -0800
@@ -0,0 +1,482 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ *
+ * See <license_file> for copyright and licensing details.
+ */
+
+/**
+ * BNA register access macros.p
+ */
+
+#ifndef __BNA_PRIV_H__
+#define __BNA_PRIV_H__
+
+
+#define bna_mem_read(_raddr, _off) bna_os_mem_read(_raddr, _off)
+#define bna_mem_write(_raddr, _off, _val) \
+ bna_os_mem_write(_raddr, _off, _val)
+
+
+/**
+ Macros to declare a bit table
+ *
+ * @param[in] _table - bit table to be declared
+ * @param[in] _size - size in bits
+ */
+#define BNA_BIT_TABLE_DECLARE(_table, _size) \
+ (u32 _table[(_size) / 32])
+/**
+ Macros to set bits in a bit table
+ *
+ * @param[in] _table - bit table to be declared
+ * @param[in] _bit - bit to be set
+ */
+#define BNA_BIT_TABLE_SET(_table, _bit) \
+ (_table[(_bit) / 32] |= (1 << ((_bit) & (32 - 1))))
+/**
+ Macros to clear bits in a bit table
+ *
+ * @param[in] _table - bit table to be declared
+ * @param[in] _bit - bit to be set
+ */
+#define BNA_BIT_TABLE_CLEAR(_table, _bit) \
+ (_table[(_bit) / 32] &= ~(1 << ((_bit) & (32 - 1))))
+/**
+ Macros to set bits in a 32 bit word
+ *
+ * @param[in] _word - word in which bit is to be set
+ * @param[in] _bit - bit to be set (starting at 0)
+ */
+#define BNA_BIT_WORD_SET(_word, _bit) \
+ ((_word) |= (1 << (_bit)))
+/**
+ Macros to clear bits in a 32 bit word
+ *
+ * @param[in] _word - word in which bit is to be cleared
+ * @param[in] _bit - bit to be cleared (starting at 0)
+ */
+#define BNA_BIT_WORD_CLEAR(_word, _bit) \
+ ((_word) &= ~(1 << (_bit)))
+
+/**
+ * BNA_GET_PAGE_NUM()
+ *
+ * Macro to calculate the page number for the
+ * memory spanning multiple pages.
+ *
+ * @param[in] _base_page - Base Page Number for memory
+ * @param[in] _offset - Offset for which page number
+ * is calculated
+ */
+#define BNA_GET_PAGE_NUM(_base_page, _offset) \
+ ((_base_page) + ((_offset) >> 15))
+/**
+ * BNA_GET_PAGE_OFFSET()
+ *
+ * Macro to calculate the page offset for the
+ * from the base offset (from the top of the block)
+ * Each page 0x8000 (32KB) in size
+ *
+ * @param[in] _offset - Offset from the top of the block
+ */
+#define BNA_GET_PAGE_OFFSET(_offset) \
+ ((_offset) & 0x7fff)
+
+/**
+ * BNA_GET_WORD_OFFSET()
+ *
+ * Macro to calculate the address of a word from
+ * the base address. Needed to access H/W memory
+ * as 4 byte words. Starts from 0.
+ *
+ * @param[in] _base_offset - Starting offset of the data
+ * @param[in] _word - Word no. for which address is calculated
+ */
+#define BNA_GET_WORD_OFFSET(_base_offset, _word) \
+ ((_base_offset) + ((_word) << 2))
+/**
+ * BNA_GET_BYTE_OFFSET()
+ *
+ * Macro to calculate the address of a byte from
+ * the base address. Most of H/W memory is accessed
+ * as 4 byte words, so use this macro carefully.
+ * Starts from 0.
+ *
+ * @param[in] _base_offset - Starting offset of the data
+ * @param[in] _byte - Byte no. for which address is calculated
+ */
+#define BNA_GET_BYTE_OFFSET(_base_offset, _byte) \
+ ((_base_offset) + (_byte))
+
+/**
+ * BNA_GET_MEM_BASE_ADDR()
+ *
+ * Macro to calculate the base address of
+ * any memory block given the bar0 address
+ * and the memory base offset
+ *
+ * @param[in] _bar0 - BARO address
+ * @param[in] _base_offset - Starting offset of the memory
+ */
+#define BNA_GET_MEM_BASE_ADDR(_bar0, _base_offset) \
+ ((_bar0) + HW_BLK_HOST_MEM_ADDR \
+ + BNA_GET_PAGE_OFFSET((_base_offset)))
+
+/**
+ * Structure which maps to Rx FnDb config
+ * Size : 4 words
+ * See catapult_spec.pdf, RxA for details
+ */
+struct bna_rx_fndb_ram {
+ u32 rss_prop;
+ u32 size_routing_props;
+ u32 rit_hds_mcastq;
+ u32 control_flags;
+};
+
+/**
+ * Structure which maps to Tx FnDb config
+ * Size : 1 word
+ * See catapult_spec.pdf, TxA for details
+ */
+struct bna_tx_fndb_ram {
+ u32 vlan_n_ctrl_flags;
+};
+
+/**
+ * Structure which maps to Unicast/Multicast CAM entry
+ * Size : 2 words
+ * See catapult_spec.pdf, LUT for details
+ */
+struct bna_cam {
+ u32 cam_mac_addr_47_32; /* 31:16->res;15:0->MAC */
+ u32 cam_mac_addr_31_0;
+};
+
+/**
+ * Structure which maps to Unicast RAM entry
+ * Size : 1 word
+ * See catapult_spec.pdf, LUT for details
+ */
+struct bna_ucast_mem {
+ u32 ucast_ram_entry;
+};
+
+/**
+ * Structure which maps to VLAN RAM entry
+ * Size : 1 word ?? Need to verify
+ * See catapult_spec.pdf, LUT for details
+ */
+struct bna_vlan_mem {
+ u32 vlan_ram_entry; /* FIXME */
+};
+#define BNA_GET_VLAN_MEM_ENTRY_ADDR(_bar0, _fn_id, _vlan_id)\
+ (_bar0 + (HW_BLK_HOST_MEM_ADDR) \
+ + (BNA_GET_PAGE_OFFSET(VLAN_RAM_BASE_OFFSET)) \
+ + (((_fn_id) & 0x3f) << 9) \
+ + (((_vlan_id) & 0xfe0) >> 3))
+
+/**
+ * Structure which maps to exact/approx MVT RAM entry
+ * Size : 4 words
+ * See catapult_spec.pdf, RxA for details
+ */
+struct bna_mvt_mem {
+ u32 reserved;
+ u32 fc_bit; /* 31:1->res;0->fc_bit */
+ u32 ll_fn_63_32; /* LL fns 63 to 32 */
+ u32 ll_fn_31_0; /* LL fns 31 to 0 */
+};
+
+/**
+ * Structure which maps to RxFn Indirection Table (RIT)
+ * Size : 1 word
+ * See catapult_spec.pdf, RxA for details
+ */
+struct bna_rit_mem {
+ u32 rxq_ids; /* 31:12->res;11:0->two 6 bit RxQ Ids */
+};
+
+/**
+ * Structure which maps to RSS Table entry
+ * Size : 16 words
+ * See catapult_spec.pdf, RAD for details
+ */
+struct bna_rss_mem {
+ u32 type_n_hash; /* 31:12->res; */
+ /* 11:8 ->protocol type */
+ /* 7:0 ->hash index */
+ u32 hash_key[10]; /* 40 byte Toeplitz hash key */
+ u32 reserved[5];
+};
+
+/**
+ * Structure which maps to RxQ Memory entry
+ * Size : 16 words, entries are 32 words apart
+ * Alternate arrangement of RxQ & TxQ
+ * See catapult_spec.pdf, HQM for details
+ */
+struct bna_rxq_mem {
+ u32 pg_tbl_addr_lo;
+ u32 pg_tbl_addr_hi;
+ u32 cur_q_entry_lo;
+ u32 cur_q_entry_hi;
+ u32 reserved1;
+ u32 reserved2;
+ u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
+ /* 15:0 ->producer pointer (index?) */
+ u32 entry_n_pg_size; /* 31:16->entry size */
+ /* 15:0 ->page size */
+ u32 sg_n_cq_n_cns_ptr; /* 31:28->reserved; 27:24->sg count */
+ /* 23:16->CQ; */
+ /* 15:0->consumer pointer(index?) */
+ u32 buf_sz_n_q_state; /* 31:16->buffer size; 15:0-> Q state */
+ u32 next_qid; /* 17:10->next QId */
+ u32 reserved3;
+ u32 reserved4[4];
+};
+
+
+/**
+ * Structure which maps to TxQ Memory entry
+ * Size : 16 words, entries are 32 words apart
+ * Alternate arrangement of RxQ & TxQ
+ * See catapult_spec.pdf, HQM for details
+ */
+struct bna_txq_mem {
+ u32 pg_tbl_addr_lo;
+ u32 pg_tbl_addr_hi;
+ u32 cur_q_entry_lo;
+ u32 cur_q_entry_hi;
+ u32 reserved1;
+ u32 reserved2;
+ u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
+ /* 15:0 ->producer pointer (index?) */
+ u32 entry_n_pg_size; /* 31:16->entry size */
+ /* 15:0 ->page size */
+ u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */
+ /* 23:16->Int Blk Offset */
+ /* 15:0 ->consumer pointer(index?) */
+ u32 cns_ptr2_n_q_state; /* 31:16->cons. ptr 2; 15:0-> Q state */
+ u32 nxt_qid_n_fid_n_pri; /* 17:10->next */
+ /* QId;9:3->FID;2:0->Priority */
+ u32 wvc_n_cquota_n_rquota; /* 31:24->WI Vector Count; */
+ /* 23:12->Cfg Quota; */
+ /* 11:0 ->Run Quota */
+ u32 reserved3[4];
+};
+
+/**
+ * Structure which maps to RxQ and TxQ Memory entry
+ * Size : 32 words, entries are 32 words apart
+ * Alternate arrangement of RxQ & TxQ
+ * See catapult_spec.pdf, HQM for details
+ */
+struct bna_rxtx_q_mem {
+ struct bna_rxq_mem rxq;
+ struct bna_txq_mem txq;
+};
+
+/**
+ * Structure which maps to CQ Memory entry
+ * Size : 16 words
+ * See catapult_spec.pdf, HQM for details
+ */
+struct bna_cq_mem {
+ u32 pg_tbl_addr_lo;
+ u32 pg_tbl_addr_hi;
+ u32 cur_q_entry_lo;
+ u32 cur_q_entry_hi;
+ u32 reserved1;
+ u32 reserved2;
+ u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
+ /* 15:0 ->producer pointer (index?) */
+ u32 entry_n_pg_size; /* 31:16->entry size */
+ /* 15:0 ->page size */
+ u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */
+ /* 23:16->Int Blk Offset */
+ /* 15:0 ->consumer pointer(index?) */
+ u32 q_state; /* 31:16->reserved; 15:0-> Q state */
+ u32 reserved3[2];
+ u32 reserved4[4];
+};
+
+/**
+ * Structure which maps to Interrupt Block Memory entry
+ * Size : 8 words (used: 5 words)
+ * See catapult_spec.pdf, HQM for details
+ */
+struct bna_ib_blk_mem {
+ u32 host_addr_lo;
+ u32 host_addr_hi;
+ u32 clsc_n_ctrl_n_msix; /* 31:24->coalescing; */
+ /* 23:16->coalescing cfg; */
+ /* 15:8 ->control; */
+ /* 7:0 ->msix; */
+ u32 ipkt_n_ent_n_idxof;
+ u32 ipkt_cnt_cfg_n_unacked;
+
+ u32 reserved[3];
+};
+
+/**
+ * Structure which maps to Index Table Block Memory entry
+ * Size : 1 word
+ * See catapult_spec.pdf, HQM for details
+ */
+struct bna_idx_tbl_mem {
+ u32 idx; /* 31:16->res;15:0->idx; */
+};
+
+/**
+ * Structure which maps to Doorbell QSet Memory,
+ * Organization of Doorbell address space for a
+ * QSet (RxQ, TxQ, Rx IB, Tx IB)
+ * For Non-VM qset entries are back to back.
+ * Size : 128 bytes / 4K bytes for Non-VM / VM
+ * See catapult_spec.pdf, HQM for details
+ */
+struct bna_doorbell_qset {
+ u32 rxq[0x20 >> 2];
+ u32 txq[0x20 >> 2];
+ u32 ib0[0x20 >> 2];
+ u32 ib1[0x20 >> 2];
+};
+
+
+#define BNA_GET_DOORBELL_BASE_ADDR(_bar0) \
+ ((_bar0) + HQM_DOORBELL_BLK_BASE_ADDR)
+
+
+/**
+ * BNA_GET_DOORBELL_ENTRY_OFFSET()
+ *
+ * Macro to calculate the offset of the Doorbell QSet
+ * in the Non VM case.
+ * Entries are 128 bytes apart. Does not need a page
+ * number register for access.
+ *
+ * @param[in] _entry - Entry Number
+ */
+#define BNA_GET_DOORBELL_ENTRY_OFFSET(_entry) \
+ ((HQM_DOORBELL_BLK_BASE_ADDR) \
+ + (_entry << 7))
+/**
+ * BNA_GET_DOORBELL_VM_ENTRY_OFFSET()
+ *
+ * Macro to calculate the offset of the Doorbell QSet
+ * in the VM case.
+ * Entries are 4K (0x1000) bytes apart.
+ * Does not need a page number register for access.
+ *
+ * @param[in] _entry - Entry Number
+ */
+#define BNA_GET_DOORBELL_VM_ENTRY_OFFSET(_entry) \
+ ((HQM_DOORBELL_VM_BLK_BASE_ADDR) \
+ + (_entry << 12))
+
+/**
+ * BNA_GET_PSS_SMEM_PAGE_NUM()
+ *
+ * Macro to calculate the page number of PSS SMEM
+ * block from a linear offset
+ *
+ * @param[in] _loff - Linear offset from the top of memory
+ */
+#define BNA_GET_PSS_SMEM_PAGE_NUM(_loff) \
+ (BNA_GET_PAGE_NUM(PSS_SMEM_BLK_PG_NUM, (_loff)))
+/**
+ * BNA_GET_PSS_SMEM_PAGE_OFFSET()
+ *
+ * Macro to calculate the page offset from the top
+ * of a PSS SMEM page, for a given linear offset
+ *
+ * @param[in] _loff - Linear offset from the top of memory
+ */
+#define BNA_GET_PSS_SMEM_PAGE_OFFSET(_loff) \
+ (PSS_SMEM_BLK_MEM_ADDR \
+ + BNA_GET_PAGE_OFFSET((_loff)))
+
+/**
+ * BNA_GET_MBOX_PAGE_NUM()
+ *
+ * Macro to calculate the page number of HostFn<->LPU/
+ * LPU<->HostFn Mailbox block from a linear offset
+ *
+ * @param[in] _loff - Linear offset from the top of memory
+ */
+#define BNA_GET_MBOX_PAGE_NUM(_loff) \
+ (BNA_GET_PAGE_NUM(CPQ_BLK_PG_NUM, (_loff)))
+/**
+ * BNA_GET_HOSTFN_LPU_MBOX_PAGE_OFFSET()
+ *
+ * Macro to calculate the HostFn<->LPU
+ * Mailbox page offset from the linear offset
+ *
+ * @param[in] _loff - Linear offset in bytes from the top of memory
+ */
+#define BNA_GET_HOSTFN_LPU_MBOX_PAGE_OFFSET(_loff) \
+ (HOSTFN_LPU_MBOX + BNA_GET_PAGE_OFFSET((_loff)))
+/**
+ * BNA_GET_LPU_HOSTFN_MBOX_PAGE_OFFSET()
+ *
+ * Macro to calculate the LPU<->HostFn
+ * Mailbox page offset from the linear offset
+ *
+ * @param[in] _loff - Linear offset from the top of memory
+ */
+#define BNA_GET_LPU_HOSTFN_MBOX_PAGE_OFFSET(_loff) \
+ (LPU_HOSTFN_MBOX + BNA_GET_PAGE_OFFSET((_loff)))
+
+
+#define bna_hw_stats_to_stats bna_dma_addr64
+
+void bna_mbox_q_init(struct bna_mbox_q *q);
+
+/**
+ * Interrupt Moderation
+ */
+
+#define BNA_80K_PKT_RATE 80000
+#define BNA_70K_PKT_RATE 70000
+#define BNA_60K_PKT_RATE 60000
+#define BNA_50K_PKT_RATE 50000
+#define BNA_40K_PKT_RATE 40000
+#define BNA_30K_PKT_RATE 30000
+#define BNA_20K_PKT_RATE 20000
+#define BNA_10K_PKT_RATE 10000
+
+/**
+ * Defines are in order of decreasing load
+ * i.e BNA_HIGH_LOAD_3 has the highest load
+ * and BNA_LOW_LOAD_3 has the lowest load.
+ */
+
+#define BNA_HIGH_LOAD_4 0 /* r >= 80 */
+#define BNA_HIGH_LOAD_3 1 /* 60 <= r < 80 */
+#define BNA_HIGH_LOAD_2 2 /* 50 <= r < 60 */
+#define BNA_HIGH_LOAD_1 3 /* 40 <= r < 50 */
+#define BNA_LOW_LOAD_1 4 /* 30 <= r < 40 */
+#define BNA_LOW_LOAD_2 5 /* 20 <= r < 30 */
+#define BNA_LOW_LOAD_3 6 /* 10 <= r < 20 */
+#define BNA_LOW_LOAD_4 7 /* r < 10 K */
+#define BNA_LOAD_TYPES BNA_LOW_LOAD_4
+
+#define BNA_BIAS_TYPES 2 /* small : small > large*2 */
+ /* large : if small is false */
+
+#endif /* __BNA_PRIV_H__ */
diff -ruP net-next-2.6-orig/drivers/net/bna/bnad_compat.h net-next-2.6-mod/drivers/net/bna/bnad_compat.h
--- net-next-2.6-orig/drivers/net/bna/bnad_compat.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bnad_compat.h 2009-11-12 19:03:38.720338000 -0800
@@ -0,0 +1,95 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ */
+
+#ifndef _BNAD_COMPAT_H_
+#define _BNAD_COMPAT_H_
+
+#include <linux/version.h>
+
+#ifndef SET_MODULE_OWNER
+#define SET_MODULE_OWNER(netdev) do { } while (0)
+#endif
+
+#ifndef SET_NETDEV_DEV
+#define SET_NETDEV_DEV(netdev, dev) do { } while (0)
+#endif
+
+#ifndef module_param
+#define module_param(name, type, perm) MODULE_PARM(name, "i");
+#endif
+
+#ifndef NETDEV_TX_OK
+#define NETDEV_TX_OK 0 /* driver took care of the packet */
+#endif
+
+#ifndef NETDEV_TX_BUSY
+#define NETDEV_TX_BUSY 1 /* driver tx path was busy */
+#endif
+
+#ifndef NETDEV_TX_LOCKED
+#define NETDEV_TX_LOCKED -1 /* driver tx lock was already taken */
+#endif
+
+#ifndef ALIGN
+#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
+#endif
+
+#ifndef ETH_FCS_LEN
+#define ETH_FCS_LEN 4
+#endif
+
+#ifndef CHECKSUM_PARTIAL
+#define CHECKSUM_PARTIAL CHECKSUM_HW
+#endif
+
+#ifndef IRQF_SHARED
+#define IRQF_SHARED SA_SHIRQ
+#endif
+
+#ifndef SKB_DATAREF_SHIFT
+#define skb_header_cloned(_skb) 0
+#endif
+
+#ifndef VERIFY_WRITE
+#define VERIFY_WRITE 1
+#endif
+
+#ifndef VERIFY_READ
+#define VERIFY_READ 0
+#endif
+
+#ifndef dev_err
+#define dev_err(dev, format, arg...) \
+ printk(KERN_ERR "bna: " format, ## arg)
+#endif
+#ifndef dev_info
+#define dev_info(dev, format, arg...) \
+ printk(KERN_INFO "bna: " format, ## arg)
+#endif
+#ifndef dev_warn
+#define dev_warn(dev, format, arg...) \
+ printk(KERN_WARNING "bna: " format, ## arg)
+#endif
+
+#ifndef __force
+#define __force
+#endif
+
+#define BNAD_VLAN_FEATURES
+
+#endif /* _BNAD_COMPAT_H_ */
diff -ruP net-next-2.6-orig/drivers/net/bna/bnad_defs.h net-next-2.6-mod/drivers/net/bna/bnad_defs.h
--- net-next-2.6-orig/drivers/net/bna/bnad_defs.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/bnad_defs.h 2009-11-12 19:03:38.728336000 -0800
@@ -0,0 +1,37 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ */
+
+#ifndef _BNAD_DEFS_H_
+#define _BNAD_DEFS_H_
+
+#define BNAD_NAME "bna"
+#ifdef BNA_DRIVER_VERSION
+#define BNAD_VERSION BNA_DRIVER_VERSION
+#else
+#define BNAD_VERSION "2.1.0.0"
+#endif
+
+#ifndef PCI_VENDOR_ID_BROCADE
+#define PCI_VENDOR_ID_BROCADE 0x1657
+#endif
+
+#ifndef PCI_DEVICE_ID_BROCADE_CATAPULT
+#define PCI_DEVICE_ID_BROCADE_CATAPULT 0x0014
+#endif
+
+#endif /* _BNAD_DEFS_H_ */
diff -ruP net-next-2.6-orig/drivers/net/bna/cna.h net-next-2.6-mod/drivers/net/bna/cna.h
--- net-next-2.6-orig/drivers/net/bna/cna.h 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/cna.h 2009-11-12 19:03:38.734346000 -0800
@@ -0,0 +1,82 @@
+/*
+ * Linux network driver for Brocade Converged Network Adapter.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License (GPL) Version 2 as
+ * published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+/*
+ * Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+ * All rights reserved
+ * www.brocade.com
+ */
+
+#ifndef __CNA_H__
+#define __CNA_H__
+
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <asm/page.h>
+#include <asm/io.h>
+#include <asm/string.h>
+
+#include <linux/smp.h>
+#include <linux/bitops.h>
+
+#include <linux/idr.h>
+#include <linux/interrupt.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/vmalloc.h>
+
+#include <linux/workqueue.h>
+
+#define BNA_PAGE_SIZE PAGE_SIZE
+#define BNA_PAGE_SHIFT PAGE_SHIFT
+
+#define BNA_ASSERT(x)
+
+#ifndef __BIGENDIAN
+#define bna_dma_addr64(_x) swab64((_x))
+#else
+#define bna_dma_addr64(_x) (_x)
+#endif
+
+#define bfa_addr_t char __iomem *
+#define bfa_u32(__pa64) ((__pa64) >> 32)
+
+#define bfa_reg_read(_raddr) readl(_raddr)
+#define bfa_reg_write(_raddr, _val) writel(_val, _raddr)
+#define bfa_os_panic()
+
+#define bfa_mem_read(_raddr, _off) \
+ ntohl(readl((_raddr) + (_off)))
+#define bfa_mem_write(_raddr, _off, _val) \
+ writel(htonl((_val)), ((_raddr) + (_off)))
+
+#define bfa_swap32(_x) swab32((_x))
+
+#ifndef __BIGENDIAN
+#define bfa_wtole(_x) (_x)
+#else
+#define bfa_wtole(_x) swab32((_x))
+#endif
+
+#define PFX "BNA: "
+#define DPRINTK(klevel, fmt, args...) do { \
+ printk(KERN_##klevel PFX fmt, ## args); \
+} while (0)
+
+extern char bfa_version[];
+void bfa_ioc_auto_recover(bool auto_recover);
+
+#endif /* __CNA_H__ */
^ permalink raw reply
* Subject: [PATCH 6/6] bna: Brocade 10Gb Ethernet device driver
From: Rasesh Mody @ 2009-11-13 3:46 UTC (permalink / raw)
To: netdev; +Cc: adapter_linux_open_src_team
From: Rasesh Mody <rmody@brocade.com>
This is patch 6/6 which contains linux driver source for
Brocade's BR1010/BR1020 10Gb CEE capable ethernet adapter.
Source is based against net-next-2.6.
We wish this patch to be considered for inclusion in net-next-2.6
Signed-off-by: Rasesh Mody <rmody@brocade.com>
---
Kconfig | 15 +++++++++++++++
Makefile | 1 +
bna/Makefile | 14 ++++++++++++++
3 files changed, 30 insertions(+)
diff -ruP net-next-2.6-orig/drivers/net/Kconfig net-next-2.6-mod/drivers/net/Kconfig
--- net-next-2.6-orig/drivers/net/Kconfig 2009-10-31 00:44:29.000000000 -0700
+++ net-next-2.6-mod/drivers/net/Kconfig 2009-11-12 19:09:25.474471000 -0800
@@ -2757,6 +2757,21 @@
To compile this driver as a module, choose M here: the module
will be called qlge.
+config BNA
+ tristate "Brocade 1010/1020 10Gb Ethernet Driver support"
+ depends on PCI
+ ---help---
+ This driver supports Brocade 1010/1020 10Gb CEE capable Ethernet
+ cards.
+
+ To compile this driver as a module, choose M here: the module
+ will be called bna.
+
+ For general information and support, go to the Brocade support
+ website at:
+
+ <http://support.brocade.com>
+
source "drivers/net/sfc/Kconfig"
source "drivers/net/benet/Kconfig"
diff -ruP net-next-2.6-orig/drivers/net/Makefile net-next-2.6-mod/drivers/net/Makefile
--- net-next-2.6-orig/drivers/net/Makefile 2009-10-31 00:44:29.000000000 -0700
+++ net-next-2.6-mod/drivers/net/Makefile 2009-11-12 19:09:25.480478000 -0800
@@ -31,6 +31,7 @@
obj-$(CONFIG_JME) += jme.o
obj-$(CONFIG_BE2NET) += benet/
obj-$(CONFIG_VMXNET3) += vmxnet3/
+obj-$(CONFIG_BNA) += bna/
gianfar_driver-objs := gianfar.o \
gianfar_ethtool.o \
diff -ruP net-next-2.6-orig/drivers/net/bna/Makefile net-next-2.6-mod/drivers/net/bna/Makefile
--- net-next-2.6-orig/drivers/net/bna/Makefile 1969-12-31 16:00:00.000000000 -0800
+++ net-next-2.6-mod/drivers/net/bna/Makefile 2009-11-12 19:09:25.502466000 -0800
@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2006-2009 Brocade Communications Systems, Inc.
+# All rights reserved.
+#
+
+obj-$(CONFIG_BNA) += bna.o
+
+bna-objs := bnad.o bnad_ethtool.o bna_fn.o bna_if.o bna_queue.o
+bna-objs += bfad_fwimg.o bfa_csdebug.o bfa_sm.o bfa_ioc.o
+bna-objs += bfa_timer.o bfa_cee.o
+
+EXTRA_CFLAGS := -Idrivers/net/bna -Idrivers/net/bna/include/cee
+EXTRA_CFLAGS += -Idrivers/net/bna/include -Idrivers/net/bna/include/cs
+EXTRA_CFLAGS += -Idrivers/net/bna/include/cna/pstats
^ permalink raw reply
* [net-next-2.6 PATCH v6 0/7 RFC] TCPCT part 1: cookie option exchange
From: William Allen Simpson @ 2009-11-13 4:03 UTC (permalink / raw)
To: Linux Kernel Network Developers
Although 'make vmlinux' compiles this successfully, it is not tested.
Keep in mind that earlier variants were extensively tested. But at least
this helps move the review comment process along....
Updated and reorganized to split the code base into several pieces, as
requested by Eric. No significant changes.
The new TCP_MSS_* symbols are now in an entirely separate patch.
^ permalink raw reply
* [net-next-2.6 PATCH v6 1/7 RFC] TCPCT part 1a: add request_values parameter for sending SYNACK
From: William Allen Simpson @ 2009-11-13 4:07 UTC (permalink / raw)
To: Linux Kernel Network Developers
In-Reply-To: <4AFCDA9E.8050003@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1006 bytes --]
Add optional function parameters associated with sending SYNACK.
These parameters are not needed after sending SYNACK, and are not
used for retransmission. Avoids extending struct tcp_request_sock,
and avoids allocating kernel memory.
Also affects DCCP as it uses common struct request_sock_ops,
but this parameter is currently reserved for future use.
Signed-off-by: William.Allen.Simpson@gmail.com
Acked-by: Eric Dumazet <eric.dumazet@gmail.com>
---
include/net/request_sock.h | 8 +++++++-
include/net/tcp.h | 3 ++-
net/dccp/ipv4.c | 5 +++--
net/dccp/ipv6.c | 5 +++--
net/dccp/minisocks.c | 2 +-
net/ipv4/inet_connection_sock.c | 2 +-
net/ipv4/tcp_ipv4.c | 19 +++++++++++--------
net/ipv4/tcp_minisocks.c | 2 +-
net/ipv4/tcp_output.c | 3 ++-
net/ipv6/tcp_ipv6.c | 28 +++++++++++++---------------
10 files changed, 44 insertions(+), 33 deletions(-)
[-- Attachment #2: TCPCT+1a6.patch --]
[-- Type: text/plain, Size: 8878 bytes --]
diff --git a/include/net/request_sock.h b/include/net/request_sock.h
index c719084..c9b50eb 100644
--- a/include/net/request_sock.h
+++ b/include/net/request_sock.h
@@ -27,13 +27,19 @@ struct sk_buff;
struct dst_entry;
struct proto;
+/* empty to "strongly type" an otherwise void parameter.
+ */
+struct request_values {
+};
+
struct request_sock_ops {
int family;
int obj_size;
struct kmem_cache *slab;
char *slab_name;
int (*rtx_syn_ack)(struct sock *sk,
- struct request_sock *req);
+ struct request_sock *req,
+ struct request_values *rvp);
void (*send_ack)(struct sock *sk, struct sk_buff *skb,
struct request_sock *req);
void (*send_reset)(struct sock *sk,
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 325bfcf..ec183fd 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -440,7 +440,8 @@ extern int tcp_connect(struct sock *sk);
extern struct sk_buff * tcp_make_synack(struct sock *sk,
struct dst_entry *dst,
- struct request_sock *req);
+ struct request_sock *req,
+ struct request_values *rvp);
extern int tcp_disconnect(struct sock *sk, int flags);
diff --git a/net/dccp/ipv4.c b/net/dccp/ipv4.c
index 2423a08..efbcfdc 100644
--- a/net/dccp/ipv4.c
+++ b/net/dccp/ipv4.c
@@ -477,7 +477,8 @@ static struct dst_entry* dccp_v4_route_skb(struct net *net, struct sock *sk,
return &rt->u.dst;
}
-static int dccp_v4_send_response(struct sock *sk, struct request_sock *req)
+static int dccp_v4_send_response(struct sock *sk, struct request_sock *req,
+ struct request_values *rv_unused)
{
int err = -1;
struct sk_buff *skb;
@@ -626,7 +627,7 @@ int dccp_v4_conn_request(struct sock *sk, struct sk_buff *skb)
dreq->dreq_iss = dccp_v4_init_sequence(skb);
dreq->dreq_service = service;
- if (dccp_v4_send_response(sk, req))
+ if (dccp_v4_send_response(sk, req, NULL))
goto drop_and_free;
inet_csk_reqsk_queue_hash_add(sk, req, DCCP_TIMEOUT_INIT);
diff --git a/net/dccp/ipv6.c b/net/dccp/ipv6.c
index 50ea91a..6574215 100644
--- a/net/dccp/ipv6.c
+++ b/net/dccp/ipv6.c
@@ -241,7 +241,8 @@ out:
}
-static int dccp_v6_send_response(struct sock *sk, struct request_sock *req)
+static int dccp_v6_send_response(struct sock *sk, struct request_sock *req,
+ struct request_values *rv_unused)
{
struct inet6_request_sock *ireq6 = inet6_rsk(req);
struct ipv6_pinfo *np = inet6_sk(sk);
@@ -468,7 +469,7 @@ static int dccp_v6_conn_request(struct sock *sk, struct sk_buff *skb)
dreq->dreq_iss = dccp_v6_init_sequence(skb);
dreq->dreq_service = service;
- if (dccp_v6_send_response(sk, req))
+ if (dccp_v6_send_response(sk, req, NULL))
goto drop_and_free;
inet6_csk_reqsk_queue_hash_add(sk, req, DCCP_TIMEOUT_INIT);
diff --git a/net/dccp/minisocks.c b/net/dccp/minisocks.c
index 5ca49ce..af226a0 100644
--- a/net/dccp/minisocks.c
+++ b/net/dccp/minisocks.c
@@ -184,7 +184,7 @@ struct sock *dccp_check_req(struct sock *sk, struct sk_buff *skb,
* counter (backoff, monitored by dccp_response_timer).
*/
req->retrans++;
- req->rsk_ops->rtx_syn_ack(sk, req);
+ req->rsk_ops->rtx_syn_ack(sk, req, NULL);
}
/* Network Duplicate, discard packet */
return NULL;
diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c
index 26fb50e..ad098d6 100644
--- a/net/ipv4/inet_connection_sock.c
+++ b/net/ipv4/inet_connection_sock.c
@@ -531,7 +531,7 @@ void inet_csk_reqsk_queue_prune(struct sock *parent,
&expire, &resend);
if (!expire &&
(!resend ||
- !req->rsk_ops->rtx_syn_ack(parent, req) ||
+ !req->rsk_ops->rtx_syn_ack(parent, req, NULL) ||
inet_rsk(req)->acked)) {
unsigned long timeo;
diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c
index cf7f208..094231b 100644
--- a/net/ipv4/tcp_ipv4.c
+++ b/net/ipv4/tcp_ipv4.c
@@ -742,8 +742,9 @@ static void tcp_v4_reqsk_send_ack(struct sock *sk, struct sk_buff *skb,
* This still operates on a request_sock only, not on a big
* socket.
*/
-static int __tcp_v4_send_synack(struct sock *sk, struct request_sock *req,
- struct dst_entry *dst)
+static int __tcp_v4_send_synack(struct sock *sk, struct dst_entry *dst,
+ struct request_sock *req,
+ struct request_values *rvp)
{
const struct inet_request_sock *ireq = inet_rsk(req);
int err = -1;
@@ -753,7 +754,7 @@ static int __tcp_v4_send_synack(struct sock *sk, struct request_sock *req,
if (!dst && (dst = inet_csk_route_req(sk, req)) == NULL)
return -1;
- skb = tcp_make_synack(sk, dst, req);
+ skb = tcp_make_synack(sk, dst, req, rvp);
if (skb) {
struct tcphdr *th = tcp_hdr(skb);
@@ -774,9 +775,10 @@ static int __tcp_v4_send_synack(struct sock *sk, struct request_sock *req,
return err;
}
-static int tcp_v4_send_synack(struct sock *sk, struct request_sock *req)
+static int tcp_v4_send_synack(struct sock *sk, struct request_sock *req,
+ struct request_values *rvp)
{
- return __tcp_v4_send_synack(sk, req, NULL);
+ return __tcp_v4_send_synack(sk, NULL, req, rvp);
}
/*
@@ -1211,13 +1213,13 @@ static struct timewait_sock_ops tcp_timewait_sock_ops = {
int tcp_v4_conn_request(struct sock *sk, struct sk_buff *skb)
{
- struct inet_request_sock *ireq;
struct tcp_options_received tmp_opt;
struct request_sock *req;
+ struct inet_request_sock *ireq;
+ struct dst_entry *dst = NULL;
__be32 saddr = ip_hdr(skb)->saddr;
__be32 daddr = ip_hdr(skb)->daddr;
__u32 isn = TCP_SKB_CB(skb)->when;
- struct dst_entry *dst = NULL;
#ifdef CONFIG_SYN_COOKIES
int want_cookie = 0;
#else
@@ -1337,7 +1339,8 @@ int tcp_v4_conn_request(struct sock *sk, struct sk_buff *skb)
}
tcp_rsk(req)->snt_isn = isn;
- if (__tcp_v4_send_synack(sk, req, dst) || want_cookie)
+ if (__tcp_v4_send_synack(sk, dst, req, NULL)
+ || want_cookie)
goto drop_and_free;
inet_csk_reqsk_queue_hash_add(sk, req, TCP_TIMEOUT_INIT);
diff --git a/net/ipv4/tcp_minisocks.c b/net/ipv4/tcp_minisocks.c
index 4be2228..7a42990 100644
--- a/net/ipv4/tcp_minisocks.c
+++ b/net/ipv4/tcp_minisocks.c
@@ -537,7 +537,7 @@ struct sock *tcp_check_req(struct sock *sk, struct sk_buff *skb,
* Enforce "SYN-ACK" according to figure 8, figure 6
* of RFC793, fixed by RFC1122.
*/
- req->rsk_ops->rtx_syn_ack(sk, req);
+ req->rsk_ops->rtx_syn_ack(sk, req, NULL);
return NULL;
}
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 616c686..1151cb8 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -2224,7 +2224,8 @@ int tcp_send_synack(struct sock *sk)
/* Prepare a SYN-ACK. */
struct sk_buff *tcp_make_synack(struct sock *sk, struct dst_entry *dst,
- struct request_sock *req)
+ struct request_sock *req,
+ struct request_values *rvp)
{
struct inet_request_sock *ireq = inet_rsk(req);
struct tcp_sock *tp = tcp_sk(sk);
diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c
index de70909..3e327bc 100644
--- a/net/ipv6/tcp_ipv6.c
+++ b/net/ipv6/tcp_ipv6.c
@@ -461,7 +461,8 @@ out:
}
-static int tcp_v6_send_synack(struct sock *sk, struct request_sock *req)
+static int tcp_v6_send_synack(struct sock *sk, struct request_sock *req,
+ struct request_values *rvp)
{
struct inet6_request_sock *treq = inet6_rsk(req);
struct ipv6_pinfo *np = inet6_sk(sk);
@@ -499,7 +500,7 @@ static int tcp_v6_send_synack(struct sock *sk, struct request_sock *req)
if ((err = xfrm_lookup(sock_net(sk), &dst, &fl, sk, 0)) < 0)
goto done;
- skb = tcp_make_synack(sk, dst, req);
+ skb = tcp_make_synack(sk, dst, req, rvp);
if (skb) {
struct tcphdr *th = tcp_hdr(skb);
@@ -1161,13 +1162,13 @@ static struct sock *tcp_v6_hnd_req(struct sock *sk,struct sk_buff *skb)
*/
static int tcp_v6_conn_request(struct sock *sk, struct sk_buff *skb)
{
+ struct tcp_options_received tmp_opt;
+ struct request_sock *req;
struct inet6_request_sock *treq;
struct ipv6_pinfo *np = inet6_sk(sk);
- struct tcp_options_received tmp_opt;
struct tcp_sock *tp = tcp_sk(sk);
- struct request_sock *req = NULL;
- __u32 isn = TCP_SKB_CB(skb)->when;
struct dst_entry *dst = __sk_dst_get(sk);
+ __u32 isn = TCP_SKB_CB(skb)->when;
#ifdef CONFIG_SYN_COOKIES
int want_cookie = 0;
#else
@@ -1239,23 +1240,20 @@ static int tcp_v6_conn_request(struct sock *sk, struct sk_buff *skb)
isn = tcp_v6_init_sequence(skb);
}
-
tcp_rsk(req)->snt_isn = isn;
security_inet_conn_request(sk, skb, req);
- if (tcp_v6_send_synack(sk, req))
- goto drop;
+ if (tcp_v6_send_synack(sk, req, NULL)
+ || want_cookie)
+ goto drop_and_free;
- if (!want_cookie) {
- inet6_csk_reqsk_queue_hash_add(sk, req, TCP_TIMEOUT_INIT);
- return 0;
- }
+ inet6_csk_reqsk_queue_hash_add(sk, req, TCP_TIMEOUT_INIT);
+ return 0;
+drop_and_free:
+ reqsk_free(req);
drop:
- if (req)
- reqsk_free(req);
-
return 0; /* don't send reset */
}
--
1.6.3.3
^ permalink raw reply related
* [net-next-2.6 PATCH v6 2/7 RFC] TCPCT part 1b: generate Responder Cookie
From: William Allen Simpson @ 2009-11-13 4:17 UTC (permalink / raw)
To: Linux Kernel Network Developers
In-Reply-To: <4AFCDA9E.8050003@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 807 bytes --]
Define (missing) hash message size for SHA1.
Define hashing size constants specific to TCP cookies, and add new function.
Maintain global secret values for tcp_cookie_generator().
This is a significantly revised implementation of earlier (15-year-old)
Photuris [RFC-2522] code for the KA9Q cooperative multitasking platform.
Linux RCU technique appears to be well-suited to this application, though
neither of the circular queue items are freed.
These functions will also be used in subsequent patches that implement
additional features.
Signed-off-by: William.Allen.Simpson@gmail.com
---
include/linux/cryptohash.h | 1 +
include/net/tcp.h | 8 +++
net/ipv4/tcp.c | 146 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 155 insertions(+), 0 deletions(-)
[-- Attachment #2: TCPCT+1b6.patch --]
[-- Type: text/plain, Size: 6995 bytes --]
diff --git a/include/linux/cryptohash.h b/include/linux/cryptohash.h
index c118b2a..ec78a4b 100644
--- a/include/linux/cryptohash.h
+++ b/include/linux/cryptohash.h
@@ -2,6 +2,7 @@
#define __CRYPTOHASH_H
#define SHA_DIGEST_WORDS 5
+#define SHA_MESSAGE_BYTES (512 /*bits*/ / 8)
#define SHA_WORKSPACE_WORDS 80
void sha_init(__u32 *buf);
diff --git a/include/net/tcp.h b/include/net/tcp.h
index ec183fd..4a99a8e 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -1478,6 +1478,14 @@ struct tcp_request_sock_ops {
#endif
};
+/* Using SHA1 for now, define some constants.
+ */
+#define COOKIE_DIGEST_WORDS (SHA_DIGEST_WORDS)
+#define COOKIE_MESSAGE_WORDS (SHA_MESSAGE_BYTES / 4)
+#define COOKIE_WORKSPACE_WORDS (COOKIE_DIGEST_WORDS + COOKIE_MESSAGE_WORDS)
+
+extern int tcp_cookie_generator(u32 *bakery);
+
extern void tcp_v4_init(void);
extern void tcp_init(void);
diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
index e0cfa63..3ae01bf 100644
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -264,6 +264,7 @@
#include <linux/cache.h>
#include <linux/err.h>
#include <linux/crypto.h>
+#include <linux/time.h>
#include <net/icmp.h>
#include <net/tcp.h>
@@ -2842,6 +2843,141 @@ EXPORT_SYMBOL(tcp_md5_hash_key);
#endif
+/**
+ * Each Responder maintains up to two secret values concurrently for
+ * efficient secret rollover. Each secret value has 4 states:
+ *
+ * Generating. (tcp_secret_generating != tcp_secret_primary)
+ * Generates new Responder-Cookies, but not yet used for primary
+ * verification. This is a short-term state, typically lasting only
+ * one round trip time (RTT).
+ *
+ * Primary. (tcp_secret_generating == tcp_secret_primary)
+ * Used both for generation and primary verification.
+ *
+ * Retiring. (tcp_secret_retiring != tcp_secret_secondary)
+ * Used for verification, until the first failure that can be
+ * verified by the newer Generating secret. At that time, this
+ * cookie's state is changed to Secondary, and the Generating
+ * cookie's state is changed to Primary. This is a short-term state,
+ * typically lasting only one round trip time (RTT).
+ *
+ * Secondary. (tcp_secret_retiring == tcp_secret_secondary)
+ * Used for secondary verification, after primary verification
+ * failures. This state lasts no more than twice the Maximum Segment
+ * Lifetime (2MSL). Then, the secret is discarded.
+ */
+struct tcp_cookie_secret {
+ /* The secret is divided into two parts. The digest part is the
+ * equivalent of previously hashing a secret and saving the state,
+ * and serves as an initialization vector (IV). The message part
+ * serves as the trailing secret.
+ */
+ u32 secrets[COOKIE_WORKSPACE_WORDS];
+ unsigned long expires;
+};
+
+#define TCP_SECRET_1MSL (HZ * TCP_PAWS_MSL)
+#define TCP_SECRET_2MSL (HZ * TCP_PAWS_MSL * 2)
+#define TCP_SECRET_LIFE (HZ * 600)
+
+static struct tcp_cookie_secret tcp_secret_one;
+static struct tcp_cookie_secret tcp_secret_two;
+
+/* Essentially a circular list, without dynamic allocation. */
+static struct tcp_cookie_secret *tcp_secret_generating;
+static struct tcp_cookie_secret *tcp_secret_primary;
+static struct tcp_cookie_secret *tcp_secret_retiring;
+static struct tcp_cookie_secret *tcp_secret_secondary;
+
+static DEFINE_SPINLOCK(tcp_secret_locker);
+
+/* Select a random word in the cookie workspace.
+ */
+static inline u32 tcp_cookie_work(const u32 *ws, const int n)
+{
+ return ws[COOKIE_DIGEST_WORDS + ((COOKIE_MESSAGE_WORDS-1) & ws[n])];
+}
+
+/* Fill bakery[COOKIE_WORKSPACE_WORDS] with generator, updating as needed.
+ * Called in softirq context.
+ * Returns: 0 for success.
+ */
+int tcp_cookie_generator(u32 *bakery)
+{
+ unsigned long jiffy = jiffies;
+
+ if (unlikely(time_after_eq(jiffy, tcp_secret_generating->expires))) {
+ spin_lock_bh(&tcp_secret_locker);
+ if (!time_after_eq(jiffy, tcp_secret_generating->expires)) {
+ /* refreshed by another */
+ spin_unlock_bh(&tcp_secret_locker);
+ memcpy(bakery,
+ &tcp_secret_generating->secrets[0],
+ sizeof(tcp_secret_generating->secrets));
+ } else {
+ u32 secrets[COOKIE_WORKSPACE_WORDS];
+
+ /* still needs refreshing */
+ get_random_bytes(secrets, sizeof(secrets));
+
+ /* The first time, paranoia assumes that the
+ * randomization function isn't as strong. But,
+ * this secret initialization is delayed until
+ * the last possible moment (packet arrival).
+ * Although that time is observable, it is
+ * unpredictably variable. Mash in the most
+ * volatile clock bits available, and expire the
+ * secret extra quickly.
+ */
+ if (unlikely(tcp_secret_primary->expires ==
+ tcp_secret_secondary->expires)) {
+ struct timespec tv;
+
+ getnstimeofday(&tv);
+ secrets[COOKIE_DIGEST_WORDS+0] ^=
+ (u32)tv.tv_nsec;
+
+ tcp_secret_secondary->expires = jiffy
+ + TCP_SECRET_1MSL
+ + (0x0f & tcp_cookie_work(secrets, 0));
+ } else {
+ tcp_secret_secondary->expires = jiffy
+ + TCP_SECRET_LIFE
+ + (0xff & tcp_cookie_work(secrets, 1));
+ tcp_secret_primary->expires = jiffy
+ + TCP_SECRET_2MSL
+ + (0x1f & tcp_cookie_work(secrets, 2));
+ }
+ memcpy(&tcp_secret_secondary->secrets[0],
+ &secrets[0],
+ sizeof(secrets));
+
+ rcu_assign_pointer(tcp_secret_generating,
+ tcp_secret_secondary);
+ rcu_assign_pointer(tcp_secret_retiring,
+ tcp_secret_primary);
+ spin_unlock_bh(&tcp_secret_locker);
+ /* Neither call_rcu() or synchronize_rcu() are needed.
+ * Retiring data is not freed. It is replaced after
+ * further (locked) pointer updates, and a quiet time
+ * (minimum 1MSL, maximum LIFE - 2MSL).
+ */
+ memcpy(bakery,
+ &secrets[0],
+ sizeof(secrets));
+ }
+ } else {
+ rcu_read_lock_bh();
+ memcpy(bakery,
+ &rcu_dereference(tcp_secret_generating)->secrets[0],
+ sizeof(tcp_secret_generating->secrets));
+ rcu_read_unlock_bh();
+ }
+ return 0;
+}
+EXPORT_SYMBOL(tcp_cookie_generator);
+
void tcp_done(struct sock *sk)
{
if (sk->sk_state == TCP_SYN_SENT || sk->sk_state == TCP_SYN_RECV)
@@ -2876,6 +3012,7 @@ void __init tcp_init(void)
struct sk_buff *skb = NULL;
unsigned long nr_pages, limit;
int order, i, max_share;
+ unsigned long jiffy = jiffies;
BUILD_BUG_ON(sizeof(struct tcp_skb_cb) > sizeof(skb->cb));
@@ -2969,6 +3106,15 @@ void __init tcp_init(void)
tcp_hashinfo.ehash_mask + 1, tcp_hashinfo.bhash_size);
tcp_register_congestion_control(&tcp_reno);
+
+ memset(&tcp_secret_one.secrets[0], 0, sizeof(tcp_secret_one.secrets));
+ memset(&tcp_secret_two.secrets[0], 0, sizeof(tcp_secret_two.secrets));
+ tcp_secret_one.expires = jiffy; /* past due */
+ tcp_secret_two.expires = jiffy; /* past due */
+ tcp_secret_generating = &tcp_secret_one;
+ tcp_secret_primary = &tcp_secret_one;
+ tcp_secret_retiring = &tcp_secret_two;
+ tcp_secret_secondary = &tcp_secret_two;
}
EXPORT_SYMBOL(tcp_close);
--
1.6.3.3
^ permalink raw reply related
* [net-next-2.6 PATCH v6 3/7 RFC] TCPCT part 1c: sysctl_tcp_cookie_size, socket option TCP_COOKIE_TRANSACTIONS
From: William Allen Simpson @ 2009-11-13 4:31 UTC (permalink / raw)
To: Linux Kernel Network Developers
In-Reply-To: <4AFCDA9E.8050003@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1190 bytes --]
Define sysctl (tcp_cookie_size) to turn on and off the cookie option
default globally, instead of a compiled configuration option.
Define per socket option (TCP_COOKIE_TRANSACTIONS) for setting constant
data values, retrieving variable cookie values, and other facilities.
Move inline tcp_clear_options() unchanged from net/tcp.h to linux/tcp.h,
near its corresponding struct tcp_options_received (prior to changes).
This is a straightforward re-implementation of an earlier (year-old)
patch that no longer applies cleanly, with permission of the original
author (Adam Langley):
http://thread.gmane.org/gmane.linux.network/102586
These functions will also be used in subsequent patches that implement
additional features.
Requires:
net: TCP_MSS_DEFAULT, TCP_MSS_DESIRED
Signed-off-by: William.Allen.Simpson@gmail.com
---
Documentation/networking/ip-sysctl.txt | 8 +++++++
include/linux/tcp.h | 33 +++++++++++++++++++++++++++++++-
include/net/tcp.h | 6 +----
net/ipv4/sysctl_net_ipv4.c | 8 +++++++
net/ipv4/tcp_output.c | 8 +++++++
5 files changed, 57 insertions(+), 6 deletions(-)
[-- Attachment #2: TCPCT+1c6.patch --]
[-- Type: text/plain, Size: 5089 bytes --]
diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt
index a0e134d..d47c000 100644
--- a/Documentation/networking/ip-sysctl.txt
+++ b/Documentation/networking/ip-sysctl.txt
@@ -164,6 +164,14 @@ tcp_congestion_control - STRING
additional choices may be available based on kernel configuration.
Default is set as part of kernel configuration.
+tcp_cookie_size - INTEGER
+ Default size of TCP Cookie Transactions (TCPCT) option, that may be
+ overridden on a per socket basis by the TCPCT socket option.
+ Values greater than the maximum (16) are interpreted as the maximum.
+ Values greater than zero and less than the minimum (8) are interpreted
+ as the minimum.
+ Default: 0 (off).
+
tcp_dsack - BOOLEAN
Allows TCP to send "duplicate" SACKs.
diff --git a/include/linux/tcp.h b/include/linux/tcp.h
index 32d7d77..eaa3113 100644
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -102,7 +102,9 @@ enum {
#define TCP_QUICKACK 12 /* Block/reenable quick acks */
#define TCP_CONGESTION 13 /* Congestion control algorithm */
#define TCP_MD5SIG 14 /* TCP MD5 Signature (RFC2385) */
+#define TCP_COOKIE_TRANSACTIONS 15 /* TCP Cookie Transactions */
+/* for TCP_INFO socket option */
#define TCPI_OPT_TIMESTAMPS 1
#define TCPI_OPT_SACK 2
#define TCPI_OPT_WSCALE 4
@@ -174,6 +176,30 @@ struct tcp_md5sig {
__u8 tcpm_key[TCP_MD5SIG_MAXKEYLEN]; /* key (binary) */
};
+/* for TCP_COOKIE_TRANSACTIONS (TCPCT) socket option */
+#define TCP_COOKIE_MIN 8 /* 64-bits */
+#define TCP_COOKIE_MAX 16 /* 128-bits */
+#define TCP_COOKIE_PAIR_SIZE (2*TCP_COOKIE_MAX)
+
+/* Flags for both getsockopt and setsockopt */
+#define TCP_COOKIE_IN_ALWAYS (1 << 0) /* Discard SYN without cookie */
+#define TCP_COOKIE_OUT_NEVER (1 << 1) /* Prohibit outgoing cookies,
+ * supercedes everything. */
+
+/* Flags for getsockopt */
+#define TCP_S_DATA_IN (1 << 2) /* Was data received? */
+#define TCP_S_DATA_OUT (1 << 3) /* Was data sent? */
+
+/* TCP_COOKIE_TRANSACTIONS data */
+struct tcp_cookie_transactions {
+ __u16 tcpct_flags; /* see above */
+ __u8 __tcpct_pad1; /* zero */
+ __u8 tcpct_cookie_desired; /* bytes */
+ __u16 tcpct_s_data_desired; /* bytes of variable data */
+ __u16 tcpct_used; /* bytes in value */
+ __u8 tcpct_value[TCP_MSS_DEFAULT];
+};
+
#ifdef __KERNEL__
#include <linux/skbuff.h>
@@ -227,6 +253,11 @@ struct tcp_options_received {
u16 mss_clamp; /* Maximal mss, negotiated at connection setup */
};
+static inline void tcp_clear_options(struct tcp_options_received *rx_opt)
+{
+ rx_opt->tstamp_ok = rx_opt->sack_ok = rx_opt->wscale_ok = rx_opt->snd_wscale = 0;
+}
+
/* This is the max number of SACKS that we'll generate and process. It's safe
* to increse this, although since:
* size = TCPOLEN_SACK_BASE_ALIGNED (4) + n * TCPOLEN_SACK_PERBLOCK (8)
@@ -435,6 +466,6 @@ static inline struct tcp_timewait_sock *tcp_twsk(const struct sock *sk)
return (struct tcp_timewait_sock *)sk;
}
-#endif
+#endif /* __KERNEL__ */
#endif /* _LINUX_TCP_H */
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 4a99a8e..738b65f 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -234,6 +234,7 @@ extern int sysctl_tcp_base_mss;
extern int sysctl_tcp_workaround_signed_windows;
extern int sysctl_tcp_slow_start_after_idle;
extern int sysctl_tcp_max_ssthresh;
+extern int sysctl_tcp_cookie_size;
extern atomic_t tcp_memory_allocated;
extern struct percpu_counter tcp_sockets_allocated;
@@ -340,11 +341,6 @@ static inline void tcp_dec_quickack_mode(struct sock *sk,
extern void tcp_enter_quickack_mode(struct sock *sk);
-static inline void tcp_clear_options(struct tcp_options_received *rx_opt)
-{
- rx_opt->tstamp_ok = rx_opt->sack_ok = rx_opt->wscale_ok = rx_opt->snd_wscale = 0;
-}
-
#define TCP_ECN_OK 1
#define TCP_ECN_QUEUE_CWR 2
#define TCP_ECN_DEMAND_CWR 4
diff --git a/net/ipv4/sysctl_net_ipv4.c b/net/ipv4/sysctl_net_ipv4.c
index 2dcf04d..3422c54 100644
--- a/net/ipv4/sysctl_net_ipv4.c
+++ b/net/ipv4/sysctl_net_ipv4.c
@@ -714,6 +714,14 @@ static struct ctl_table ipv4_table[] = {
},
{
.ctl_name = CTL_UNNUMBERED,
+ .procname = "tcp_cookie_size",
+ .data = &sysctl_tcp_cookie_size,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = proc_dointvec
+ },
+ {
+ .ctl_name = CTL_UNNUMBERED,
.procname = "udp_mem",
.data = &sysctl_udp_mem,
.maxlen = sizeof(sysctl_udp_mem),
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 1151cb8..e59fa5a 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -59,6 +59,14 @@ int sysctl_tcp_base_mss __read_mostly = 512;
/* By default, RFC2861 behavior. */
int sysctl_tcp_slow_start_after_idle __read_mostly = 1;
+#ifdef CONFIG_SYSCTL
+/* By default, let the user enable it. */
+int sysctl_tcp_cookie_size __read_mostly = 0;
+#else
+int sysctl_tcp_cookie_size __read_mostly = TCP_COOKIE_MAX;
+#endif
+
+
/* Account for new data that has been sent to the network. */
static void tcp_event_new_data_sent(struct sock *sk, struct sk_buff *skb)
{
--
1.6.3.3
^ permalink raw reply related
* [net-next-2.6 PATCH 1/7] igb: change type for ring sizes to u16 in igb_set_ring_param
From: Jeff Kirsher @ 2009-11-13 4:36 UTC (permalink / raw)
To: davem; +Cc: netdev, gospo, Alexander Duyck, Jeff Kirsher
From: Alexander Duyck <alexander.h.duyck@intel.com>
Change the type for the ring size values to u16 and use min/max_t instead of
min/max.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/igb/igb_ethtool.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c
index 90b89a8..f2b2825 100644
--- a/drivers/net/igb/igb_ethtool.c
+++ b/drivers/net/igb/igb_ethtool.c
@@ -735,17 +735,17 @@ static int igb_set_ringparam(struct net_device *netdev,
struct igb_adapter *adapter = netdev_priv(netdev);
struct igb_ring *temp_ring;
int i, err = 0;
- u32 new_rx_count, new_tx_count;
+ u16 new_rx_count, new_tx_count;
if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
return -EINVAL;
- new_rx_count = min(ring->rx_pending, (u32)IGB_MAX_RXD);
- new_rx_count = max(new_rx_count, (u32)IGB_MIN_RXD);
+ new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
+ new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
- new_tx_count = min(ring->tx_pending, (u32)IGB_MAX_TXD);
- new_tx_count = max(new_tx_count, (u32)IGB_MIN_TXD);
+ new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
+ new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
if ((new_tx_count == adapter->tx_ring_count) &&
^ permalink raw reply related
* [PATCH] ifb: add multi-queue support
From: Changli Gao @ 2009-11-13 4:37 UTC (permalink / raw)
To: David S. Miller, Stephen Hemminger, Patrick McHardy
Cc: xiaosuo, Eric Dumazet, Tom Herbert, netdev
In-Reply-To: <4AFBD911.6000900@gmail.com>
ifb: add multi-queue support
Add multi-queue support, and one kernel thread is created for per queue.
It can used to emulate multi-queue NIC in software, and distribute work
among CPUs.
gentux linux # modprobe ifb numtxqs=2
gentux linux # ifconfig ifb0 up
gentux linux # pgrep ifb0
18508
18509
gentux linux # taskset -p 1 18508
pid 18508's current affinity mask: 3
pid 18508's new affinity mask: 1
gentux linux # taskset -p 2 18509
pid 18509's current affinity mask: 3
pid 18509's new affinity mask: 2
gentux linux # tc qdisc add dev br0 ingress
gentux linux # tc filter add dev br0 parent ffff: protocol ip basic
action mirred egress redirect dev ifb0
This patch also introduces a ip link option "numtxqs" for specifying the
number of the TX queues. so you can add a new ifb with the command:
ip link add numtxqs 4 type ifb
Signed-off-by: Changli Gao <xiaosuo@gmail.com>
----
drivers/net/ifb.c | 491 ++++++++++++++++++++++++++++++++++--------------
include/linux/if_link.h | 1
net/core/rtnetlink.c | 3
3 files changed, 360 insertions(+), 135 deletions(-)
diff --git a/drivers/net/ifb.c b/drivers/net/ifb.c
index 69c2566..96ab20a 100644
--- a/drivers/net/ifb.c
+++ b/drivers/net/ifb.c
@@ -33,161 +33,162 @@
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/moduleparam.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/kthread.h>
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/if_vlan.h>
+#include <linux/if_pppox.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
#include <net/pkt_sched.h>
#include <net/net_namespace.h>
-#define TX_TIMEOUT (2*HZ)
-
#define TX_Q_LIMIT 32
+
+struct ifb_private_q {
+ struct net_device *dev;
+ struct sk_buff_head rq;
+ wait_queue_head_t wq;
+ struct task_struct *task;
+ unsigned long rx_packets;
+ unsigned long rx_bytes;
+ unsigned long rx_dropped;
+} ____cacheline_aligned_in_smp;
+
struct ifb_private {
- struct tasklet_struct ifb_tasklet;
- int tasklet_pending;
- /* mostly debug stats leave in for now */
- unsigned long st_task_enter; /* tasklet entered */
- unsigned long st_txq_refl_try; /* transmit queue refill attempt */
- unsigned long st_rxq_enter; /* receive queue entered */
- unsigned long st_rx2tx_tran; /* receive to trasmit transfers */
- unsigned long st_rxq_notenter; /*receiveQ not entered, resched */
- unsigned long st_rx_frm_egr; /* received from egress path */
- unsigned long st_rx_frm_ing; /* received from ingress path */
- unsigned long st_rxq_check;
- unsigned long st_rxq_rsch;
- struct sk_buff_head rq;
- struct sk_buff_head tq;
+ struct ifb_private_q *pq;
};
+/* Number of ifb devices to be set up by this module. */
static int numifbs = 2;
+module_param(numifbs, int, 0444);
+MODULE_PARM_DESC(numifbs, "Number of ifb devices");
-static void ri_tasklet(unsigned long dev);
-static netdev_tx_t ifb_xmit(struct sk_buff *skb, struct net_device *dev);
-static int ifb_open(struct net_device *dev);
-static int ifb_close(struct net_device *dev);
+/* Number of TX queues per ifb */
+static unsigned int numtxqs = 1;
+module_param(numtxqs, uint, 0444);
+MODULE_PARM_DESC(numtxqs, "Number of TX queues per ifb");
-static void ri_tasklet(unsigned long dev)
+static int ifb_thread(void *priv)
{
-
- struct net_device *_dev = (struct net_device *)dev;
- struct ifb_private *dp = netdev_priv(_dev);
- struct net_device_stats *stats = &_dev->stats;
- struct netdev_queue *txq;
+ struct ifb_private_q *pq = priv;
+ struct net_device *dev = pq->dev, *_dev;
+ int num = pq - ((struct ifb_private *)netdev_priv(dev))->pq;
+ struct netdev_queue *txq = netdev_get_tx_queue(dev, num);
struct sk_buff *skb;
-
- txq = netdev_get_tx_queue(_dev, 0);
- dp->st_task_enter++;
- if ((skb = skb_peek(&dp->tq)) == NULL) {
- dp->st_txq_refl_try++;
- if (__netif_tx_trylock(txq)) {
- dp->st_rxq_enter++;
- while ((skb = skb_dequeue(&dp->rq)) != NULL) {
- skb_queue_tail(&dp->tq, skb);
- dp->st_rx2tx_tran++;
- }
- __netif_tx_unlock(txq);
- } else {
- /* reschedule */
- dp->st_rxq_notenter++;
- goto resched;
+ DEFINE_WAIT(wait);
+ struct sk_buff_head tq;
+
+ __skb_queue_head_init(&tq);
+ while (1) {
+ /* move skb from rq to tq */
+ while (1) {
+ prepare_to_wait(&pq->wq, &wait, TASK_UNINTERRUPTIBLE);
+ __netif_tx_lock_bh(txq);
+ skb_queue_splice_tail_init(&pq->rq, &tq);
+ if (netif_queue_stopped(dev))
+ netif_wake_queue(dev);
+ __netif_tx_unlock_bh(txq);
+ if (kthread_should_stop() || !skb_queue_empty(&tq))
+ break;
+ schedule();
}
- }
-
- while ((skb = skb_dequeue(&dp->tq)) != NULL) {
- u32 from = G_TC_FROM(skb->tc_verd);
-
- skb->tc_verd = 0;
- skb->tc_verd = SET_TC_NCLS(skb->tc_verd);
- stats->tx_packets++;
- stats->tx_bytes +=skb->len;
-
- rcu_read_lock();
- skb->dev = dev_get_by_index_rcu(&init_net, skb->iif);
- if (!skb->dev) {
- rcu_read_unlock();
- dev_kfree_skb(skb);
- stats->tx_dropped++;
+ finish_wait(&pq->wq, &wait);
+ if (kthread_should_stop()) {
+ __skb_queue_purge(&tq);
break;
}
- rcu_read_unlock();
- skb->iif = _dev->ifindex;
-
- if (from & AT_EGRESS) {
- dp->st_rx_frm_egr++;
- dev_queue_xmit(skb);
- } else if (from & AT_INGRESS) {
- dp->st_rx_frm_ing++;
- skb_pull(skb, skb->dev->hard_header_len);
- netif_rx(skb);
- } else
- BUG();
- }
-
- if (__netif_tx_trylock(txq)) {
- dp->st_rxq_check++;
- if ((skb = skb_peek(&dp->rq)) == NULL) {
- dp->tasklet_pending = 0;
- if (netif_queue_stopped(_dev))
- netif_wake_queue(_dev);
- } else {
- dp->st_rxq_rsch++;
- __netif_tx_unlock(txq);
- goto resched;
+ if (need_resched())
+ schedule();
+
+ /* transfer packets */
+ while ((skb = __skb_dequeue(&tq)) != NULL) {
+ u32 from = G_TC_FROM(skb->tc_verd);
+
+ skb->tc_verd = 0;
+ skb->tc_verd = SET_TC_NCLS(skb->tc_verd);
+ txq->tx_packets++;
+ txq->tx_bytes +=skb->len;
+
+ rcu_read_lock();
+ _dev = dev_get_by_index_rcu(&init_net, skb->iif);
+ if (_dev != NULL) {
+ skb->dev = _dev;
+ skb->iif = dev->ifindex;
+ if (from & AT_EGRESS) {
+ dev_queue_xmit(skb);
+ } else if (from & AT_INGRESS) {
+ skb_pull(skb, _dev->hard_header_len);
+ netif_rx_ni(skb);
+ } else {
+ BUG();
+ }
+ } else {
+ dev_kfree_skb(skb);
+ txq->tx_dropped++;
+ }
+ rcu_read_unlock();
}
- __netif_tx_unlock(txq);
- } else {
-resched:
- dp->tasklet_pending = 1;
- tasklet_schedule(&dp->ifb_tasklet);
}
+ return 0;
}
-static const struct net_device_ops ifb_netdev_ops = {
- .ndo_open = ifb_open,
- .ndo_stop = ifb_close,
- .ndo_start_xmit = ifb_xmit,
- .ndo_validate_addr = eth_validate_addr,
-};
-
-static void ifb_setup(struct net_device *dev)
+struct net_device_stats* ifb_get_stats(struct net_device *dev)
{
- /* Initialize the device structure. */
- dev->destructor = free_netdev;
- dev->netdev_ops = &ifb_netdev_ops;
+ struct net_device_stats *stats = &dev->stats;
+ struct ifb_private *dp = netdev_priv(dev);
+ struct ifb_private_q *pq = dp->pq;
+ struct netdev_queue *txq;
+ int i;
+ unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
+ unsigned long tx_packets = 0, tx_bytes = 0, tx_dropped = 0;
+
+ for (i = 0; i < dev->real_num_tx_queues; i++) {
+ rx_packets += pq[i].rx_packets;
+ rx_bytes += pq[i].rx_bytes;
+ rx_dropped += pq[i].rx_dropped;
+ txq = netdev_get_tx_queue(dev, i);
+ tx_packets += txq->tx_packets;
+ tx_bytes += txq->tx_bytes;
+ tx_dropped += txq->tx_dropped;
+ }
- /* Fill in device structure with ethernet-generic values. */
- ether_setup(dev);
- dev->tx_queue_len = TX_Q_LIMIT;
+ stats->rx_packets = rx_packets;
+ stats->rx_bytes = rx_bytes;
+ stats->rx_dropped = rx_dropped;
+ stats->tx_packets = tx_packets;
+ stats->tx_bytes = tx_bytes;
+ stats->tx_dropped = tx_dropped;
- dev->flags |= IFF_NOARP;
- dev->flags &= ~IFF_MULTICAST;
- dev->priv_flags &= ~IFF_XMIT_DST_RELEASE;
- random_ether_addr(dev->dev_addr);
+ return stats;
}
static netdev_tx_t ifb_xmit(struct sk_buff *skb, struct net_device *dev)
{
- struct ifb_private *dp = netdev_priv(dev);
- struct net_device_stats *stats = &dev->stats;
u32 from = G_TC_FROM(skb->tc_verd);
+ int num = skb_get_queue_mapping(skb);
+ struct ifb_private *dp = netdev_priv(dev);
+ struct ifb_private_q *pq = dp->pq + num;
+ struct netdev_queue *txq = netdev_get_tx_queue(dev, num);
- stats->rx_packets++;
- stats->rx_bytes+=skb->len;
+ pq->rx_packets++;
+ pq->rx_bytes += skb->len;
if (!(from & (AT_INGRESS|AT_EGRESS)) || !skb->iif) {
dev_kfree_skb(skb);
- stats->rx_dropped++;
+ pq->rx_dropped++;
return NETDEV_TX_OK;
}
- if (skb_queue_len(&dp->rq) >= dev->tx_queue_len) {
+ txq->trans_start = jiffies;
+ __skb_queue_tail(&pq->rq, skb);
+ if (skb_queue_len(&pq->rq) >= dev->tx_queue_len)
netif_stop_queue(dev);
- }
-
- dev->trans_start = jiffies;
- skb_queue_tail(&dp->rq, skb);
- if (!dp->tasklet_pending) {
- dp->tasklet_pending = 1;
- tasklet_schedule(&dp->ifb_tasklet);
- }
+ if (skb_queue_len(&pq->rq) == 1)
+ wake_up(&pq->wq);
return NETDEV_TX_OK;
}
@@ -195,26 +196,230 @@ static netdev_tx_t ifb_xmit(struct sk_buff *skb,
struct net_device *dev)
static int ifb_close(struct net_device *dev)
{
struct ifb_private *dp = netdev_priv(dev);
+ struct ifb_private_q *pq = dp->pq;
+ int i;
- tasklet_kill(&dp->ifb_tasklet);
netif_stop_queue(dev);
- skb_queue_purge(&dp->rq);
- skb_queue_purge(&dp->tq);
+ for (i = 0; i < dev->real_num_tx_queues; i++) {
+ kthread_stop(pq[i].task);
+ __skb_queue_purge(&pq[i].rq);
+ }
+
return 0;
}
static int ifb_open(struct net_device *dev)
{
struct ifb_private *dp = netdev_priv(dev);
-
- tasklet_init(&dp->ifb_tasklet, ri_tasklet, (unsigned long)dev);
- skb_queue_head_init(&dp->rq);
- skb_queue_head_init(&dp->tq);
+ struct ifb_private_q *pq = dp->pq;
+ int i;
+
+ for (i = 0; i < dev->real_num_tx_queues; i++) {
+ pq[i].task = kthread_run(ifb_thread, &pq[i], "%s/%d", dev->name,
+ i);
+ if (IS_ERR(pq[i].task)) {
+ int err = PTR_ERR(pq[i].task);
+ while (--i >= 0)
+ kthread_stop(pq[i].task);
+ return err;
+ }
+ }
netif_start_queue(dev);
return 0;
}
+static u32 simple_tx_hashrnd;
+
+static inline __be16 pppoe_proto(const struct sk_buff *skb)
+{
+ return *((__be16 *)(skb_mac_header(skb) + ETH_HLEN +
+ sizeof(struct pppoe_hdr)));
+}
+
+static u16 ifb_select_queue(struct net_device *dev, struct sk_buff *skb)
+{
+ u32 addr1, addr2;
+ u32 hash;
+ union {
+ u16 in16[2];
+ u32 in32;
+ } ports;
+ u8 ip_proto;
+ unsigned int pull_len, proto_pull_len;
+ int ihl;
+
+ if ((hash = skb_rx_queue_recorded(skb))) {
+ while (hash >= dev->real_num_tx_queues)
+ hash -= dev->real_num_tx_queues;
+ return hash;
+ }
+
+ /* act_mirred pushed the skb before calling dev_queue_xmit() */
+ proto_pull_len = 0;
+ pull_len = skb_network_header(skb) - skb->data;
+ if (unlikely(skb_pull(skb, pull_len) == NULL)) {
+ pull_len = 0;
+ goto process_other;
+ }
+
+ ihl = 0;
+ switch (skb->protocol) {
+ case __constant_htons(ETH_P_8021Q):
+ if (unlikely(skb_pull(skb, VLAN_HLEN) == NULL))
+ goto process_other;
+ pull_len += VLAN_HLEN;
+ skb->network_header += VLAN_HLEN;
+ proto_pull_len = VLAN_HLEN;
+ switch (vlan_eth_hdr(skb)->h_vlan_encapsulated_proto) {
+ case __constant_htons(ETH_P_IP):
+ goto process_ip;
+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
+ case __constant_htons(ETH_P_IPV6):
+ goto process_ipv6;
+#endif
+ default:
+ goto process_other;
+ }
+ break;
+ case __constant_htons(ETH_P_PPP_SES):
+ if (unlikely(skb_pull(skb, PPPOE_SES_HLEN) == NULL))
+ goto process_other;
+ pull_len += PPPOE_SES_HLEN;
+ skb->network_header += PPPOE_SES_HLEN;
+ proto_pull_len = PPPOE_SES_HLEN;
+ switch (pppoe_proto(skb)) {
+ case __constant_htons(ETH_P_IP):
+ goto process_ip;
+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
+ case __constant_htons(ETH_P_IPV6):
+ goto process_ipv6;
+#endif
+ default:
+ goto process_other;
+ }
+ break;
+ case __constant_htons(ETH_P_IP):
+process_ip:
+ if (unlikely(!pskb_may_pull(skb, sizeof(struct iphdr))))
+ goto process_other;
+ if (!(ip_hdr(skb)->frag_off & htons(IP_MF | IP_OFFSET)))
+ ip_proto = ip_hdr(skb)->protocol;
+ else
+ ip_proto = 0;
+ addr1 = ip_hdr(skb)->saddr;
+ addr2 = ip_hdr(skb)->daddr;
+ ihl = ip_hdrlen(skb);
+ break;
+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
+ case __constant_htons(ETH_P_IPV6):
+process_ipv6:
+ if (unlikely(!pskb_may_pull(skb, sizeof(struct ipv6hdr))))
+ goto process_other;
+ addr1 = ipv6_hdr(skb)->saddr.s6_addr32[3];
+ addr2 = ipv6_hdr(skb)->daddr.s6_addr32[3];
+ ihl = ipv6_skip_exthdr(skb, sizeof(struct ipv6hdr), &ip_proto);
+ if (unlikely(ihl < 0))
+ goto process_other_trans;
+ break;
+#endif
+ default:
+process_other:
+ if (pull_len != 0) {
+ skb_push(skb, pull_len);
+ if (proto_pull_len != 0)
+ skb->network_header -= proto_pull_len;
+ }
+ return skb->protocol % dev->real_num_tx_queues;
+ }
+ if (addr1 > addr2)
+ swap(addr1, addr2);
+
+ switch (ip_proto) {
+ case IPPROTO_TCP:
+ case IPPROTO_UDP:
+ case IPPROTO_DCCP:
+ case IPPROTO_ESP:
+ case IPPROTO_AH:
+ case IPPROTO_SCTP:
+ case IPPROTO_UDPLITE:
+ if (unlikely(skb_copy_bits(skb, ihl, &ports.in32, 4) < 0))
+ goto process_other_trans;
+ if (ports.in16[0] > ports.in16[1])
+ swap(ports.in16[0], ports.in16[1]);
+ break;
+ default:
+process_other_trans:
+ ports.in32 = 0;
+ break;
+ }
+
+ if (pull_len != 0) {
+ skb_push(skb, pull_len);
+ if (proto_pull_len != 0)
+ skb->network_header -= proto_pull_len;
+ }
+
+ hash = jhash_3words(addr1, addr2, ports.in32,
+ simple_tx_hashrnd ^ ip_proto);
+
+ return (u16) (((u64) hash * dev->real_num_tx_queues) >> 32);
+}
+
+static int ifb_init(struct net_device *dev)
+{
+ struct ifb_private *dp = netdev_priv(dev);
+ struct ifb_private_q *pq = dp->pq;
+ int i;
+
+ pq = kcalloc(dev->real_num_tx_queues, sizeof(*pq), GFP_KERNEL);
+ if (pq == NULL)
+ return -ENOMEM;
+ dp->pq = pq;
+
+ for (i = 0; i < dev->real_num_tx_queues; i++) {
+ pq[i].dev = dev;
+ __skb_queue_head_init(&pq[i].rq);
+ init_waitqueue_head(&pq[i].wq);
+ }
+
+ return 0;
+}
+
+static void ifb_uninit(struct net_device *dev)
+{
+ struct ifb_private *dp = netdev_priv(dev);
+
+ kfree(dp->pq);
+}
+
+static const struct net_device_ops ifb_netdev_ops = {
+ .ndo_init = ifb_init,
+ .ndo_uninit = ifb_uninit,
+ .ndo_open = ifb_open,
+ .ndo_stop = ifb_close,
+ .ndo_start_xmit = ifb_xmit,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_select_queue = ifb_select_queue,
+ .ndo_get_stats = ifb_get_stats,
+};
+
+static void ifb_setup(struct net_device *dev)
+{
+ /* Initialize the device structure. */
+ dev->destructor = free_netdev;
+ dev->netdev_ops = &ifb_netdev_ops;
+
+ /* Fill in device structure with ethernet-generic values. */
+ ether_setup(dev);
+ dev->tx_queue_len = TX_Q_LIMIT;
+
+ dev->flags |= IFF_NOARP;
+ dev->flags &= ~IFF_MULTICAST;
+ dev->priv_flags &= ~IFF_XMIT_DST_RELEASE;
+ random_ether_addr(dev->dev_addr);
+}
+
static int ifb_validate(struct nlattr *tb[], struct nlattr *data[])
{
if (tb[IFLA_ADDRESS]) {
@@ -226,25 +431,38 @@ static int ifb_validate(struct nlattr *tb[],
struct nlattr *data[])
return 0;
}
+static int ifb_get_tx_queues(struct net *net, struct nlattr *tb[],
+ unsigned int *num_tx_queues,
+ unsigned int *real_num_tx_queues)
+{
+ if (tb[IFLA_NTXQ]) {
+ *num_tx_queues = nla_get_u32(tb[IFLA_NTXQ]);
+ if (*num_tx_queues < 1)
+ return -EINVAL;
+ *real_num_tx_queues = *num_tx_queues;
+ } else {
+ *num_tx_queues = numtxqs;
+ *real_num_tx_queues = numtxqs;
+ }
+
+ return 0;
+}
+
static struct rtnl_link_ops ifb_link_ops __read_mostly = {
.kind = "ifb",
- .priv_size = sizeof(struct ifb_private),
.setup = ifb_setup,
.validate = ifb_validate,
+ .get_tx_queues = ifb_get_tx_queues,
+ .priv_size = sizeof(struct ifb_private),
};
-/* Number of ifb devices to be set up by this module. */
-module_param(numifbs, int, 0);
-MODULE_PARM_DESC(numifbs, "Number of ifb devices");
-
static int __init ifb_init_one(int index)
{
struct net_device *dev_ifb;
int err;
- dev_ifb = alloc_netdev(sizeof(struct ifb_private),
- "ifb%d", ifb_setup);
-
+ dev_ifb = alloc_netdev_mq(sizeof(struct ifb_private), "ifb%d",
+ ifb_setup, numtxqs);
if (!dev_ifb)
return -ENOMEM;
@@ -268,9 +486,12 @@ static int __init ifb_init_module(void)
{
int i, err;
+ if (numtxqs < 1)
+ return -EINVAL;
+
+ get_random_bytes(&simple_tx_hashrnd, 4);
rtnl_lock();
err = __rtnl_link_register(&ifb_link_ops);
-
for (i = 0; i < numifbs && !err; i++)
err = ifb_init_one(i);
if (err)
diff --git a/include/linux/if_link.h b/include/linux/if_link.h
index 1d3b242..99da411 100644
--- a/include/linux/if_link.h
+++ b/include/linux/if_link.h
@@ -78,6 +78,7 @@ enum {
#define IFLA_LINKINFO IFLA_LINKINFO
IFLA_NET_NS_PID,
IFLA_IFALIAS,
+ IFLA_NTXQ,
__IFLA_MAX
};
diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
index 33148a5..1cbe555 100644
--- a/net/core/rtnetlink.c
+++ b/net/core/rtnetlink.c
@@ -597,6 +597,7 @@ static inline size_t if_nlmsg_size(const struct
net_device *dev)
+ nla_total_size(4) /* IFLA_MASTER */
+ nla_total_size(1) /* IFLA_OPERSTATE */
+ nla_total_size(1) /* IFLA_LINKMODE */
+ + nla_total_size(4) /* IFLA_NTXQ */
+ rtnl_link_get_size(dev); /* IFLA_LINKINFO */
}
@@ -627,6 +628,7 @@ static int rtnl_fill_ifinfo(struct sk_buff *skb,
struct net_device *dev,
netif_running(dev) ? dev->operstate : IF_OPER_DOWN);
NLA_PUT_U8(skb, IFLA_LINKMODE, dev->link_mode);
NLA_PUT_U32(skb, IFLA_MTU, dev->mtu);
+ NLA_PUT_U32(skb, IFLA_NTXQ, dev->real_num_tx_queues);
if (dev->ifindex != dev->iflink)
NLA_PUT_U32(skb, IFLA_LINK, dev->iflink);
@@ -725,6 +727,7 @@ const struct nla_policy ifla_policy[IFLA_MAX+1] = {
[IFLA_LINKINFO] = { .type = NLA_NESTED },
[IFLA_NET_NS_PID] = { .type = NLA_U32 },
[IFLA_IFALIAS] = { .type = NLA_STRING, .len = IFALIASZ-1 },
+ [IFLA_NTXQ] = { .type = NLA_U32 },
};
EXPORT_SYMBOL(ifla_policy);
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