* Re: [PATCH] mwifiex: Fix skipped vendor specific IEs
From: Kalle Valo @ 2018-07-31 6:58 UTC (permalink / raw)
To: roman.stratiienko
Cc: akarwar, nishants, linux-wireless, netdev, linux-kernel,
sergei.shtylyov, Roman Stratiienko
In-Reply-To: <1532432847-2885-1-git-send-email-roman.stratiienko@globallogic.com>
roman.stratiienko@globallogic.com wrote:
> From: Roman Stratiienko <roman.stratiienko@globallogic.com>
>
> Mwifiex firmware inserts only Microsoft information element
> Allow other vendor specific IEs to pass from userspace
>
> Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
When you submit a new version fo a patch please always add a version number to
the title and include a changelog:
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches#patch_version_missing
But this is for the future, no need to resend this patch.
--
https://patchwork.kernel.org/patch/10541923/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] net/wireless/intersil/hostap: fix defined but not usedwarnings
From: Kalle Valo @ 2018-07-31 7:07 UTC (permalink / raw)
To: Randy Dunlap
Cc: Jouni Malinen, linux-wireless-u79uwXL29TY76Z2rM5mHXA,
David Miller, netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <b2a357a4-dfae-5561-deda-33b2124fc4cf-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
Randy Dunlap <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org> wrote:
> From: Randy Dunlap <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
>
> Fix build warnings in drivers/net/wireless/intersil/hostap/ when
> CONFIG_PROC_FS is not enabled by marking the unused functions as
> __maybe_unused.
>
> ../drivers/net/wireless/intersil/hostap/hostap_ap.c:70:12: warning: 'ap_debug_proc_show' defined but not used [-Wunused-function]
> ../drivers/net/wireless/intersil/hostap/hostap_ap.c:994:12: warning: 'prism2_sta_proc_show' defined but not used [-Wunused-function]
> ../drivers/net/wireless/intersil/hostap/hostap_proc.c:16:12: warning: 'prism2_debug_proc_show' defined but not used [-Wunused-function]
> ../drivers/net/wireless/intersil/hostap/hostap_proc.c:49:12: warning: 'prism2_stats_proc_show' defined but not used [-Wunused-function]
> ../drivers/net/wireless/intersil/hostap/hostap_proc.c:177:12: warning: 'prism2_crypt_proc_show' defined but not used [-Wunused-function]
> ../drivers/net/wireless/intersil/hostap/hostap_hw.c:2901:12: warning: 'prism2_registers_proc_show' defined but not used [-Wunused-function]
>
> Signed-off-by: Randy Dunlap <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
> Cc: Jouni Malinen <j@w1.fi>
> Cc: linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: Kalle Valo <kvalo-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: "David S. Miller" <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>
> Cc: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
I'll drop this as I take Yue's patch.
Patch set to Changes Requested.
--
https://patchwork.kernel.org/patch/10512915/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] mwifiex: Fix skipped vendor specific IEs
From: Kalle Valo @ 2018-07-31 7:13 UTC (permalink / raw)
To: roman.stratiienko
Cc: akarwar, nishants, linux-wireless, netdev, linux-kernel,
sergei.shtylyov, Roman Stratiienko
In-Reply-To: <1532432847-2885-1-git-send-email-roman.stratiienko@globallogic.com>
roman.stratiienko@globallogic.com wrote:
> From: Roman Stratiienko <roman.stratiienko@globallogic.com>
>
> Mwifiex firmware inserts only Microsoft information element
> Allow other vendor specific IEs to pass from userspace
>
> Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Patch applied to wireless-drivers-next.git, thanks.
bfc83ea196ad mwifiex: Fix skipped vendor specific IEs
--
https://patchwork.kernel.org/patch/10541923/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] airo: remove unused variables len and dev and clean upformatting
From: Kalle Valo @ 2018-07-31 7:17 UTC (permalink / raw)
To: Colin King
Cc: David S . Miller, linux-wireless, netdev, kernel-janitors,
linux-kernel
In-Reply-To: <20180709133843.15615-1-colin.king@canonical.com>
Colin King <colin.king@canonical.com> wrote:
> From: Colin Ian King <colin.king@canonical.com>
>
> Variables len and dev assigned values but are never used hence they
> are redundant and can be removed. Also add in white space in for-loop
> and remove some { } braces on if statement.
>
> Cleans up clang warnings:
> warning: variable 'len' set but not used [-Wunused-but-set-variable]
> warning: variable 'dev' set but not used [-Wunused-but-set-variable]
>
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
Patch applied to wireless-drivers-next.git, thanks.
d01a4e04dab7 airo: remove unused variables len and dev and clean up formatting
--
https://patchwork.kernel.org/patch/10514607/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] ipw2x00: remove redundant variables len, ret, reason and crypt
From: Kalle Valo @ 2018-07-31 7:18 UTC (permalink / raw)
To: Colin King
Cc: Stanislav Yakovlev, David S . Miller,
linux-wireless-u79uwXL29TY76Z2rM5mHXA,
kernel-janitors-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20180711071212.3018-1-colin.king-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org>
Colin King <colin.king-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org> wrote:
> From: Colin Ian King <colin.king-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org>
>
> Variables len, ret, reason and crypt are assigned values that
> are never read, hence they are redundant and can be removed.
>
> Note: For the variable ret, a return code is being assigned, but
> this is not returned and 0 is currently being returned, I believe
> this is OK.
>
> Cleans up clang warnings:
> warning: variable 'len' set but not used [-Wunused-but-set-variable]
> variable 'ret' set but not used [-Wunused-but-set-variable]
> warning: variable 'reason' set but not used [-Wunused-but-set-variable]
> warning: variable 'crypt' set but not used [-Wunused-but-set-variable]
>
> Signed-off-by: Colin Ian King <colin.king-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org>
Patch applied to wireless-drivers-next.git, thanks.
0e139e97f58e ipw2x00: remove redundant variables len, ret, reason and crypt
--
https://patchwork.kernel.org/patch/10518849/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] iwlegacy: remove several redundant variables
From: Kalle Valo @ 2018-07-31 7:19 UTC (permalink / raw)
To: Colin King
Cc: Stanislaw Gruszka, David S . Miller, linux-wireless, netdev,
kernel-janitors, linux-kernel
In-Reply-To: <20180711074253.4192-1-colin.king@canonical.com>
Colin King <colin.king@canonical.com> wrote:
> From: Colin Ian King <colin.king@canonical.com>
>
> Variables id, unicast, write, conf, a_band, accum_tx and ucode are
> assigned a value but it is never read, hence they are redundant and
> can be removed.
>
> Cleans up clang warnings:
> warning: variable 'id' set but not used [-Wunused-but-set-variable]
> warning: variable 'unicast' set but not used [-Wunused-but-set-variable]
> warning: variable 'write' set but not used [-Wunused-but-set-variable]
> warning: variable 'conf' set but not used [-Wunused-but-set-variable]
> warning: variable 'a_band' set but not used [-Wunused-but-set-variable]
> warning: variable 'tx' set but not used [-Wunused-but-set-variable]
> warning: variable 'accum_tx' set but not used [-Wunused-but-set-variable]
> warning: variable 'ucode' set but not used [-Wunused-but-set-variable]
>
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
> Acked-by: Stanislaw Gruszka <sgruszka@redhat.com>
Patch applied to wireless-drivers-next.git, thanks.
454127ad36fb iwlegacy: remove several redundant variables
--
https://patchwork.kernel.org/patch/10519029/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] ray_cs: remove redundant pointer 'p'
From: Kalle Valo @ 2018-07-31 7:20 UTC (permalink / raw)
To: Colin King
Cc: David S . Miller, linux-wireless, netdev, kernel-janitors,
linux-kernel
In-Reply-To: <20180720180740.21018-1-colin.king@canonical.com>
Colin King <colin.king@canonical.com> wrote:
> From: Colin Ian King <colin.king@canonical.com>
>
> Pointer 'p' is being assigned but is never used hence it is
> redundant and can be removed. Also re-work if statement to remove
> redundant assignment of p.
>
> Cleans up clang warning:
> warning: variable 'p' set but not used [-Wunused-but-set-variable]
>
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
Patch applied to wireless-drivers-next.git, thanks.
f21bcefcf91c ray_cs: remove redundant pointer 'p'
--
https://patchwork.kernel.org/patch/10538143/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] hostap: hide unused procfs helpers
From: Kalle Valo @ 2018-07-31 7:21 UTC (permalink / raw)
To: YueHaibing; +Cc: j, linux-kernel, netdev, linux-wireless, davem, YueHaibing
In-Reply-To: <20180713070317.6724-1-yuehaibing@huawei.com>
YueHaibing <yuehaibing@huawei.com> wrote:
> When CONFIG_PROC_FS isn't set, gcc warning this:
>
> drivers/net/wireless/intersil/hostap/hostap_hw.c:2901:12: warning: ‘prism2_registers_proc_show’ defined but not used [-Wunused-function]
> static int prism2_registers_proc_show(struct seq_file *m, void *v)
>
> drivers/net/wireless/intersil/hostap/hostap_proc.c:16:12: warning: ‘prism2_debug_proc_show’ defined but not used [-Wunused-function]
> static int prism2_debug_proc_show(struct seq_file *m, void *v)
> ^
> drivers/net/wireless/intersil/hostap/hostap_proc.c:49:12: warning: ‘prism2_stats_proc_show’ defined but not used [-Wunused-function]
> static int prism2_stats_proc_show(struct seq_file *m, void *v)
> ^
> drivers/net/wireless/intersil/hostap/hostap_proc.c:177:12: warning: ‘prism2_crypt_proc_show’ defined but not used [-Wunused-function]
> static int prism2_crypt_proc_show(struct seq_file *m, void *v)
> ^
>
> fix this by adding #ifdef around them.
> hfa384x_read_reg is only used by prism2_registers_proc_show,so move it
> into #ifdef.
>
> Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Patch applied to wireless-drivers-next.git, thanks.
6ade689711ee hostap: hide unused procfs helpers
--
https://patchwork.kernel.org/patch/10522651/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] wlcore: remove duplicate \n for some warnings
From: Kalle Valo @ 2018-07-31 7:23 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Arnd Bergmann, Reizer, Eyal, Kees Cook, H. Nikolaus Schaller,
linux-wireless, netdev, linux-kernel, letux-kernel, kernel
In-Reply-To: <af660348ade58fd33396d2dca432536d2ac85cf7.1532498079.git.hns@goldelico.com>
"H. Nikolaus Schaller" <hns@goldelico.com> wrote:
> wl1271_warning() already appends a \n to the format,
> so adding one to the warning string gives empty lines in the log.
>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Patch applied to wireless-drivers-next.git, thanks.
18dc5a4bbcc5 wlcore: remove duplicate \n for some warnings
--
https://patchwork.kernel.org/patch/10543473/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] atmel: Replace mdelay() with msleep() in probe_atmel_card()
From: Kalle Valo @ 2018-07-31 7:25 UTC (permalink / raw)
To: Jia-Ju Bai; +Cc: simon, linux-wireless, netdev, linux-kernel, Jia-Ju Bai
In-Reply-To: <20180727084535.3848-1-baijiaju1990@gmail.com>
Jia-Ju Bai <baijiaju1990@gmail.com> wrote:
> probe_atmel_card() is never called in atomic context.
> It calls mdelay() to busily wait, which is not necessary.
> mdelay() can be replaced with msleep().
>
> This is found by a static analysis tool named DCNS written by myself.
>
> Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Patch applied to wireless-drivers-next.git, thanks.
5685bee313e9 atmel: Replace mdelay() with msleep() in probe_atmel_card()
--
https://patchwork.kernel.org/patch/10546747/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH] rtl818x: Replace mdelay() with msleep() in rtl8225se_rf_init
From: Kalle Valo @ 2018-07-31 7:27 UTC (permalink / raw)
To: Jia-Ju Bai
Cc: linux-wireless-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Jia-Ju Bai
In-Reply-To: <20180727085045.3949-1-baijiaju1990-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Jia-Ju Bai <baijiaju1990-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> rtl8225se_rf_init() is never called in atomic context.
> It calls mdelay() to busily wait, which is not necessary.
> mdelay() can be replaced with msleep().
> This patch only replaces the mdelay() that has >20ms time to wait.
>
> This is found by a static analysis tool named DCNS written by myself.
>
> Signed-off-by: Jia-Ju Bai <baijiaju1990-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Patch applied to wireless-drivers-next.git, thanks.
622e938240db rtl818x: Replace mdelay() with msleep() in rtl8225se_rf_init
--
https://patchwork.kernel.org/patch/10546749/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* [PATCH net-next 1/2] rds: rds_ib_recv_alloc_cache() should call alloc_percpu_gfp() instead
From: Ka-Cheong Poon @ 2018-07-31 5:48 UTC (permalink / raw)
To: netdev; +Cc: santosh.shilimkar, davem, rds-devel
Currently, rds_ib_conn_alloc() calls rds_ib_recv_alloc_caches()
without passing along the gfp_t flag. But rds_ib_recv_alloc_caches()
and rds_ib_recv_alloc_cache() should take a gfp_t parameter so that
rds_ib_recv_alloc_cache() can call alloc_percpu_gfp() using the
correct flag instead of calling alloc_percpu().
Signed-off-by: Ka-Cheong Poon <ka-cheong.poon@oracle.com>
---
net/rds/ib.h | 2 +-
net/rds/ib_cm.c | 2 +-
net/rds/ib_recv.c | 10 +++++-----
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/net/rds/ib.h b/net/rds/ib.h
index beb95b8..73427ff 100644
--- a/net/rds/ib.h
+++ b/net/rds/ib.h
@@ -400,7 +400,7 @@ int rds_ib_update_ipaddr(struct rds_ib_device *rds_ibdev,
int rds_ib_recv_init(void);
void rds_ib_recv_exit(void);
int rds_ib_recv_path(struct rds_conn_path *conn);
-int rds_ib_recv_alloc_caches(struct rds_ib_connection *ic);
+int rds_ib_recv_alloc_caches(struct rds_ib_connection *ic, gfp_t gfp);
void rds_ib_recv_free_caches(struct rds_ib_connection *ic);
void rds_ib_recv_refill(struct rds_connection *conn, int prefill, gfp_t gfp);
void rds_ib_inc_free(struct rds_incoming *inc);
diff --git a/net/rds/ib_cm.c b/net/rds/ib_cm.c
index a33b82d..0d654d9 100644
--- a/net/rds/ib_cm.c
+++ b/net/rds/ib_cm.c
@@ -1102,7 +1102,7 @@ int rds_ib_conn_alloc(struct rds_connection *conn, gfp_t gfp)
if (!ic)
return -ENOMEM;
- ret = rds_ib_recv_alloc_caches(ic);
+ ret = rds_ib_recv_alloc_caches(ic, gfp);
if (ret) {
kfree(ic);
return ret;
diff --git a/net/rds/ib_recv.c b/net/rds/ib_recv.c
index 557ccbb..d300186 100644
--- a/net/rds/ib_recv.c
+++ b/net/rds/ib_recv.c
@@ -98,12 +98,12 @@ static void rds_ib_cache_xfer_to_ready(struct rds_ib_refill_cache *cache)
}
}
-static int rds_ib_recv_alloc_cache(struct rds_ib_refill_cache *cache)
+static int rds_ib_recv_alloc_cache(struct rds_ib_refill_cache *cache, gfp_t gfp)
{
struct rds_ib_cache_head *head;
int cpu;
- cache->percpu = alloc_percpu(struct rds_ib_cache_head);
+ cache->percpu = alloc_percpu_gfp(struct rds_ib_cache_head, gfp);
if (!cache->percpu)
return -ENOMEM;
@@ -118,13 +118,13 @@ static int rds_ib_recv_alloc_cache(struct rds_ib_refill_cache *cache)
return 0;
}
-int rds_ib_recv_alloc_caches(struct rds_ib_connection *ic)
+int rds_ib_recv_alloc_caches(struct rds_ib_connection *ic, gfp_t gfp)
{
int ret;
- ret = rds_ib_recv_alloc_cache(&ic->i_cache_incs);
+ ret = rds_ib_recv_alloc_cache(&ic->i_cache_incs, gfp);
if (!ret) {
- ret = rds_ib_recv_alloc_cache(&ic->i_cache_frags);
+ ret = rds_ib_recv_alloc_cache(&ic->i_cache_frags, gfp);
if (ret)
free_percpu(ic->i_cache_incs.percpu);
}
--
1.8.3.1
^ permalink raw reply related
* [PATCH net-next 2/2] rds: Remove IPv6 dependency
From: Ka-Cheong Poon @ 2018-07-31 5:48 UTC (permalink / raw)
To: netdev; +Cc: santosh.shilimkar, davem, rds-devel
In-Reply-To: <1533016122-12654-1-git-send-email-ka-cheong.poon@oracle.com>
This patch removes the IPv6 dependency from RDS.
Signed-off-by: Ka-Cheong Poon <ka-cheong.poon@oracle.com>
---
net/rds/Kconfig | 2 +-
net/rds/af_rds.c | 32 +++++++++++++++++++-------------
net/rds/bind.c | 4 +++-
net/rds/connection.c | 26 ++++++++++++++++++++++++--
net/rds/ib.c | 31 ++++++++++++++++++++++++++-----
net/rds/ib_cm.c | 9 +++++++++
net/rds/ib_rdma.c | 2 ++
net/rds/rdma_transport.c | 10 ++++++++++
net/rds/recv.c | 2 ++
net/rds/send.c | 2 ++
net/rds/tcp.c | 25 +++++++++++++++++++++++++
net/rds/tcp_listen.c | 21 +++++++++++++++++----
12 files changed, 140 insertions(+), 26 deletions(-)
diff --git a/net/rds/Kconfig b/net/rds/Kconfig
index 4c7f259..41f7556 100644
--- a/net/rds/Kconfig
+++ b/net/rds/Kconfig
@@ -1,7 +1,7 @@
config RDS
tristate "The RDS Protocol"
- depends on INET && IPV6
+ depends on INET
---help---
The RDS (Reliable Datagram Sockets) protocol provides reliable,
sequenced delivery of datagrams over Infiniband or TCP.
diff --git a/net/rds/af_rds.c b/net/rds/af_rds.c
index fc5c48b..65387e1 100644
--- a/net/rds/af_rds.c
+++ b/net/rds/af_rds.c
@@ -156,18 +156,20 @@ static int rds_getname(struct socket *sock, struct sockaddr *uaddr,
return sizeof(*sin);
}
- if (ipv6_addr_type(&rs->rs_conn_addr) &
- IPV6_ADDR_MAPPED) {
- sin = (struct sockaddr_in *)uaddr;
- memset(sin, 0, sizeof(*sin));
- sin->sin_family = AF_INET;
- return sizeof(*sin);
+#if IS_ENABLED(CONFIG_IPV6)
+ if (!(ipv6_addr_type(&rs->rs_conn_addr) &
+ IPV6_ADDR_MAPPED)) {
+ sin6 = (struct sockaddr_in6 *)uaddr;
+ memset(sin6, 0, sizeof(*sin6));
+ sin6->sin6_family = AF_INET6;
+ return sizeof(*sin6);
}
+#endif
- sin6 = (struct sockaddr_in6 *)uaddr;
- memset(sin6, 0, sizeof(*sin6));
- sin6->sin6_family = AF_INET6;
- return sizeof(*sin6);
+ sin = (struct sockaddr_in *)uaddr;
+ memset(sin, 0, sizeof(*sin));
+ sin->sin_family = AF_INET;
+ return sizeof(*sin);
}
if (ipv6_addr_v4mapped(&rs->rs_bound_addr)) {
sin = (struct sockaddr_in *)uaddr;
@@ -501,9 +503,7 @@ static int rds_connect(struct socket *sock, struct sockaddr *uaddr,
{
struct sock *sk = sock->sk;
struct sockaddr_in *sin;
- struct sockaddr_in6 *sin6;
struct rds_sock *rs = rds_sk_to_rs(sk);
- int addr_type;
int ret = 0;
lock_sock(sk);
@@ -528,7 +528,11 @@ static int rds_connect(struct socket *sock, struct sockaddr *uaddr,
rs->rs_conn_port = sin->sin_port;
break;
- case AF_INET6:
+#if IS_ENABLED(CONFIG_IPV6)
+ case AF_INET6: {
+ struct sockaddr_in6 *sin6;
+ int addr_type;
+
sin6 = (struct sockaddr_in6 *)uaddr;
if (addr_len < sizeof(struct sockaddr_in6)) {
ret = -EINVAL;
@@ -575,6 +579,8 @@ static int rds_connect(struct socket *sock, struct sockaddr *uaddr,
rs->rs_conn_addr = sin6->sin6_addr;
rs->rs_conn_port = sin6->sin6_port;
break;
+ }
+#endif
default:
ret = -EAFNOSUPPORT;
diff --git a/net/rds/bind.c b/net/rds/bind.c
index ba77876..3ab5578 100644
--- a/net/rds/bind.c
+++ b/net/rds/bind.c
@@ -165,7 +165,6 @@ int rds_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
struct in6_addr v6addr, *binding_addr;
struct rds_transport *trans;
__u32 scope_id = 0;
- int addr_type;
int ret = 0;
__be16 port;
@@ -183,8 +182,10 @@ int rds_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
ipv6_addr_set_v4mapped(sin->sin_addr.s_addr, &v6addr);
binding_addr = &v6addr;
port = sin->sin_port;
+#if IS_ENABLED(CONFIG_IPV6)
} else if (uaddr->sa_family == AF_INET6) {
struct sockaddr_in6 *sin6 = (struct sockaddr_in6 *)uaddr;
+ int addr_type;
if (addr_len < sizeof(struct sockaddr_in6))
return -EINVAL;
@@ -212,6 +213,7 @@ int rds_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
}
binding_addr = &sin6->sin6_addr;
port = sin6->sin6_port;
+#endif
} else {
return -EINVAL;
}
diff --git a/net/rds/connection.c b/net/rds/connection.c
index 051e35c..3bd2f4a 100644
--- a/net/rds/connection.c
+++ b/net/rds/connection.c
@@ -63,8 +63,12 @@ static struct hlist_head *rds_conn_bucket(const struct in6_addr *laddr,
net_get_random_once(&rds6_hash_secret, sizeof(rds6_hash_secret));
lhash = (__force u32)laddr->s6_addr32[3];
+#if IS_ENABLED(CONFIG_IPV6)
fhash = __ipv6_addr_jhash(faddr, rds6_hash_secret);
- hash = __inet6_ehashfn(lhash, 0, fhash, 0, rds_hash_secret);
+#else
+ fhash = (__force u32)faddr->s6_addr32[3];
+#endif
+ hash = __inet_ehashfn(lhash, 0, fhash, 0, rds_hash_secret);
return &rds_conn_hash[hash & RDS_CONNECTION_HASH_MASK];
}
@@ -201,6 +205,8 @@ static struct rds_connection *__rds_conn_create(struct net *net,
conn->c_isv6 = !ipv6_addr_v4mapped(laddr);
conn->c_faddr = *faddr;
conn->c_dev_if = dev_if;
+
+#if IS_ENABLED(CONFIG_IPV6)
/* If the local address is link local, set c_bound_if to be the
* index used for this connection. Otherwise, set it to 0 as
* the socket is not bound to an interface. c_bound_if is used
@@ -209,6 +215,7 @@ static struct rds_connection *__rds_conn_create(struct net *net,
if (ipv6_addr_type(laddr) & IPV6_ADDR_LINKLOCAL)
conn->c_bound_if = dev_if;
else
+#endif
conn->c_bound_if = 0;
rds_conn_net_set(conn, net);
@@ -500,9 +507,11 @@ static void __rds_inc_msg_cp(struct rds_incoming *inc,
struct rds_info_iterator *iter,
void *saddr, void *daddr, int flip, bool isv6)
{
+#if IS_ENABLED(CONFIG_IPV6)
if (isv6)
rds6_inc_info_copy(inc, iter, saddr, daddr, flip);
else
+#endif
rds_inc_info_copy(inc, iter, *(__be32 *)saddr,
*(__be32 *)daddr, flip);
}
@@ -581,6 +590,7 @@ static void rds_conn_message_info(struct socket *sock, unsigned int len,
rds_conn_message_info_cmn(sock, len, iter, lens, want_send, false);
}
+#if IS_ENABLED(CONFIG_IPV6)
static void rds6_conn_message_info(struct socket *sock, unsigned int len,
struct rds_info_iterator *iter,
struct rds_info_lengths *lens,
@@ -588,6 +598,7 @@ static void rds6_conn_message_info(struct socket *sock, unsigned int len,
{
rds_conn_message_info_cmn(sock, len, iter, lens, want_send, true);
}
+#endif
static void rds_conn_message_info_send(struct socket *sock, unsigned int len,
struct rds_info_iterator *iter,
@@ -596,12 +607,14 @@ static void rds_conn_message_info_send(struct socket *sock, unsigned int len,
rds_conn_message_info(sock, len, iter, lens, 1);
}
+#if IS_ENABLED(CONFIG_IPV6)
static void rds6_conn_message_info_send(struct socket *sock, unsigned int len,
struct rds_info_iterator *iter,
struct rds_info_lengths *lens)
{
rds6_conn_message_info(sock, len, iter, lens, 1);
}
+#endif
static void rds_conn_message_info_retrans(struct socket *sock,
unsigned int len,
@@ -611,6 +624,7 @@ static void rds_conn_message_info_retrans(struct socket *sock,
rds_conn_message_info(sock, len, iter, lens, 0);
}
+#if IS_ENABLED(CONFIG_IPV6)
static void rds6_conn_message_info_retrans(struct socket *sock,
unsigned int len,
struct rds_info_iterator *iter,
@@ -618,6 +632,7 @@ static void rds6_conn_message_info_retrans(struct socket *sock,
{
rds6_conn_message_info(sock, len, iter, lens, 0);
}
+#endif
void rds_for_each_conn_info(struct socket *sock, unsigned int len,
struct rds_info_iterator *iter,
@@ -734,6 +749,7 @@ static int rds_conn_info_visitor(struct rds_conn_path *cp, void *buffer)
return 1;
}
+#if IS_ENABLED(CONFIG_IPV6)
static int rds6_conn_info_visitor(struct rds_conn_path *cp, void *buffer)
{
struct rds6_info_connection *cinfo6 = buffer;
@@ -761,6 +777,7 @@ static int rds6_conn_info_visitor(struct rds_conn_path *cp, void *buffer)
*/
return 1;
}
+#endif
static void rds_conn_info(struct socket *sock, unsigned int len,
struct rds_info_iterator *iter,
@@ -774,6 +791,7 @@ static void rds_conn_info(struct socket *sock, unsigned int len,
sizeof(struct rds_info_connection));
}
+#if IS_ENABLED(CONFIG_IPV6)
static void rds6_conn_info(struct socket *sock, unsigned int len,
struct rds_info_iterator *iter,
struct rds_info_lengths *lens)
@@ -785,6 +803,7 @@ static void rds6_conn_info(struct socket *sock, unsigned int len,
buffer,
sizeof(struct rds6_info_connection));
}
+#endif
int rds_conn_init(void)
{
@@ -807,12 +826,13 @@ int rds_conn_init(void)
rds_conn_message_info_send);
rds_info_register_func(RDS_INFO_RETRANS_MESSAGES,
rds_conn_message_info_retrans);
+#if IS_ENABLED(CONFIG_IPV6)
rds_info_register_func(RDS6_INFO_CONNECTIONS, rds6_conn_info);
rds_info_register_func(RDS6_INFO_SEND_MESSAGES,
rds6_conn_message_info_send);
rds_info_register_func(RDS6_INFO_RETRANS_MESSAGES,
rds6_conn_message_info_retrans);
-
+#endif
return 0;
}
@@ -830,11 +850,13 @@ void rds_conn_exit(void)
rds_conn_message_info_send);
rds_info_deregister_func(RDS_INFO_RETRANS_MESSAGES,
rds_conn_message_info_retrans);
+#if IS_ENABLED(CONFIG_IPV6)
rds_info_deregister_func(RDS6_INFO_CONNECTIONS, rds6_conn_info);
rds_info_deregister_func(RDS6_INFO_SEND_MESSAGES,
rds6_conn_message_info_send);
rds_info_deregister_func(RDS6_INFO_RETRANS_MESSAGES,
rds6_conn_message_info_retrans);
+#endif
}
/*
diff --git a/net/rds/ib.c b/net/rds/ib.c
index a4245c4..89c6333 100644
--- a/net/rds/ib.c
+++ b/net/rds/ib.c
@@ -321,6 +321,7 @@ static int rds_ib_conn_info_visitor(struct rds_connection *conn,
return 1;
}
+#if IS_ENABLED(CONFIG_IPV6)
/* IPv6 version of rds_ib_conn_info_visitor(). */
static int rds6_ib_conn_info_visitor(struct rds_connection *conn,
void *buffer)
@@ -357,6 +358,7 @@ static int rds6_ib_conn_info_visitor(struct rds_connection *conn,
}
return 1;
}
+#endif
static void rds_ib_ic_info(struct socket *sock, unsigned int len,
struct rds_info_iterator *iter,
@@ -370,6 +372,7 @@ static void rds_ib_ic_info(struct socket *sock, unsigned int len,
sizeof(struct rds_info_rdma_connection));
}
+#if IS_ENABLED(CONFIG_IPV6)
/* IPv6 version of rds_ib_ic_info(). */
static void rds6_ib_ic_info(struct socket *sock, unsigned int len,
struct rds_info_iterator *iter,
@@ -382,6 +385,7 @@ static void rds6_ib_ic_info(struct socket *sock, unsigned int len,
buffer,
sizeof(struct rds6_info_rdma_connection));
}
+#endif
/*
* Early RDS/IB was built to only bind to an address if there is an IPoIB
@@ -398,7 +402,9 @@ static int rds_ib_laddr_check(struct net *net, const struct in6_addr *addr,
{
int ret;
struct rdma_cm_id *cm_id;
+#if IS_ENABLED(CONFIG_IPV6)
struct sockaddr_in6 sin6;
+#endif
struct sockaddr_in sin;
struct sockaddr *sa;
bool isv4;
@@ -418,6 +424,7 @@ static int rds_ib_laddr_check(struct net *net, const struct in6_addr *addr,
sin.sin_addr.s_addr = addr->s6_addr32[3];
sa = (struct sockaddr *)&sin;
} else {
+#if IS_ENABLED(CONFIG_IPV6)
memset(&sin6, 0, sizeof(sin6));
sin6.sin6_family = AF_INET6;
sin6.sin6_addr = *addr;
@@ -432,21 +439,30 @@ static int rds_ib_laddr_check(struct net *net, const struct in6_addr *addr,
if (ipv6_addr_type(addr) & IPV6_ADDR_LINKLOCAL) {
struct net_device *dev;
- if (scope_id == 0)
- return -EADDRNOTAVAIL;
+ if (scope_id == 0) {
+ ret = -EADDRNOTAVAIL;
+ goto out;
+ }
/* Use init_net for now as RDS is not network
* name space aware.
*/
dev = dev_get_by_index(&init_net, scope_id);
- if (!dev)
- return -EADDRNOTAVAIL;
+ if (!dev) {
+ ret = -EADDRNOTAVAIL;
+ goto out;
+ }
if (!ipv6_chk_addr(&init_net, addr, dev, 1)) {
dev_put(dev);
- return -EADDRNOTAVAIL;
+ ret = -EADDRNOTAVAIL;
+ goto out;
}
dev_put(dev);
}
+#else
+ ret = -EADDRNOTAVAIL;
+ goto out;
+#endif
}
/* rdma_bind_addr will only succeed for IB & iWARP devices */
@@ -461,6 +477,7 @@ static int rds_ib_laddr_check(struct net *net, const struct in6_addr *addr,
addr, scope_id, ret,
cm_id->device ? cm_id->device->node_type : -1);
+out:
rdma_destroy_id(cm_id);
return ret;
@@ -491,7 +508,9 @@ void rds_ib_exit(void)
rds_ib_set_unloading();
synchronize_rcu();
rds_info_deregister_func(RDS_INFO_IB_CONNECTIONS, rds_ib_ic_info);
+#if IS_ENABLED(CONFIG_IPV6)
rds_info_deregister_func(RDS6_INFO_IB_CONNECTIONS, rds6_ib_ic_info);
+#endif
rds_ib_unregister_client();
rds_ib_destroy_nodev_conns();
rds_ib_sysctl_exit();
@@ -553,7 +572,9 @@ int rds_ib_init(void)
rds_trans_register(&rds_ib_transport);
rds_info_register_func(RDS_INFO_IB_CONNECTIONS, rds_ib_ic_info);
+#if IS_ENABLED(CONFIG_IPV6)
rds_info_register_func(RDS6_INFO_IB_CONNECTIONS, rds6_ib_ic_info);
+#endif
goto out;
diff --git a/net/rds/ib_cm.c b/net/rds/ib_cm.c
index 0d654d9..bfbb31f 100644
--- a/net/rds/ib_cm.c
+++ b/net/rds/ib_cm.c
@@ -678,6 +678,7 @@ static u32 rds_ib_protocol_compatible(struct rdma_cm_event *event, bool isv6)
return version;
}
+#if IS_ENABLED(CONFIG_IPV6)
/* Given an IPv6 address, find the net_device which hosts that address and
* return its index. This is used by the rds_ib_cm_handle_connect() code to
* find the interface index of where an incoming request comes from when
@@ -704,6 +705,7 @@ static u32 __rds_find_ifindex(struct net *net, const struct in6_addr *addr)
return idx;
}
+#endif
int rds_ib_cm_handle_connect(struct rdma_cm_id *cm_id,
struct rdma_cm_event *event, bool isv6)
@@ -732,6 +734,7 @@ int rds_ib_cm_handle_connect(struct rdma_cm_id *cm_id,
dp = event->param.conn.private_data;
if (isv6) {
+#if IS_ENABLED(CONFIG_IPV6)
dp_cmn = &dp->ricp_v6.dp_cmn;
saddr6 = &dp->ricp_v6.dp_saddr;
daddr6 = &dp->ricp_v6.dp_daddr;
@@ -756,6 +759,10 @@ int rds_ib_cm_handle_connect(struct rdma_cm_id *cm_id,
goto out;
}
}
+#else
+ err = -EOPNOTSUPP;
+ goto out;
+#endif
} else {
dp_cmn = &dp->ricp_v4.dp_cmn;
ipv6_addr_set_v4mapped(dp->ricp_v4.dp_saddr, &s_mapped_addr);
@@ -893,9 +900,11 @@ int rds_ib_conn_path_connect(struct rds_conn_path *cp)
/* XXX I wonder what affect the port space has */
/* delegate cm event handler to rdma_transport */
+#if IS_ENABLED(CONFIG_IPV6)
if (conn->c_isv6)
handler = rds6_rdma_cm_event_handler;
else
+#endif
handler = rds_rdma_cm_event_handler;
ic->i_cm_id = rdma_create_id(&init_net, handler, conn,
RDMA_PS_TCP, IB_QPT_RC);
diff --git a/net/rds/ib_rdma.c b/net/rds/ib_rdma.c
index e3c8bbb..99ccafb 100644
--- a/net/rds/ib_rdma.c
+++ b/net/rds/ib_rdma.c
@@ -180,6 +180,7 @@ void rds_ib_get_mr_info(struct rds_ib_device *rds_ibdev, struct rds_info_rdma_co
iinfo->rdma_mr_size = pool_1m->fmr_attr.max_pages;
}
+#if IS_ENABLED(CONFIG_IPV6)
void rds6_ib_get_mr_info(struct rds_ib_device *rds_ibdev,
struct rds6_info_rdma_connection *iinfo6)
{
@@ -188,6 +189,7 @@ void rds6_ib_get_mr_info(struct rds_ib_device *rds_ibdev,
iinfo6->rdma_mr_max = pool_1m->max_items;
iinfo6->rdma_mr_size = pool_1m->fmr_attr.max_pages;
}
+#endif
struct rds_ib_mr *rds_ib_reuse_mr(struct rds_ib_mr_pool *pool)
{
diff --git a/net/rds/rdma_transport.c b/net/rds/rdma_transport.c
index ad78929..6b0f57c 100644
--- a/net/rds/rdma_transport.c
+++ b/net/rds/rdma_transport.c
@@ -39,7 +39,9 @@
/* Global IPv4 and IPv6 RDS RDMA listener cm_id */
static struct rdma_cm_id *rds_rdma_listen_id;
+#if IS_ENABLED(CONFIG_IPV6)
static struct rdma_cm_id *rds6_rdma_listen_id;
+#endif
static int rds_rdma_cm_event_handler_cmn(struct rdma_cm_id *cm_id,
struct rdma_cm_event *event,
@@ -155,11 +157,13 @@ int rds_rdma_cm_event_handler(struct rdma_cm_id *cm_id,
return rds_rdma_cm_event_handler_cmn(cm_id, event, false);
}
+#if IS_ENABLED(CONFIG_IPV6)
int rds6_rdma_cm_event_handler(struct rdma_cm_id *cm_id,
struct rdma_cm_event *event)
{
return rds_rdma_cm_event_handler_cmn(cm_id, event, true);
}
+#endif
static int rds_rdma_listen_init_common(rdma_cm_event_handler handler,
struct sockaddr *sa,
@@ -214,7 +218,9 @@ static int rds_rdma_listen_init_common(rdma_cm_event_handler handler,
static int rds_rdma_listen_init(void)
{
int ret;
+#if IS_ENABLED(CONFIG_IPV6)
struct sockaddr_in6 sin6;
+#endif
struct sockaddr_in sin;
sin.sin_family = PF_INET;
@@ -226,6 +232,7 @@ static int rds_rdma_listen_init(void)
if (ret != 0)
return ret;
+#if IS_ENABLED(CONFIG_IPV6)
sin6.sin6_family = PF_INET6;
sin6.sin6_addr = in6addr_any;
sin6.sin6_port = htons(RDS_CM_PORT);
@@ -237,6 +244,7 @@ static int rds_rdma_listen_init(void)
/* Keep going even when IPv6 is not enabled in the system. */
if (ret != 0)
rdsdebug("Cannot set up IPv6 RDMA listener\n");
+#endif
return 0;
}
@@ -247,11 +255,13 @@ static void rds_rdma_listen_stop(void)
rdma_destroy_id(rds_rdma_listen_id);
rds_rdma_listen_id = NULL;
}
+#if IS_ENABLED(CONFIG_IPV6)
if (rds6_rdma_listen_id) {
rdsdebug("cm %p\n", rds6_rdma_listen_id);
rdma_destroy_id(rds6_rdma_listen_id);
rds6_rdma_listen_id = NULL;
}
+#endif
}
static int rds_rdma_init(void)
diff --git a/net/rds/recv.c b/net/rds/recv.c
index 03cd8df..504cd6b 100644
--- a/net/rds/recv.c
+++ b/net/rds/recv.c
@@ -793,6 +793,7 @@ void rds_inc_info_copy(struct rds_incoming *inc,
rds_info_copy(iter, &minfo, sizeof(minfo));
}
+#if IS_ENABLED(CONFIG_IPV6)
void rds6_inc_info_copy(struct rds_incoming *inc,
struct rds_info_iterator *iter,
struct in6_addr *saddr, struct in6_addr *daddr,
@@ -817,3 +818,4 @@ void rds6_inc_info_copy(struct rds_incoming *inc,
rds_info_copy(iter, &minfo6, sizeof(minfo6));
}
+#endif
diff --git a/net/rds/send.c b/net/rds/send.c
index 18e2b4d..36a5dba 100644
--- a/net/rds/send.c
+++ b/net/rds/send.c
@@ -1103,6 +1103,7 @@ int rds_sendmsg(struct socket *sock, struct msghdr *msg, size_t payload_len)
dport = usin->sin_port;
break;
+#if IS_ENABLED(CONFIG_IPV6)
case AF_INET6: {
int addr_type;
@@ -1142,6 +1143,7 @@ int rds_sendmsg(struct socket *sock, struct msghdr *msg, size_t payload_len)
dport = sin6->sin6_port;
break;
}
+#endif
default:
ret = -EINVAL;
diff --git a/net/rds/tcp.c b/net/rds/tcp.c
index f23925a..2c7b7c3 100644
--- a/net/rds/tcp.c
+++ b/net/rds/tcp.c
@@ -51,7 +51,9 @@
* rds6_tcp_tc_count counts both IPv4 and IPv6 connections.
*/
static unsigned int rds_tcp_tc_count;
+#if IS_ENABLED(CONFIG_IPV6)
static unsigned int rds6_tcp_tc_count;
+#endif
/* Track rds_tcp_connection structs so they can be cleaned up */
static DEFINE_SPINLOCK(rds_tcp_conn_lock);
@@ -118,7 +120,9 @@ void rds_tcp_restore_callbacks(struct socket *sock,
/* done under the callback_lock to serialize with write_space */
spin_lock(&rds_tcp_tc_list_lock);
list_del_init(&tc->t_list_item);
+#if IS_ENABLED(CONFIG_IPV6)
rds6_tcp_tc_count--;
+#endif
if (!tc->t_cpath->cp_conn->c_isv6)
rds_tcp_tc_count--;
spin_unlock(&rds_tcp_tc_list_lock);
@@ -207,7 +211,9 @@ void rds_tcp_set_callbacks(struct socket *sock, struct rds_conn_path *cp)
/* done under the callback_lock to serialize with write_space */
spin_lock(&rds_tcp_tc_list_lock);
list_add_tail(&tc->t_list_item, &rds_tcp_tc_list);
+#if IS_ENABLED(CONFIG_IPV6)
rds6_tcp_tc_count++;
+#endif
if (!tc->t_cpath->cp_conn->c_isv6)
rds_tcp_tc_count++;
spin_unlock(&rds_tcp_tc_list_lock);
@@ -273,6 +279,7 @@ static void rds_tcp_tc_info(struct socket *rds_sock, unsigned int len,
spin_unlock_irqrestore(&rds_tcp_tc_list_lock, flags);
}
+#if IS_ENABLED(CONFIG_IPV6)
/* Handle RDS6_INFO_TCP_SOCKETS socket option. It returns both IPv4 and
* IPv6 connections. IPv4 connection address is returned in an IPv4 mapped
* address.
@@ -314,12 +321,15 @@ static void rds6_tcp_tc_info(struct socket *sock, unsigned int len,
spin_unlock_irqrestore(&rds_tcp_tc_list_lock, flags);
}
+#endif
static int rds_tcp_laddr_check(struct net *net, const struct in6_addr *addr,
__u32 scope_id)
{
struct net_device *dev = NULL;
+#if IS_ENABLED(CONFIG_IPV6)
int ret;
+#endif
if (ipv6_addr_v4mapped(addr)) {
if (inet_addr_type(net, addr->s6_addr32[3]) == RTN_LOCAL)
@@ -340,9 +350,11 @@ static int rds_tcp_laddr_check(struct net *net, const struct in6_addr *addr,
}
rcu_read_unlock();
}
+#if IS_ENABLED(CONFIG_IPV6)
ret = ipv6_chk_addr(net, addr, dev, 0);
if (ret)
return 0;
+#endif
return -EADDRNOTAVAIL;
}
@@ -545,18 +557,27 @@ static __net_init int rds_tcp_init_net(struct net *net)
err = -ENOMEM;
goto fail;
}
+
+#if IS_ENABLED(CONFIG_IPV6)
rtn->rds_tcp_listen_sock = rds_tcp_listen_init(net, true);
+#else
+ rtn->rds_tcp_listen_sock = rds_tcp_listen_init(net, false);
+#endif
if (!rtn->rds_tcp_listen_sock) {
pr_warn("could not set up IPv6 listen sock\n");
+#if IS_ENABLED(CONFIG_IPV6)
/* Try IPv4 as some systems disable IPv6 */
rtn->rds_tcp_listen_sock = rds_tcp_listen_init(net, false);
if (!rtn->rds_tcp_listen_sock) {
+#endif
unregister_net_sysctl_table(rtn->rds_tcp_sysctl);
rtn->rds_tcp_sysctl = NULL;
err = -EAFNOSUPPORT;
goto fail;
+#if IS_ENABLED(CONFIG_IPV6)
}
+#endif
}
INIT_WORK(&rtn->rds_tcp_accept_w, rds_tcp_accept_worker);
return 0;
@@ -670,7 +691,9 @@ static void rds_tcp_exit(void)
rds_tcp_set_unloading();
synchronize_rcu();
rds_info_deregister_func(RDS_INFO_TCP_SOCKETS, rds_tcp_tc_info);
+#if IS_ENABLED(CONFIG_IPV6)
rds_info_deregister_func(RDS6_INFO_TCP_SOCKETS, rds6_tcp_tc_info);
+#endif
unregister_pernet_device(&rds_tcp_net_ops);
rds_tcp_destroy_conns();
rds_trans_unregister(&rds_tcp_transport);
@@ -702,7 +725,9 @@ static int rds_tcp_init(void)
rds_trans_register(&rds_tcp_transport);
rds_info_register_func(RDS_INFO_TCP_SOCKETS, rds_tcp_tc_info);
+#if IS_ENABLED(CONFIG_IPV6)
rds_info_register_func(RDS6_INFO_TCP_SOCKETS, rds6_tcp_tc_info);
+#endif
goto out;
out_recv:
diff --git a/net/rds/tcp_listen.c b/net/rds/tcp_listen.c
index 0cf0147..c12203f 100644
--- a/net/rds/tcp_listen.c
+++ b/net/rds/tcp_listen.c
@@ -132,7 +132,10 @@ int rds_tcp_accept_one(struct socket *sock)
int conn_state;
struct rds_conn_path *cp;
struct in6_addr *my_addr, *peer_addr;
- int dev_if;
+#if !IS_ENABLED(CONFIG_IPV6)
+ struct in6_addr saddr, daddr;
+#endif
+ int dev_if = 0;
if (!sock) /* module unload or netns delete in progress */
return -ENETUNREACH;
@@ -165,12 +168,21 @@ int rds_tcp_accept_one(struct socket *sock)
inet = inet_sk(new_sock->sk);
+#if IS_ENABLED(CONFIG_IPV6)
my_addr = &new_sock->sk->sk_v6_rcv_saddr;
peer_addr = &new_sock->sk->sk_v6_daddr;
- rdsdebug("accepted tcp %pI6c:%u -> %pI6c:%u\n",
+#else
+ ipv6_addr_set_v4mapped(inet->inet_saddr, &saddr);
+ ipv6_addr_set_v4mapped(inet->inet_daddr, &daddr);
+ my_addr = &saddr;
+ peer_addr = &daddr;
+#endif
+ rdsdebug("accepted family %d tcp %pI6c:%u -> %pI6c:%u\n",
+ sock->sk->sk_family,
my_addr, ntohs(inet->inet_sport),
peer_addr, ntohs(inet->inet_dport));
+#if IS_ENABLED(CONFIG_IPV6)
/* sk_bound_dev_if is not set if the peer address is not link local
* address. In this case, it happens that mcast_oif is set. So
* just use it.
@@ -184,9 +196,10 @@ int rds_tcp_accept_one(struct socket *sock)
} else {
dev_if = new_sock->sk->sk_bound_dev_if;
}
+#endif
+
conn = rds_conn_create(sock_net(sock->sk),
- &new_sock->sk->sk_v6_rcv_saddr,
- &new_sock->sk->sk_v6_daddr,
+ my_addr, peer_addr,
&rds_tcp_transport, GFP_KERNEL, dev_if);
if (IS_ERR(conn)) {
--
1.8.3.1
^ permalink raw reply related
* Re: [PATCH net] inet: frag: enforce memory limits earlier
From: Florian Westphal @ 2018-07-31 5:54 UTC (permalink / raw)
To: Eric Dumazet
Cc: David S . Miller, netdev, Jann Horn, Eric Dumazet,
Florian Westphal, Peter Oskolkov, Paolo Abeni
In-Reply-To: <20180731030911.248637-1-edumazet@google.com>
Eric Dumazet <edumazet@google.com> wrote:
> We currently check current frags memory usage only when
> a new frag queue is created. This allows attackers to first
> consume the memory budget (default : 4 MB) creating thousands
> of frag queues, then sending tiny skbs to exceed high_thresh
> limit by 2 to 3 order of magnitude.
>
> Note that before commit 648700f76b03 ("inet: frags: use rhashtables
> for reassembly units"), work queue could be starved under DOS,
> getting no cpu cycles.
> After commit 648700f76b03, only the per frag queue timer can eventually
> remove an incomplete frag queue and its skbs.
I'm not sure this is a good idea.
This can now prevent "good" queue from completing just because attacker
is sending garbage.
^ permalink raw reply
* Re: [PATCH] net: wireless: ath6kl: Replace GFP_ATOMIC with GFP_KERNEL in ath6kl_bmi_init()
From: Kalle Valo @ 2018-07-31 7:50 UTC (permalink / raw)
To: Jia-Ju Bai; +Cc: kvalo, linux-wireless, netdev, linux-kernel, Jia-Ju Bai
In-Reply-To: <20180727084318.3345-1-baijiaju1990@gmail.com>
Jia-Ju Bai <baijiaju1990@gmail.com> wrote:
> ath6kl_bmi_init() is never called in atomic context.
> It calls kzalloc() with GFP_ATOMIC, which is not necessary.
> GFP_ATOMIC can be replaced with GFP_KERNEL.
>
> This is found by a static analysis tool named DCNS written by myself.
>
> Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Patch applied to ath-next branch of ath.git, thanks.
bfc55fe65987 ath6kl: replace GFP_ATOMIC with GFP_KERNEL in ath6kl_bmi_init()
--
https://patchwork.kernel.org/patch/10546741/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [PATCH net-next 01/10] MIPS: mscc: ocelot: make HSIO registers address range a syscon
From: Alexandre Belloni @ 2018-07-31 7:51 UTC (permalink / raw)
To: Quentin Schulz
Cc: ralf, paul.burton, jhogan, robh+dt, mark.rutland, davem, kishon,
andrew, f.fainelli, linux-mips, devicetree, linux-kernel, netdev,
allan.nielsen, thomas.petazzoni
In-Reply-To: <c250b2591a70bd8b31eef56d82cf5f5ccb47cc22.1532954208.git-series.quentin.schulz@bootlin.com>
On 30/07/2018 14:43:46+0200, Quentin Schulz wrote:
> HSIO contains registers for PLL5 configuration, SerDes/switch port
> muxing and a thermal sensor, hence we can't keep it in the switch DT
> node.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> arch/mips/boot/dts/mscc/ocelot.dtsi | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> index afe8fc9..c51663a 100644
> --- a/arch/mips/boot/dts/mscc/ocelot.dtsi
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -96,7 +96,6 @@
> reg = <0x1010000 0x10000>,
> <0x1030000 0x10000>,
> <0x1080000 0x100>,
> - <0x10d0000 0x10000>,
> <0x11e0000 0x100>,
> <0x11f0000 0x100>,
> <0x1200000 0x100>,
> @@ -110,10 +109,10 @@
> <0x1280000 0x100>,
> <0x1800000 0x80000>,
> <0x1880000 0x10000>;
> - reg-names = "sys", "rew", "qs", "hsio", "port0",
> - "port1", "port2", "port3", "port4", "port5",
> - "port6", "port7", "port8", "port9", "port10",
> - "qsys", "ana";
> + reg-names = "sys", "rew", "qs", "port0", "port1",
> + "port2", "port3", "port4", "port5", "port6",
> + "port7", "port8", "port9", "port10", "qsys",
> + "ana";
> interrupts = <21 22>;
> interrupt-names = "xtr", "inj";
>
> @@ -220,5 +219,10 @@
> pinctrl-0 = <&miim1>;
> status = "disabled";
> };
> +
> + hsio: syscon@10d0000 {
> + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
> + reg = <0x10d0000 0x10000>;
> + };
> };
> };
> --
> git-series 0.9.1
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH net-next 02/10] dt-bindings: net: ocelot: remove hsio from the list of register address spaces
From: Alexandre Belloni @ 2018-07-31 7:52 UTC (permalink / raw)
To: Quentin Schulz
Cc: ralf, paul.burton, jhogan, robh+dt, mark.rutland, davem, kishon,
andrew, f.fainelli, linux-mips, devicetree, linux-kernel, netdev,
allan.nielsen, thomas.petazzoni
In-Reply-To: <3558e538b55a2249b0a179c04c27e9d3715bbbaa.1532954208.git-series.quentin.schulz@bootlin.com>
On 30/07/2018 14:43:47+0200, Quentin Schulz wrote:
> HSIO register address space should be handled outside of the MAC
> controller as there are some registers for PLL5 configuring,
> SerDes/switch port muxing and a thermal sensor IP, so let's remove it.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> Documentation/devicetree/bindings/mips/mscc.txt | 16 ++++++++++++-
> Documentation/devicetree/bindings/net/mscc-ocelot.txt | 9 ++-----
> 2 files changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
> index ae15ec3..bc817e9 100644
> --- a/Documentation/devicetree/bindings/mips/mscc.txt
> +++ b/Documentation/devicetree/bindings/mips/mscc.txt
> @@ -41,3 +41,19 @@ Example:
> compatible = "mscc,ocelot-cpu-syscon", "syscon";
> reg = <0x70000000 0x2c>;
> };
> +
> +o HSIO regs:
> +
> +The SoC has a few registers (HSIO) handling miscellaneous functionalities:
> +configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
> +status, SerDes muxing and a thermal sensor.
> +
> +Required properties:
> +- compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
> +- reg : Should contain registers location and length
> +
> +Example:
> + syscon@10d0000 {
> + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
> + reg = <0x10d0000 0x10000>;
> + };
> diff --git a/Documentation/devicetree/bindings/net/mscc-ocelot.txt b/Documentation/devicetree/bindings/net/mscc-ocelot.txt
> index 0a84711..9e5c17d 100644
> --- a/Documentation/devicetree/bindings/net/mscc-ocelot.txt
> +++ b/Documentation/devicetree/bindings/net/mscc-ocelot.txt
> @@ -12,7 +12,6 @@ Required properties:
> - "sys"
> - "rew"
> - "qs"
> - - "hsio"
> - "qsys"
> - "ana"
> - "portX" with X from 0 to the number of last port index available on that
> @@ -45,7 +44,6 @@ Example:
> reg = <0x1010000 0x10000>,
> <0x1030000 0x10000>,
> <0x1080000 0x100>,
> - <0x10d0000 0x10000>,
> <0x11e0000 0x100>,
> <0x11f0000 0x100>,
> <0x1200000 0x100>,
> @@ -59,10 +57,9 @@ Example:
> <0x1280000 0x100>,
> <0x1800000 0x80000>,
> <0x1880000 0x10000>;
> - reg-names = "sys", "rew", "qs", "hsio", "port0",
> - "port1", "port2", "port3", "port4", "port5",
> - "port6", "port7", "port8", "port9", "port10",
> - "qsys", "ana";
> + reg-names = "sys", "rew", "qs", "port0", "port1", "port2",
> + "port3", "port4", "port5", "port6", "port7",
> + "port8", "port9", "port10", "qsys", "ana";
> interrupts = <21 22>;
> interrupt-names = "xtr", "inj";
>
> --
> git-series 0.9.1
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH net-next 03/10] net: mscc: ocelot: get HSIO regmap from syscon
From: Alexandre Belloni @ 2018-07-31 7:53 UTC (permalink / raw)
To: Quentin Schulz
Cc: ralf, paul.burton, jhogan, robh+dt, mark.rutland, davem, kishon,
andrew, f.fainelli, linux-mips, devicetree, linux-kernel, netdev,
allan.nielsen, thomas.petazzoni
In-Reply-To: <fc4e6c0effa84417bddb32b4a53c6021f0b9e546.1532954208.git-series.quentin.schulz@bootlin.com>
On 30/07/2018 14:43:48+0200, Quentin Schulz wrote:
> HSIO address space was moved to a syscon, hence we need to get the
> regmap of this address space from there and no more from the device
> node.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> drivers/net/ethernet/mscc/ocelot_board.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/mscc/ocelot_board.c b/drivers/net/ethernet/mscc/ocelot_board.c
> index 26bb3b1..b7d755b 100644
> --- a/drivers/net/ethernet/mscc/ocelot_board.c
> +++ b/drivers/net/ethernet/mscc/ocelot_board.c
> @@ -9,6 +9,7 @@
> #include <linux/netdevice.h>
> #include <linux/of_mdio.h>
> #include <linux/of_platform.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/skbuff.h>
>
> #include "ocelot.h"
> @@ -162,6 +163,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
> struct device_node *np = pdev->dev.of_node;
> struct device_node *ports, *portnp;
> struct ocelot *ocelot;
> + struct regmap *hsio;
> u32 val;
>
> struct {
> @@ -173,7 +175,6 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
> { QSYS, "qsys" },
> { ANA, "ana" },
> { QS, "qs" },
> - { HSIO, "hsio" },
> };
>
> if (!np && !pdev->dev.platform_data)
> @@ -196,6 +197,14 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
> ocelot->targets[res[i].id] = target;
> }
>
> + hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");
> + if (IS_ERR(hsio)) {
> + dev_err(&pdev->dev, "missing hsio syscon\n");
> + return PTR_ERR(hsio);
> + }
> +
> + ocelot->targets[HSIO] = hsio;
> +
> err = ocelot_chip_init(ocelot);
> if (err)
> return err;
> --
> git-series 0.9.1
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH net-next 04/10] net: mscc: ocelot: move the HSIO header to include/soc
From: Alexandre Belloni @ 2018-07-31 8:02 UTC (permalink / raw)
To: Quentin Schulz
Cc: ralf, paul.burton, jhogan, robh+dt, mark.rutland, davem, kishon,
andrew, f.fainelli, linux-mips, devicetree, linux-kernel, netdev,
allan.nielsen, thomas.petazzoni
In-Reply-To: <01e5bd12299a1121b94265c64ed2a91f5f629b9a.1532954208.git-series.quentin.schulz@bootlin.com>
On 30/07/2018 14:43:49+0200, Quentin Schulz wrote:
> Since HSIO address space can be used by different drivers (PLL, SerDes
> muxing, temperature sensor), let's move it somewhere it can be included
> by all drivers.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> drivers/net/ethernet/mscc/ocelot.h | 1 +-
> drivers/net/ethernet/mscc/ocelot_hsio.h | 785 +-------------------------
> drivers/net/ethernet/mscc/ocelot_regs.c | 1 +-
> include/soc/mscc/ocelot_hsio.h | 785 +++++++++++++++++++++++++-
> 4 files changed, 786 insertions(+), 786 deletions(-)
> delete mode 100644 drivers/net/ethernet/mscc/ocelot_hsio.h
> create mode 100644 include/soc/mscc/ocelot_hsio.h
>
> diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
> index 616bec3..2da20a3 100644
> --- a/drivers/net/ethernet/mscc/ocelot.h
> +++ b/drivers/net/ethernet/mscc/ocelot.h
> @@ -16,7 +16,6 @@
>
> #include "ocelot_ana.h"
> #include "ocelot_dev.h"
> -#include "ocelot_hsio.h"
> #include "ocelot_qsys.h"
> #include "ocelot_rew.h"
> #include "ocelot_sys.h"
> diff --git a/drivers/net/ethernet/mscc/ocelot_hsio.h b/drivers/net/ethernet/mscc/ocelot_hsio.h
> deleted file mode 100644
> index d93ddec..0000000
> --- a/drivers/net/ethernet/mscc/ocelot_hsio.h
> +++ /dev/null
> @@ -1,785 +0,0 @@
> -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> -/*
> - * Microsemi Ocelot Switch driver
> - *
> - * Copyright (c) 2017 Microsemi Corporation
> - */
> -
> -#ifndef _MSCC_OCELOT_HSIO_H_
> -#define _MSCC_OCELOT_HSIO_H_
> -
> -#define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
> -#define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
> -#define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
> -#define HSIO_PLL5G_CFG0_DIV4 BIT(28)
> -#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
> -#define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
> -#define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
> -#define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
> -#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
> -#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
> -#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
> -#define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
> -#define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
> -#define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
> -#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
> -#define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
> -#define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
> -#define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
> -#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
> -#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6)
> -#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6)
> -#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0))
> -#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)
> -
> -#define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
> -#define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17)
> -#define HSIO_PLL5G_CFG1_ROT_DIR BIT(16)
> -#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15)
> -#define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14)
> -#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
> -#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6)
> -#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
> -#define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5)
> -#define HSIO_PLL5G_CFG1_PWD_TX BIT(4)
> -#define HSIO_PLL5G_CFG1_PWD_RX BIT(3)
> -#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2)
> -#define HSIO_PLL5G_CFG1_HALF_RATE BIT(1)
> -#define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0)
> -
> -#define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30)
> -#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29)
> -#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28)
> -#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27)
> -#define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26)
> -#define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25)
> -#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24)
> -#define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16))
> -#define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16)
> -#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16)
> -#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15)
> -#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14)
> -#define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13)
> -#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12)
> -#define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11)
> -#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10)
> -#define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5))
> -#define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)
> -#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5)
> -#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4)
> -#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3)
> -#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2)
> -#define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1)
> -#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0)
> -
> -#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22))
> -#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22)
> -#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22)
> -#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19))
> -#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19)
> -#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19)
> -#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18)
> -#define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17)
> -#define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16)
> -#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15)
> -#define HSIO_PLL5G_CFG3_RST_FB_N BIT(14)
> -#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13)
> -#define HSIO_PLL5G_CFG3_FORCE_LO BIT(12)
> -#define HSIO_PLL5G_CFG3_FORCE_HI BIT(11)
> -#define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10)
> -#define HSIO_PLL5G_CFG3_FORCE_CP BIT(9)
> -#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8)
> -#define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0))
> -#define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)
> -
> -#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
> -#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16)
> -#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
> -#define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0))
> -#define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0)
> -
> -#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
> -#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16)
> -#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
> -#define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0))
> -#define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0)
> -
> -#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23)
> -#define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20))
> -#define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20)
> -#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20)
> -#define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19)
> -#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16))
> -#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16)
> -#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16)
> -#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8))
> -#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8)
> -#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8)
> -#define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7)
> -#define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6)
> -#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0))
> -#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)
> -
> -#define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12)
> -#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11)
> -#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10)
> -#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9)
> -#define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1))
> -#define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)
> -#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1)
> -#define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0)
> -
> -#define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21))
> -#define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21)
> -#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21)
> -#define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16))
> -#define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16)
> -#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16)
> -#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4))
> -#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4)
> -#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4)
> -#define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1))
> -#define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1)
> -#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1)
> -#define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0)
> -
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31)
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30)
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20))
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20)
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20)
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16))
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16)
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16)
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0))
> -#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0)
> -
> -#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4))
> -#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4)
> -#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4)
> -#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2)
> -#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1)
> -#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0)
> -
> -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16))
> -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16)
> -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16)
> -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0))
> -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0)
> -
> -#define HSIO_RCOMP_CFG0_PWD_ENA BIT(13)
> -#define HSIO_RCOMP_CFG0_RUN_CAL BIT(12)
> -#define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10))
> -#define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10)
> -#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10)
> -#define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8))
> -#define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8)
> -#define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
> -#define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4)
> -#define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0))
> -#define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0)
> -
> -#define HSIO_RCOMP_STATUS_BUSY BIT(12)
> -#define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7)
> -#define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0))
> -#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0)
> -
> -#define HSIO_SYNC_ETH_CFG_RSZ 0x4
> -
> -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4))
> -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4)
> -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4)
> -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1))
> -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1)
> -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1)
> -#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0)
> -
> -#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0)
> -
> -#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
> -#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
> -#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
> -#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11))
> -#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11)
> -#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11)
> -#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8))
> -#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8)
> -#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8)
> -#define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5))
> -#define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5)
> -#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5)
> -#define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4)
> -#define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1))
> -#define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1)
> -#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1)
> -#define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0)
> -
> -#define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27)
> -#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24))
> -#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24)
> -#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24)
> -#define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19))
> -#define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19)
> -#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19)
> -#define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14)
> -#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13)
> -#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12)
> -#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11)
> -#define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10)
> -#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9)
> -#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6))
> -#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6)
> -#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6)
> -#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4))
> -#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4)
> -#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4)
> -#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
> -#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0)
> -
> -#define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17))
> -#define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17)
> -#define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17)
> -#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13))
> -#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13)
> -#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
> -#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10))
> -#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10)
> -#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
> -#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9)
> -#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8)
> -#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4))
> -#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4)
> -#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4)
> -#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
> -#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
> -
> -#define HSIO_S1G_SER_CFG_SER_IDLE BIT(9)
> -#define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8)
> -#define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7)
> -#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6)
> -#define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
> -#define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
> -#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
> -#define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3)
> -#define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2)
> -#define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1)
> -#define HSIO_S1G_SER_CFG_SER_ENALI BIT(0)
> -
> -#define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31)
> -#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21)
> -#define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18)
> -#define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17)
> -#define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16)
> -#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13))
> -#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13)
> -#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13)
> -#define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12)
> -#define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11)
> -#define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10)
> -#define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9)
> -#define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8)
> -#define HSIO_S1G_COMMON_CFG_HRATE BIT(7)
> -#define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0)
> -
> -#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22)
> -#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21)
> -#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8))
> -#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8)
> -#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8)
> -#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7)
> -#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6)
> -#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5)
> -#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3)
> -
> -#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12)
> -#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11)
> -#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10)
> -#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
> -#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
> -
> -#define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31)
> -#define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23)
> -#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
> -#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
> -#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
> -#define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
> -#define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
> -#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
> -#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
> -#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
> -#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2)
> -#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0)
> -
> -#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
> -#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
> -#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
> -#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
> -#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
> -#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
> -#define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3)
> -#define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
> -#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
> -#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
> -
> -#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
> -#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
> -#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
> -#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
> -#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
> -#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
> -#define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3)
> -#define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
> -#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
> -#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
> -
> -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
> -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16))
> -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16)
> -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16)
> -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
> -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
> -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
> -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
> -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
> -
> -#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
> -#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
> -#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
> -#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
> -#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
> -#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
> -#define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
> -#define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
> -#define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
> -#define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
> -#define HSIO_S1G_MISC_CFG_LANE_RST BIT(0)
> -
> -#define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
> -#define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
> -#define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
> -#define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3)
> -#define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2)
> -#define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
> -#define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0)
> -
> -#define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
> -
> -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31)
> -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30)
> -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0))
> -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0)
> -
> -#define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16))
> -#define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16)
> -#define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16)
> -#define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7)
> -#define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6)
> -#define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3))
> -#define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3)
> -#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3)
> -#define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0))
> -#define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0)
> -
> -#define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31)
> -#define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23)
> -#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
> -#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
> -#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
> -#define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
> -#define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
> -#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
> -#define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
> -#define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
> -#define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2)
> -#define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0)
> -
> -#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
> -#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
> -#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
> -#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
> -#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
> -#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
> -#define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3)
> -#define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
> -#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
> -#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
> -
> -#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
> -#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
> -#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
> -#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
> -#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
> -#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
> -#define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3)
> -#define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
> -#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
> -#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
> -
> -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
> -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16))
> -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16)
> -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16)
> -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
> -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
> -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
> -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
> -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
> -
> -#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13))
> -#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13)
> -#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13)
> -#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
> -#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
> -#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
> -#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
> -#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
> -#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
> -#define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7)
> -#define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6)
> -#define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
> -#define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
> -#define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
> -#define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
> -#define HSIO_S6G_MISC_CFG_LANE_RST BIT(0)
> -
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23)
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18))
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18)
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18)
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13))
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13)
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13)
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6)
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0))
> -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0)
> -
> -#define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8)
> -#define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
> -#define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
> -#define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
> -#define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3)
> -#define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2)
> -#define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
> -#define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0)
> -
> -#define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
> -
> -#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
> -#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
> -#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
> -#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10))
> -#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10)
> -#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
> -#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8))
> -#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8)
> -#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
> -#define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5))
> -#define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5)
> -#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5)
> -#define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4)
> -#define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1))
> -#define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1)
> -#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1)
> -#define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0)
> -
> -#define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29))
> -#define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29)
> -#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29)
> -#define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28)
> -#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24))
> -#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24)
> -#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24)
> -#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20))
> -#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20)
> -#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20)
> -#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18))
> -#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18)
> -#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18)
> -#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15))
> -#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15)
> -#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15)
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13))
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13)
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13)
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11))
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11)
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11)
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9))
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9)
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9)
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7))
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7)
> -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7)
> -#define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6)
> -#define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5)
> -#define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4)
> -#define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3)
> -#define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2)
> -#define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1)
> -#define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0)
> -
> -#define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17))
> -#define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17)
> -#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17)
> -#define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12))
> -#define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12)
> -#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12)
> -#define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8))
> -#define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8)
> -#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8)
> -#define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7)
> -#define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6)
> -#define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5)
> -#define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4)
> -#define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3)
> -#define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2)
> -#define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1)
> -#define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0)
> -
> -#define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27))
> -#define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27)
> -#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27)
> -#define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22))
> -#define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22)
> -#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22)
> -#define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19))
> -#define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19)
> -#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19)
> -#define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16))
> -#define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16)
> -#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16)
> -#define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10))
> -#define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10)
> -#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10)
> -#define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5))
> -#define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5)
> -#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5)
> -#define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3))
> -#define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3)
> -#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3)
> -#define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0))
> -#define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0)
> -
> -#define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18))
> -#define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18)
> -#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
> -#define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12))
> -#define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12)
> -#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
> -#define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6))
> -#define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6)
> -#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
> -#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0))
> -#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0)
> -
> -#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18))
> -#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18)
> -#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
> -#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12))
> -#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12)
> -#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
> -#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6))
> -#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6)
> -#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
> -#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0))
> -#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0)
> -
> -#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18))
> -#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18)
> -#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
> -#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12))
> -#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12)
> -#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
> -#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6))
> -#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6)
> -#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
> -#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0))
> -#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0)
> -
> -#define HSIO_S6G_OB_CFG_OB_IDLE BIT(31)
> -#define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30)
> -#define HSIO_S6G_OB_CFG_OB_POL BIT(29)
> -#define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
> -#define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23)
> -#define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
> -#define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18))
> -#define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18)
> -#define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18)
> -#define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17)
> -#define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16)
> -#define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11))
> -#define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11)
> -#define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11)
> -#define HSIO_S6G_OB_CFG_OB_R_COR BIT(10)
> -#define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9)
> -#define HSIO_S6G_OB_CFG_OB_SR_H BIT(8)
> -#define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4))
> -#define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4)
> -#define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4)
> -#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
> -#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
> -
> -#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
> -#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6)
> -#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
> -#define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0))
> -#define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0)
> -
> -#define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8)
> -#define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7)
> -#define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6)
> -#define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
> -#define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
> -#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
> -#define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3)
> -#define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2)
> -#define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1)
> -#define HSIO_S6G_SER_CFG_SER_ENALI BIT(0)
> -
> -#define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17)
> -#define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16)
> -#define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15)
> -#define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14)
> -#define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13)
> -#define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12)
> -#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9))
> -#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9)
> -#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9)
> -#define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8)
> -#define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7)
> -#define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6)
> -#define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5)
> -#define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4)
> -#define HSIO_S6G_COMMON_CFG_HRATE BIT(3)
> -#define HSIO_S6G_COMMON_CFG_QRATE BIT(2)
> -#define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0))
> -#define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0)
> -
> -#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16))
> -#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16)
> -#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16)
> -#define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15)
> -#define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14)
> -#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
> -#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6)
> -#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
> -#define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5)
> -#define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4)
> -#define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3)
> -#define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2)
> -#define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1)
> -#define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0)
> -
> -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5)
> -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4)
> -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3)
> -#define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2)
> -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1)
> -#define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0)
> -
> -#define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16))
> -#define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16)
> -#define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16)
> -#define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0))
> -#define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0)
> -
> -#define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8)
> -#define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7)
> -#define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6)
> -#define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5)
> -#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4)
> -#define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3)
> -#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2)
> -#define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1)
> -#define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0)
> -
> -#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18))
> -#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18)
> -#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18)
> -#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12))
> -#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12)
> -#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12)
> -#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6))
> -#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6)
> -#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6)
> -#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0))
> -#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0)
> -
> -#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2)
> -#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1)
> -#define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0)
> -
> -#define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10)
> -#define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9)
> -#define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8)
> -#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
> -#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
> -
> -#define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26))
> -#define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26)
> -#define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26)
> -#define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21))
> -#define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21)
> -#define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21)
> -#define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16))
> -#define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16)
> -#define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16)
> -#define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10))
> -#define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10)
> -#define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10)
> -#define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5))
> -#define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5)
> -#define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5)
> -#define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0))
> -#define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0)
> -
> -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31)
> -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30)
> -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0))
> -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0)
> -
> -#define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6)
> -#define HSIO_HW_CFG_DEV1G_9_MODE BIT(5)
> -#define HSIO_HW_CFG_DEV1G_6_MODE BIT(4)
> -#define HSIO_HW_CFG_DEV1G_5_MODE BIT(3)
> -#define HSIO_HW_CFG_DEV1G_4_MODE BIT(2)
> -#define HSIO_HW_CFG_PCIE_ENA BIT(1)
> -#define HSIO_HW_CFG_QSGMII_ENA BIT(0)
> -
> -#define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3)
> -#define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2)
> -#define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1)
> -#define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0)
> -
> -#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1))
> -#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1)
> -#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1)
> -#define HSIO_HW_QSGMII_STAT_SYNC BIT(0)
> -
> -#define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1))
> -#define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1)
> -#define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1)
> -#define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0)
> -
> -#define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5)
> -#define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4)
> -#define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3)
> -#define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2)
> -#define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1)
> -#define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0)
> -
> -#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8))
> -#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8)
> -#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8)
> -#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0))
> -#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0)
> -
> -#define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8)
> -#define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0))
> -#define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0)
> -
> -#endif
> diff --git a/drivers/net/ethernet/mscc/ocelot_regs.c b/drivers/net/ethernet/mscc/ocelot_regs.c
> index e334b40..bf0c609 100644
> --- a/drivers/net/ethernet/mscc/ocelot_regs.c
> +++ b/drivers/net/ethernet/mscc/ocelot_regs.c
> @@ -5,6 +5,7 @@
> * Copyright (c) 2017 Microsemi Corporation
> */
> #include "ocelot.h"
> +#include <soc/mscc/ocelot_hsio.h>
>
> static const u32 ocelot_ana_regmap[] = {
> REG(ANA_ADVLEARN, 0x009000),
> diff --git a/include/soc/mscc/ocelot_hsio.h b/include/soc/mscc/ocelot_hsio.h
> new file mode 100644
> index 0000000..d93ddec
> --- /dev/null
> +++ b/include/soc/mscc/ocelot_hsio.h
> @@ -0,0 +1,785 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Microsemi Ocelot Switch driver
> + *
> + * Copyright (c) 2017 Microsemi Corporation
> + */
> +
> +#ifndef _MSCC_OCELOT_HSIO_H_
> +#define _MSCC_OCELOT_HSIO_H_
> +
> +#define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
> +#define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
> +#define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
> +#define HSIO_PLL5G_CFG0_DIV4 BIT(28)
> +#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
> +#define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
> +#define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
> +#define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
> +#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
> +#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
> +#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
> +#define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
> +#define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
> +#define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
> +#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
> +#define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
> +#define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
> +#define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
> +#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
> +#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6)
> +#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6)
> +#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0))
> +#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)
> +
> +#define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
> +#define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17)
> +#define HSIO_PLL5G_CFG1_ROT_DIR BIT(16)
> +#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15)
> +#define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14)
> +#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
> +#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6)
> +#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
> +#define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5)
> +#define HSIO_PLL5G_CFG1_PWD_TX BIT(4)
> +#define HSIO_PLL5G_CFG1_PWD_RX BIT(3)
> +#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2)
> +#define HSIO_PLL5G_CFG1_HALF_RATE BIT(1)
> +#define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0)
> +
> +#define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30)
> +#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29)
> +#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28)
> +#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27)
> +#define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26)
> +#define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25)
> +#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24)
> +#define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16))
> +#define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16)
> +#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16)
> +#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15)
> +#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14)
> +#define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13)
> +#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12)
> +#define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11)
> +#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10)
> +#define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5))
> +#define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)
> +#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5)
> +#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4)
> +#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3)
> +#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2)
> +#define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1)
> +#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0)
> +
> +#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22))
> +#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22)
> +#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22)
> +#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19))
> +#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19)
> +#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19)
> +#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18)
> +#define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17)
> +#define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16)
> +#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15)
> +#define HSIO_PLL5G_CFG3_RST_FB_N BIT(14)
> +#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13)
> +#define HSIO_PLL5G_CFG3_FORCE_LO BIT(12)
> +#define HSIO_PLL5G_CFG3_FORCE_HI BIT(11)
> +#define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10)
> +#define HSIO_PLL5G_CFG3_FORCE_CP BIT(9)
> +#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8)
> +#define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0))
> +#define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)
> +
> +#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
> +#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16)
> +#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
> +#define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0))
> +#define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0)
> +
> +#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
> +#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16)
> +#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
> +#define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0))
> +#define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0)
> +
> +#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23)
> +#define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20))
> +#define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20)
> +#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20)
> +#define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19)
> +#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16))
> +#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16)
> +#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16)
> +#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8))
> +#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8)
> +#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8)
> +#define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7)
> +#define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6)
> +#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0))
> +#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)
> +
> +#define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12)
> +#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11)
> +#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10)
> +#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9)
> +#define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1))
> +#define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)
> +#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1)
> +#define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0)
> +
> +#define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21))
> +#define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21)
> +#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21)
> +#define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16))
> +#define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16)
> +#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16)
> +#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4))
> +#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4)
> +#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4)
> +#define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1))
> +#define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1)
> +#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1)
> +#define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0)
> +
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31)
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30)
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20))
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20)
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20)
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16))
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16)
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16)
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0))
> +#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0)
> +
> +#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4))
> +#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4)
> +#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2)
> +#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1)
> +#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0)
> +
> +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16))
> +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16)
> +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16)
> +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0))
> +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0)
> +
> +#define HSIO_RCOMP_CFG0_PWD_ENA BIT(13)
> +#define HSIO_RCOMP_CFG0_RUN_CAL BIT(12)
> +#define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10))
> +#define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10)
> +#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10)
> +#define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8))
> +#define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8)
> +#define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
> +#define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4)
> +#define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0))
> +#define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0)
> +
> +#define HSIO_RCOMP_STATUS_BUSY BIT(12)
> +#define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7)
> +#define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0))
> +#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0)
> +
> +#define HSIO_SYNC_ETH_CFG_RSZ 0x4
> +
> +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4))
> +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4)
> +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1))
> +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1)
> +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1)
> +#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0)
> +
> +#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0)
> +
> +#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
> +#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
> +#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
> +#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11))
> +#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11)
> +#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11)
> +#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8))
> +#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8)
> +#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8)
> +#define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5))
> +#define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5)
> +#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5)
> +#define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4)
> +#define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1))
> +#define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1)
> +#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1)
> +#define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0)
> +
> +#define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27)
> +#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24))
> +#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24)
> +#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24)
> +#define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19))
> +#define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19)
> +#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19)
> +#define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14)
> +#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13)
> +#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12)
> +#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11)
> +#define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10)
> +#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9)
> +#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6))
> +#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6)
> +#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6)
> +#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4))
> +#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4)
> +#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4)
> +#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
> +#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0)
> +
> +#define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17))
> +#define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17)
> +#define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17)
> +#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13))
> +#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13)
> +#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
> +#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10))
> +#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10)
> +#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
> +#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9)
> +#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8)
> +#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4))
> +#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4)
> +#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
> +#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
> +
> +#define HSIO_S1G_SER_CFG_SER_IDLE BIT(9)
> +#define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8)
> +#define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7)
> +#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6)
> +#define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
> +#define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
> +#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
> +#define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3)
> +#define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2)
> +#define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1)
> +#define HSIO_S1G_SER_CFG_SER_ENALI BIT(0)
> +
> +#define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31)
> +#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21)
> +#define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18)
> +#define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17)
> +#define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16)
> +#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13))
> +#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13)
> +#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13)
> +#define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12)
> +#define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11)
> +#define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10)
> +#define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9)
> +#define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8)
> +#define HSIO_S1G_COMMON_CFG_HRATE BIT(7)
> +#define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0)
> +
> +#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22)
> +#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21)
> +#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8))
> +#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8)
> +#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8)
> +#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7)
> +#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6)
> +#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5)
> +#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3)
> +
> +#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12)
> +#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11)
> +#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10)
> +#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
> +#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
> +
> +#define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31)
> +#define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23)
> +#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
> +#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
> +#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
> +#define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
> +#define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
> +#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
> +#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
> +#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
> +#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2)
> +#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0)
> +
> +#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
> +#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
> +#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
> +#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
> +#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
> +#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3)
> +#define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
> +#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
> +#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
> +
> +#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
> +#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
> +#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
> +#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
> +#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
> +#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3)
> +#define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
> +#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
> +#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
> +
> +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
> +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16))
> +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16)
> +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16)
> +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
> +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
> +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
> +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
> +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
> +
> +#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
> +#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
> +#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
> +#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
> +#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
> +#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
> +#define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
> +#define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
> +#define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
> +#define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
> +#define HSIO_S1G_MISC_CFG_LANE_RST BIT(0)
> +
> +#define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
> +#define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
> +#define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
> +#define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3)
> +#define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2)
> +#define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
> +#define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0)
> +
> +#define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
> +
> +#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31)
> +#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30)
> +#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0))
> +#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0)
> +
> +#define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16))
> +#define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16)
> +#define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16)
> +#define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7)
> +#define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6)
> +#define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3))
> +#define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3)
> +#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3)
> +#define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0))
> +#define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0)
> +
> +#define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31)
> +#define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23)
> +#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
> +#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
> +#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
> +#define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
> +#define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
> +#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
> +#define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
> +#define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
> +#define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2)
> +#define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0)
> +
> +#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
> +#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
> +#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
> +#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
> +#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
> +#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3)
> +#define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
> +#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
> +#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
> +
> +#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
> +#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
> +#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
> +#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
> +#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
> +#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3)
> +#define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
> +#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
> +#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
> +
> +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
> +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16))
> +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16)
> +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16)
> +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
> +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
> +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
> +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
> +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
> +
> +#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13))
> +#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13)
> +#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13)
> +#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
> +#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
> +#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
> +#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
> +#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
> +#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
> +#define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7)
> +#define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6)
> +#define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
> +#define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
> +#define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
> +#define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
> +#define HSIO_S6G_MISC_CFG_LANE_RST BIT(0)
> +
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23)
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18))
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18)
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18)
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13))
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13)
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13)
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6)
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0))
> +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0)
> +
> +#define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8)
> +#define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
> +#define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
> +#define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
> +#define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3)
> +#define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2)
> +#define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
> +#define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0)
> +
> +#define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
> +
> +#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
> +#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
> +#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
> +#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10))
> +#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10)
> +#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
> +#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8))
> +#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8)
> +#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
> +#define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5))
> +#define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5)
> +#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5)
> +#define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4)
> +#define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1))
> +#define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1)
> +#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1)
> +#define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0)
> +
> +#define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29))
> +#define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29)
> +#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29)
> +#define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28)
> +#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24))
> +#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24)
> +#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24)
> +#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20))
> +#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20)
> +#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20)
> +#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18))
> +#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18)
> +#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18)
> +#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15))
> +#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15)
> +#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15)
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13))
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13)
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13)
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11))
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11)
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11)
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9))
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9)
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9)
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7))
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7)
> +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7)
> +#define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6)
> +#define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5)
> +#define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4)
> +#define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3)
> +#define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2)
> +#define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1)
> +#define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0)
> +
> +#define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17))
> +#define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17)
> +#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17)
> +#define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12))
> +#define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12)
> +#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12)
> +#define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8))
> +#define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8)
> +#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8)
> +#define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7)
> +#define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6)
> +#define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5)
> +#define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4)
> +#define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3)
> +#define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2)
> +#define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1)
> +#define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0)
> +
> +#define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27))
> +#define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27)
> +#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27)
> +#define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22))
> +#define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22)
> +#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22)
> +#define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19))
> +#define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19)
> +#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19)
> +#define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16))
> +#define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16)
> +#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16)
> +#define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10))
> +#define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10)
> +#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10)
> +#define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5))
> +#define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5)
> +#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5)
> +#define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3))
> +#define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3)
> +#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3)
> +#define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0))
> +#define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0)
> +
> +#define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18))
> +#define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18)
> +#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
> +#define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12))
> +#define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12)
> +#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
> +#define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6))
> +#define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6)
> +#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
> +#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0))
> +#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0)
> +
> +#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18))
> +#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18)
> +#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
> +#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12))
> +#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12)
> +#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
> +#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6))
> +#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6)
> +#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
> +#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0))
> +#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0)
> +
> +#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18))
> +#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18)
> +#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
> +#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12))
> +#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12)
> +#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
> +#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6))
> +#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6)
> +#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
> +#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0))
> +#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0)
> +
> +#define HSIO_S6G_OB_CFG_OB_IDLE BIT(31)
> +#define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30)
> +#define HSIO_S6G_OB_CFG_OB_POL BIT(29)
> +#define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
> +#define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23)
> +#define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
> +#define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18))
> +#define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18)
> +#define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18)
> +#define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17)
> +#define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16)
> +#define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11))
> +#define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11)
> +#define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11)
> +#define HSIO_S6G_OB_CFG_OB_R_COR BIT(10)
> +#define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9)
> +#define HSIO_S6G_OB_CFG_OB_SR_H BIT(8)
> +#define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4))
> +#define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4)
> +#define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
> +#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
> +
> +#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
> +#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6)
> +#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
> +#define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0))
> +#define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0)
> +
> +#define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8)
> +#define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7)
> +#define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6)
> +#define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
> +#define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
> +#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
> +#define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3)
> +#define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2)
> +#define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1)
> +#define HSIO_S6G_SER_CFG_SER_ENALI BIT(0)
> +
> +#define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17)
> +#define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16)
> +#define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15)
> +#define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14)
> +#define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13)
> +#define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12)
> +#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9))
> +#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9)
> +#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9)
> +#define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8)
> +#define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7)
> +#define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6)
> +#define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5)
> +#define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4)
> +#define HSIO_S6G_COMMON_CFG_HRATE BIT(3)
> +#define HSIO_S6G_COMMON_CFG_QRATE BIT(2)
> +#define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0))
> +#define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0)
> +
> +#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16))
> +#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16)
> +#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16)
> +#define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15)
> +#define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14)
> +#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
> +#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6)
> +#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
> +#define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5)
> +#define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4)
> +#define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3)
> +#define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2)
> +#define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1)
> +#define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0)
> +
> +#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5)
> +#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4)
> +#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3)
> +#define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2)
> +#define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1)
> +#define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0)
> +
> +#define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16))
> +#define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16)
> +#define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16)
> +#define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0))
> +#define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0)
> +
> +#define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8)
> +#define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7)
> +#define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6)
> +#define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5)
> +#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4)
> +#define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3)
> +#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2)
> +#define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1)
> +#define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0)
> +
> +#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18))
> +#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18)
> +#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18)
> +#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12))
> +#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12)
> +#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12)
> +#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6))
> +#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6)
> +#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6)
> +#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0))
> +#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0)
> +
> +#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2)
> +#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1)
> +#define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0)
> +
> +#define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10)
> +#define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9)
> +#define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8)
> +#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
> +#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
> +
> +#define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26))
> +#define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26)
> +#define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26)
> +#define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21))
> +#define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21)
> +#define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21)
> +#define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16))
> +#define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16)
> +#define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16)
> +#define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10))
> +#define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10)
> +#define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10)
> +#define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5))
> +#define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5)
> +#define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5)
> +#define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0))
> +#define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0)
> +
> +#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31)
> +#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30)
> +#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0))
> +#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0)
> +
> +#define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6)
> +#define HSIO_HW_CFG_DEV1G_9_MODE BIT(5)
> +#define HSIO_HW_CFG_DEV1G_6_MODE BIT(4)
> +#define HSIO_HW_CFG_DEV1G_5_MODE BIT(3)
> +#define HSIO_HW_CFG_DEV1G_4_MODE BIT(2)
> +#define HSIO_HW_CFG_PCIE_ENA BIT(1)
> +#define HSIO_HW_CFG_QSGMII_ENA BIT(0)
> +
> +#define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3)
> +#define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2)
> +#define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1)
> +#define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0)
> +
> +#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1))
> +#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1)
> +#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1)
> +#define HSIO_HW_QSGMII_STAT_SYNC BIT(0)
> +
> +#define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1))
> +#define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1)
> +#define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1)
> +#define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0)
> +
> +#define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5)
> +#define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4)
> +#define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3)
> +#define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2)
> +#define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1)
> +#define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0)
> +
> +#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8))
> +#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8)
> +#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8)
> +#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0))
> +#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0)
> +
> +#define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8)
> +#define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0))
> +#define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0)
> +
> +#endif
> --
> git-series 0.9.1
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH net-next 05/10] net: mscc: ocelot: simplify register access for PLL5 configuration
From: Alexandre Belloni @ 2018-07-31 8:02 UTC (permalink / raw)
To: Quentin Schulz
Cc: ralf, paul.burton, jhogan, robh+dt, mark.rutland, davem, kishon,
andrew, f.fainelli, linux-mips, devicetree, linux-kernel, netdev,
allan.nielsen, thomas.petazzoni
In-Reply-To: <df5856230f6a2932a8e0289dc6e8d12234a02bfe.1532954208.git-series.quentin.schulz@bootlin.com>
On 30/07/2018 14:43:50+0200, Quentin Schulz wrote:
> Since HSIO address space can be accessed by different drivers, let's
> simplify the register address definitions so that it can be easily used
> by all drivers and put the register address definition in the
> include/soc/mscc/ocelot_hsio.h header file.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> drivers/net/ethernet/mscc/ocelot.h | 73 +---------------------
> drivers/net/ethernet/mscc/ocelot_regs.c | 92 ++------------------------
> include/soc/mscc/ocelot_hsio.h | 74 +++++++++++++++++++++-
> 3 files changed, 83 insertions(+), 156 deletions(-)
>
> diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
> index 2da20a3..3720e51 100644
> --- a/drivers/net/ethernet/mscc/ocelot.h
> +++ b/drivers/net/ethernet/mscc/ocelot.h
> @@ -332,79 +332,6 @@ enum ocelot_reg {
> SYS_CM_DATA_RD,
> SYS_CM_OP,
> SYS_CM_DATA,
> - HSIO_PLL5G_CFG0 = HSIO << TARGET_OFFSET,
> - HSIO_PLL5G_CFG1,
> - HSIO_PLL5G_CFG2,
> - HSIO_PLL5G_CFG3,
> - HSIO_PLL5G_CFG4,
> - HSIO_PLL5G_CFG5,
> - HSIO_PLL5G_CFG6,
> - HSIO_PLL5G_STATUS0,
> - HSIO_PLL5G_STATUS1,
> - HSIO_PLL5G_BIST_CFG0,
> - HSIO_PLL5G_BIST_CFG1,
> - HSIO_PLL5G_BIST_CFG2,
> - HSIO_PLL5G_BIST_STAT0,
> - HSIO_PLL5G_BIST_STAT1,
> - HSIO_RCOMP_CFG0,
> - HSIO_RCOMP_STATUS,
> - HSIO_SYNC_ETH_CFG,
> - HSIO_SYNC_ETH_PLL_CFG,
> - HSIO_S1G_DES_CFG,
> - HSIO_S1G_IB_CFG,
> - HSIO_S1G_OB_CFG,
> - HSIO_S1G_SER_CFG,
> - HSIO_S1G_COMMON_CFG,
> - HSIO_S1G_PLL_CFG,
> - HSIO_S1G_PLL_STATUS,
> - HSIO_S1G_DFT_CFG0,
> - HSIO_S1G_DFT_CFG1,
> - HSIO_S1G_DFT_CFG2,
> - HSIO_S1G_TP_CFG,
> - HSIO_S1G_RC_PLL_BIST_CFG,
> - HSIO_S1G_MISC_CFG,
> - HSIO_S1G_DFT_STATUS,
> - HSIO_S1G_MISC_STATUS,
> - HSIO_MCB_S1G_ADDR_CFG,
> - HSIO_S6G_DIG_CFG,
> - HSIO_S6G_DFT_CFG0,
> - HSIO_S6G_DFT_CFG1,
> - HSIO_S6G_DFT_CFG2,
> - HSIO_S6G_TP_CFG0,
> - HSIO_S6G_TP_CFG1,
> - HSIO_S6G_RC_PLL_BIST_CFG,
> - HSIO_S6G_MISC_CFG,
> - HSIO_S6G_OB_ANEG_CFG,
> - HSIO_S6G_DFT_STATUS,
> - HSIO_S6G_ERR_CNT,
> - HSIO_S6G_MISC_STATUS,
> - HSIO_S6G_DES_CFG,
> - HSIO_S6G_IB_CFG,
> - HSIO_S6G_IB_CFG1,
> - HSIO_S6G_IB_CFG2,
> - HSIO_S6G_IB_CFG3,
> - HSIO_S6G_IB_CFG4,
> - HSIO_S6G_IB_CFG5,
> - HSIO_S6G_OB_CFG,
> - HSIO_S6G_OB_CFG1,
> - HSIO_S6G_SER_CFG,
> - HSIO_S6G_COMMON_CFG,
> - HSIO_S6G_PLL_CFG,
> - HSIO_S6G_ACJTAG_CFG,
> - HSIO_S6G_GP_CFG,
> - HSIO_S6G_IB_STATUS0,
> - HSIO_S6G_IB_STATUS1,
> - HSIO_S6G_ACJTAG_STATUS,
> - HSIO_S6G_PLL_STATUS,
> - HSIO_S6G_REVID,
> - HSIO_MCB_S6G_ADDR_CFG,
> - HSIO_HW_CFG,
> - HSIO_HW_QSGMII_CFG,
> - HSIO_HW_QSGMII_STAT,
> - HSIO_CLK_CFG,
> - HSIO_TEMP_SENSOR_CTRL,
> - HSIO_TEMP_SENSOR_CFG,
> - HSIO_TEMP_SENSOR_STAT,
> };
>
> enum ocelot_regfield {
> diff --git a/drivers/net/ethernet/mscc/ocelot_regs.c b/drivers/net/ethernet/mscc/ocelot_regs.c
> index bf0c609..9271af1 100644
> --- a/drivers/net/ethernet/mscc/ocelot_regs.c
> +++ b/drivers/net/ethernet/mscc/ocelot_regs.c
> @@ -103,82 +103,6 @@ static const u32 ocelot_qs_regmap[] = {
> REG(QS_INH_DBG, 0x000048),
> };
>
> -static const u32 ocelot_hsio_regmap[] = {
> - REG(HSIO_PLL5G_CFG0, 0x000000),
> - REG(HSIO_PLL5G_CFG1, 0x000004),
> - REG(HSIO_PLL5G_CFG2, 0x000008),
> - REG(HSIO_PLL5G_CFG3, 0x00000c),
> - REG(HSIO_PLL5G_CFG4, 0x000010),
> - REG(HSIO_PLL5G_CFG5, 0x000014),
> - REG(HSIO_PLL5G_CFG6, 0x000018),
> - REG(HSIO_PLL5G_STATUS0, 0x00001c),
> - REG(HSIO_PLL5G_STATUS1, 0x000020),
> - REG(HSIO_PLL5G_BIST_CFG0, 0x000024),
> - REG(HSIO_PLL5G_BIST_CFG1, 0x000028),
> - REG(HSIO_PLL5G_BIST_CFG2, 0x00002c),
> - REG(HSIO_PLL5G_BIST_STAT0, 0x000030),
> - REG(HSIO_PLL5G_BIST_STAT1, 0x000034),
> - REG(HSIO_RCOMP_CFG0, 0x000038),
> - REG(HSIO_RCOMP_STATUS, 0x00003c),
> - REG(HSIO_SYNC_ETH_CFG, 0x000040),
> - REG(HSIO_SYNC_ETH_PLL_CFG, 0x000048),
> - REG(HSIO_S1G_DES_CFG, 0x00004c),
> - REG(HSIO_S1G_IB_CFG, 0x000050),
> - REG(HSIO_S1G_OB_CFG, 0x000054),
> - REG(HSIO_S1G_SER_CFG, 0x000058),
> - REG(HSIO_S1G_COMMON_CFG, 0x00005c),
> - REG(HSIO_S1G_PLL_CFG, 0x000060),
> - REG(HSIO_S1G_PLL_STATUS, 0x000064),
> - REG(HSIO_S1G_DFT_CFG0, 0x000068),
> - REG(HSIO_S1G_DFT_CFG1, 0x00006c),
> - REG(HSIO_S1G_DFT_CFG2, 0x000070),
> - REG(HSIO_S1G_TP_CFG, 0x000074),
> - REG(HSIO_S1G_RC_PLL_BIST_CFG, 0x000078),
> - REG(HSIO_S1G_MISC_CFG, 0x00007c),
> - REG(HSIO_S1G_DFT_STATUS, 0x000080),
> - REG(HSIO_S1G_MISC_STATUS, 0x000084),
> - REG(HSIO_MCB_S1G_ADDR_CFG, 0x000088),
> - REG(HSIO_S6G_DIG_CFG, 0x00008c),
> - REG(HSIO_S6G_DFT_CFG0, 0x000090),
> - REG(HSIO_S6G_DFT_CFG1, 0x000094),
> - REG(HSIO_S6G_DFT_CFG2, 0x000098),
> - REG(HSIO_S6G_TP_CFG0, 0x00009c),
> - REG(HSIO_S6G_TP_CFG1, 0x0000a0),
> - REG(HSIO_S6G_RC_PLL_BIST_CFG, 0x0000a4),
> - REG(HSIO_S6G_MISC_CFG, 0x0000a8),
> - REG(HSIO_S6G_OB_ANEG_CFG, 0x0000ac),
> - REG(HSIO_S6G_DFT_STATUS, 0x0000b0),
> - REG(HSIO_S6G_ERR_CNT, 0x0000b4),
> - REG(HSIO_S6G_MISC_STATUS, 0x0000b8),
> - REG(HSIO_S6G_DES_CFG, 0x0000bc),
> - REG(HSIO_S6G_IB_CFG, 0x0000c0),
> - REG(HSIO_S6G_IB_CFG1, 0x0000c4),
> - REG(HSIO_S6G_IB_CFG2, 0x0000c8),
> - REG(HSIO_S6G_IB_CFG3, 0x0000cc),
> - REG(HSIO_S6G_IB_CFG4, 0x0000d0),
> - REG(HSIO_S6G_IB_CFG5, 0x0000d4),
> - REG(HSIO_S6G_OB_CFG, 0x0000d8),
> - REG(HSIO_S6G_OB_CFG1, 0x0000dc),
> - REG(HSIO_S6G_SER_CFG, 0x0000e0),
> - REG(HSIO_S6G_COMMON_CFG, 0x0000e4),
> - REG(HSIO_S6G_PLL_CFG, 0x0000e8),
> - REG(HSIO_S6G_ACJTAG_CFG, 0x0000ec),
> - REG(HSIO_S6G_GP_CFG, 0x0000f0),
> - REG(HSIO_S6G_IB_STATUS0, 0x0000f4),
> - REG(HSIO_S6G_IB_STATUS1, 0x0000f8),
> - REG(HSIO_S6G_ACJTAG_STATUS, 0x0000fc),
> - REG(HSIO_S6G_PLL_STATUS, 0x000100),
> - REG(HSIO_S6G_REVID, 0x000104),
> - REG(HSIO_MCB_S6G_ADDR_CFG, 0x000108),
> - REG(HSIO_HW_CFG, 0x00010c),
> - REG(HSIO_HW_QSGMII_CFG, 0x000110),
> - REG(HSIO_HW_QSGMII_STAT, 0x000114),
> - REG(HSIO_CLK_CFG, 0x000118),
> - REG(HSIO_TEMP_SENSOR_CTRL, 0x00011c),
> - REG(HSIO_TEMP_SENSOR_CFG, 0x000120),
> - REG(HSIO_TEMP_SENSOR_STAT, 0x000124),
> -};
> -
> static const u32 ocelot_qsys_regmap[] = {
> REG(QSYS_PORT_MODE, 0x011200),
> REG(QSYS_SWITCH_PORT_MODE, 0x011234),
> @@ -303,7 +227,6 @@ static const u32 ocelot_sys_regmap[] = {
> static const u32 *ocelot_regmap[] = {
> [ANA] = ocelot_ana_regmap,
> [QS] = ocelot_qs_regmap,
> - [HSIO] = ocelot_hsio_regmap,
> [QSYS] = ocelot_qsys_regmap,
> [REW] = ocelot_rew_regmap,
> [SYS] = ocelot_sys_regmap,
> @@ -454,9 +377,11 @@ static void ocelot_pll5_init(struct ocelot *ocelot)
> /* Configure PLL5. This will need a proper CCF driver
> * The values are coming from the VTSS API for Ocelot
> */
> - ocelot_write(ocelot, HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
> - HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8), HSIO_PLL5G_CFG4);
> - ocelot_write(ocelot, HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
> + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
> + HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
> + HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
> + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
> + HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
> HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
> HSIO_PLL5G_CFG0_ENA_BIAS |
> HSIO_PLL5G_CFG0_ENA_VCO_BUF |
> @@ -466,13 +391,14 @@ static void ocelot_pll5_init(struct ocelot *ocelot)
> HSIO_PLL5G_CFG0_SELBGV820(4) |
> HSIO_PLL5G_CFG0_DIV4 |
> HSIO_PLL5G_CFG0_ENA_CLKTREE |
> - HSIO_PLL5G_CFG0_ENA_LANE, HSIO_PLL5G_CFG0);
> - ocelot_write(ocelot, HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
> + HSIO_PLL5G_CFG0_ENA_LANE);
> + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
> + HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
> HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
> HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
> HSIO_PLL5G_CFG2_ENA_AMPCTRL |
> HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
> - HSIO_PLL5G_CFG2_AMPC_SEL(0x10), HSIO_PLL5G_CFG2);
> + HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
> }
>
> int ocelot_chip_init(struct ocelot *ocelot)
> diff --git a/include/soc/mscc/ocelot_hsio.h b/include/soc/mscc/ocelot_hsio.h
> index d93ddec..43112dd 100644
> --- a/include/soc/mscc/ocelot_hsio.h
> +++ b/include/soc/mscc/ocelot_hsio.h
> @@ -8,6 +8,80 @@
> #ifndef _MSCC_OCELOT_HSIO_H_
> #define _MSCC_OCELOT_HSIO_H_
>
> +#define HSIO_PLL5G_CFG0 0x0000
> +#define HSIO_PLL5G_CFG1 0x0004
> +#define HSIO_PLL5G_CFG2 0x0008
> +#define HSIO_PLL5G_CFG3 0x000c
> +#define HSIO_PLL5G_CFG4 0x0010
> +#define HSIO_PLL5G_CFG5 0x0014
> +#define HSIO_PLL5G_CFG6 0x0018
> +#define HSIO_PLL5G_STATUS0 0x001c
> +#define HSIO_PLL5G_STATUS1 0x0020
> +#define HSIO_PLL5G_BIST_CFG0 0x0024
> +#define HSIO_PLL5G_BIST_CFG1 0x0028
> +#define HSIO_PLL5G_BIST_CFG2 0x002c
> +#define HSIO_PLL5G_BIST_STAT0 0x0030
> +#define HSIO_PLL5G_BIST_STAT1 0x0034
> +#define HSIO_RCOMP_CFG0 0x0038
> +#define HSIO_RCOMP_STATUS 0x003c
> +#define HSIO_SYNC_ETH_CFG 0x0040
> +#define HSIO_SYNC_ETH_PLL_CFG 0x0048
> +#define HSIO_S1G_DES_CFG 0x004c
> +#define HSIO_S1G_IB_CFG 0x0050
> +#define HSIO_S1G_OB_CFG 0x0054
> +#define HSIO_S1G_SER_CFG 0x0058
> +#define HSIO_S1G_COMMON_CFG 0x005c
> +#define HSIO_S1G_PLL_CFG 0x0060
> +#define HSIO_S1G_PLL_STATUS 0x0064
> +#define HSIO_S1G_DFT_CFG0 0x0068
> +#define HSIO_S1G_DFT_CFG1 0x006c
> +#define HSIO_S1G_DFT_CFG2 0x0070
> +#define HSIO_S1G_TP_CFG 0x0074
> +#define HSIO_S1G_RC_PLL_BIST_CFG 0x0078
> +#define HSIO_S1G_MISC_CFG 0x007c
> +#define HSIO_S1G_DFT_STATUS 0x0080
> +#define HSIO_S1G_MISC_STATUS 0x0084
> +#define HSIO_MCB_S1G_ADDR_CFG 0x0088
> +#define HSIO_S6G_DIG_CFG 0x008c
> +#define HSIO_S6G_DFT_CFG0 0x0090
> +#define HSIO_S6G_DFT_CFG1 0x0094
> +#define HSIO_S6G_DFT_CFG2 0x0098
> +#define HSIO_S6G_TP_CFG0 0x009c
> +#define HSIO_S6G_TP_CFG1 0x00a0
> +#define HSIO_S6G_RC_PLL_BIST_CFG 0x00a4
> +#define HSIO_S6G_MISC_CFG 0x00a8
> +#define HSIO_S6G_OB_ANEG_CFG 0x00ac
> +#define HSIO_S6G_DFT_STATUS 0x00b0
> +#define HSIO_S6G_ERR_CNT 0x00b4
> +#define HSIO_S6G_MISC_STATUS 0x00b8
> +#define HSIO_S6G_DES_CFG 0x00bc
> +#define HSIO_S6G_IB_CFG 0x00c0
> +#define HSIO_S6G_IB_CFG1 0x00c4
> +#define HSIO_S6G_IB_CFG2 0x00c8
> +#define HSIO_S6G_IB_CFG3 0x00cc
> +#define HSIO_S6G_IB_CFG4 0x00d0
> +#define HSIO_S6G_IB_CFG5 0x00d4
> +#define HSIO_S6G_OB_CFG 0x00d8
> +#define HSIO_S6G_OB_CFG1 0x00dc
> +#define HSIO_S6G_SER_CFG 0x00e0
> +#define HSIO_S6G_COMMON_CFG 0x00e4
> +#define HSIO_S6G_PLL_CFG 0x00e8
> +#define HSIO_S6G_ACJTAG_CFG 0x00ec
> +#define HSIO_S6G_GP_CFG 0x00f0
> +#define HSIO_S6G_IB_STATUS0 0x00f4
> +#define HSIO_S6G_IB_STATUS1 0x00f8
> +#define HSIO_S6G_ACJTAG_STATUS 0x00fc
> +#define HSIO_S6G_PLL_STATUS 0x0100
> +#define HSIO_S6G_REVID 0x0104
> +#define HSIO_MCB_S6G_ADDR_CFG 0x0108
> +#define HSIO_HW_CFG 0x010c
> +#define HSIO_HW_QSGMII_CFG 0x0110
> +#define HSIO_HW_QSGMII_STAT 0x0114
> +#define HSIO_CLK_CFG 0x0118
> +#define HSIO_TEMP_SENSOR_CTRL 0x011c
> +#define HSIO_TEMP_SENSOR_CFG 0x0120
> +#define HSIO_TEMP_SENSOR_STAT 0x0124
> +
> #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
> #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
> #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
> --
> git-series 0.9.1
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: linux-next: manual merge of the crypto tree with the net-next tree
From: Krzysztof Kozlowski @ 2018-07-31 6:24 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Herbert Xu, David Miller, Networking, Linux-Next Mailing List,
Linux Kernel Mailing List
In-Reply-To: <20180730132253.33633f56@canb.auug.org.au>
Hi All,
The resolution looks correct. The other way would be to amend the
commit 5d258b48efbd ("net: ethernet: Use existing define with
polynomial") in crypto tree and remove changes to freescale drivers.
Best regards,
Krzysztof
On 30 July 2018 at 05:22, Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> Hi Herbert,
>
> Today's linux-next merge of the crypto tree got conflicts in:
>
> drivers/net/ethernet/freescale/fec_main.c
> drivers/net/ethernet/freescale/fs_enet/mac-fec.c
>
> between commits:
>
> 16f6e9835bcd ("net: ethernet: freescale: Use generic CRC32 implementation")
> d805f6a86829 ("net: ethernet: fs-enet: Use generic CRC32 implementation")
>
> from the net-next tree and commit:
>
> 5d258b48efbd ("net: ethernet: Use existing define with polynomial")
>
> from the crypto tree.
>
> I fixed it up (I used the net-next tree versions (but kept the rmeoval
> of the CRC32_POLY and FEC_CRC_POLY defines) and can carry the fix as
> necessary. This is now fixed as far as linux-next is concerned, but any
> non trivial conflicts should be mentioned to your upstream maintainer
> when your tree is submitted for merging. You may also want to consider
> cooperating with the maintainer of the conflicting tree to minimise any
> particularly complex conflicts.
>
> --
> Cheers,
> Stephen Rothwell
^ permalink raw reply
* Re: [PATCH net-next 0/3] xsk: improvements to RX queue check and replace
From: Björn Töpel @ 2018-07-31 6:34 UTC (permalink / raw)
To: Jakub Kicinski
Cc: David Miller, Alexei Starovoitov, Daniel Borkmann, Netdev,
oss-drivers, Björn Töpel, Magnus Karlsson,
Karlsson, Magnus
In-Reply-To: <20180731034353.3774-1-jakub.kicinski@netronome.com>
Den tis 31 juli 2018 kl 05:46 skrev Jakub Kicinski
<jakub.kicinski@netronome.com>:
>
> Hi!
>
> First 3 patches of my recent RFC. The first one make the check against
> real_num_rx_queues slightly more reliable, while the latter two redefine
> XDP_QUERY_XSK_UMEM slightly to disallow replacing UMEM in the driver at
> the stack level.
>
> I'm not sure where this lays on the bpf vs net trees scale, but there
> should be no conflicts with either tree.
>
> Jakub Kicinski (3):
> net: update real_num_rx_queues even when !CONFIG_SYSFS
> xsk: refactor xdp_umem_assign_dev()
> xsk: don't allow umem replace at stack level
>
> include/linux/netdevice.h | 10 +++---
> net/xdp/xdp_umem.c | 70 +++++++++++++++++++++++----------------
> 2 files changed, 47 insertions(+), 33 deletions(-)
>
> --
> 2.17.1
>
LGTM!
For the series:
Acked-by: Björn Töpel <bjorn.topel@intel.com>
^ permalink raw reply
* Re: [patch net-next] net: sched: don't dump chains only held by actions
From: Jiri Pirko @ 2018-07-31 6:32 UTC (permalink / raw)
To: Cong Wang
Cc: Linux Kernel Network Developers, David Miller, Jamal Hadi Salim,
Jakub Kicinski, mlxsw
In-Reply-To: <CAM_iQpWE1SW44dQGASSwB6UHD_tBCM+K_N2=y6-JcO9ANOSiww@mail.gmail.com>
Mon, Jul 30, 2018 at 08:19:56PM CEST, xiyou.wangcong@gmail.com wrote:
>On Sun, Jul 29, 2018 at 12:54 AM Jiri Pirko <jiri@resnulli.us> wrote:
>>
>> Sat, Jul 28, 2018 at 07:39:36PM CEST, xiyou.wangcong@gmail.com wrote:
>> >On Sat, Jul 28, 2018 at 10:20 AM Cong Wang <xiyou.wangcong@gmail.com> wrote:
>> >>
>> >> On Fri, Jul 27, 2018 at 12:47 AM Jiri Pirko <jiri@resnulli.us> wrote:
>> >> >
>> >> > From: Jiri Pirko <jiri@mellanox.com>
>> >> >
>> >> > In case a chain is empty and not explicitly created by a user,
>> >> > such chain should not exist. The only exception is if there is
>> >> > an action "goto chain" pointing to it. In that case, don't show the
>> >> > chain in the dump. Track the chain references held by actions and
>> >> > use them to find out if a chain should or should not be shown
>> >> > in chain dump.
>> >> >
>> >> > Signed-off-by: Jiri Pirko <jiri@mellanox.com>
>> >>
>> >> Looks reasonable to me.
>> >>
>> >> Acked-by: Cong Wang <xiyou.wangcong@gmail.com>
>> >
>> >Hold on...
>> >
>> >If you increase the refcnt for a zombie chain on NEWCHAIN path,
>> >then it would become a non-zombie, this makes sense. However,
>> >if the action_refcnt gets increased again when another action uses it,
>> >it become a zombie again because refcnt==action_refcnt??
>>
>> No. action always increases both refcnt and action_refcnt
>
>Hmm, then the name zombie is confusing, with your definition all
>chains implicitly created by actions are zombies, unless touched
>by user explicitly. Please find a better name.
Okay. Perhaps chain_inactive?
>
>Also, tcf_chain_get_by_act() could send out RTM_NEWCHAIN too,
>which is confusing too as it is still a "zombie".
Will check.
^ permalink raw reply
* Re: [net-next PATCH] mlx5: handle DMA mapping error case for XDP redirect
From: Tariq Toukan @ 2018-07-31 6:35 UTC (permalink / raw)
To: Jesper Dangaard Brouer, Saeed Mahameed, Tariq Toukan; +Cc: netdev, eugenia
In-Reply-To: <153297294832.31547.16715215152984131209.stgit@firesoul>
On 30/07/2018 8:49 PM, Jesper Dangaard Brouer wrote:
> Commit 58b99ee3e3eb ("net/mlx5e: Add support for XDP_REDIRECT in device-out side")
> forgot to return/free the xdp_frame in case the DMA mapping failed, correct this.
>
> Also DMA unmap the frame in case mlx5e_xmit_xdp_frame() fails.
>
> Fixes: 58b99ee3e3eb ("net/mlx5e: Add support for XDP_REDIRECT in device-out side")
> Signed-off-by: Jesper Dangaard Brouer <brouer@redhat.com>
> ---
> drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
> index bab8cd44d1c5..1881468dbcfa 100644
> --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
> +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
> @@ -283,6 +283,7 @@ int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
> xdpi.dma_addr = dma_map_single(sq->pdev, xdpf->data, xdpf->len,
> DMA_TO_DEVICE);
> if (unlikely(dma_mapping_error(sq->pdev, xdpi.dma_addr))) {
> + xdp_return_frame_rx_napi(xdpf);
> drops++;
> continue;
> }
> @@ -290,6 +291,8 @@ int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
> xdpi.xdpf = xdpf;
>
> if (unlikely(!mlx5e_xmit_xdp_frame(sq, &xdpi))) {
> + dma_unmap_single(sq->pdev, xdpi.dma_addr,
> + xdpf->len, DMA_TO_DEVICE);
> xdp_return_frame_rx_napi(xdpf);
> drops++;
> }
>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Thanks Jesper!
^ permalink raw reply
* KASAN: use-after-free Read in refcount_sub_and_test
From: syzbot @ 2018-07-31 8:22 UTC (permalink / raw)
To: davem, kuznet, linux-kernel, netdev, syzkaller-bugs, yoshfuji
Hello,
syzbot found the following crash on:
HEAD commit: 61f4b23769f0 netlink: Don't shift with UB on nlk->ngroups
git tree: net
console output: https://syzkaller.appspot.com/x/log.txt?x=16ed5cf0400000
kernel config: https://syzkaller.appspot.com/x/.config?x=ffb4428fdc82f93b
dashboard link: https://syzkaller.appspot.com/bug?extid=8c17db54fd0c0a2ee849
compiler: gcc (GCC) 8.0.1 20180413 (experimental)
Unfortunately, I don't have any reproducer for this crash yet.
IMPORTANT: if you fix the bug, please add the following tag to the commit:
Reported-by: syzbot+8c17db54fd0c0a2ee849@syzkaller.appspotmail.com
device lo left promiscuous mode
==================================================================
BUG: KASAN: use-after-free in atomic_read
include/asm-generic/atomic-instrumented.h:21 [inline]
BUG: KASAN: use-after-free in refcount_sub_and_test+0x9a/0x350
lib/refcount.c:179
Read of size 4 at addr ffff8801d96d2844 by task syz-executor1/4479
CPU: 0 PID: 4479 Comm: syz-executor1 Not tainted 4.18.0-rc6+ #34
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS
Google 01/01/2011
Call Trace:
__dump_stack lib/dump_stack.c:77 [inline]
dump_stack+0x1c9/0x2b4 lib/dump_stack.c:113
print_address_description+0x6c/0x20b mm/kasan/report.c:256
kasan_report_error mm/kasan/report.c:354 [inline]
kasan_report.cold.7+0x242/0x2fe mm/kasan/report.c:412
check_memory_region_inline mm/kasan/kasan.c:260 [inline]
check_memory_region+0x13e/0x1b0 mm/kasan/kasan.c:267
kasan_check_read+0x11/0x20 mm/kasan/kasan.c:272
atomic_read include/asm-generic/atomic-instrumented.h:21 [inline]
refcount_sub_and_test+0x9a/0x350 lib/refcount.c:179
refcount_dec_and_test+0x1a/0x20 lib/refcount.c:212
fib6_metrics_release+0x4f/0x90 net/ipv6/ip6_fib.c:178
fib6_drop_pcpu_from net/ipv6/ip6_fib.c:899 [inline]
fib6_purge_rt+0x5ec/0x7f0 net/ipv6/ip6_fib.c:934
fib6_del_route net/ipv6/ip6_fib.c:1784 [inline]
fib6_del+0xc11/0x1310 net/ipv6/ip6_fib.c:1815
fib6_clean_node+0x3ee/0x5e0 net/ipv6/ip6_fib.c:1976
fib6_walk_continue+0x4b1/0x8e0 net/ipv6/ip6_fib.c:1899
fib6_walk+0x95/0xf0 net/ipv6/ip6_fib.c:1947
fib6_clean_tree+0x1ea/0x360 net/ipv6/ip6_fib.c:2024
__fib6_clean_all+0x21c/0x420 net/ipv6/ip6_fib.c:2040
fib6_clean_all+0x27/0x30 net/ipv6/ip6_fib.c:2051
rt6_sync_down_dev net/ipv6/route.c:4083 [inline]
rt6_disable_ip+0x111/0x7e0 net/ipv6/route.c:4088
addrconf_ifdown+0x16f/0x1670 net/ipv6/addrconf.c:3650
addrconf_notify+0x6e9/0x27f0 net/ipv6/addrconf.c:3575
notifier_call_chain+0x180/0x390 kernel/notifier.c:93
__raw_notifier_call_chain kernel/notifier.c:394 [inline]
raw_notifier_call_chain+0x2d/0x40 kernel/notifier.c:401
call_netdevice_notifiers_info+0x3f/0x90 net/core/dev.c:1735
call_netdevice_notifiers net/core/dev.c:1753 [inline]
dev_close_many+0x447/0x8d0 net/core/dev.c:1505
rollback_registered_many+0x52b/0xef0 net/core/dev.c:7452
rollback_registered+0x1e9/0x420 net/core/dev.c:7517
unregister_netdevice_queue+0x32f/0x660 net/core/dev.c:8561
unregister_netdevice include/linux/netdevice.h:2548 [inline]
__tun_detach+0x11d1/0x15e0 drivers/net/tun.c:727
tun_detach drivers/net/tun.c:744 [inline]
tun_chr_close+0xe3/0x180 drivers/net/tun.c:3271
__fput+0x355/0x8b0 fs/file_table.c:209
____fput+0x15/0x20 fs/file_table.c:243
task_work_run+0x1ec/0x2a0 kernel/task_work.c:113
exit_task_work include/linux/task_work.h:22 [inline]
do_exit+0x1b08/0x2750 kernel/exit.c:865
do_group_exit+0x177/0x440 kernel/exit.c:968
__do_sys_exit_group kernel/exit.c:979 [inline]
__se_sys_exit_group kernel/exit.c:977 [inline]
__x64_sys_exit_group+0x3e/0x50 kernel/exit.c:977
do_syscall_64+0x1b9/0x820 arch/x86/entry/common.c:290
entry_SYSCALL_64_after_hwframe+0x49/0xbe
RIP: 0033:0x456a09
Code: Bad RIP value.
RSP: 002b:00007fffa8ff4908 EFLAGS: 00000246 ORIG_RAX: 00000000000000e7
RAX: ffffffffffffffda RBX: 0000000000000001 RCX: 0000000000456a09
RDX: 00000000004104e0 RSI: 0000000000a44bd0 RDI: 0000000000000045
RBP: 00000000004c1904 R08: 000000000000000b R09: 0000000000000000
R10: 0000000001445940 R11: 0000000000000246 R12: 0000000001446940
R13: 0000000000000000 R14: 000000000000057e R15: badc0ffeebadface
Allocated by task 28651:
save_stack+0x43/0xd0 mm/kasan/kasan.c:448
set_track mm/kasan/kasan.c:460 [inline]
kasan_kmalloc+0xc4/0xe0 mm/kasan/kasan.c:553
kmem_cache_alloc_trace+0x152/0x780 mm/slab.c:3620
kmalloc include/linux/slab.h:513 [inline]
kzalloc include/linux/slab.h:707 [inline]
fib6_metric_set+0x163/0x2c0 net/ipv6/ip6_fib.c:645
fib6_add_rt2node+0xe36/0x27f0 net/ipv6/ip6_fib.c:1000
fib6_add+0xaae/0x14d0 net/ipv6/ip6_fib.c:1308
__ip6_ins_rt+0x54/0x80 net/ipv6/route.c:1163
ip6_route_add+0x6d/0xc0 net/ipv6/route.c:3171
addrconf_prefix_route.isra.48+0x51d/0x720 net/ipv6/addrconf.c:2347
inet6_addr_modify net/ipv6/addrconf.c:4627 [inline]
inet6_rtm_newaddr+0x112e/0x1b50 net/ipv6/addrconf.c:4743
rtnetlink_rcv_msg+0x46e/0xc30 net/core/rtnetlink.c:4665
netlink_rcv_skb+0x172/0x440 net/netlink/af_netlink.c:2453
rtnetlink_rcv+0x1c/0x20 net/core/rtnetlink.c:4683
netlink_unicast_kernel net/netlink/af_netlink.c:1315 [inline]
netlink_unicast+0x5a0/0x760 net/netlink/af_netlink.c:1341
netlink_sendmsg+0xa18/0xfd0 net/netlink/af_netlink.c:1906
sock_sendmsg_nosec net/socket.c:642 [inline]
sock_sendmsg+0xd5/0x120 net/socket.c:652
___sys_sendmsg+0x7fd/0x930 net/socket.c:2126
__sys_sendmsg+0x11d/0x290 net/socket.c:2164
__do_sys_sendmsg net/socket.c:2173 [inline]
__se_sys_sendmsg net/socket.c:2171 [inline]
__x64_sys_sendmsg+0x78/0xb0 net/socket.c:2171
do_syscall_64+0x1b9/0x820 arch/x86/entry/common.c:290
entry_SYSCALL_64_after_hwframe+0x49/0xbe
Freed by task 4479:
save_stack+0x43/0xd0 mm/kasan/kasan.c:448
set_track mm/kasan/kasan.c:460 [inline]
__kasan_slab_free+0x11a/0x170 mm/kasan/kasan.c:521
kasan_slab_free+0xe/0x10 mm/kasan/kasan.c:528
__cache_free mm/slab.c:3498 [inline]
kfree+0xd9/0x260 mm/slab.c:3813
fib6_metrics_release+0x77/0x90 net/ipv6/ip6_fib.c:179
fib6_drop_pcpu_from net/ipv6/ip6_fib.c:899 [inline]
fib6_purge_rt+0x5ec/0x7f0 net/ipv6/ip6_fib.c:934
fib6_del_route net/ipv6/ip6_fib.c:1784 [inline]
fib6_del+0xc11/0x1310 net/ipv6/ip6_fib.c:1815
fib6_clean_node+0x3ee/0x5e0 net/ipv6/ip6_fib.c:1976
fib6_walk_continue+0x4b1/0x8e0 net/ipv6/ip6_fib.c:1899
fib6_walk+0x95/0xf0 net/ipv6/ip6_fib.c:1947
fib6_clean_tree+0x1ea/0x360 net/ipv6/ip6_fib.c:2024
__fib6_clean_all+0x21c/0x420 net/ipv6/ip6_fib.c:2040
fib6_clean_all+0x27/0x30 net/ipv6/ip6_fib.c:2051
rt6_sync_down_dev net/ipv6/route.c:4083 [inline]
rt6_disable_ip+0x111/0x7e0 net/ipv6/route.c:4088
addrconf_ifdown+0x16f/0x1670 net/ipv6/addrconf.c:3650
addrconf_notify+0x6e9/0x27f0 net/ipv6/addrconf.c:3575
notifier_call_chain+0x180/0x390 kernel/notifier.c:93
__raw_notifier_call_chain kernel/notifier.c:394 [inline]
raw_notifier_call_chain+0x2d/0x40 kernel/notifier.c:401
call_netdevice_notifiers_info+0x3f/0x90 net/core/dev.c:1735
call_netdevice_notifiers net/core/dev.c:1753 [inline]
dev_close_many+0x447/0x8d0 net/core/dev.c:1505
rollback_registered_many+0x52b/0xef0 net/core/dev.c:7452
rollback_registered+0x1e9/0x420 net/core/dev.c:7517
unregister_netdevice_queue+0x32f/0x660 net/core/dev.c:8561
unregister_netdevice include/linux/netdevice.h:2548 [inline]
__tun_detach+0x11d1/0x15e0 drivers/net/tun.c:727
tun_detach drivers/net/tun.c:744 [inline]
tun_chr_close+0xe3/0x180 drivers/net/tun.c:3271
__fput+0x355/0x8b0 fs/file_table.c:209
____fput+0x15/0x20 fs/file_table.c:243
task_work_run+0x1ec/0x2a0 kernel/task_work.c:113
exit_task_work include/linux/task_work.h:22 [inline]
do_exit+0x1b08/0x2750 kernel/exit.c:865
do_group_exit+0x177/0x440 kernel/exit.c:968
__do_sys_exit_group kernel/exit.c:979 [inline]
__se_sys_exit_group kernel/exit.c:977 [inline]
__x64_sys_exit_group+0x3e/0x50 kernel/exit.c:977
do_syscall_64+0x1b9/0x820 arch/x86/entry/common.c:290
entry_SYSCALL_64_after_hwframe+0x49/0xbe
The buggy address belongs to the object at ffff8801d96d2800
which belongs to the cache kmalloc-96 of size 96
The buggy address is located 68 bytes inside of
96-byte region [ffff8801d96d2800, ffff8801d96d2860)
The buggy address belongs to the page:
page:ffffea000765b480 count:1 mapcount:0 mapping:ffff8801dac004c0
index:0xffff8801d96d2700
flags: 0x2fffc0000000100(slab)
raw: 02fffc0000000100 ffffea0006c46348 ffffea0006d0d288 ffff8801dac004c0
raw: ffff8801d96d2700 ffff8801d96d2000 0000000100000003 0000000000000000
page dumped because: kasan: bad access detected
Memory state around the buggy address:
ffff8801d96d2700: fb fb fb fb fb fb fb fb fb fb fb fb fc fc fc fc
ffff8801d96d2780: fb fb fb fb fb fb fb fb fb fb fb fb fc fc fc fc
> ffff8801d96d2800: fb fb fb fb fb fb fb fb fb fb fb fb fc fc fc fc
^
ffff8801d96d2880: fb fb fb fb fb fb fb fb fb fb fb fb fc fc fc fc
ffff8801d96d2900: fb fb fb fb fb fb fb fb fb fb fb fb fc fc fc fc
==================================================================
---
This bug is generated by a bot. It may contain errors.
See https://goo.gl/tpsmEJ for more information about syzbot.
syzbot engineers can be reached at syzkaller@googlegroups.com.
syzbot will keep track of this bug report. See:
https://goo.gl/tpsmEJ#bug-status-tracking for how to communicate with
syzbot.
^ permalink raw reply
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