From: Mark Hatle <mark.hatle@kernel.crashing.org>
To: openembedded-core@lists.openembedded.org
Subject: [PATCH 6/6] linux-yocto.inc: State riscv required tune_features
Date: Sun, 15 Jun 2025 21:29:25 -0500 [thread overview]
Message-ID: <1750040965-15015-7-git-send-email-mark.hatle@kernel.crashing.org> (raw)
In-Reply-To: <1750040965-15015-1-git-send-email-mark.hatle@kernel.crashing.org>
From: Mark Hatle <mark.hatle@amd.com>
Required:
rv32ima_zicsr_zifencei
rv64ima_zicsr_zifencei
See the arch/riscv/Makefile:
riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
---
meta/recipes-kernel/linux/linux-yocto.inc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/meta/recipes-kernel/linux/linux-yocto.inc b/meta/recipes-kernel/linux/linux-yocto.inc
index cdf2583698..80db85fe89 100644
--- a/meta/recipes-kernel/linux/linux-yocto.inc
+++ b/meta/recipes-kernel/linux/linux-yocto.inc
@@ -51,6 +51,11 @@ SRC_URI_RISCV = "\
SRC_URI:append:riscv32 = "${SRC_URI_RISCV}"
SRC_URI:append:riscv64 = "${SRC_URI_RISCV}"
+inherit features_check
+
+REQUIRED_TUNE_FEATURES:riscv32 = "rv 32 i m a zicsr zifencei"
+REQUIRED_TUNE_FEATURES:riscv64 = "rv 64 i m a zicsr zifencei"
+
# A KMACHINE is the mapping of a yocto $MACHINE to what is built
# by the kernel. This is typically the branch that should be built,
# and it can be specific to the machine or shared
--
2.34.1
next prev parent reply other threads:[~2025-06-16 2:29 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle
2025-06-16 2:29 ` [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle
2025-06-16 10:11 ` [OE-core] " Richard Purdie
2025-06-16 14:21 ` Mark Hatle
2025-06-16 2:29 ` [PATCH 2/6] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections Mark Hatle
2025-06-16 10:50 ` Bruce Ashfield
2025-06-16 2:29 ` [PATCH 3/6] u-boot: Dynamic RISC-V ISA configuration Mark Hatle
2025-06-16 2:29 ` [PATCH 4/6] qemuriscv: Dynamically configure qemu CPU Mark Hatle
2025-06-16 2:29 ` [PATCH 5/6] features_check.bbclass: Add support for required TUNE_FEATURES Mark Hatle
2025-06-16 2:29 ` Mark Hatle [this message]
2025-06-16 11:05 ` [OE-core] [PATCH 6/6] linux-yocto.inc: State riscv required tune_features Bruce Ashfield
2025-06-16 14:07 ` Mark Hatle
2025-06-16 10:11 ` [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation Gyorgy Sarvari
2025-06-16 14:12 ` Mark Hatle
[not found] ` <18498B713347A8EF.22186@lists.openembedded.org>
2025-06-16 16:00 ` Mark Hatle
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